# press 2 sec. Enter Manual Test Mode
01 # Exit Manual Test Mode
07 # Mute Rx Audio Path
08 # Unmute Rx Audio Path
09 # Mute Tx Audio Path
10 # Unmute Tx Audio Path
11 # Program Main Local Osc. to Channelbb
12 # Set Tx Power level to fixed valure
19 # Display SW Version Number of Call Processor
20 # Display SW Version Number of Modem
22 # Display SW Version Number of Speech Coder
25 # Set Continuous AGC
26xxxx # Set Continuous AFC
31x # Initiate Pseudo-Random Sequence with Midamble
33xxx # Synchronize to BCH Carrier
36 # Initiate Acoustic Loopback
37 # Stop Test
45xxx # Serving Cell Power Level
46 # Display Current Valure od AFC DAC
47x # Set Audio Volume
58 / xxxxxx # Display / Modify Security Code
59 / xxx # Display / Modify Lock Code
60 # Display IMEI
LOGIC BOARD SIGNALS
DATA BUS
ADDRESSS BUS
SRAM
U704
EEPROM
U705
FLASH
U702
ADDRESSS BUS
DATA BUS
J600
U703
BIC
ADDRESSS BUS
DATA BUS
Encoded
Voice Data
RX / TX
SIGNAL
PROCESSING
BATT_FDBK
A/D
D/A
DATA
12-16
6
1-5
11
U701, 16
3334 38 40 39 46
58
64
3548
37
20
DOWNLINK
(non-voice d data)
UPLINK
(non-voice d data)
12 11
CHARGER
15
17
47
9
20
19
5
28
22
6
21
GCAP
U900
J802
CODEC
U803
A / D
D / A
VAG
MULTIPLEXER
U802
DOUBLER
U805
13
8
3
18
19
1
4
5
3
78
84
X2 Multiplexer
2
6
13_DCLK_B
26 MHz
37
10
25, 40
B+
V3
V2
DC - DC
R+2.75V
L+2.75V
J601
1
2
-1
-
-
+
+
-
ALERT
EARPIECE ( Only av ailabl e with a com plete fl ip assembl y)
MIC
RESET
+ 2.75V
1
43
81
CLK_AUD
FS_AUD
8 KHz
512 KHz
+ 2,75V
7, 19, 26, 50, 56
66, 75, 85, 100
VERIFY THESE WAVEFORMS
BATT_SENSE
DAC_OUT
T902
37 VSWITCH
L500
R475
3
32, 41
Q501
R2.75V
B
E
C
TX_EN
+ 2,75V
SCI_RX
16
37, 108-114
DUAL_CS
DP_EN
RAM2CS
RAM1CS
ROM1CS
U704 SRam
U704 SRam
U702
U702 Eprom
217 Hz WAVEFORM NEEDED HERE !
17
13_DCLK_B
38
from U201, 59
to U501, 42
3.85V
BIC_INT
46 49
MF_INT
48
4
DOUBLER_EN
5
92
SC_INT
45
DM_CS
TX_KEY
MDM_RD
MDM_WR
RESET
RF_START
to U501
RX_ACQ
RX_EN
120
85
12
6
121
14
1, 3, 97
41
83
to U201, 97
U804
3
5
SC_INT
94
95
32.768 kHz
J601
Q601
Q602
4
14
EXT_B+
R602
ISENSE
16
CR605
J101, 21
31
32
DOWNLIN K_AUD
UPLINK _AUD
7
8
+
-
VSWITCH
MUX
SPI DATA BUS
BATT+
AD_THERM
BATT_GND
30
RESET
DUAL_CS
16
43
42
RAM1_CS
RAM2_CS
ROM1_CS
26
U701
CALL
PROCESSOR
U801
SPEECH
CODER
from J601, 11
Part
Designa-
tor
Part
Description
Part
Number
Part
Designator
Part
Description
Part
Number
A2 / A3 Ground clips Ant. tube 4209480E01 T902 Choke / Vswitch 2509306J01
AL800 Alert 5009473S01 U703 IC BIC 5109743E13
CR605 Diode / Charger 4809653F03 U704 IC SRAM 5109688L09
J101 32 Pin Display Connector 2809454C02 U801 IC Speech Coder 5199285C01
J600 15 Pin Extern Connector 0909449B04 U802 IC Multiplexer 5109632D44
J601 Flip Flexprint Connector 0909059E01 U803 Codec IC 5109920D15
J802 Microphone Connector 0909195E01 U804 IC Buffer 5109522E10
J900 SIM Connector 4009169E01 U805 IC Frquency Doubler 5109781E47
MIC Microphone 5009536H15 U900 IC GCAP 5109632D69
Q501 Transitor TX_EN 4809607E05 Y701 XTAL 32.768KHZ 4809995L05
Q601 Power Transistor Charger 4809579E17 U702 Flashed Eprom (boot sector) 5102486T01
Q602 Transistor Batt Feedback 4809939C04 S1 - S3 Volume / Mute Switch 4009060E01
R602 Resisor / Charger Sensing 0680195M64 SH25 - 27 Ground Clips 4204774Z01
DCS StarTAC AUDIO LOGIC BLOCK DIAGRAM
TEST COMMANDS
2.8Vpp
DUAL_CS
RESET
2,8Vrms
TX_EN
RX_EN
2.8mVpp
RAM1_CS
RAM2_CS
Doubler_EN
Measured in standby mode
DP_EN
10ms / cm
7Vpp
10ms / cm
200ms / cm
100ns / cm
2.8Vpp
100ns / cm
2.8Vpp
100ns / cm
2.8Vpp
100ns / cm
start up or
press key
start up or
press key
2.8Vpp
2ns / cm
SC_INT
2.8vpp
100ms / cm
MF_INT
BIC_INT
2.8Vpp
1ms / cm
2.8Vpp
50us / cm
press a key
UPLINK
DOWNLINK
5Vpp
10us / cm
2.8Vpp
10us / cm
AUDIO IN
2.7Vpp
5us / cm
test mode
08#, 10#, 36#
434#, 477#
AUDIO OUT
2.8Vpp
5us / cm
test mode
08#, 10#, 36#
434#, 477#
CLK_AUD
FS_AUD
2.8Vpp
5us / cm
2.8Vpp
5us / cm
CLK_13_IN
1.6Vpp
50ns / cm
power on
power on
From the CPU (U701). When high, Rx path enabled and low muted.
From CPU (U701), but inverted by Q501. High when
1. Enable the Rf switch for transmit mode & also the GIFSYN for transmit mode.
2. Supply Voltage for the PAC IC.
3. Isolates RF, by switching the PA Bias Circuitry ( Not shown).
1. Enables the Rf switch (U400) for receive mode.
2. Biases the mixer Q420, and low noise amp (Q421).
Controlled at power up by GCAP (U900) & CPU (U701).
1. Connected to CPU (U701), BIC (U703), Modem (U501) & Speech coder (U801).
After power up sequence, any chip can hold RESET low to power phone off if there is a problem.
From CPU (U701) to Eprom.
1. Chip Enable controlling read/write access to and from Eprom (U702).
From CPU (U701) to SRAM.
1. Chip Enable controlling read/write access to and from 1st half of SRAM (U704).
From CPU (U701) to SRAM.
1. Chip Enable controlling read/write access to and from 2nd half of SRAM (U704).
From CPU (U701) to Eprom.
1. Chip Enable controlling read/write access to and from Eprom (U702).
ROM1_CS
2.8Vpp
100ns / cm
Measured in test mode
From CPU (U701) to display, via connector J101.
1. Processor selects to enable display. When high, the display is enabled and low disabled.
Speech Coder Interface. This is a signal from uP (U701) to Speech Coder (U801).
1) This is a 20ms timing signal from U701 which times the decoding and encoding function of the Speech Coder
U801.
From CPU (U701) to Clock Doubler U805.
1) This signal enables the Clock Doubler U805 which doubles the 13MHz clock to 26MHz to time the Speech
Coder. When high U805 is enabled and low disabled.
From BIC chip (U703) to butt plug (J600). . This is a comms link from an external peripherale and the phone,
and could be either data information or speech information. It is also used to sense the presence of a DHFA and
the ignition status of the DHFA with DC levels
. This is a comms link from an external peripherale and the phone,
and could be either data information or speech information. It is also used to sense the presence of a DHFA and
the ignition status of the DHFA with DC levels
From butt plug (J600) to BIC chip (U703).
From GIF Syn to BIC IC - 13MHz clock..
Motorola Confidential Proprietary
From BIC to uP.
This is the master clock reference required for the radio
This signal periodically interrupts the uP at 217Hz. During Power Saving mode this signal is set
to DC.
From BIC to uP. This signal interrupts the uP for a number of reasons.
1. Keypad detection
2. Power Sense
3. SIM Functions
4. DSC Bus Status Indicators
External audio from butt plug, directly to Speech Coder IC
External audio from Speech Coder via GCAP to butt plug
This signal is from the BIC to the Speech Coder
It is a timing signal and runs at 512KHz, and times the transfer of speech information on the DSC
Bus between BIC and Speech Coder.
This signal is from the BIC to the Speech Coder IC.
It is a timing signal at 8KHz and provides for frame synchronisation during speech transfer on
the DSC bus.
AL LAYER - ORDERABLE SPARES
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
Y701
Europe Middle East & Africa Customer Services 03.07.98
LEVEL 3 COLOUR DIAGRAMS Rev. 1.2
DCS StarTAC
Colin Jack, Michael Hansen, Billy Jenkins, Ralf Lorenzen Page 1 of 2
REVISIONS