Mitsubishi M5M51008DVP-70H, M5M51008DVP-55H, M5M51008DRV-70H, M5M51008DRV-55H, M5M51008DKV-70H Datasheet
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MITSUBISHI LSIs
Ver. 1.1
MITSUBISHI
ELECTRIC
NC : NO CONNECTION
DESCRIPTION
FEATURES
Type name
Access
time
(max)
Active
(max)
stand-by
(max)
Power supply current
The M5M51008DP,FP,VP,RV,KV are a 1048576-bit CMOS static
RAM organized as 131072 word by 8-bit which are fabricated using
high-performance quadruple-polysilicon and double metal CMOS
technology. The use of thin film transistor (TFT) load cells and
CMOS periphery result in a high density and low power static
RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M51008DVP,RV,KV are packaged in a 32-pin thin small
outline package which is a high reliability and high density surface
mount device(SMD). Two types of devices are available.
M5M51008DVP(normal lead bend type package),
M5M51008DRV(reverse lead bend type package).Using both types
of devices, it becomes very easy to design a printed circuit board.
Package
APPLICATION
Small capacity memory units
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
M5M51008DFP,VP,RV,KV-55H
55ns
15mA
70ns
20µA
(1MHz)
M5M51008DFP,VP,RV,KV-70H
PIN CONFIGURATION (TOP VIEW)
NC
A16
A14
A12A7A6A5A4A3A2A1A0
DQ1
DQ2
DQ3
GND
VCC
A15S2W
A13A8A9
A11OEA10S1DQ8
DQ7
DQ6
DQ5
DQ4
A11A9A8
A13WS2
A15
VCCNCA16
A14
A12A7A6A5A4OEA10S1DQ8
DQ7
DQ6
DQ5
DQ4
GND
DQ3
DQ2
DQ1A0A1A2A3A4A5A6A7
A11A2A0OEA1
A3
M5M51008DVP,KV
A14
A16NCVCC
A15S2W
A13A8A9
DQ1
DQ2
DQ3
GND
DQ4
DQ5
DQ6
DQ7
DQ8S1A10
A12
32P3K-B(KV)
INPUT
INPUT
INPUT
ADDRESS
INPUTS
INPUT
INPUT
INPUT
DATA
INPUTS/
OUTPUTS
ADDRESS
INPUTS
DATA
INPUTS/
OUTPUTS
M5M51008DRV
(Vcc=5.5V)
(1MHz)
1
M5M51008DFP ············ 32pin 525mil SOP
M5M51008DVP,RV ············ 32pin 8 X 20 mm TSOP
M5M51008DKV ············ 32pin 8 X 13.4 mm TSOP
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
ADDRESS
CHIP SELECT
WRITE CONTROL
OUTPUT ENABLE
ADDRESS
CHIP SELECT
Outline 32P2M-A(FP)
1
2
3
4
5
6
7
8
9
2
2
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Outline 32P3H-E(VP),
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Outline 32P3H-F(RV)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
MITSUBISHI LSIs
Ver. 1.1
MITSUBISHI
ELECTRIC
FUNCTION
BLOCK DIAGRAM
The operation mode of the M5M51008D series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or
S2,whichever occurs first,requiring the set-up and hold time relative
to these edge to be maintained. The output enable input OE
directly controls the output stage. Setting the OE at a high level,
the output stage is in a high-impedance state, and the data bus
contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).
When setting S1 at a high level or S2 at a low level, the chip are in
a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery back-up
operation during power failure or power-down operation in the nonselected mode.
S1S2WOEMode
DQ
ICCLLHHHHLH
Non selection
Write
Read
High-impedance
Din
Dout
Active
Stand-by
Non selection
High-impedance
High-impedance
Active
Active
Stand-by
FUNCTION TABLE
LHLXHXXXXLX
X
CLOCK
GENERATOR
131072 WORDS
X 8 BITS
(512 ROWS
X128 COLUMNS
X 16BLOCKS)
21222325262728291314151718192021530632829223024321624A3A2A5A6A7
A12
A14
A16
A15
A13A8A9
A11A1A0
A10
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8WS1S2OE
VCC
(0V)
* Pin numbers inside dotted line show those of TSOP
*
*
A42710345671091112131415181723123428272612520191112312316
8
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
ADDRESS
INPUTS
WRITE
CONTROL
INPUT
OUTPUT
ENABLE
INPUT
GND
DATA
INPUTS/
OUTPUTS
CHIP
SELECT
INPUTS
MITSUBISHI LSIs
Ver. 1.1
MITSUBISHI
ELECTRIC
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
Symbol
Parameter
Test conditions
pFpFUnit
Max10Typ
Min
Limits
Input capacitance
Output capacitance
CICOParameter
Supply voltage
Input voltage
Output voltage
Power dissipation
Operating temperature
Storage temperature
UnitVVVmW°C°C
Conditions
With respect to GND
Ta=25°C
700
0~70
– 65~150
Ratings
Symbol
V
cc
VIVOPdT
oprTstg
DC ELECTRICAL CHARACTERISTICS
(Ta=0~70°C, Vcc=5V±10%, unless otherwise noted)
Symbol
Parameter
VVV
Max
Typ
Limits
Min
Test conditions
UnitVµA
– 0.3*~7
– 0.3*~Vcc + 0.3
(Ta=0~70°C, Vcc=5V±10% unless otherwise noted)
0~Vcc
* –3.0V in case of AC ( Pulse width ≤ 50ns )
Note 1: Direction for current flowing into an IC is positive (no mark).
2: Typical value is Vcc = 5V, Ta = 25°C
mA
* –3.0V in case of AC ( Pulse width ≤ 50ns )
µAµAmA
V
Vcc + 0.3
0.8
2.2–0.3*
2.43Stand-by current
0.4±1Active supply current
(AC, MOS level)
Active supply current
(AC, TTL level)
Vcc – 0.5
±1
80
VIH
VIL
VOH
VOLIIIO
ICC1
ICC2
ICC3
ICC4
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
Output current in off-state
Stand-by current
IOH= –1.0mA
IOH= –0.1mA
IOL=2mA
VI=0~Vcc
S1=VIH or S2=VIL or OE=VIH
VI/O=0~VCC
S1=VIL,S2=VIH,
other inputs=VIH or VIL
Output-open(duty 100%)
1) S2 ≤ 0.2V,
other inputs=0~VCC
2) S1 ≥ VCC–0.2V,
S2 ≥ VCC–0.2V,
other inputs=0~VCC
S1=VIH or S2=VIL,
other inputs=0~VCC
~25°C
~40°C
~70°C
-H2620mA151MHz
S1 ≤ 0.2V, S2 ≥ VCC–0.2V
other inputs ≤ 0.2V or ≥ VCC–0.2V
Output-open(duty 100%)
851570ns
55ns7070
1MHz
70ns
55ns
VO=GND,VO=25mVrms, f=1MHz
FP,VP,RV,KV
FP,VP,RV,KV
VI=GND, VI=25mVrms, f=1MHz
8345343739
42
M5M51008DFP,VP,RV,KV,KR -55H, -70H
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
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