Mitsubishi M5M51008BKV-12VLL, M5M51008BKV-12VL, M5M51008BKV-10VLL, M5M51008BKV-10VL, M5M51008BFP-10VL Datasheet

1997-1/21

MITSUBISHI LSIs

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

DESCRIPTION

The M5M51008BFP,VP,RV,KV,KR are a 1048576-bit CMOS
static RAM organized as 131072 word by 8-bit which are
fabricated using high-performance triple polysilicon CMOS
technology. The use of resistive load NMOS cells and CMOS
periphery result in a high density and low power static RAM.
They are low standby current and low operation current and ideal
for the battery back-up application.
The M5M51008BVP,RV,KV,KR are packaged in a 32-pin thin
small outline package which is a high reliability and high density
surface mount device(SMD).Two types of devices are available.
VP,KV(normal lead bend type package),RV,KR(reverse lead bend
type package). Using both types of devices, it becomes very easy
to design a printed circuit board.

FEATURES

Access

Type name

M5M51008BFP,VP,RV,KV,KR-70VL
M5M51008BFP,VP,RV,KV,KR-10VL
M5M51008BFP,VP,RV,KV,KR-12VL
M5M51008BFP,VP,RV,KV,KR-15VL
M5M51008BFP,VP,RV,KV,KR-70VLL
M5M51008BFP,VP,RV,KV,KR-10VLL
M5M51008BFP,VP,RV,KV,KR-12VLL
M5M51008BFP,VP,RV,KV,KR-15VLL

time

(max)

70ns
100ns
120ns
150ns

70ns

100ns

120ns

150ns

3.3±0.3V

3.0±0.3V

3.3±0.3V

3.0±0.3V

Low stand-by current 0.3µA (typ.)
Directly TTL compatible : All inputs and outputs
Easy memory expansion and power down by S1,S2
Data hold on +2V power supply
Three-state outputs : OR - tie capability
OE prevents data contention in the I/O bus
Common data I/O
Package
M5M51008BFP ············ 32pin 525mil SOP
M5M51008BVP,RV ············ 32pin 8 X 20 mm TSOP
M5M51008BKV,KR ············ 32pin 8 X 13.4 mm TSOP

VCC

Power supply current

Active

stand-by

(1MHz)

(max)

10mA

10mA

10mA

10mA

2

(max)

60µA

55µA

12µA

11µA

2

PIN CONFIGURATION (TOP VIEW)

ADDRESS

INPUTS

DATA

INPUTS/

OUTPUTS

NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ1
DQ2
DQ3
GND

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

M5M51008BFP

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

Outline 32P2M-A

1

A11

2

A9

3

A8

4

A13

5

W

6

S2

7

A15

8

VCC
NC
A16
A14
A12
A7
A6
A5
A4

9
10
11
12
13
14
15
16

M5M51008BVP,KV

VCC

ADDRESS

A15

INPUT

CHIP SELECT

S2

INPUT

WRITE CONTROL

W

INPUT

A13
A8
A9
A11

OUTPUT ENABLE

OE

INPUT

ADDRESS

A10

INPUT

CHIP SELECT

S1

INPUT

DQ8
DQ7
DQ6
DQ5
DQ4

ADDRESS
INPUTS

DATA
INPUTS/
OUTPUTS

32

OE

31

A10

30

S1

29

DQ8

28

DQ7

27

DQ6

26

DQ5

25

DQ4

24

GND

23

DQ3

22

DQ2

21

DQ1

20

A0

19

A1

18

A2

17

A3

APPLICATION

Small capacity memory units

1

A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
S2
W
A13
A8
A9
A11

MITSUBISHI
ELECTRIC

Outline 32P3H-E(VP), 32P3K-B(KV)

16
15
14
13
12
11
10

9

8

7

6

5

4

3

2

1

M5M51008BRV,KR

Outline 32P3H-F(RV), 32P3K-C(KR)

NC : NO CONNECTION

17

A3

18

A2

19

A1

20

A0

21

DQ1

22

DQ2

23

DQ3

24

GND

25

DQ4

26

DQ5

27

DQ6

28

DQ7

29

DQ8

30

S1

31

A10

32

OE

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

FUNCTION

The operation mode of the M5M51008B series are determined by
a combination of the device control inputs S1,S2,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S1 and the high level S2. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S1 or
S2,whichever occurs first,requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the data
bus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S1 and S2 are in an active state(S1=L,S2=H).

FUNCTION TABLE

S1 S2 W OE
X L X X
H X X X
L H L X

LLHHHHL

Mode DQ ICC

Non selection

High-impedance

Non selection High-impedance

Write

Read

H

Din

Dout

High-impedance

Stand-by
Stand-by

Active
Active
Active

1997-1/21

MITSUBISHI LSIs

When setting S1 at a high level or S2 at a low level, the chip are
in a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S1 and S2. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the
memory data can be held at +2V power supply, enabling battery
back-up operation during power failure or power-down operation in
the non-selected mode.

BLOCK DIAGRAM

8

A4
A5

7
6

A6

5

A7

4

A12

3

A14

2

A16

31

A15

28

A13

A8

27

ADDRESS

INPUTS

A0

12

A2

10

A3

9

23

A10

A1

11

A11

25
26

A9

16
15
14
13
12
11
10

7

ADDRESS INPUT

4
3

20
18
17
31

19

1
2

ADDRESS INPUT

BUFFER

ADDRESS INPUT

BUFFER

BUFFER

ROW

COLUMN

DECODER

BLOCK

DECODER

131072 WORDS

X 8 BITS
(1024 ROWS

X128 COLUMNS

X 8BLOCKS)

DECODER

CLOCK

GENERATOR

SENSE AMP.

OUTPUT

BUFFER

DATA INPUT

BUFFER

**

21
22
23
25
26
27
28
29

5

30

6

32

8

24

13
14
15
17
18
19

20

29

22
30

24

32

16

21

DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

WRITE
CONTROL

W

INPUT

S1
S2

OE

VCC

GND
(0V)

DATA
INPUTS/
OUTPUTS

CHIP
SELECT
INPUTS

OUTPUT
ENABLE
INPUT

* Pin numbers inside dotted line show those of TSOP

2

MITSUBISHI
ELECTRIC

M5M51008BFP,VP,RV,KV,KR -70VL,-10VL,-12VL,-15VL,

-70VLL,-10VLL,-12VLL,-15VLL

ABSOLUTE MAXIMUM RATINGS

Symbol

V

cc
VI
V

O

P

d

T

opr

Tstg

* –3.0V in case of AC ( Pulse width ≤ 30ns )

Supply voltage
Input voltage
Output voltage

Power dissipation
Operating temperature
Storage temperature

Parameter

1997-1/21

MITSUBISHI LSIs

1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM

Conditions

With respect to GND

Ta=25°C

Ratings
– 0.3*~4.6

– 0.3*~Vcc + 0.3

(Max 4.6)

0~Vcc

700

0~70

– 65~150

Unit

V
V

V

mW

°C
°C

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter

VIH
VIL

VOH1
VOH2
VOL

II
IO

ICC1

ICC2

ICC3

ICC4

* –3.0V in case of AC ( Pulse width ≤ 30ns )

High-level input voltage
Low-level input voltage

High-level output voltage 1
High-level output voltage 2
Low-level output voltage

Input current

Output current in off-state
Active supply current

(Min cycle )
Active supply current

(1MHz)

Stand-by current

Stand-by current

IOH= –0.5mA
IOH= –0.05mA
IOL=2mA

VI=0~Vcc
S1=VIH or S2=VIL or OE=VIH

VI/O=0~VCC
S1=VIL,S2=VIH,

other inputs=VIH or VIL
Output-open(duty 100%)

1) S2 ≤ 0.2V

2) S1 ≥ VCC–0.2V,
S2 ≥ VCC–0.2V
other inputs=0~VCC

S1=VIH or S2=VIL,
other inputs=0~VCC

(Ta=0~70°C, unless otherwise noted)

Test conditions

2.0

–0.3

2.4

Vcc

-0.5V

-L

-LL

Limits

-70VL, -70VLL

-10VL, -10VLL

VCC=3.3±0.3V VCC=3.0±0.3V

MaxTypMin

Vcc

+0.3V

0.6

0.4

±1
±1

3520

103

60

12

0.33

-12VL, -12VLL

-15VL, -15VLL

Min

2.0

–0.3

2.4

Vcc

-0.5V

15

+0.3V

±1
±1

MaxTyp

Vcc

0.6

0.4

30

103

55

11

0.33

Unit

V
V

V
V

V

µA
µA

mA

µA

mA

CAPACITANCE

Symbol

CI
CO

Note 1: Direction for current flowing into an IC is positive (no mark).

2: Typical value is Vcc = 3V, Ta = 25°C

(Ta=0~70°C, unless otherwise noted)

Parameter

Input capacitance

Output capacitance

3

Test conditions

VI=GND, VI=25mVrms, f=1MHz
VO=GND,VO=25mVrms, f=1MHz

MITSUBISHI
ELECTRIC

Min

Limits

Typ

Max

6
8

Unit

pF
pF