Mitsubishi M34512M4-XXXFP, M34512M2-XXXFP Datasheet

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 4512 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D converter. The various microcomputers in the 4512 Group include variations of the built-in memory size as shown in the table below.

FEATURES

●Minimum instruction execution time ................................ 0.75 µs

(at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0 V to 5.5 V)

●Supply voltage.....4.0 V to 5.5 V (at 4.2 MHz oscillation frequency)

Product

M34512M2-XXXFP M34512M4-XXXFP

ROM (PROM) size

(✕ 10 bits) 2048 words 4096 words

PIN CONFIGURATION (TOP VIEW)

0

2

1

D

D

D

32

30

31

●Timers

Timer 1...................................... 8-bit timer with a reload register

Timer 2...................................... 8-bit timer with a reload register

Timer 3...................................... 8-bit timer with a reload register

Timer 4...................................... 8-bit timer with a reload register

●Interrupt ........................................................................ 8 sources

●Serial I/O....................................................................... 8 bit-wide

●A-D converter .................. 10-bit successive comparison method

●Watchdog timer ................................................................. 16 bits

●Clock generating circuit (ceramic resonator)

●LED drive directly enabled (port D)

APPLICATION

Electrical household appliance, consumer electronic products, office automation equipment, etc.

RAM size

(✕ 4 bits) 128 words 256 words

3

2

P1

P1

28

29

1

P1

Package 32P6B-A

32P6B-A

3

0

P0

P1

27

25

26

ROM type

Mask ROM Mask ROM

P20/S

P21/S

P22/S

D D D D D

OUT

P0

3

1

4

2

5

3 4

6

7

CK

IN

M34512Mx-XXXFP

5 6 7 8

9

11

13

12

10

IN

OUT

X

SS

X

V

SS

CNV

RESET

16

14

15

DD

N.F

V

INT0

2

24

P0

1

23

P0

0

22 21

A

IN3

A

IN2

20

A

IN1

19

A

IN0

18

INT1

17

N.F: No Function

SS

as an

Outline 32P6B-A

However, connect toV unused pin.

PRELIMINARY

RAM

ROM

Memory

I/O port

Internal peripheral functions

Timer

Timer 1 (8 bits)

System clock generating circuit

Timer 2 (8 bits)

128, 256 words ✕ 4 bits

2048, 4096 words ✕ 10 bits

4500 Series

CPU core

Register B (4 bits)Register A (4 bits)

Register D (3 bits)

Register E (8 bits)

Stack register SK (8 levels)

Interrupt stack register SDP (1level)

ALU (4 bits)

X

IN

-X

OUT

Timer 3 (8 bits)

Timer 4 (8 bits)

Watchdog timer

(16 bits)

(10 bits ✕ 4 ch)

A-D converter

Serial I/O

(8 bits ✕ 1)

Port P0

4

|[go1

Port P1

4

Port P2

3

Port D

8

Notice: This is not a final specification.

Some parametric limits are subject to

change.

BLOCK DIAGRAM

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

2

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

PERFORMANCE OVERVIEW

Parameter Number of basic instructions Minimum instruction execution time Memory sizes

Input/Output ports

Timers

A-D converter Serial I/O Interrupt

Subroutine nesting Device structure Package Operating temperature range Supply voltage Power

dissipation (typical value)

ROM

RAM

D0–D7 P00–P03

P10–P13

P20–P22 INT0 INT1 Timer 1 Timer 2 Timer 3 Timer 4

Sources Nesting

Active mode

RAM back-up mode

M34512M2 M34512M4 M34512M2 M34512M4 I/O I/O

I/O

Input Input Input

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Function

117

0.75 µs (at 4.0 MHz oscillation frequency, in high-speed mode) 2048 words ✕ 10 bits 4096 words ✕ 10 bits 128 words ✕ 4 bits 256 words ✕ 4 bits Eight independent I/O ports. Input is examined by skip decision. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

functions can be switched by software. 3-bit input port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively. 1-bit input; INT0 pin is equipped with a key-on wakeup function. 1-bit input; INT1 pin is equipped with a key-on wakeup function. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register. 10-bit wide, This is equipped with an 8-bit comparator function. 8-bit ✕ 1 8 (two for external, four for timer, one for A-D, and one for serial I/O) 1 level 8 levels CMOS silicon gate 32-pin plastic molded LQFP(32P6B-A) –20 °C to 85 °C

4.0 V to 5.5 V

3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state)

0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)

3

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

PIN DESCRIPTION

Pin VDD VSS N.F CNVSS RESET

XIN XOUT

D0–D7

P00–P03

P10–P13

P20–P22

AIN0–AIN3 INT0, INT1

SIN

SOUT

SCK

Name Power supply Ground No Function CNVSS Reset input

System clock input System clock output

I/O port D

I/O port P0

I/O port P1

Input port P2

Analog input Interrupt input

Serial data input

Serial data output

Serial I/O clock input/output

Input/Output

— — — —

I/O

Input

Output

I/O

I/O

Input

Input Input

Input

Output

I/O

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Function Connected to a plus power supply. Connected to a 0 V power supply. This pin has no function, and connect to VSS as an unused pin. Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the watchdog timer

causes the system to be reset, the RESET pin outputs “L” level. I/O pins of the system clock generating circuit. XIN and XOUT can be connected to

ceramic resonator. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out-

put latch. For input use, set the latch of the specified bit to “1.” Input is examined by skip decision. The output structure is N-channel open-drain.

Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain.

Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software.

3-bit input port. Ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively.

Analog input pins for A-D converter. INT0, INT1 pins accept external interrupts. They also accept the input signal to re-

turn the system from the RAM back-up state. SIN pin is used to input serial data signals by software. SIN pin is also used as port P22. SOUT pin is used to output serial data signals by software. SOUT pin is also used as port P21. SCK pin is used to input and output synchronous clock signals for serial data transfer

by software. SCK pin is also used as port P20.

4

MITSUBISHI MICROCOMPUTERS

4512 Group

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MULTIFUNCTION CONNECTIONS OF UNUSED PINS

Pin P20 P21 P22

Notes 1: Pins except above have just single function.

2: The input of P2

selected.

Multifunction SCK SOUT SIN

0–P22 can be used even when SCK, SOUT, SIN are

DEFINITION OF CLOCK AND CYCLE

● System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bit 3 of the clock control register MR.

Table Selection of system clock

Register MR

MR3

0 1

Note: f(XIN)/2 is selected after system is released from reset.

● Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle.

● Machine cycle The machine cycle is the standard cycle required to execute the instruction.

Pin SCK SOUT SIN

System clock

f(XIN)/2

f(XIN)

Multifunction P20 P21 P22

XOUT N.F D0–D7

P20/SCK P21/SOUT P22/SIN INT0 INT1 AIN0–AIN3 P00–P03 P10–P13

Note: When the P0

(Note when the output latch is set to “0” and pins are open)

● After system is released from reset, port is in a high-impedance state until it is set the output latch to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high-impedance state.

● To set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away (caused by noise).

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Pin

Open (when using an external clock). Connect to VSS. Connect to VSS, or set the output latch

to “0” and open. Connect to VSS.

Connect to VSS.

Connect to VSS. Open or connect to VSS (Note) Open or connect to VSS (Note)

pull-up transistors (register PU0i=“0”) and also invalidate the key-on wakeup functions (register K0i=“0”) by software. When these pins are connected to V system fails to return from RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0i=“1”) by software, or set the output latch to “0.” Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.)

0–P03 and P10–P13 are connected to VSS, turn off their

SS while the key-on wakeup functions are left valid, the

Connection

PORT FUNCTION

Port

Port D

Port P0

Port P1

Port P2

Pin

D0–D7

P00–P03

P10–P13

P20/SCK P21/SOUT P22/SIN

Input

Output

I/O (8)

I/O (4)

I/O (4)

Input

(3)

Output structure

N-channel open-drain

N-channel open-drain

N-channel open-drain

(Note when connecting to V

● Connect the unused pins to V shortest distance against noise.

I/O

unit

1

Control

instructions

SD, RD

SS and VDD)

Control

registers

SZD CLD

4

OP0A

PU0, K0

IAP0

4

OP1A

PU0, K0

IAP1

3

IAP2

J1

SS and VDD using the thickest wire at the

Remark

Built-in programmable pull-up functions Key-on wakeup functions (programmable)

Built-in programmable pull-up functions Key-on wakeup functions (programmable)

5

Y

PRELIMINAR

Notice: This is not a final specification.

Some parametric limits are subject to

change.

PORT BLOCK DIAGRAMS

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Key-on wakeup input

Register A

Ai

OP0A instruction

Key-on wakeup input

Register A

Ai

OP0A instruction

Key-on wakeup input

Register A

Ai

OP1A instruction

K00

IAP0 instruction

D

Q

T

K01

IAP0 instruction

D

T

Q

K02

IAP1 instruction

D

T

Q

Pull-up transistor

PU00

Pull-up transistor

PU01

Pull-up transistor

PU02

0

P0

,P01

P02,P03

P10,P11

Register A

Synchronous clock input for serial transfer

Synchronous clock

output for serial transfer

J10

Register A

Serial data output

Serial data input

IAP2 instruction

Register A

Key-on wakeup input

External interrupt circuit

IAP2 instruction

1

J1

0

1

IAP2 instruction

1

J1

0

1

P20/SCK

P21/SOUT

P22/SIN

INT0, INT1

Key-on wakeup input

Register A

OP1A instruction

6

Ai

K03

IAP1 instruction

D

T

Q

Pull-up transistor

PU03

P12,P13

Analog input

Register Y

SD instruction RD instruction

•

• Applied potential to ports P2

• Applied potential to ports D

• i represents 0, 1, 2, or 3.

Decoder

CLD instruction

This symbol represents a parasitic diode on the port.

Q1

Decoder

Skip decision

(SZD instruction)

R

0–P22 must be VDD.

0–D7 must be 12 V.

AIN0–AIN3

S

Q

D0–D7

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

I12

INT0

Falling

0

1

Rising

SNZI0

One-sided edge detection circuit

Both edges detection circuit

Wakeup

Skip

I11

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

0

EXF0

1

External 0 interrupt

I22

Falling

INT1

Rising

External interrupt circuit structure

0

1

SNZI1

One-sided edge detection circuit

Both edges detection circuit

Wakeup

Skip

•

I21

0

EXF1

1

External 1 interrupt

This symbol represents a parasitic diode on the port.

7

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

FUNCTION BLOCK OPERATIONS CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation.

(2) Register A and carry flag

Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

<Carry>

(CY)

(M(DP))

Addition

(A)

Fig. 1 AMC instruction execution example

<Set>

SC instruction

RC instruction

CY A3A2A1A

ALU

<Result>

<Clear>

0

(3) Registers B and E

Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3).

(4) Register D

Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4).

TABP p instruction

Specifying address

RAR instruction

A

0

CY A3A2A

Fig. 2 RAR instruction execution example

Register B Register A

B3B2B1B

Register E

Fig. 3 Registers A, B and register E

E7E6E5E4E3E2E1E

B3B2B1B

Register B Register A

TAB instruction

0

TEAB instruction

TABE instruction

0

TBA instruction

A3A2A1A

A3A2A1A

ROM

840

<Rotation>

1

0

0

0

PC

H

p6p5p4p3p2p1p

Immediate field

value p

Fig. 4 TABP p instruction execution example

8

0

DR2DR1DR

The contents of

register D

PC

L

A3A2A1A

0

The contents of

register A

Low-order 4bits

0

Register A (4)

Middle-order 4 bits

Register B (4)

PRELIMINARY

n

M

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(5) Stack registers (SKS) and stack pointer (SP)

Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

• branching to an interrupt service routine (referred to as an interrupt service routine),

• performing a subroutine call, or

• executing the table reference instruction (TABP p).

Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call.

(6) Interrupt stack register (SDP)

Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.

(7) Skip flag

Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.

Program counter (PC)

SK SK SK

SK SK SK SK SK

0 1 2

3 4 5 6 7

Executing RT

instruction

Executing BM

instruction

Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0

0

and the contents of SK

Fig. 5 Stack registers (SKs) structure

is destroyed.

(SP) ← 0 (SK

0

) ← 0001

(PC) ← SUB1

16

Main program

Address 0000

16

NOP

16

BM SUB1

0001 000216 NOP

(SP) = 0 (SP) = 1 (SP) = 2

(SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7

Subroutine

SUB1 :

NOP

RT

0

.

·

·

·

(PC) ← (SK0) (SP) ← 7

Returning to the BM instruction executio

Note :

address with the RT instruction, and the B instruction becomes the NOP instruction.

Fig. 6 Example of operation at subroutine call

9

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(8) Program counter (PC)

Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM.

(9) Data pointer (DP)

Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure

8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).

Program counter

p5p4p3p2p1p0a6a5a4a3a2a1a

p

6

PC

H

Specifying page

Fig. 7 Program counter (PC) structure

Specifying address

Data pointer (DP)

Z1Z0X3X2X1X0Y3Y2Y1Y

Register Y (4)

Register X (4)

Register Z (2)

Specifying RAM file group

0

PC

L

0

Specifying RAM digit

Specifying RAM file

Fig. 8 Data pointer (DP) structure

Specifying bit position

D

7

0101 1 Register Y (4)

Fig. 9 SD instruction execution example

Port D output latch

Set

D

5

D

6

D4D

0

10

PRELIMINARY

g

Notice: This is not a final specification.

Some parametric limits are subject to

change.

PROGRAM MEMOY (ROM)

The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34512M4.

Table 1 ROM size and pages

Product

M34512M2 M34512M4

ROM size

(✕ 10 bits) 2048 words 4096 words

Pages

16 (0 to 15) 32 (0 to 31)

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

0000 007

F16

008016

00FF16

010016 017F16

018016

9

16

Interrupt address page

Subroutine special page

087654321

Page 0 Page 1 Page 2 Page 3

A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.

0FFF16

Fig. 10 ROM map of M34512M4

9087654321

0080

0082

0084

0086

0088

008A

008C

008E

External 0 interrupt address

16

External 1 interrupt address

16

Timer 1 interrupt address

16

16

Timer 2 interrupt address

Timer 3 interrupt address

16

16

Timer 4 interrupt address

16

16

A-D interrupt address

Serial I/O interrupt address

Pa

e 31

00FF

16

Fig. 11 Page 1 (addresses 008016 to 00FF16) structure

11

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DATA MEMORY (RAM)

1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map.

RAM 256 words ✕ 4 bits (1024 bits)

Register Z Register X

0 1 2 3 4 5 6 7 8

Register Y

9

10 11 12 13 14 15

0

23 6

1

Table 2 RAM size

M34512M2 M34512M4

0

7

Product

••••••••

RAM size 128 words ✕ 4 bits (512 bits) 256 words ✕ 4 bits (1024 bits)

15

Fig. 12 RAM map

M34512M4

M34512M2

Z=0, X=0 to 15 Z=0, X=0 to 7

256 words

128 words

12

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INTERRUPT FUNCTION

The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)

• Interrupt enable bit is enabled (“1”)

• Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)

(1) Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed.

(2) Interrupt enable bit

Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function.

(3) Interrupt request flag

When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;

• an interrupt occurs, or

• the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.

Table 3 Interrupt sources

Priority

level

1

2

3

4

5

6

7

8

Table 4 Interrupt request flag, interrupt enable bit and skip in-

Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A-D interrupt Serial I/O interrupt

Table 5 Interrupt enable bit function

Interrupt enable bit

Interrupt name

External 0 interrupt

External 1 interrupt

Timer 1 interrupt

Timer 2 interrupt

Timer 3 interrupt

Timer 4 interrupt

A-D interrupt

Serial I/O interrupt

struction

Request flag

EXF0 EXF1

Occurrence of interrupt 1 0

Activated condition

Level change of INT0 pin

Level change of INT1 pin

Timer 1 underflow

Timer 2 underflow

Timer 3 underflow

Timer 4 underflow

Completion of A-D conversion

Completion of serial I/O transfer

T1F T2F T3F T4F

ADF

SIOF

Enabled

Disabled

Skip instruction

SNZ0

SNZ1 SNZT1 SNZT2 SNZT3 SNZT4

SNZAD

SNZSI

Interrupt

address

Address 0 in page 1

Address 2 in page 1

Address 4 in page 1

Address 6 in page 1

Address 8 in page 1

Address A in page 1

Address C in page 1

Address E in page 1

Enable bit

V10 V11 V12 V13 V20 V21 V22 V23

Skip instruction

Invalid

Valid

13

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(4) Internal state during an interrupt

The internal state of the microcomputer during an interrupt is as follows (Figure 14).

• Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).

• Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.

• Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”

• Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).

(5) Interrupt processing

When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)

• Program counter (PC)

............................................................... Each interrupt address

• Stack register (SK)

....................................................................................................

The address of main routine to be executed when returning

• Interrupt enable flag (INTE)

.................................................................. 0 (Interrupt disabled)

• Interrupt request flag (only the flag for the current interrupt

source)................................................................................... 0

• Data pointer, carry flag, registers A and B, skip flag

........ Stored in the interrupt stack register (SDP) automatically

Fig. 14 Internal state when interrupt occurs

INT0 pin

(L→H or H→L input)

INT1 pin

(L→H or H→L input)

Timer 1 underflow

EXF0

EXF1 V1

T1F V1

V1

0

1

2

Address 0 in page 1

Address 2 in page 1

Address 4 in page 1

Main

routine

Interrupt

service routine

Interrupt

occurs

•

•

•

•

EI RTI

Interrupt is

enabled

: Interrupt enabled state : Interrupt disabled state

Fig. 13 Program example of interrupt processing

Timer 2 underflow

Timer 3 underflow

Timer 4 underflow

Completion of A-D conversion

Completion of

serial I/O transfer

Activated condition

T2F V1

T3F V2

T4F V2

ADF V2

SIOF V2

Request flag

(state retained)

Fig. 15 Interrupt system diagram

3

0

1

2

3

Enable

bit

INTE

Enable

flag

Address 6 in page 1

Address 8 in page 1

Address A in page 1

Address C in page 1

Address E in page 1

14

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(6) Interrupt control registers

• Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.

Table 6 Interrupt control registers

Interrupt control register V1

V13

V12

V11

V10

V23

V22

V21

V20

Note: “R” represents read enabled, and “W” represents write enabled.

Timer 2 interrupt enable bit

Timer 1 interrupt enable bit

External 1 interrupt enable bit

External 0 interrupt enable bit

Interrupt control register V2 R/Wat RAM back-up : 00002

Serial I/O interrupt enable bit

A-D interrupt enable bit

Timer 4 interrupt enable bit

Timer 3 interrupt enable bit

• Interrupt control register V2 Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A.

at RAM back-up : 00002

at reset : 00002 R/W

at reset : 00002

0

Interrupt disabled (SNZT2 instruction is valid)

1

Interrupt enabled (SNZT2 instruction is invalid)

0

Interrupt disabled (SNZT1 instruction is valid)

1

Interrupt enabled (SNZT1 instruction is invalid)

0

Interrupt disabled (SNZ1 instruction is valid)

1

Interrupt enabled (SNZ1 instruction is invalid)

0

Interrupt disabled (SNZ0 instruction is valid)

1

Interrupt enabled (SNZ0 instruction is invalid)

at reset : 00002

0

Interrupt disabled (SNZSI instruction is valid)

1

Interrupt enabled (SNZSI instruction is invalid)

0

Interrupt disabled (SNZAD instruction is valid)

1

Interrupt enabled (SNZAD instruction is invalid)

0

Interrupt disabled (SNZT4 instruction is valid)

1

Interrupt enabled (SNZT4 instruction is invalid)

0

Interrupt disabled (SNZT3 instruction is valid)

1

Interrupt enabled (SNZT3 instruction is invalid)

at RAM back-up : 00002

R/W

15

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V13 and V20–V2 3), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc-

When an interrupt request flag is set after its interrupt is enabled (Note 1)

f (XIN) (middle-speed mode)

IN

) (high-speed mode)

f (X

1 machine cycle

T2T

3

T2T

T

1

System clock

Interrupt enable

flag (INTE)

T

1

EI instruction

execution cycle

curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).

T2T

3

T

1

Interrupt enabled state

3

T2T

T

1

3

Interrupt disabled state

T2T

T

1

3

INT0, INT1

External interrupt

EXF0, EXF1

Timer 1, Timer 2, Timer 3, Timer 4, A-D, and Serial I/O interrupts

Notes 1: The 4512 Group operates in the middle-speed mode after system is released from reset.

T1F, T2F, T3F,

T4F, ADF,SIOF

2: The address is stacked to the last cycle.

3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.

Fig. 16 Interrupt sequence

Interrupt activated condition is satisfied.

2 to 3 machine cycles

(Notes 2, 3)

Retaining level of system clock for 4 periods or more is necessary.

Flag cleared

The program starts from the interrupt address.

16

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

EXTERNAL INTERRUPTS

The 4512 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupts can be controlled with the interrupt control registers I1 and I2.

Table 7 External interrupt activated conditions

Name

External 0 interrupt

External 1 interrupt

INT0

INT1

Input pin

When the next waveform is input to INT0 pin

• Falling waveform (“H”→“L”)

• Rising waveform (“L”→“H”)

• Both rising and falling waveforms When the next waveform is input to INT1 pin

• Falling waveform (“H”→“L”)

• Rising waveform (“L”→“H”)

• Both rising and falling waveforms

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Activated condition

MITSUBISHI MICROCOMPUTERS

4512 Group

Valid waveform

selection bit I11 I12

I21 I22

INT0

INT1

I12

Falling

Rising

I22

Falling

Rising

One-sided edge

SNZI0

detection circuit

Both edges detection circuit

Wakeup

One-sided edge detection circuit

Both edges detection circuit

Wakeup

0

1

0

1

Skip

I11

I21

0

EXF0

1

0

EXF1

1

External 0 interrupt

External 1 interrupt

Fig. 17 External interrupt circuit structure

SNZI1

Skip

•

This symbol represents a parasitic diode on the port.

17

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(1) External 0 interrupt request flag (EXF0)

External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure

16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.

• External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows.

➀ Select the valid waveform with the bits 1 and 2 of register I1. ➁ Clear the EXF0 flag to “0” with the SNZ0 instruction. ➂ Set the NOP instruction for the case when a skip is performed

with the SNZ0 instruction.

➃ Set both the external 0 interrupt enable bit (V10) and the INTE

flag to “1.”

(2) External 1 interrupt request flag (EXF1)

External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure

16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.

• External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows.

➀ Select the valid waveform with the bits 1 and 2 of register I2. ➁ Clear the EXF1 flag to “0” with the SNZ1 instruction. ➂ Set the NOP instruction for the case when a skip is performed

with the SNZ1 instruction.

➃ Set both the external 1 interrupt enable bit (V11) and the INTE

flag to “1.”

The external 0 interrupt is now enabled. Now when a valid waveform is input to the INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs.

The external 1 interrupt is now enabled. Now when a valid waveform is input to the INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs.

18

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(3) External interrupt control registers

• Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.

Table 8 External interrupt control registers

Interrupt control register I1 R/Wat RAM back-up : state retainedat reset : 00002

I13

I12

I11

I10

I23

I22

I21

I20

Notes 1: “R” represents read enabled, and “W” represents write enabled.

Not used

Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2)

INT0 pin edge detection circuit control bit INT0 pin

timer 1 control enable bit

Interrupt control register I2

Not used

Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3)

INT1 pin edge detection circuit control bit INT1 pin

timer 3 control enable bit

2: When the contents of I1 3: When the contents of I2

2 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 2 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.

0 1

0

1 0

1 0 1

0 1

0

1 0

1 0 1

• Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A.

This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0

instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled

at reset : 00002

This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT1 pin is recognized with the SNZI1

instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled

at RAM back-up : state retained

R/W

19

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

TIMERS

The 4512 Group has the following timers.

• Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).

FF

16

n : Counter initial value

Count starts

n

1st underflow 2nd underflow

The contents of counter

16

00

n+1 count n+1 count

• Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse.

Reload Reload

Time

Timer interrupt request flag

Fig. 18 Auto-reload function

“1” “0”

An interrupt occurs or

a skip instruction is executed.

20

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

The 4512 Group timer consists of the following circuits.

• Prescaler : frequency divider

• Timer 1 : 8-bit programmable timer

• Timer 2 : 8-bit programmable timer

• Timer 3 : 8-bit programmable timer

• Timer 4 : 8-bit programmable timer (Timers 1 to 4 have the interrupt function, respectively)

• 16-bit timer

Table 9 Function related timers

Circuit

Prescaler Timer 1

Timer 2

Timer 3

Timer 4

16-bit timer

Structure

Frequency divider 8-bit programmable binary down counter (link to INT0 input) 8-bit programmable binary down counter

8-bit programmable binary down counter (link to INT1 input) 8-bit programmable binary down counter 16-bit fixed dividing frequency

Count source

• Instruction clock

• Prescaler output (ORCLK)

• Timer 1 underflow

• Prescaler output (ORCLK)

• 16-bit timer underflow

• Timer 2 underflow

• Prescaler output (ORCLK)

• Timer 3 underflow

• Prescaler output (ORCLK)

• Instruction clock

Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W4. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below.

Frequency

dividing ratio 4, 16 1 to 256

1 to 256

1 to 256

1 to 256

65536

Use of output signal

• Timer 1, 2, 3 and 4 count sources

• Timer 2 count source

• Timer 1 interrupt

• Timer 3 count source

• Timer 2 interrupt

• Timer 4 count source

• Timer 3 interrupt

• Timer 4 interrupt

• Watchdog timer (The 15th bit is counted twice)

• Timer 2 count source (16-bit timer underflow)

Control register

W1 W1

W2

W3

W4

21

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Instruction clock

Divistion circuit

(divided by 2)

X

IN

INT0

MR

3

1 0

Internal clock generating circuit (divided by 3)

I1

2

One-sided edge

Falling

detection circuit

0 1

Both edges detection circuit

Rising

1

(Note 3)W1

W1

0 1

(TAB1)

W21,W2

0

00 01

Not available

10 11

W23(Note 3)

0 1

Prescaler

3

0

1

I1

I1

0

1

0

1

1/16

(Note 1)

Q

S

R

W1

1/4

ORCLK

W1

Timer 1 (8)

Reload register R1 (8)

T1AB

(TR1AB)

Register B

T1AB

Register A

Timer 1 underflow signal

Timer 2 (8)

Reload register R2 (8)

2

0

1

0

1 0

T1F

Timer 1 interrupt

T2F

Timer 2 interrupt

(T2AB)

INT1

I2

2

Falling

0 1

Rising

W31,W3

00 01

10

Not available Not available

11

(TAB2)

One-sided edge detection circuit

Both edges detection circuit

0

W33(Note 3)

0 1

(TAB3)

Register B

I2

1

0

1

I2

0

Register A

Timer 2 underflow signal

(Note 2)

Q

S

R

Timer 3 (8)

Reload register R3 (8)

T3AB

(TR3AB)

Register B

T3AB

Register A

W3

2

1 0

T3F

Timer 3

interrupt

Data is set automatically from each reload register when timer 1, 2, 3, or 4 underflows (auto-reload function)

Notes 1: Timer 1 count start synchronous circuit is set

0

by the valid edge of P3

1

bits 1 (I1

) and 2 (I12) of register I1.

/INT0 pin selected by

2: Timer 3 count start synchronous circuit is set

1

by the valid edge of P3

1

bits 1 (I2

) and 2 (I22) of register I2.

/INT1 pin selected by

3: Count source is stopped by clearing to “0.”

Fig. 19 Timers structure

22

W41,W4

0

00 01

Not available

10

Not available

11

W43(Note 3)

(TAB4)

Instruction clock

WRST instruction

Reset signal

Timer 3 underflow signal

0 1

Reload register R4 (8)

Register B

16-bit timer (WDT)

1 - - - - - - - - - - - 15 16

S

WEF

R

Timer 4 (8)

(T4AB)

Register A

Q

WDF1 WDF2

T4F

System reset

Timer 4 interrupt

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

Table 10 Timer control registers

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

W13

W12

W11

W10

W23

W22

W21

W20

W33

W32

W31

W30

Timer control register W1 R/Wat RAM back-up : 00002

Prescaler control bit

Prescaler dividing ratio selection bit

Timer 1 control bit

Timer 1 count start synchronous circuit control bit

Timer control register W2 R/Wat RAM back-up : state retainedat reset : 00002

Timer 2 control bit

Not used

Timer 2 count source selection bits

Timer control register W3

Timer 3 control bit

Timer 3 count start synchronous circuit control bit

Timer 3 count source selection bits

W21

0 0 1 1

W31

0 0 1 1

0 1 0 1 0 1 0 1

0 1 0 1

W20

0 1 0 1

0 1 0 1

W30

0 1 0 1

at reset : 00002

at reset : 00002

Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected

Stop (state retained) Operating

This bit has no function, but read/write is enabled.

Count source Timer 1 underflow signal Prescaler output Not available 16 bit timer (WDT) underflow signal

at reset : 00002

Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected

Timer 2 underflow signal Prescaler output Not available Not available

at RAM back-up : state retained

Count source

R/Wat RAM back-up : 00002

R/W

Timer control register W4

W43

W42

W41

W40

Note: “R” represents read enabled, and “W” represents write enabled.

Timer 4 control bit

Not used

Timer 4 count source selection bits

W41

0 0 1 1

at reset : 00002

Stop (state retained)

0

Operating

1 0

This bit has no function, but read/write is enabled.

1

W40

Timer 3 underflow signal

0

Prescaler output

1

Not available

0

Not available

1

at RAM back-up : state retained

Count source

R/W

23

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to

change.

MITSUBISHI MICROCOMPUTERS

4512 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(1) Timer control registers

• Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A.

• Timer control register W2 Register W2 controls the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.

• Timer control register W3 Register W3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.

• Timer control register W4 Register W4 controls the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.

(2) Precautions

Note the following for the use of timers.

• Prescaler Stop the prescaler operation to change its frequency dividing ratio.

• Count source Stop timer 1, 2, 3, or 4 counting to change its count source.

• Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data.

• Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows.

(3) Prescaler

Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to “0.”

(4) Timer 1 (interrupt function)

Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1. Timer 1 starts counting after the following process;

➀ set data in timer 1, and ➁ set the bit 1 of register W1 to “1.”

However, INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to “1.” When a value set is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction.

(5) Timer 2 (interrupt function)

Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Timer 2 starts counting after the following process;

➀ set data in timer 2, ➁ select the count source with the bits 0 and 1 of register W2, and ➂ set the bit 3 of register W2 to “1.”

When a value set is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 instruction.

24

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