Mitsubishi M34501M4-XXXFP, M34501M2-XXXFP, M34501E4FP Datasheet

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DESCRIPTION

The 4501 Group is a 4-bit single-chip microcomputer designed with
CMOS technology. Its CPU is that of the 4500 series using a
simple, high-speed instruction set. The computer is equipped with
two 8-bit timers (each timer has a reload register), interrupts, and
10-bit A-D converter.
The various microcomputers in the 4501 Group include variations
of the built-in memory size as shown in the table below.

FEATURES

●Minimum instruction execution time ................................ 0.68 µs

(at 4.4 MHz oscillation frequency, in high-speed mode)

●Supply voltage.........................................................VRST to 5.5 V

(VRST: detection voltage of voltage drop detection circuit)

Product

M34501M2-XXXFP
M34501M4-XXXFP
M34501E4FP (Note)

Note: Shipped in blank.

ROM (PROM) size

(✕ 10 bits)
2048 words
4096 words
4096 words

●Timers

Timer 1...................................... 8-bit timer with a reload register

Timer 2...................................... 8-bit timer with a reload register

●Interrupt ........................................................................ 4 sources

●Key-on wakeup function pins ................................................... 12

●Input/Output port ......................................................................14

●A-D converter .................. 10-bit successive comparison method

●Watchdog timer

●Clock generating circuit (ceramic resonator/RC oscillation)

●LED drive directly enabled (port D)

●Power-on reset circuit

●Voltage drop detection circuit ........................... VRST: Typ. 3.5 V

(Ta = 25 °C)

APPLICATION

Electrical household appliance, consumer electronic products, of­fice automation equipment, etc.

RAM size

(✕ 4 bits)
128 words
256 words
256 words

Package
20P2N-A

20P2N-A
20P2N-A

ROM type

Mask ROM
Mask ROM

One Time PROM

PIN CONFIGURATION

P 21/ A
P 20/ A

V

D D

V

S S

X

I N

X

O U T

C N V

S S

R E S E T

I N 1

I N 0

D3/ K
D

2

/ C

1

2

3

4

5

6

7

8

9

1 0

M

P

M

P

P0

2 0

3 4 5 0 1 M x - X X X F

3 4 5 0 1 E 4 F

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

0

P0

1

P0

2

P0

3

P1

0

P1

1

P12/CNTR

3

/INT

P1
D

0

D

1

Pin configuration (top view) (4501 Group)

O u t l i n e 2 0 P 2 N - A

BLOCK DIAGRAM

R

A

M
R

O

M

e m o r

y

/

O

p

o

r

t

I

n t e r n a l p e r i p h e r a l f u n c t i o n

s

T

i m e

r
T

i

m

e

r

1

(

8

b

i

t

s

)

S

y

s

t

e

m

c

l

o

c

k

g

e

n

e

r

a

t

i

n

g

c

i

r

c

u

i

t

T

i

m

e

r

2

(

8

b

i

t

s

)

1

2 8 , 2 5 6 w o r d s

✕

4 b i t

s

2

0

4

8

,

4

0

9

6

w

o

r

d

s

✕

1

0

b

i

t

s

4

5 0 0 S e r i e

s

C

P U c o r

e

R

e g i s t e r B ( 4 b i t s

)

R

e g i s t e r A ( 4 b i t s

)

R

e

g

i

s

t

e

r

D

(

3

b

i

t

s

)

R

e g i s t e r E ( 8 b i t s

)

S

t a c k r e g i s t e r S K ( 8 l e v e l s

)

I

n t e r r u p t s t a c k r e g i s t e r S D P ( 1 l e v e l

)

A

L U ( 4 b i t s

)

I

N

-

X

O

U

T

W

a t c h d o g t i m e

r

(

1 6 b i t s

)

(

1 0 b i t s

✕

2

c

h

)

A

-

D

c

o

n

v

e

r

t

e

r

o

r

t

P

0

4

P

o r t P

1

4

P

o r t P

2
o

r

t

D
4

P

o

w

e

r

-

o

n

r

e

s

e

t

c

i

r

c

u

i

t

V

o

l

t

a

g

e

d

r

o

p

d

e

t

e

c

t

i

o

n

c

i

r

c

u

i

t

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Block diagram (4501 Group)

2

PERFORMANCE OVERVIEW

Parameter
Number of basic instructions
Minimum instruction execution time
Memory sizes

Input/Output
ports

Timers

A-D converter

Interrupt

Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage

Power
dissipation

(typical value)

ROM

RAM

D0–D3

P00–P03

P10–P13

P20, P21

C

K

CNTR

INT

AIN0, AIN1

Timer 1

Timer 2

Analog input

Sources

Nesting

Active mode

RAM back-up mode

M34501M2
M34501M4/E4
M34501M2
M34501M4/E4
I/O

I/O

I/O

I/O

I/O
I/O
Timer I/O
Interrupt input
Analog input

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Function

111

0.68 µs (at 4.4 MHz oscillation frequency, in high-speed mode)
2048 words ✕ 10 bits
4096 words ✕ 10 bits
128 words ✕ 4 bits
256 words ✕ 4 bits
Four independent I/O ports.

Input is examined by skip decision.
Ports D2 and D3 are equipped with a pull-up function and a key-on wakeup function. Both func­tions can be switched by software.
Ports D2 and D3 are also used as ports C and K, respectively.

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P12 and P13 are also used as CNTR and INT, respectively.

2-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both
functions can be switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.

1-bit I/O; Port C is also used as port D2.
1-bit I/O; Port K is also used as port D3.
1-bit I/O; CNTR pin is also used as port P12.
1-bit input; INT pin is also used as port P13.
Two independent I/O ports. AIN0–AIN1 is also used as ports P20, P21, respectively.
8-bit programmable timer with a reload register.
8-bit programmable timer with a reload register and has a event counter.
10-bit wide, This is equipped with an 8-bit comparator function.
2 channel (AIN0 pin, AIN1 pin)
4 (one for external, two for timer, one for A-D)
1 level
8 levels
CMOS silicon gate
20-pin plastic molded SOP (20P2N-A)
–20 °C to 85 °C
VRST to 5.5 V (VRST: detected voltage of voltage drop detection circuit. Refer to the voltage

drop detection circuit characteristics.)

1.7 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors
in the cut-off state)

0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state)

3

PIN DESCRIPTION

Pin
VDD
VSS
CNVSS
RESET

XIN
XOUT System clock output Output
D0–D3

P00–P03

P10–P13

P20, P21

Port C

Port K

CNTR

INT

AIN0–AIN1

Name
Power supply
Ground
CNVSS
Reset input/output

System clock input

I/O port D

I/O

I/O port P1

I/O port P2

I/O port C

I/O port K

Timer input/output

Interrupt input

Analog input

Input/Output

—
—
—

I/O

Input

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Input

Input

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Function
Connected to a plus power supply.
Connected to a 0 V power supply.
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. When the watchdog timer or the

voltage drop detection circuit cause the system to be reset, the RESET pin outputs
“L” level.

I/O pins of the system clock generating circuit. When using a ceramic resonator, connect
it between pins XIN and XOUT. A feedback resistor is built-in between them. When using
the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open.

Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out­put latch. For input use, set the latch of the specified bit to “1.” Input is examined by
skip decision. The output structure is N-channel open-drain. Ports D2 and D3 are
equipped with a pull-up function and a key-on wakeup function. Both functions can
be switched by software.
Ports D2 and D3 are also used as ports C and K, respectively.

Port P0 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P0 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.

Port P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P1 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P12 and P13 are also used as CNTR and INT, respectively.

Port P2 serves as a 2-bit I/O port, and it can be used as inputs when the output latch
is set to “1.” The output structure is N-channel open-drain. Port P2 has a key-on
wakeup function and a pull-up function. Both functions can be switched by software.
Ports P20 and P21 are also used as AIN0 and AIN1, respectively.

1-bit I/O port. Port C can be used as inputs when the output latch is set to “1.” The
output structure is N-channel open-drain. Port C has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port C is also used
as port D2.

1-bit I/O port. Port K can be used as inputs when the output latch is set to “1.” The
output structure is N-channel open-drain. Port K has a key-on wakeup function and
a pull-up function. Both functions can be switched by software. Port K is also used
as port D3.

CNTR pin has the function to input the clock for the timer 2 event counter, and to out­put the timer 1 or timer 2 underflow signal divided by 2. This pin is also used as port
P12.

INT pin accepts external interrupts. It has the key-on wakeup function which can be
switched by software. This pin is also used as port P13.

A-D converter analog input pins. AIN0 and AIN1 are also used as ports P20 and P21,
respectively.

MULTIFUNCTION

Pin
D2
D3
P12
P13

Notes 1: Pins except above have just single function.

2: The input/output of D
3: The input of P1
4: The input/output of P2

4

Multifunction
C
K
CNTR
INT

2, D3, P12 and P13 can be used even when C, K, INT and CNTR (input) are selected.

2 can be used even when CNTR (output) is selected.

0, P21 can be used even when AIN0, AIN1 are selected.

Pin
C
K
CNTR
INT

Multifunction
D2
D3
P12
P13

P20
P21

Pin

Multifunction
AIN0
AIN1

AIN0
AIN1

Pin

Multifunction
P20
P21

DEFINITION OF CLOCK AND CYCLE

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

● Operation source clock
The operation source clock is the source clock to operate this
product. In this product, the following clocks are used.

• External ceramic resonator

• External RC oscillation

• Clock (f(X

• Clock (f(RING)) of the ring oscillator which is the internal oscil-

lator.

● System clock
The system clock is the basic clock for controlling this product.
The system clock is selected by the bits 2 and 3 of the clock con­trol register MR.

Table Selection of system clock

Register MR System clock

MR3

0
0
1
1

Notes 1: The ring oscillator clock is f(RING), the clock by the ce-

IN)) by the external clock

Operation mode

MR2

0
1
0
1

ramic resonator, RC oscillation or external clock is f(XIN).

2: The default mode is selected after system is released

from reset and is returned from RAM back-up.

(Note 1)
f(XIN) or f(RING)
f(XIN)/2 or f(RING)/2
f(XIN)/4 or f(RING)/4
f(XIN)/8 or f(RING)/8

High-speed mode
Middle-speed mode
Low-speed mode
Default mode

● Instruction clock
The instruction clock is a signal derived by dividing the system
clock by 3. The one instruction clock cycle generates the one
machine cycle.

● Machine cycle
The machine cycle is the standard cycle required to execute the
instruction.

PORT FUNCTION

Port

Port D

Port P0

Port P1

Port P2

D0, D1
D2/C
D3/K

P00–P03

P10, P11
P12/CNTR,
P13/INT

P20/AIN0
P21/AIN1

Input

Output

I/O
(4)

I/O
(4)

I/O
(4)

I/O
(2)

Output structure

N-channel open-drain

N-channel open-drain

N-channel open-drain

N-channel open-drain

I/O

unit

1

4

4

2

Control

instructions

SD, RD
SZD, CLD
SCP, RCP
SNZCP
IAK, OKA

OP0A
IAP0

OP1A
IAP1

OP2A
IAP2

Control

registers

PU2, K2

PU0, K0

PU1, K1
W6, I1

PU2, K2
Q1

RemarkPin

Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)

Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)

Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)

Built-in programmable pull-up
functions
Key-on wakeup functions
(programmable)

5

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

CONNECTIONS OF UNUSED PINS

Connection

System operates by the ring oscillator. (Note 1)
System operates by the external clock.

XIN
XOUT

Pin

Connect to VSS.
Open.

(The ceramic resonator is selected with the CMCK instruction.)
System operates by the RC oscillator.
(The RC oscillation is selected with the CRCK instruction.)
System operates by the ring oscillator. (Note 1)

D0, D1

Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)

Connect to VSS.
D2/C
D3/K

P00–P03

P10, P11
P12/CNTR

P13/INT

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

Open. (Output latch is set to “1.”)

Open. (Output latch is set to “0.”)

Connect to VSS.

Open. (Output latch is set to “1.”)

The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. The input to INT pin is disabled.

(Notes 4, 5)
Open. (Output latch is set to “0.”)
Connect to VSS.

P20/AIN0
P21/AIN1

Open. (Output latch is set to “1.”)
Open. (Output latch is set to “0.”)
Connect to VSS.

Notes 1: When the ceramic resonator or the RC oscillation is not selected by program, system operates by the ring oscillator (internal oscillator).

2: When the pull-up function is left valid, the supply current is increased. Do not select the pull-up function.
3: When the key-on wakeup function is left valid, the system returns from the RAM back-up state immediately after going into the RAM back-up state.

Do not select the key-on wakeup function.
4: When selecting the key-on wakeup function, select also the pull-up function.
5: Clear the bit 3 (I1

3) of register I1 to “0” to disable to input to INT pin (after reset: I13 = “0”)

The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The key-on wakeup function is not selected. (Note 4)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)
The pull-up function and the key-on wakeup function are not selected. (Notes 2, 3)

Usage condition

(Note when connecting to V

● Connect the unused pins to V

SS and VDD)

SS and VDD using the thickest wire at the shortest distance against noise.

6

PORT BLOCK DIAGRAMS

R e g i s t e r Y

SD instruction

R D i n s t r u c t i o n

D e c o d e rR e g i s t e r Y

D e c o d e r

CLD

instruction

Key-on wakeup

Skip decision

(SZD instruction)

S

RQ

“L” level

detection circuit

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

D0, D

1

(Note 1)

Pull-up
transistor

PU2

K2

2

2

SD instruction

R D i n s t r u c t i o n

SD instruction

R D i n s t r u c t i o n

C L D

i n s t r u c t i o n

SCP instruction

RCP instruction

DecoderRegister Y

K e y - o n w a k e u p

C L D

i n s t r u c t i o n

Skip decision

(SZD instruction)

Skip decision

S

(SNZCP

instruction)

(Note 1)

D2/ C

( N o t e 2 )
RQ
S

RQ

Pull-up
transistor

PU2

3

K 2

3

“L” level

detection circuit

Skip decision

(SZD instruction)

IAK instruction

S

Register A

(Note 1)

D3/K

( N o t e 2 )
RQ

A

0

D

Port block diagram (1)

O K A i n s t r u c t i o n

TQ

N o t e s 1 :

This symbol represents a parasitic diode on the port.

2: Applied potential to ports D

2

/C and D3/K must be VDD or less.

7

R e g i s t e r A

A

( N o t e 2 )

I A P 0 i n s t r u c t i o n

i

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

P u l l - u p t r a n s i s t o r

( N o t e 2 )

PU0

i

( N o t e 1 )

i

A

O P 0 A i n s t r u c t i o n

K e y - o n w a k e u p i n p u t

R e g i s t e r A

A

j

( N o t e 3 )

A

j

O P 0 A i n s t r u c t i o n

K e y - o n w a k e u p

“L ” l e v e l

d e t e c t i o n c i r c u i t

IAP0 instruction

“L” level detection

D

Q

T

D

Q

T

circuit

K0

K0

P 00, P 0

i

P u l l - u p t r a n s i s t o r

( N o t e 3 )

PU0

j

( N o t e 4 )

1

( N o t e 1 )

P 02, P 0

j

(Note 4)

3

Port block diagram (2)

8

Notes 1:

T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t .
2 : i r e p r e s e n t s 0 o r 1 .
3 : j r e p r e s e n t s 2 o r 3 .
4 : A p p l i e d p o t e n t i a l t o p o r t P 0 m u s t b e V

D D

o r l e s s .

K e y - o n w a k e u p i n p u t

“L” level

detection circuit

K1

i

Pull-up transistor

( N o t e 2 )

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

PU1

i

(Note 2)

Register A

Ai

( N o t e 2 )

A i

O P 1 A i n s t r u c t i o n

K e y - o n w a k e u p i n p u t

Clock input for timer 2 event counter

R e g i s t e r A

A

2

A

2

OP1A instruction

T i m e r 1 o r t i m e r 2 u n d e r f l o w
s i g n a l d i v i d e d b y 2

I A P 1 i n s t r u c t i o n

“ L ” l e v e l

d e t e c t i o n c i r c u i t

IAP1 instruction

D

TQ

D
TQ

W 2

1

W 2

0

K1

2

W6

( N o t e 1 )

P10, P1

1

(Note 3)

Pull-up transistor

PU1

2

(Note 1)

P 12/ C N T R ( N o t e 3 )

0

0
1

Key-on wakeup input

E x t e r n a l 0 i n t e r r u p tE x t e r n a l i n t e r r u p t c i r c u i t

Port block diagram (3)

R e g i s t e r A

A

A

O P 1 A i n s t r u c t i o n

d e t e c t i o n c i r c u i t

I A P 1 i n s t r u c t i o n

3

3

“ L ” l e v e l

D
T

K1

3

K 1

3

Q

N o t e s 1 :

T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t .
2 : i r e p r e s e n t s 0 o r 1 .
3 : A p p l i e d p o t e n t i a l t o p o r t P 1 m u s t b e V

P u l l - u p t r a n s i s t o r

PU1

3

(Note 1)

D D

P13/INT (Note 3)

o r l e s s .

9

K e y - o n w a k e u p i n p u t

R e g i s t e r A

A

0

A

0

O P 2 A i n s t r u c t i o n

d e t e c t i o n c i r c u i t

I A P 2 i n s t r u c t i o n

A n a l o g i n p u t

“ L ” l e v e l

D
T

Q

K 2

0

Q 1

D e c o d e r

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Pull-up transistor

PU2

( N o t e 1 )

MITSUBISHI MICROCOMPUTERS

4501 Group

0

I N 0

(Note 3)

P 20/ A

K e y - o n w a k e u p i n p u t

R e g i s t e r A

Port block diagram (4)

I A P 2 i n s t r u c t i o n

A

1

A

1

O P 2 A i n s t r u c t i o n

Analog input

K 2

1

Pull-up transistor

“ L ” l e v e l

d e t e c t i o n c i r c u i t

D

Q

T

Q1

Decoder

N o t e s 1 :

T h i s s y m b o l r e p r e s e n t s a p a r a s i t i c d i o d e o n t h e p o r t .
2 : i r e p r e s e n t s 0 o r 1 .
3 : A p p l i e d p o t e n t i a l t o p o r t s P 2 a n d P 3 m u s t b e V

PU2

( N o t e 1 )

1

P 21/ A

I N 1

D D

o r l e s s .

( N o t e 3 )

10

P1

( N o t e )

3

/INT

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

I1

2

F a l l i n g

0

I 1

3

1

R i s i n g

K 1

3

O n e - s i d e d e d g e
d e t e c t i o n c i r c u i t

B o t h e d g e s
d e t e c t i o n c i r c u i t

Wakeup

I 1

1

0

E X F 0

1

E x t e r n a l 0
i n t e r r u p t

Timer 1 count start
synchronization
circuit input

External interrupt circuit structure

S N Z I 0 i n s t r u c t i o n

Skip

•

This symbol represents a parasitic diode on the port.

11

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

FUNCTION BLOCK OPERATIONS
CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such as 4­bit data addition, comparison, AND operation, OR operation, and
bit manipulation.

(2) Register A and carry flag

Register A is a 4-bit register used for arithmetic, transfer, ex­change, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Fig­ure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.

(3) Registers B and E

Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and re­turned from the RAM back-up. Accordingly, set the initial value.

(4) Register D

Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed (Figure 4).
Register D is undefined after system is released from reset and re­turned from the RAM back-up. Accordingly, set the initial value.

< C a r r y >

( C Y )

( M ( D P ) )

Addition

ALU

(A)

< R e s u l t >

Fig. 1 AMC instruction execution example

<Set>

SC instruction

< C l e a r >

R C i n s t r u c t i o n

C YA3A2A1A

<Rotation>

RAR instruction

A

0

C YA3A2A

Fig. 2 RAR instruction execution example

R e g i s t e r BR

B3B2B1B

TAB instruction

0

A3A2A1A

T E A B i n s t r u c t i o n

Register E

E7E6E5E4E3E2E1E

T A B E i n s t r u c t i o n

B3B2B1B

Register B Register A

0

TBA instruction

A3A2A1A

0

1

e g i s t e r

A

0

0

0

T A B P p i n s t r u c t i o n

PCH

p6 p5 p4 p3 p2 p1 p0

I m m e d i a t e f i e l d

v a l u e p

Fig. 4 TABP p instruction execution example

12

DR2DR1DR0

T h e c o n t e n t s o f

r e g i s t e r D

Fig. 3 Registers A, B and register E

S p e c i f y i n g a d d r e s s

PCL

A3 A2 A1 A0

The contents of

register A

ROM

840

L o w - o r d e r 4 b i t s

R e g i s t e r A ( 4 )

Middle-order 4 bits

R e g i s t e r B ( 4 )

MITSUBISHI MICROCOMPUTERS

r

”

e

t

0

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(5) Stack registers (SKS) and stack pointer (SP)

Stack registers (SKs) are used to temporarily store the contents of
program counter (PC) just before branching until returning to the
original routine when;

• branching to an interrupt service routine (referred to as an inter­rupt service routine),

• performing a subroutine call, or

• executing the table reference instruction (TABP p).

Stack registers (SKs) are eight identical registers, so that subrou­tines can be nested up to 8 levels. However, one of stack registers
is used respectively when using an interrupt service routine and
when executing a table reference instruction. Accordingly, be care­ful not to over the stack when performing these operations
together. The contents of registers SKs are destroyed when 8 lev­els are exceeded.
The register SK nesting level is pointed automatically by 3-bit
stack pointer (SP). The contents of the stack pointer (SP) can be
transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.

(6) Interrupt stack register (SDP)

Interrupt stack register (SDP) is a 1-stage register. When an inter­rupt occurs, this register (SDP) is used to temporarily store the
contents of data pointer, carry flag, skip flag, register A, and regis­ter B just before an interrupt until returning to the original routine.
Unlike the stack registers (SKs), this register (SDP) is not used
when executing the subroutine call instruction and the table refer­ence instruction.

(7) Skip flag

Skip flag controls skip decision for the conditional skip instructions
and continuous described skip instructions. When an interrupt oc­curs, the contents of skip flag is stored automatically in the interrupt
stack register (SDP) and the skip condition is retained.

Program counter (PC)

S K
S K
S K
S K
S K
S K
S K
SK

0
1
2
3
4
5
6
7

E x e c u t i n g R T

i n s t r u c t i o n

Executing BM

instruction

Stack pointer (SP) points “7” at reset o
returning from RAM back-up mode. It points “0
by executing the first BM instruction, and th
contents of program counter is stored in SK0.
When the BM instruction is executed after eigh
stack registers are used ((SP) = 7), (SP) =
and the contents of SK0 is destroyed.

Fig. 5 Stack registers (SKs) structure

(SP) ← 0

(SK

0

Main program

A d d r e s s
N O
0 0 0 0

1

6

16 BM SUB1

0001

) ← 0001

(PC) ← SUB1

P

16

Subroutine

S U B 1 :

000216 NOP

( S P ) = 0
( S P ) = 1
( S P ) = 2
( S P ) = 3
( S P ) = 4
( S P ) = 5
( S P ) = 6
(SP) = 7

NOP

·

·

·

RT

( P C ) ← ( S K0)
( S P ) ← 7

Note :

Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction becomes the NOP instruction.

Fig. 6 Example of operation at subroutine call

13

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(8) Program counter (PC)

Program counter (PC) is used to specify a ROM address (page and
address). It determines a sequence in which instructions stored in
ROM are read. It is a binary counter that increments the number of
instruction bytes each time an instruction is executed. However,
the value changes to a specified address when branch instructions,
subroutine call instructions, return instructions, or the table refer­ence instruction (TABP p) is executed.
Program counter consists of PCH (most significant bit to bit 7)
which specifies to a ROM page and PCL (bits 6 to 0) which speci­fies an address within a page. After it reaches the last address
(address 127) of a page, it specifies address 0 of the next page
(Figure 7).
Make sure that the PCH does not specify after the last page of the
built-in ROM.

(9) Data pointer (DP)

Data pointer (DP) is used to specify a RAM address and consists
of registers Z, X, and Y. Register Z specifies a RAM file group, reg­ister X specifies a file, and register Y specifies a RAM digit (Figure

8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y certainly
and execute the SD, RD, or SZD instruction (Figure 9).

• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.

P r o g r a m c o u n t e r

p5p4p3p2p1p0a6a5a4a3a2a1a

p

6

P C

H

S p e c i f y i n g p a g e

Fig. 7 Program counter (PC) structure

S p e c i f y i n g a d d r e s s

D a t a p o i n t e r ( D P )

Z1Z0X3X2X1X0Y3Y2Y1Y

Register Y (4)

R e g i s t e r X ( 4 )

Register Z (2)

Fig. 8 Data pointer (DP) structure

S p e c i f y i n g R A M f i l e

Specifying RAM file group

Specifying bit position

P C

L

S p e c i f y i n g
R A M d i g i t

Set

0

0

D

2

D

3

0 01

0

Register Y (4)

Fig. 9 SD instruction execution example

Port D output latch

D1D

1

0

14

PROGRAM MEMOY (ROM)

6

The program memory is a mask ROM. 1 word of ROM is composed
of 10 bits. ROM is separated every 128 words by the unit of page
(addresses 0 to 127). Table 1 shows the ROM size and pages. Fig­ure 10 shows the ROM map of M34501M4.

Table 1 ROM size and pages

Product

M34501M2
M34501M4
M34501E4

A part of page 1 (addresses 008016 to 00FF16) is reserved for in­terrupt addresses (Figure 11). When an interrupt occurs, the
address (interrupt address) corresponding to each interrupt is set
in the program counter, and the instruction at the interrupt address
is executed. When using an interrupt service routine, write the in­struction generating the branch to that routine at an interrupt
address.
Page 2 (addresses 010016 to 017F16) is the special page for sub­routine calls. Subroutines written in this page can be called from
any page with the 1-word instruction (BM). Subroutines extending
from page 2 to another page can also be called with the BM in­struction when it starts on page 2.
ROM pattern (bits 7 to 0) of all addresses can be used as data ar­eas with the TABP p instruction.

ROM (PROM) size

(✕ 10 bits)
2048 words
4096 words
4096 words

Pages

16 (0 to 15)
32 (0 to 31)
32 (0 to 31)

MITSUBISHI MICROCOMPUTERS

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

9

1 6

0 0 0 0
0 0 7

F1

6

0 0 8 0

1 6

0 0

F F1

0 1 0 0
0 1 7

F1

0 1 8 0

0

F F F1

Fig. 10 ROM map of M34501M4/M34501E4

0082

0084

Interrupt address page

6

1 6

S u b r o u t i n e s p e c i a l p a g e

6

1 6

9087654321

16

External 0 interrupt address0080

16

16

Timer 1 interrupt address

4501 Group

087654321

P a g e 0
P a g e 1
P a g e 2
P a g e 3

P a g e 3 1

0 0 8 6

1 6

Timer 2 interrupt address

0088

16

0 0 8 A

1 6

008C

16

008E

16

00FF

16

Fig. 11 Page 1 (addresses 008016 to 00FF16) structure

A-D interrupt address

15

MITSUBISHI MICROCOMPUTERS

R

Z

R

X

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

DATA MEMORY (RAM)

1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.

• Note
Register Z of data pointer is undefined after system is released
from reset.
Also, registers Z, X and Y are undefined in the RAM back-up. After
system is returned from the RAM back-up, set these registers.

R A M 2 5 6 w o r d s ✕ 4 b i t s ( 1 0 2 4 b i t s )

e g i s t e r
e g i s t e r

0

23 6

1

0
1
2
3
4
5
6

Y

7
8

R

9
1 0
1 1
1 2
13
14
1 5

e g i s t e r

0

. . .

Table 2 RAM size

M34501M2
M34501M4
M34501E4

. . . . . . . .

7

Product

15

RAM size
128 words ✕ 4 bits (512 bits)
256 words ✕ 4 bits (1024 bits)
256 words ✕ 4 bits (1024 bits)

Z = 0 , X = 0 t o 1 5

Z = 0 , X = 0 t o 7

Fig. 12 RAM map

16

1 2 8 w o r d s ( 5 1 2 b i t s ) M 3 4 5 0 1 M 2

2 5 6 w o r d s ( 1 0 2 4 b i t s ) M 3 4 5 0 1 M 4 / E 4

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INTERRUPT FUNCTION

The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source. An
interrupt occurs when the following 3 conditions are satisfied.

• An interrupt activated condition is satisfied (request flag = “1”)

• Interrupt enable bit is enabled (“1”)

• Interrupt enable flag is enabled (INTE = “1”)

Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)

(1) Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether the every inter­rupt enable/disable. Interrupts are enabled when INTE flag is set to

“1” with the EI instruction and disabled when INTE flag is cleared to
“0” with the DI instruction. When any interrupt occurs, the INTE flag

is automatically cleared to “0,” so that other interrupts are disabled
until the EI instruction is executed.

(2) Interrupt enable bit

Use an interrupt enable bit of interrupt control registers V1 and V2
to select the corresponding interrupt or skip instruction.
Table 4 shows the interrupt request flag, interrupt enable bit and
skip instruction.
Table 5 shows the interrupt enable bit function.

(3) Interrupt request flag

When the activated condition for each interrupt is satisfied, the cor­responding interrupt request flag is set to “1.” Each interrupt
request flag is cleared to “0” when either;

• an interrupt occurs, or

• the next instruction is skipped with a skip instruction.

Each interrupt request flag is set when the activated condition is
satisfied even if the interrupt is disabled by the INTE flag or its in­terrupt enable bit. Once set, the interrupt request flag retains set
until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable state is
released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt dis­able state is released, the interrupt priority level is as follows
shown in Table 3.

Table 3 Interrupt sources

Priority

level

1

2

3

4

Table 4 Interrupt request flag, interrupt enable bit and skip in-

Interrupt name
External 0 interrupt
Timer 1 interrupt
Timer 2 interrupt
A-D interrupt

Table 5 Interrupt enable bit function

Interrupt enable bit

Interrupt name

External 0 interrupt

Timer 1 interrupt

Timer 2 interrupt

A-D interrupt

struction

Request flag

Occurrence of interrupt
1
0

Activated condition

Level change of INT
pin

Timer 1 underflow

Timer 2 underflow

Completion of
A-D conversion

EXF0

T1F
T2F

ADF

Enabled

Disabled

Skip instruction

SNZ0
SNZT1
SNZT2

SNZAD

Interrupt

address

Address 0
in page 1

Address 4
in page 1

Address 6
in page 1

Address C
in page 1

Enable bit

V10
V12
V13
V22

Skip instruction

Invalid

Valid

17

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(4) Internal state during an interrupt

The internal state of the microcomputer during an interrupt is as fol­lows (Figure 14).

• Program counter (PC)
An interrupt address is set in program counter. The address to be
executed when returning to the main routine is automatically
stored in the stack register (SK).

• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.

• Interrupt request flag
Only the request flag for the current interrupt source is cleared to

“0.”

• Data pointer, carry flag, skip flag, registers A and B

The contents of these registers and flags are stored automatically
in the interrupt stack register (SDP).

(5) Interrupt processing

When an interrupt occurs, a program at an interrupt address is ex­ecuted after branching a data store sequence to stack register.
Write the branch instruction to an interrupt service routine at an in­terrupt address.
Use the RTI instruction to return from an interrupt service routine.
Interrupt enabled by executing the EI instruction is performed after
executing 1 instruction (just after the next instruction is executed).
Accordingly, when the EI instruction is executed just before the RTI
instruction, interrupts are enabled after returning the main routine.
(Refer to Figure 13)

M a i n

r o u t i n e

I n t e r r u p t

s e r v i c e r o u t i n e

• Program counter (PC)

............................................................... Each interrupt address

• Stack register (SK)

....................................................................................................

The address of main routine to be
executed when returning

• Interrupt enable flag (INTE)

.................................................................. 0 (Interrupt disabled)

• Interrupt request flag (only the flag for the current interrupt

source)................................................................................... 0

• Data pointer, carry flag, registers A and B, skip flag

........ Stored in the interrupt stack register (SDP) automatically

Fig. 14 Internal state when interrupt occurs

INT pin

( L→H o r
H→L i n p u t )

Timer 1
underflow

Timer 2
underflow

Completion of

A-D conversion

Activated
condition

EXF0

T1F V1

T2F V1

ADF V 2

R e q u e s t f l a g

( s t a t e r e t a i n e d )

V1

2

E n a b l e

b i t

0

2

3

INTE

E n a b l e

f l a g

A d d r e s s 0
i n p a g e 1

A d d r e s s 4
i n p a g e 1

Address 6
in page 1

Address C
in page 1

Interrupt

occurs

•

•

•

•

E I
R T I

Interrupt is

enabled

: I n t e r r u p t e n a b l e d s t a t e

: I n t e r r u p t d i s a b l e d s t a t e

Fig. 13 Program example of interrupt processing

Fig. 15 Interrupt system diagram

18

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(6) Interrupt control registers

• Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are as­signed to register V1. Set the contents of this register through
register A with the TV1A instruction. The TAV1 instruction can be
used to transfer the contents of register V1 to register A.

Table 6 Interrupt control registers

Interrupt control register V1

V13

V12

V11

V10

V23

V22

V21

V20

Notes 1: “R” represents read enabled, and “W” represents write enabled.

Timer 2 interrupt enable bit

Timer 1 interrupt enable bit

Not used

External 0 interrupt enable bit

Interrupt control register V2 R/Wat RAM back-up : 00002

Not used

A-D interrupt enable bit

Not used

Not used

2: These instructions are equivalent to the NOP instrucion.

0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
1

• Interrupt control register V2
The A-D interrupt enable bit is assigned to register V2. Set the
contents of this register through register A with the TV2A instruc­tion. The TAV2 instruction can be used to transfer the contents of
register V2 to register A.

at RAM back-up : 00002

at reset : 00002 R/W

at reset : 00002

Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid) (Note 2)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid) (Note 2)

This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)

Interrupt enabled (SNZ0 instruction is invalid) (Note 2)

at reset : 00002

This bit has no function, but read/write is enabled.
Interrupt disabled (SNZAD instruction is valid)

Interrupt enabled (SNZAD instruction is invalid) (Note 2)
This bit has no function, but read/write is enabled.

This bit has no function, but read/write is enabled.

at RAM back-up : 00002

R/W

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt en­able bits (V10, V12, V13, V22), and interrupt request flag are “1.”
The interrupt actually occurs 2 to 3 machine cycles after the cycle
in which all three conditions are satisfied. The interrupt occurs after
3 machine cycles only when the three interrupt conditions are sat­isfied on execution of other than one-cycle instructions (Refer to
Figure 16).

19

MITSUBISHI MICROCOMPUTERS

T

1 F , T 2 F D

F

N

T

X

F

0
T

1

T

2

T

3

T

1

T

2

T

3

T2T

3

T1T

1

T2T

3

T

1

T

2

S

y s t e m c l o c

k

T

h e p r o g r a m s t a r t s f r o m h e i n t e r r u p t a d d r e s s

.

I

n

t

e

r

r

u

p

t

e

n

a

b

l

e

d

s

t

a

t

e

●

W h e n a n i n t e r r u p t r e q u e s t f l a g i s s e t a f t e r i t s i n t e r r u p t i s e n a b l e d ( N o t e 1

)

1

m

a

c

h

i

n

e

c

y

c

l

e

E

I i n s t r u c t i o n e x e c u t i o n c y c l

e

I

n t e r r u p t e n a b l

e

f

l a g ( I N T E

)

R

e t a i n i n g l e v e l o f s y s t e m

c

l o c k f o r 4 p e r i o d s o r m o r e

i

s n e c e s s a r y

.

I

n t e r r u p t d i s a b l e d s t a t

e

E

x t e r n a l

i

n t e r r u p

t

T

i m e r 1 , i m e r 2 , n d A - D n t e r r u p t

s

I

n t e r r u p t a c t i v a t e d

c

o n d i t i o n i s s a t i s f i e d

.

2

: T h e a d d r e s s i s s t a c k e d t o t h e l a s t c y c l e

.

3

: T h i s i n t e r v a l o f c y c l e s d e p e n d s o n t h e e x e c u t e d i n s t r u c t i o n a t t h e t i m e w h e n e a c h i n t e r r u p t a c t i v a t e d c o n d i t i o n i s s a t i s f i e d

.

N

o t e s 1 : T h e 4 5 0 1 G r o u p o p e r a t e s i n t h e d e f a u l t m o d e a f t e r s y s t e m i s r e l e a s e d f r o m r e s e t ( sy s t e m c l o c k = o p e r a t i o n s o u r c e c l o c k d i v i d e d b y 8)

.

f

(

X

I

N

)

(

d

e

f

a

u

l

t

m

o

d

e

)

f

(

X

I

N

)

( l o w - s p e e d m o d e

)

f

(

X

I

N

)

(

h

i

g

h

-

s

p

e

e

d

m

o

d

e

)

f

(

X

I

N

)

(

m

i

d

d

l

e

-

s

p

e

e

d

m

o

d

e

)

F

l a g c l e a r e

d

t

o

3

m

a

c

h

i

n

e

c

y

c

l

e

s

N

o

t

e

s

2

,

3

)

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Fig. 16 Interrupt sequence

20

EXTERNAL INTERRUPTS

The 4501 Group has the external 0 interrupt. An external interrupt
request occurs when a valid waveform is input to an interrupt input
pin (edge detection).
The external interrupt can be controlled with the interrupt control
register I1.

Table 7 External interrupt activated conditions

Name

External 0 interrupt

INT

Input pin

When the next waveform is input to INT pin

• Falling waveform (“H”→“L”)

• Rising waveform (“L”→“H”)

• Both rising and falling waveforms

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Activated condition

MITSUBISHI MICROCOMPUTERS

4501 Group

Valid waveform

selection bit
I11
I12

I1

2

F a l l i n g

0

1

P1

( N o t e )

3

/INT

I 1

3

R i s i n g

K 1

3

S N Z I 0 i n s t r u c t i o n

Fig. 17 External interrupt circuit structure

(1) External 0 interrupt request flag (EXF0)

External 0 interrupt request flag (EXF0) is set to “1” when a valid
waveform is input to INT pin.
The valid waveforms causing the interrupt must be retained at their
level for 4 clock cycles or more of the system clock (Refer to Figure

16).
The state of EXF0 flag can be examined with the skip instruction
(SNZ0). Use the interrupt control register V1 to select the interrupt
or the skip instruction. The EXF0 flag is cleared to “0” when an in­terrupt occurs or when the next instruction is skipped with the skip
instruction.

• External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a valid
waveform is input to INT pin.
The valid waveform can be selected from rising waveform, falling
waveform or both rising and falling waveforms. An example of
how to use the external 0 interrupt is as follows.

O n e - s i d e d e d g e
d e t e c t i o n c i r c u i t

B o t h e d g e s
d e t e c t i o n c i r c u i t

I 1

1

0

E X F 0

1

E x t e r n a l 0
i n t e r r u p t

Timer 1 count start
synchronization

Wakeup

circuit input

Skip

•

This symbol represents a parasitic diode on the port.

➀ Set the bit 3 of register I1 to “1” for the INT pin to be in the input

enabled state.

➁ Select the valid waveform with the bits 1 and 2 of register I1.
➂ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➃ Set the NOP instruction for the case when a skip is performed

with the SNZ0 instruction.

➄ Set both the external 0 interrupt enable bit (V10) and the INTE

flag to “1.”

The external 0 interrupt is now enabled. Now when a valid wave­form is input to the INT pin, the EXF0 flag is set to “1” and the
external 0 interrupt occurs.

21

(2) External interrupt control registers

• Interrupt control register I1
Register I1 controls the valid waveform for the external 0 inter­rupt. Set the contents of this register through register A with the
TI1A instruction. The TAI1 instruction can be used to transfer the
contents of register I1 to register A.

Table 8 External interrupt control register

Interrupt control register I1 R/Wat RAM back-up : state retainedat reset : 00002

I13

I12

I11

I10

Notes 1: “R” represents read enabled, and “W” represents write enabled.

INT pin input control bit (Note 2)

Interrupt valid waveform for INT pin/
return level selection bit (Note 2)

INT pin edge detection circuit control bit
INT pin

timer 1 control enable bit

2: When the contents of I1

struction when the bit 0 (V1
performed with the SNZ0 instruction.

2 and I13 are changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 in-

0) of register V1 to “0”. In this time, set the NOP instruction after the SNZ0 instruction, for the case when a skip is

0
1

0

1
0

1
0
1

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

INT pin input disabled
INT pin input enabled
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled

22

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(3) Notes on interrupts

➀ Note [1] on bit 3 of register I1

When the input of the INT pin is controlled with the bit 3 of regis­ter I1 in software, be careful about the following notes.

• Depending on the input state of the P1
terrupt request flag (EXF0) may be set when the bit 3 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 18➀)
and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
after executing at least one instruction (refer to Figure 18➁).
Also, set the NOP instruction for the case when a skip is per­formed with the SNZ0 instruction (refer to Figure 18➂).

•••

LA 4 ; (✕✕✕0

TV1A ; The SNZ0 instruction is valid...........➀

LA 8 ; (1✕✕✕2)
TI1A ; Control of INT pin input is changed

NOP ........................................................... ➁

SNZ0 ; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP ........................................................... ➂

2)

•••

✕ : these bits are not used here.

Fig. 18 External 0 interrupt program example-1

3/INT pin, the external 0 in-

➂ Note [3] on bit 2 of register I1

When the interrupt valid waveform of the P13/INT pin is changed
with the bit 2 of register I1 in software, be careful about the fol­lowing notes.

• Depending on the input state of the P13/INT pin, the external 0 in-
terrupt request flag (EXF0) may be set when the bit 2 of register
I1 is changed. In order to avoid the occurrence of an unexpected
interrupt, clear the bit 0 of register V1 to “0” (refer to Figure 20➀)
and then, change the bit 2 of register I1 is changed.
In addition, execute the SNZ0 instruction to clear the EXF0 flag
after executing at least one instruction (refer to Figure 20➁).
Also, set the NOP instruction for the case when a skip is per­formed with the SNZ0 instruction (refer to Figure 20➂).

•••

LA 4 ; (✕✕✕02)

TV1A ; The SNZ0 instruction is valid...........➀

LA 12
TI1A ; Interrupt valid waveform is changed

NOP ........................................................... ➁

SNZ0 ; The SNZ0 instruction is executed

(EXF0 flag cleared)

NOP ........................................................... ➂

•••

✕ : these bits are not used here.

Fig. 20 External 0 interrupt program example-3

➁ Note [2] on bit 3 of register I1

When the bit 3 of register I1 is cleared, the RAM back-up mode is
selected and the input of INT pin is disabled, be careful about the
following notes.

• When the key-on wakeup function of port P13 is not used (regis-
ter K13 = “0”), clear bits 2 and 3 of register I1 before system
enters to the RAM back-up mode. (refer to Figure 19➀).

•••

LA 0 ; (00✕✕2)

TI1A ; Input of INT disabled........................➀

DI
EPOF
POF ; RAM back-up

•••

✕ : these bits are not used here.

Fig. 19 External 0 interrupt program example-2

23

MITSUBISHI MICROCOMPUTERS

t

t

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

TIMERS

The 4501 Group has the following timers.

• Programmable timer

The programmable timer has a reload register and enables the
frequency dividing ratio to be set. It is decremented from a set­ting value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload reg­ister, and count continues (auto-reload function).

F F

1 6

n : C o u n t e r i n i t i a l v a l u e

Count starts

n

r

T

h e c o n t e n t s o f c o u n t e

00

16

1st underflow 2nd underflow

n + 1 c o u n

• Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency divid­ing ratio (n). An interrupt request flag is set to “1” after every n
count of a count pulse.

Reload Reload

n + 1 c o u n

T i m e

T i m e r i n t e r r u p t
r e q u e s t f l a g

Fig. 21 Auto-reload function

The 4501 Group timer consists of the following circuits.

• Prescaler : frequency divider

• Timer 1 : 8-bit programmable timer

• Timer 2 : 8-bit programmable timer

(Timers 1 and 2 have the interrupt function, respectively)

• 16-bit timer

Table 9 Function related timers

Circuit

Prescaler
Timer 1

Timer 2

16-bit timer

“1”
“0”

Structure

Frequency divider
8-bit programmable
binary down counter
(link to INT input)
8-bit programmable
binary down counter

16-bit fixed dividing
frequency binary down
counter

Count source

• Instruction clock

• Prescaler output (ORCLK)

• Timer 1 underflow

• Prescaler output (ORCLK)

• CNTR input

• System clock

• Instruction clock

An interrupt occurs or

a skip instruction is executed.

Prescaler and timers 1 and 2 can be controlled with the timer con­trol registers W1, W2 and W6. The 16-bit timer is a free counter
which is not controlled with the control register.
Each function is described below.

Frequency

dividing ratio
4, 16
1 to 256

1 to 256

65536

Use of output signal

• Timer 1 and 2 count sources

• Timer 2 count source

• CNTR output

• Timer 1 interrupt

• CNTR output

• Timer 2 interrupt

• Watchdog timer

(The 16th bit is counted twice)

Control
register

W1
W1
W2

W2

24

MITSUBISHI MICROCOMPUTERS

g

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

X

I N

C l o c k
g e n e r a t i o n
c i r c u i t

D i v i s i o n c i r c u i t

d i v i d e d b y 8
d i v i d e d b y 4
d i v i d e d b y 2

I1

S y s t e m c l o c k

MR3, MR

2

1 1
10
0 1
0 0

P 13/ I N T

3

T i m e r 1 u n d e r f l o w s i g n a l

Internal clock
generating circuit
(divided by 3)

( N o t e 2 )

W 1

Rising

0

1

I1

Falling

1

Instruction clock

2

One-sided edge

0

detection circuit

1

B o t h e d g e s
d e t e c t i o n c i r c u i t

I 1

0

W 2

2

(TAB1)

P r e s c a l e r

W 1

3

0

1

ORCLK

1 / 4

1 / 1 6

I1

1

( N o t e 1 )

0

QRS

1

T i m e r 1 ( 8 )

Reload register R1 (8)

T1AB T1AB

(TR1AB)

Register B

R e g i s t e r A

W 1

0

1

(TAB1)

2

W 1

0

1
0

T i m e r 1

T 1 F

i n t e r r u p t

I n s t r u c t i o n c l o c k

W 21, W 2
0 0

01
10
1 1

P 12/ C N T R

1 6 - b i t t i m e r ( W D T )

116

WRST instruction

(Note 3)

Reset signal

D W D T i n s t r u c t i o n

+

W R S T i n s t r u c t i o n

( N o t e 4 )

W6

Timer 1 underflow signal

0

( N o t e 2 )

W2

3

0
1

Timer 2 (8)

T2F

Timer 2
interrupt

Reload register R2 (8)

(TAB2)

0

0
1

R

P1

W D F 1

W E F

2

output

QS

QRS

W6

Reset si

Register B

1

0

1

D

W D F 2

T

R

nal

(T2AB)

Register A

Q

1 / 2
1 / 2

W a t c h d o g
r e s e t s i g n a l

(TAB2)

Timer 2 underflow signal

D a t a i s s e t a u t o m a t i c a l l y f r o m e a c h r e l o a d
r e g i s t e r w h e n t i m e r 1 o r 2 u n d e r f l o w s
( a u t o - r e l o a d f u n c t i o n )

Notes 1: Timer 1 count start synchronous circuit is set

by the valid edge of P1
bits 1 (I1

1

2: Count source is stopped by clearing to “0.”
3: When the WRST instruction is executed at

4: When the DWDT and WRST instructions are

) and 2 (I12) of register I1.

WDF1 flag = “1,” WDF1 flag is cleared to “0”
and the next instruction is skipped.
When the WRST instruction is executed at
WDF1 flag = “0,” skip is not executed.

executed continuously, WEF flag is cleared to
“0” and reset by watchdog timer is not executed.

3

/INT pin selected by

Fig. 22 Timers structure

25

Table 10 Timer control registers

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

Timer control register W1 R/Wat RAM back-up : 00002

W13

W12

W11

W10

W23

W22

W21

W20

W63

W62

W61

W60

Notes 1: “R” represents read enabled, and “W” represents write enabled.

Prescaler control bit

Prescaler dividing ratio selection bit

Timer 1 control bit

Timer 1 count start synchronous circuit
control bit

Timer control register W2 R/Wat RAM back-up : state retained

Timer 2 control bit

Timer 1 count auto-stop circuit selection
bit (Note 2)

Timer 2 count source selection bits

Timer control register W6

Not used

Not used

CNTR output selection bit

P12/CNTR function selection bit

2: This function is valid only when the timer 1 count start synchronization circuit is selected.
3: CNTR input is valid only when CNTR input is selected as the timer 2 count source.

0
1
0
1
0
1
0
1

at reset : 00002

0
1
0
1

W21

W20

0

0

0

1

1

0

1

1

at reset : 00002

0
1
0
1
0
1
0
1

at reset : 00002

at reset : 00002

Stop (state initialized)
Operating
Instruction clock divided by 4
Instruction clock divided by 16
Stop (state retained)
Operating
Count start synchronous circuit not selected
Count start synchronous circuit selected

Stop (state retained)
Operating
Count auto-stop circuit not selected
Count auto-stop circuit selected

Timer 1 underflow signal
Prescaler output (ORCLK)
CNTR input
System clock

This bit has no function, but read/write is enabled.

This bit has no function, but read/write is enabled.
Timer 1 underflow signal divided by 2 output

Timer 2 underflow signal divided by 2 output
P12(I/O)/CNTR input (Note 3)
P12 (input)/CNTR input/output (Note 3)

Count source

at RAM back-up : state retained

R/Wat RAM back-up : 00002

R/W

(1) Timer control registers

• Timer control register W1
Register W1 controls the count operation of timer 1, the selection
of count start synchronous circuit, and the frequency dividing ra­tio and count operation of prescaler. Set the contents of this
register through register A with the TW1A instruction. The TAW1
instruction can be used to transfer the contents of register W1 to
register A.

• Timer control register W2
Register W2 controls the selection of timer 1 count auto-stop cir­cuit, and the count operation and count source of timer 2. Set the
contents of this register through register A with the TW2A instruc­tion. The TAW2 instruction can be used to transfer the contents
of register W2 to register A.

• Timer control register W6
Register W6 controls the P12/CNTR pin function and the selec­tion of CNTR output. Set the contents of this register through
register A with the TW6A instruction. The TAW6 instruction can
be used to transfer the contents of register W6 to register A..

26

(2) Prescaler

Prescaler is a frequency divider. Its frequency dividing ratio can be
selected. The count source of prescaler is the instruction clock.
Use the bit 2 of register W1 to select the prescaler dividing ratio
and the bit 3 to start and stop its operation. Prescaler is initialized,
and the output signal (ORCLK) stops when the bit 3 of register W1
is cleared to “0.”

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(3) Timer 1 (interrupt function)

Timer 1 is an 8-bit binary down counter with the timer 1 reload reg­ister (R1). Data can be set simultaneously in timer 1 and the reload
register (R1) with the T1AB instruction. Stop counting and then ex­ecute the T1AB instruction to set data to timer 1. Data can be
written to reload register (R1) with the TR1AB instruction.
When writing data to reload register R1 with the TR1AB instruction,
the downcount after the underflow is started from the setting value
of reload register R1.
Timer 1 starts counting after the following process;

➀ set data in timer 1, and
➁ set the bit 1 of register W1 to “1.”

However, INT pin input can be used as the start trigger for timer 1
count operation by setting the bit 0 of register W1 to “1.”
Also, in this time, the auto-stop function by timer 1 underflow can
be performed by setting the bit 2 of register W2 to “1.”
When a value set is n, timer 1 divides the count source signal by n
+ 1 (n = 0 to 255).
Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the timer
1 interrupt request flag (T1F) is set to “1,” new data is loaded from
reload register R1, and count continues (auto-reload function).
Data can be read from timer 1 with the TAB1 instruction. When
reading the data, stop the counter and then execute the TAB1 in­struction.

(4) Timer 2 (interrupt function)

Timer 2 is an 8-bit binary down counter with the timer 2 reload reg­ister (R2). Data can be set simultaneously in timer 2 and the reload
register (R2) with the T2AB instruction. Stop counting and then ex­ecute the T2AB instruction to set data to timer 2.
Timer 2 starts counting after the following process;

➀ set data in timer 2,
➁ select the count source with the bits 0 and 1 of register W2, and
➂ set the bit 3 of register W2 to “1.”

When a value set is n, timer 2 divides the count source signal by n
+ 1 (n = 0 to 255).
Once count is started, when timer 2 underflows (the next count
pulse is input after the contents of timer 2 becomes “0”), the timer
2 interrupt request flag (T2F) is set to “1,” new data is loaded from
reload register R2, and count continues (auto-reload function).
Data can be read from timer 2 with the TAB2 instruction. When
reading the data, stop the counter and then execute the TAB2 in­struction.

(5) Timer interrupt request flags (T1F, T2F)

Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with the skip
instructions (SNZT1, SNZT2).
Use the interrupt control register V1 to select an interrupt or a skip
instruction.
An interrupt request flag is cleared to “0” when an interrupt occurs
or when the next instruction is skipped with a skip instruction.

(6) Count start synchronization circuit (timer 1)

Timer 1 has the count start synchronous circuit which synchronizes
the input of INT pin, and can start the timer count operation.
Timer 1 count start synchronous circuit function is selected by set­ting the bit 0 of register W1 to “1.” The control by INT pin input can
be performed by setting the bit 0 of register I1 to “1.”
The count start synchronous circuit is set by level change (“H”→“L”
or “L”→“H”) of INT pin input. This valid waveform is selected by bits
1 (I11) and 2 (I12) of register I1 as follows;

• I11 = “0”: Synchronized with one-sided edge (falling or rising)

• I11 = “1”: Synchronized with both edges (both falling and rising)

When register I11=“0” (synchronized with the one-sided edge), the ris-
ing or falling waveform can be selected by the bit 2 of register I1;

• I12 = “0”: Falling waveform

• I12 = “1”: Rising waveform

When timer 1 count start synchronous circuit is used, the count
start synchronous circuit is set, the count source is input to each
timer by inputting valid waveform to INT pin. Once set, the count
start synchronous circuit is cleared by clearing the bit I10 to “0” or
reset.
However, when the count auto-stop circuit is selected (register W22
= “1”), the count start synchronous circuit is cleared (auto-stop) at
the timer 1 underflow.

(7) Count auto-stop circuit (timer 1)

Timer 1 has the count auto-stop circuit which is used to stop timer
1 automatically by the timer 1 underflow when the count start syn­chronous circuit is used.
The count auto-stop cicuit is valid by setting the bit 2 of register W2
to “1”. It is cleared by the timer 1 underflow and the count source to
timer 1 is stopped.
This function is valid only when the timer 1 count start synchronous
circuit is selected.

27

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

(8) Timer input/output pin (P12/CNTR pin)

CNTR pin is used to input the timer 2 count source and output the
timer 1 and timer 2 underflow signal divided by 2.
The P12/CNTR pin function can be selected by bit 0 of register W6.
The CNTR output signal can be selected by bit 1 of register W6.
When the CNTR input is selected for timer 2 count source, timer 2
counts the falling waveform of CNTR input.

CNTR input

Timer 2 count

03

16

02

16

(9) Precautions

Note the following for the use of timers.

• Prescaler
Stop the prescaler operation to change its frequency dividing ra­tio.

• Count source
Stop timer 1 or 2 counting to change its count source.

• Reading the count value
Stop timer 1 or 2 counting and then execute the TAB1 or TAB2
instruction to read its data.

• Writing to the timer
Stop timer 1 or 2 counting and then execute the T1AB or T2AB
instruction to write its data.

• Writing to reload register R1
When writing data to reload register R1 while timer 1 is operat­ing, avoid a timing when timer 1 underflows.

(Note)

01

16

00

16

FF

16

FE

16

Timer 2 interrupt
request flag
(T2F)

Note: This is an example when “FF

Fig. 23 Count timing diagram at CNTR input

16

” is set to timer 2 reload register R2L.

28

WATCHDOG TIMER

Watchdog timer provides a method to reset the system when a pro­gram run-away occurs. Watchdog timer consists of timer
WDT(16-bit binary counter), watchdog timer enable flag (WEF),
and watchdog timer flags (WDF1, WDF2).
The timer WDT downcounts the instruction clocks as the count
source from “FFFF16” after system is released from reset.
After the count is started, when the timer WDT underflow occurs
(after the count value of timer WDT reaches “FFFF16,” the next
count pulse is input), the WDF1 flag is set to “1.”
If the WRST instruction is never executed until the timer WDT un­derflow occurs (until timer WDT counts 65534), WDF2 flag is set to
“1,” and the RESET pin outputs “L” level to reset the microcom­puter.
Execute the WRST instruction at each period of 65534 machine
cycle or less by software when using watchdog timer to keep the
microcomputer operating normally.

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

When the WEF flag is set to “1” after system is released from reset,
the watchdog timer function is valid.
When the DWDT instruction and the WRST instruction are ex­ecuted continuously, the WEF flag is cleared to “0” and the
watchdog timer function is invalid.
However, in order to set the WEF flag to “1” again once it has
cleared to “0”, execute system reset.
The WRST instruction has the skip function. When the WRST in­struction is executed while the WDF1 flag is “1”, the WDF1 flag is
cleared to “0” and the next instruction is skipped.
When the WRST instruction is executed while the WDF1 flag is “0”,
the next instruction is not skipped.
The skip function of the WRST instruction can be used even when
the watchdog timer function is invalid.

V a l u e o f 1 6 - b i t t i m e r ( W D T )

R E S E T p i n o u t p u t

➀ A f t e r s y s t e m i s r e l e a s e d f r o m r e s e t ( = a f t e r p r o g r a m i s s t a r t e d ) , t i m e r W D T s t a r t s c o u n t d o w n .
➁ W h e n t i m e r W D T u n d e r f l o w o c c u r s , W D F 1 f l a g i s s e t t o “ 1 . ”
➂ W h e n t h e W R S T i n s t r u c t i o n i s e x e c u t e d , W D F 1 f l a g i s c l e a r e d t o “ 0 , ” t h e n e x t i n s t r u c t i o n i s s k i p p e d .
➃ W h e n t i m e r W D T u n d e r f l o w o c c u r s w h i l e W D F 1 f l a g i s “ 1 , ” W D F 2 f l a g i s s e t t o “ 1 ” a n d t h e

w a t c h d o g r e s e t s i g n a l i s o u t p u t .

➄ T h e o u t p u t t r a n s i s t o r o f R E S E T p i n i s t u r n e d “ O N ” b y t h e w a t c h d o g r e s e t s i g n a l a n d s y s t e m r e s e t i s

e x e c u t e d .

F F F F

0000

W D F 1 f l a g

WDF2 flag

1 6

16

released

➁

➁

6 5 5 3 4 c o u n t

( N o t e )

➃

➂ W R S T i n s t r u c t i o n

➄ System reset➀ Reset

e x e c u t e d
( s k i p e x e c u t e d )

N o t e : T h e n u m b e r o f c o u n t i s e q u a l t o t h e n u m b e r o f c y c l e b e c a u s e t h e c o u n t s o u r c e o f w a t c h d o g t i m e r

i s t h e i n s t r u c t i o n c l o c k .

Fig. 24 Watchdog timer function

29

When the watchdog timer is used, clear the WDF1 flag at the pe­riod of 65534 machine cycles or less with the WRST instruction.
When the watchdog timer is not used, execute the DWDT instruc­tion and the WRST instruction continuously (refer to Figure 25).
The watchdog timer is not stopped with only the DWDT instruction.
The contents of WDF1 flag and timer WDT are initialized at the
RAM back-up mode.
When using the watchdog timer and the RAM back-up mode, ini­tialize the WDF1 flag with the WRST instruction just before the
microcomputer enters the RAM back-up state (refer to Figure 26)
The watchdog timer function is valid after system is returned from
the RAM back-up. When not using the watchdog timer function, ex­ecute the DWDT instruction and the WRST instruction continuously
every system is returned from the RAM back-up, and stop the
watchdog timer function.

MITSUBISHI MICROCOMPUTERS

4501 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

•••

WRST ; WDF1 flag cleared

•••

DWDT ; Watchdog timer function enabled/disabled
WRST ; WEF and WDF1 flags cleared

•••

Fig. 25 Program example to start/stop watchdog timer

•••

WRST ; WDF1 flag cleared
NOP
DI ; Interrupt disabled
EPOF ; POF instruction enabled
POF
↓
Oscillation stop (RAM back-up mode)

•••

Fig. 26 Program example to enter the RAM back-up mode

when using the watchdog timer

30