Mitsubishi M34280M1-XXXGP, M34280M1-XXXFP, M34280E1GP, M34280E1FP Datasheet

MITSUBISHI MICROCOMPUTERS

4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

DESCRIPTION

The 4280 Group is a 4-bit single-chip microcomputer designed
with CMOS technology for remote control transmitters. The 4280
Group has 7 carrier waves and enables fabrication of 8 × 7 key
matrix.

FEATURES

• Number of basic instructions ............................................. 62

• Minimum instruction execution time ............................ 8.0

(at f(X

IN) = 4.0 MHz, system clock = f(XIN)/8, VDD=3.0 V)

• Supply voltage ................................................. 1.8 V to 3.6 V

• Subroutine nesting ..................................................... 4 levels

• Timer

Timer 1 ................................................................... 8-bit timer

with a reload register and carrier wave output auto-control
function

Product

M34280M1-XXXFP
M34280M1-XXXGP
M34280E1FP
M34280E1GP

ROM (PROM) size

(× 9 bits)
1024 words
1024 words
1024 words
1024 words

µ

• Carrier wave output function (port CARR)
f(X

IN), f(XIN)/4, f(XIN)/8, f(XIN)/12

f(X

IN)/64, f(XIN)/96, “H” output fixed

• Logic operation function (XOR, OR, AND)

• RAM back-up function

• Key-on wakeup function (ports D

• I/O port (ports D, E, G, CARR) .......................................... 16

• Oscillation circuit..................................... Ceramic resonance

• Watchdog timer

s

• Power-on reset circuit

• Voltage drop detection circuit ......................... Typical:1.50 V

7, E0–E2, G0–G3) ............. 8

APPLICATION

Various remote control transmitters

RAM size

(× 4 bits)
32 words
32 words
32 words
32 words

Package

20P2N-A

20P2E/F-A

20P2N-A

20P2E/F-A

ROM type

Mask ROM

Mask ROM
One Time PROM
One Time PROM

PIN CONFIGURATION (TOP VIEW)

M34280M1-XXXFP/GP

V

X

SS

E
E

X

IN

OUT

E
G
G
G
G

2

1

0

0

1

2

3

1
2
3
4
5
6
7
8
9

10

DD

20
19

V
CARR

M34280M1-XXXFP/GP

D
D

D
D
D

D
D
D

0

1

2

3

4

5

6

7

18
17
16
15
14
13
12
11

Outline 20P2N-A

20P2E/F-A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

X

IN

–X

OUT

1

4

2

7

1

I/O port

Internal peripheral functions

Timer

System clock generating circuit

Remote control carrier wave output

Memory

ROM (Note)

1024 words × 9 bits

RAM

32 words × 4 bits

720 Series

CPU core

ALU (4 bits)

Register A (4 bits) Register B (4 bits)

Register D (3 bits) Register E (8 bits)

Stack register SK (4 levels)

Port E Port G Port D

Timer 1 (8 bits)

Note: PROM 1024 words × 9 bits

BLOCK DIAGRAM

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4280 Group

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

PERFORMANCE OVERVIEW

Parameter
Number of basic instructions
Minimum instruction execution time

Memory sizes

Input/Output
ports

Timer 1
Subroutine nesting
Device structure
Package
Operating temperature range
Supply voltage
Power
dissipation
(typical value)

ROM
RAM
D0–D6
D7
E0–E2
E0, E1
G0–G3
CARR

Active mode

RAM back-up mode

M34280M1/
E1
Output
I/O
Input
Output
I/O
Output

MITSUBISHI MICROCOMPUTERS

4280 Group

Function

62

8.0 µs (at 4.0 MHz system clock frequency)
(f(X

IN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V)

1024 words ✕ 9 bits
32 words ✕ 4 bits
Seven independent output ports
1-bit I/O port with the pull-down function
3-bit input port with the pull-down function
2-bit output port (E0, E1)
4-bit I/O port with the pull-down function
1-bit output port; CMOS output
8-bit timer with a reload register
4 levels (However, only 3 levels can be used when the TABP p instruction is executed)
CMOS silicon gate
20-pin plastic molded SOP (20P2N-A)/SSOP (20P2E/F-A)
–20 °C to 85 °C

1.8 V to 3.6 V
400 µA
(f(X

IN) = 4.0 MHz, system clock = f(XIN)/8, VDD = 3 V)

0.1

µ

A (at room temperature, VDD = 3 V)

PIN DESCRIPTION

Name
Power supply
Ground
System clock input

System clock output
Output port D

I/O port D

I/O port E

I/O port G

Carrier wave output
for remote control

V

DD

VSS
XIN

XOUT
D0–D6

D7

E0–E2

G0–G3

CARR

Pin

Input/Output

—
—

Input

Output
Output

I/O

Output

Input

I/O

Output

Function
Connected to a plus power supply.
Connected to a 0 V power supply.
I/O pins of the system clock generating circuit. Connect a ceramic resonator
between pins X
and XOUT.
Each pin of port D has an independent 1-bit wide output function. The output
structure is P-channel open-drain.
1-bit I/O port. For input use, turn on the built-in pull-down transistor and set the
latch of the specified bit to “0.” In addition, key-on wakeup function using “H”
level sense becomes valid. The output structure is P-channel open-drain.
2-bit (E

0, E1) output port. The output structure is P-channel open-drain.

3-bit input port. For input use (E
set the latch of the specified bit to “0.” In addition, key-on wakeup function using
“H” level sense becomes valid. Port E2 has an input-only port and has a key-on
wakeup function using “H” level sense and pull-down transistor.
4-bit I/O port. For input use, set the latch of the specified bit to “0.” The output
structure is P-channel open-drain. Port G has a key-on wakeup function using
“H” level sense and pull-down transistor.
Carrier wave output pin for remote control. The output structure is CMOS circuit.

IN and XOUT. The feedback resistor is built-in between pins XIN

0, E1), turn on the built-in pull-down transistor and

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4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

CONNECTIONS OF UNUSED PINS

Pin

D

0–D7

E0, E1

Open or connect to V
Set the output latch to “1” and open, or
connect to VDD pin (Note 2).

E2
G0–G3

Open or connect to V
Set the output latch to “0” and open, or
connect to VSS pin.

Notes 1: Port D7: Set the bit 2 (PU02) of the pull-down control register PU0 to “0” by software and turn the pull-down transistor OFF.

2: Set the corresponding bits (PU0

transistor OFF.

(Note in order to set the output latch to “0” to make pins open)

• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.

• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).

Connection

DD pin (Note 1).

SS pin.

0, PU01) of the pull-down control register PU0 to “0” by software and turn the pull-down

(Note when connecting to V

SS and VDD)

• Connect the unused pins to V

PORT FUNCTION

Port

Port D

Port E

Port G

Port CARR

0–D6

D

D7

E0
E1

E2

G0–G3

CARR

Pin

SS or VDD at the shortest distance and use the thick wire against noise.

Input/
Output
Output

(7)

Output structure

P-channel open-drain

Control

bits

1 bit

Control
instructions
SD
RD

Control

registers

CLD

I/O
(1)

SD
RD

PU0

CLD
SZD

I/O

P-channel open-drain

(2)

Output:

2 bits

OEA
IAE

PU0

Input:

Input

3 bits

IAE

(1)
I/O
(4)

Output

P-channel open-drain

CMOS

4 bits

1 bit

OGA
IAG

OCRA

C

(1)

Remark

Pull-down function and key-on
wakeup function
(programmable)

Pull-down function and key-on
wakeup function
(programmable)

Pull-down function and key-on
wakeup function

DEFINITION OF CLOCK AND CYCLE

• System clock (STCK)
The system clock is the source clock for controlling this product.
It can be selected as shown below whether to use the CCK
instruction.

CCK instruction
When not using
When using

4

System clock

f(X

IN)/8

IN)

f(X

Instruction clock

f(X

IN)/32

IN)/4

f(X

• Instruction clock (INSTCK)
The instruction clock is a signal derived by dividing the system
clock by 4, and is the basic clock for controlling CPU. The one
instruction clock cycle is equivalent to one machine cycle.

• Machine cycle
The machine cycle is the cycle required to execute the
instruction.

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

PORT BLOCK DIAGRAMS

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4280 Group

Register Y Decoder

SD instruction
RD instruction

Register Y Decoder

SD instruction
RD instruction

Skip decision (SZD instruction)

Register A

Register A

CLD instruction

Key-on wakeup input

A

0

A

0

Key-on wakeup input

A

1

A

1

Key-on wakeup input

OEA

instruction

OEA

instruction

CLD instruction

Q

D

IAE instruction

T

Q

D

IAE instruction

T

S

Q

R

S

Q

R

Pull-down
transistor

PU0

2

Pull-down
transistor

PU0

0

Pull-down
transistor

PU0

1

(Note 1)

Ports D

(Note 1)

Port D7 (Note 4)

(Note 1)

Port E

(Note 1)

Port E

0–D6

0

(Note 4)

1

(Note 4)

Key-on wakeup input

Register A

A

i

(Note 2)

instruction

A

i

Key-on wakeup input

Register A

A

j

TAC instruction

(Note 3)

OCRA instruction

Timer 1 underflow signal

Register A

OGA

Register C

Carrier wave
output circuit

Register A

A

2

D

Q

T

IAG instruction

TCA instruction

A

3

V1

2

IAE instruction

Register A

A

j

(Note 3)

Q

D

TCA

R

T

instruction

2

(Note 4)

Port E

Pull-down
transistor

Pull-down
transistor

To timer 1

D

Q

R

V1

T

0

(Note 1)

(Note 1)

(Note 1)

Notes 1:

0–G3

Ports G

CARRY

Port CARR

Carrier wave
output control
signal

(Note 4)

This symbol represents a parasitic diode.

2:

i represents bits 0 to 3.

3:

j represents bits 0 to 2.

4:

Applied voltage must be less than V

DD

.

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

FUNCTION BLOCK OPERATIONS
CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, and bit manipulation.

(CY)

(M(DP))

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4280 Group

<Carry>

Addition

ALU

(2) Register A and carry flag

Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.

(3) Registers B and E

Register B is a 4-bit register used for temporary storage of 4­bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).

(4) Register D

Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).

0 is stored in carry flag CY with the RAR

(A)

<Result>

Fig. 1 AMC instruction execution example

<Set>

SC instruction

<Clear>

RC instruction

CY A3 A2 A1 A0

<Rotation>

RAR instruction

A0 CY A3 A2 A1

Fig. 2 RAR instruction execution example

Register B Register A

B3B2B1B

TAB instruction

0

A3A2A1A

TEAB instruction

Register E

ER7ER6ER5ER4ER3ER2ER1ER

0

0

TABP p instruction

Specifying address

PCH

p3 p2 p1 p0

Immediate field

value p

Fig. 4 TABP p instruction execution example

DR2 DR1DR0

The contents

of register D

PCL

A3 A2 A1 A0

The contents

of register A

B3B2B1B

Register B Register A

Fig. 3 Registers A, B and register E

ROM

8

40

Low-order 4 bits

Middle-order 4 bits

Most significant 1 bit

URS flag (1)

URSC instruction

TABE instruction

0

A3A2A1A

TBA instruction

Register A (4)
Register B (4)

Carry flag CY (1)

0

6

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

(5) Most significant ROM code reference enable flag (URS)

URS flag controls whether to refer to the contents of the most
significant 1 bit (bit 8) of ROM code when executing the TABP
p instruction. If URS flag is “0,” the contents of the most
significant 1 bit of ROM code is not referred even when
executing the TABP p instruction. However, if URS flag is “1,”
the contents of the most significant 1 bit of ROM code is set to
flag CY when executing the TABP p instruction (Figure 4).
URS flag is “0” after system is released from reset and returned
from RAM back-up mode. It can be set to “1” with the URSC
instruction, but cannot be cleared to “0.”

(6) Stack registers (SKs) and stack pointer (SP)

Stack registers (SKs) are used to temporarily store the contents
of program counter (PC) just before branching until returning
to the original routine when;

• performing a subroutine call, or

• executing the table reference instruction (TABP p).
Stack registers (SKs) are four identical registers, so that
subroutines can be nested up to 4 levels. However, one of
stack registers is used when executing a table reference
instruction. Accordingly, be careful not to over the stack. The
contents of registers SKs are destroyed when 4 levels are
exceeded.
The register SK nesting level is pointed automatically by 2-bit
stack pointer (SP).
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.

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4280 Group

Program counter (PC)

Executing BM

instruction

Stack pointer (SP) points “3” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK
When the BM instruction is executed after four
stack registers are used ((SP) = 3), (SP) = 0
and the contents of SK

Fig. 5 Stack registers (SKs) structure

Executing RT

instruction

SK0
SK1
SK2

SK3

0 is destroyed.

(SP) 0
(SK0) 000116
(PC) SUB1

(SP) = 0
(SP) = 1
(SP) = 2

(SP) = 3

0.

(7) Skip flag

Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions.
Note : The 4280 Group just invalidates the next instruction

when a skip is performed. The contents of program
counter is not increased by 2. Accordingly, the number
of cycles does not change even if skip is not performed.
However, the cycle count becomes “1” if the TABP p,
RT, or RTS instruction is skipped.

Main program

Address

16 NOP

0000

16 BM SUB1

0001

Subroutine

SUB1 :

000216 NOP

(PC) (SK0)
(SP) 3

Note:

Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.

Fig. 6 Example of operation at subroutine call

NOP

·

·

·

RT

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4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

(8) Program counter (PC)

Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PC
which specifies to a ROM page and PC
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PC
the built-in ROM.

(9) Data pointer (DP)

Data pointer (DP) is used to specify a RAM address and
consists of registers X and Y. Register X specifies a file and
register Y specifies a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD, RD, or SZD instruction (Figure

9).

H does not exceed after the last page of

H (most significant bit to bit 7)

L (bits 6 to 0) which

Fig. 7 Program counter (PC) structure

Register X (2)

Program counter (PC)

p3p2p1p0a6a5a4a3a2a1a

PC

H

Specifying

PC

L

Specifying address

page

Data pointer (DP)

X1 X0 Y3 Y2 Y1 Y0

Register Y (4)

Specifying
RAM digit

Specifying RAM file

0

Fig. 8 Data pointer (DP) structure

Specifying bit position

Set

D5D7

1

01

0

Register Y (4)

Fig. 9 SD instruction execution example

1

Port D output latch

D0

8

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

PROGRAM MEMORY (ROM)

The program memory is a mask ROM. 1 word of ROM is
composed of 9 bits. ROM is separated every 128 words by the
unit of page (addresses 0 to 127).

Table 1 ROM size and pages

Product
M34280M1
M34280E1

Page 2 (addresses 0100
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern of all addresses can be used as data areas with
the TABP p instruction.

ROM size (✕ 9 bits)

1024 words

16 to 017F16) is the special page for

Pages

8 (0 to 7)

DATA MEMORY (RAM)

1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers X and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.

Table 2 RAM size

Product
M34280M1
M34280E1

32 words ✕ 4 bits (128 bits)

RAM size

16

0000
007

F16

008016
00FF16

010016
017F16

Subroutine special page

018016

03FF16

Fig. 10 ROM map of M34280M1

RAM 32 words × 4 bits (128 bits)

Register X

0

1
2

3
4

5

Register Y

6
7

087654321

Page 0
Page 1
Page 2

Page 3

Page 7

23

0

1

Fig. 11 RAM map

32 words

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

TIMERS

The 4280 Group has the programmable timer.

• Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
setting value n. When it underflows (count to n + 1), a timer 1
underflow flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).

FF16

n : Counter initial value

Count starts

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4280 Group

Reload Reload

n

The contents of counter
0016

Timer 1 underflow flag

Fig. 12 Auto-reload function

1st underflow 2nd underflow

Time

n+1 count n+1 count

A skip instruction is executed.

10

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

The 4280 Group timer consists of the following circuit.

• Timer 1 : 8-bit programmable timer

This timer can be controlled with the timer control register V1.
Timer 1 function is described below.

Table 3 Function related timer

Circuit

Timer 1

Structure

8-bit programmable
binary down counter

Count source

• Carrier generating circuit
output (CARRY)

• Bit 5 of watchdog timer

Frequency

dividing ratio

1 to 256

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4280 Group

Use of output signal

• Carrier wave output control

Control
register

V1

CARRY

XIN

CCK instruction

Initializing signal

V1

1

0
1

(Note 3)

INSTCK

V1

0

(Note 1)

0
1

(TAB1)

Frequency
divider
(divided by 8)

S

Q

R

Timer 1 (8)

Reload register R1 (8)

(T1AB)

Register B

Synchronous
circuit

Initializing signal

14-bit timer (WDT)

5

(Note 2)

Register A

(Note 3)

130

SNZT1 instruction

V1

2

STCK (System clock)

Frequency
divider
(divided by 4)

WDF1 WDF2

T1F

D
T

Q

V1

R

(Instruction clock)

System reset

Carrier wave output control signal

0

INSTCK

Fig. 13 Timers structure

WRST instruction

Initializing signal

(Note 3)

Notes 1: Counting is stopped by clearing to “0.”
2: When the T1AB instruction is executed after V1
writing is performed only to reload register R1.
3: The initializing signal is output at reset or RAM back-up mode.

: Data is automatically set from a reload register
when timer 1 underflows (auto-reload function).

0

is set to “1,”

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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

Table 4 Control registers related to timer

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4280 Group

Timer control register V1

V1

V11

V10

Note: “W” represents write enabled.

(1) Control register related to timer

• Timer control register V1

(2) Precautions

Note the following for the use of timers.

• Count source

• Watchdog timer

• Writing to reload register R1

Carrier wave output auto-control bit

2

Timer 1 count source selection bit

Timer 1 control bit

Register V1 controls the timer 1 count source and auto­control function of carrier wave output from port CARR by
timer 1. Set the contents of this register through register A
with the TV1A instruction.

Stop timer 1 counting to change its count source.

Be sure that the timing to execute the WRST instruction in
order to operate WDT efficiently.

When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.

at reset : 0002 Wat RAM back-up : 0002

Auto-control output by timer 1 is invalid

0

Auto-control output by timer 1 is valid

1

Carrier output (CARRY)

0

Bit 5 of watchdog timer (WDT)

1

Stop (Timer 1 state retained)

0

Operating

1

(4) Timer 1 underflow flag (T1F)

Timer 1 underflow flag is set to “1” when the timer 1 underflows.
The state of this flag can be examined with the skip instruction
(SNZT1).
T1F flag is cleared to “0” when the next instruction is skipped
with a skip instruction.

(3) Timer 1

Timer 1 is an 8-bit binary down counter with the timer 1 reload
register (R1).
When timer is stopped, data can be set simultaneously in timer
1 and the reload register (R1) with the T1AB instruction.
When timer is operating, data can be set to only reload register
R1 with the T1AB instruction.
When setting the next count data to reload register R1 at
operating, set data before timer 1 underflows.
Timer 1 starts counting after the following process;

➀ set data in timer 1,
➁ select the count source with the bit 1 of register V1, and
➂ set the bit 0 of register V1 to “1.”

Once count is started, when timer 1 underflows (the next count
pulse is input after the contents of timer 1 becomes “0”), the
timer 1 underflow flag (T1F) is set to “1,” new data is loaded
from reload register R1, and count continues (auto-reload
function).
When a value set in reload register R1 is n, timer 1 divides the
count source signal by n + 1 (n = 0 to 255).
Data can be read from timer 1 to registers A and B. When
reading the data, stop the counter and then execute the TAB1
instruction.

12

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ELECTRIC

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

WATCHDOG TIMER

Watchdog timer provides a method to reset and restart the system
when a program runs wild. Watchdog timer consists of 14-bit
timer (WDT) and watchdog timer flags (WDF1, WDF2).
Watchdog timer downcounts the instruction clock (INSTCK) as
the count source. When the timer WDT count value becomes
0000

16 and underflow occurs, the WDF1 flag is set to “1.” Then,

when the WRST instruction is not executed before the timer WDT
counts 16383, WDF2 flag is set to “1” and internal reset signal is
generated and system reset is performed.
When using the watchdog timer, execute the WRST instruction
at period of 16383 machine cycle or less to keep the
microcomputer operation normal.
Timer WDT is also used for generation of oscillation stabilization
time. When system is returned from reset and from RAM back­up mode by key-input, software starts after the stabilization
oscillation time until timer WDT downcounts to 3E00

16 elapses.

MITSUBISHI MICROCOMPUTERS

4280 Group

3FFF16
3E0016

Value of timer WDT

0000 16

WDF1 flag

WDF2 flag

Internal reset signal

System reset Return

Fig. 14 Watchdog timer function

“1”
“0”

“1”
“0”

“H”
“L”

Software
start

POF

instruction

execution

Software
start

WRST

instruction

execution

Software
start

System reset

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ELECTRIC

13

MITSUBISHI MICROCOMPUTERS

4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

CARRIER GENERATING CIRCUIT

The 4280 Group can output the various carrier waveforms by
the carrier wave selection register C.
Set the contents of this register through register A with the TCA
instruction. The TAC instruction can be used to transfer the
contents of register C to register A. When the TCA instruction is
executed, the output latch of port CARR is cleared to “0.”
The carrier waveform selected by setting register C can be output
from port CARR by setting port CARR output latch to “1.” When
the CARR output latch is cleared to “0,” carrier wave output is
stopped and port CARR output is fixed to “L” level. The CARR
output latch can be set through bit 3 (A
OCRA instruction.

Carrier wave selection register C (at reset: 111

Register C

setting value

LA 8

1

C

C

2

C

0

0

0

0

0

“H”
“L”

“H”

1

0

“L”

3) of register A with the

OCRA

2

, at RAM back-up: 1112)

Output waveform

The relationship between the setting value of register C and
selected waveform is described below.
Also, timer 1 can auto-control the carrier wave output from port
CARR by setting the timer control register V1.

Carrier wave

Frequency

Duty

LA 0

(TCA)

OCRA

1/3

System clock/
12

1/2

0

0

1

1

1

1

Note: This carrier wave can be used only when system clock f(X

“L”

“H”

1

1

“L”

“H”

0

0

“L”

“H”

1

0

“L”

“H”

0

1

“L”

“H”

1

1

“L”

IN

)/8 is selected.

“H”

0

1

The carrier wave output is fixed to “L” level when system clock f(X

IN

) is selected.

System clock/
8

System clock

No carrier wave

f(XIN)/4
(Note)

“L” level fixed

1/4

1/2

1/2

1/2

Fig. 15 Carrier wave selection register

14

MITSUBISHI
ELECTRIC

MITSUBISHI MICROCOMPUTERS

4280 Group

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER for INFRARED REMOTE CONTROL TRANSMITTERS

Timer 1 start

(V1

0)←1

a

a

b

b

cd

c d

Timer 1 underflow

Port CARR output

“1”
“0”

“H”
“L”

Set the interval “a” to timer 1.
Select count source CARRY

Timer 1 underflow

Port CARR output

Register V12

(V11)←0

Auto-control valid

(V1

CARRY

2)←1

“1”
“0”

“H”
“L”

“H”
“L”

“1”
“0”

Carrier wave output start

Set the interval “b”
to reload register R1.

Carrier wave output start

Set the interval “c”
to reload register R1.

Auto-control invalid Auto-control invalid

2)←0 (V12)←1 (V12)←0 (V12)←1

(V1

Set the interval “d”
to reload register R1.

Timer 1 stop

0)←0

(V1

(Note)

Carrier wave output stop

Note: When timer 1 is stopped, the port CARR output auto-control is terminated regardless of bit 2 (V12) of register V1.

Fig. 16 Port CARR output auto-control by timer 1

LOGIC OPERATION FUNCTION

The 4280 Group has the 4-bit logic operation function. The logic
operation between the contents of register A and the low-order 4
bits of register E is performed and its result is stored in register
A.

Each logic operation can be selected by setting logic operation
selection register LO.
Set the contents of this register through register A with the TLOA
instruction. The logic operation selected by register LO is
executed with the LGOP instruction.
Table 5 shows the logic operation selection register LO.

Table 5 Logic operation selection register LO

Logic operation selection register LO

LO1

Logic operation selection bits

LO0

at reset : 002 at RAM back-up : 002 W

L

O

1

O

0

L

0

0

Exclusive logic OR operation (XOR)

0

1

OR operation (OR)

1

0

AND operation (AND)

1

1

Not available

Logic operation function

Note: “W” represents write enabled.

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15