ADVANCED AND EVER ADVANCING
Preliminary
Mitsubishi 32-bit RISC Single-chip Microcomputers
M32R Family M32R/E Series
MSD-M32170-U-0003
32170
Group
M32170F6VFP/WG
M32170F4VFP/WG
M32170F3VFP/WG
User’s Manual
2000-03-17 Ver0.10
NOTE
Information in this manual may be changed without prior notice.
Mitsubishi Electric Corporation
Mitsubishi Electric Semiconductor Systems Corporation
Keep safety first in your circuit designs!
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malfunction or mishap.
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PREFACE
This manual describes the hardware specifications of Mitsubishi’s 32170 group of 32-bit
CMOS microcomputers.
This manual was created to help you understand the hardware specifications of the
32170-group microcomputers so you can take
full advantage of the versatile performance capabilities of these microcomputers. The CPU
features and the functionality of each internal
peripheral circuit are described in detail, which
we hope will prove useful for your circuit design.
For details about the M32R-family software
products and development support tools,
please refer to the user’s manuals and related
other documentation included with your products and tools.
How to read internal I/O register tables
➀ Bit Numbers: Each register is connected with an internal bus of 16-bit
wide, so the bit numbers of the registers located at even
addresses are D0-D7, and those at odd addresses are
D8-D15.
➁ State of Register at Reset: Represents the initial state of each register
immediately after reset with hexadecimal numbers
(undefined bits after reset are indicated each in column ➂.)
➂ At read: ... read enabled
? ... read disabled (read value invalid)
0 ... Read always as 0
1 ... Read always as 1
④ At write: : Write enabled
: Write enable conditionally
(include some conditions at write)
- : Write disabled (Written value invalid)
<Example of representation>
Not implemented
in the shaded portion.
1
Bit name Function
D
0
Not assigned.
Abit
1
(...................)
2
Bbit
(...................)
3
Cbit
(...................)
1234D0
Abit
Bbit Cbit
0: ----1: -----
0: ----1: -----
0: ----1: -----
Registers represented with thick rectangles
are accessible only with halfwords or words
(not accessible with bytes).
<at reset: H'04>
2
WR
0
3 4
Contents
CHAPTER 1 OVERVIEW
1.1 Outline of the 32170..........................................................................................1-2
1.1.1 M32R Family CPU Core .............................................................................1-2
1.1.2 Built-in Multiply-Accumulate Operation Function ........................................1-3
1.1.3 Built-in Flash Memory and RAM .................................................................1-3
1.1.4 Built-in Clock Frequency Multiplier ............................................................. 1-4
1.1.5 Built-in Powerful Peripheral Functions........................................................1-4
1.1.6 Built-in Full-CAN Function .......................................................................... 1-6
1.1.7 Built-in Debug Function .............................................................................. 1-6
1.2 Block Diagram...................................................................................................1-7
1.3 Pin Function .................................................................................................... 1-10
1.4 Pin Layout........................................................................................................ 1-18
CHAPTER 2 CPU
2.1 CPU Registers ................................................................................................... 2-2
2.2 General-purpose Registers..............................................................................2-2
2.3 Control Registers..............................................................................................2-3
2.3.1 Processor Status Word Register: PSW (CR0)............................................2-4
2.3.2 Condition Bit Register: CBR (CR1)............................................................. 2-5
2.3.3 Interrupt Stack Pointer: SPI (CR2)..............................................................2-5
User Stack Pointer: SPU (CR3)..................................................................2-5
2.3.4 Backup PC: BPC (CR6)..............................................................................2-5
2.4 Accumulator ...................................................................................................... 2-6
2.5 Program Counter .............................................................................................. 2-6
2.6 Data Formats .....................................................................................................2-7
2.6.1 Data Types ................................................................................................. 2-7
2.6.2 Data Formats ..............................................................................................2-8
(1)
CHAPTER 3 ADDRESS SPACE
3.1 Outline of Address Space ................................................................................ 3-2
3.2 Operation Modes............................................................................................... 3-6
3.3 Internal ROM Area and Extended External Area............................................3-8
3.3.1 Internal ROM Area...................................................................................... 3-8
3.3.2 Extended External Area.............................................................................. 3-8
3.4 Internal RAM Area and SFR Area .................................................................... 3-9
3.4.1 Internal RAM Area ......................................................................................3-9
3.4.2 Special Function Register (SFR) Area........................................................3-9
3.5 EIT Vector Entry .............................................................................................. 3-28
3.6 ICU Vector Table ............................................................................................. 3-29
3.7 Note about Address Space ............................................................................ 3-31
CHAPTER 4 EIT
4.1 Outline of EIT..................................................................................................... 4-2
4.2 EIT Event............................................................................................................ 4-3
4.2.1 Exception ....................................................................................................4-3
4.2.2 Interrupt ......................................................................................................4-3
4.2.3 Trap ............................................................................................................4-3
4.3 EIT Processing Procedure ............................................................................... 4-4
4.4 EIT Processing Mechanism ............................................................................. 4-6
4.5 Acceptance of EIT Event .................................................................................. 4-7
4.6 Saving and Restoring the PC and PSW ..........................................................4-8
4.7 EIT Vector Entry .............................................................................................. 4-10
4.8 Exception Processing .................................................................................... 4-11
4.8.1 Reserved Instruction Exception (RIE).......................................................4-11
4.8.2 Address Exception (AE)............................................................................4-13
4.9 Interrupt Processing.......................................................................................4-15
4.9.1 Reset Interrupt (RI) ...................................................................................4-15
4.9.2 System Break Interrupt (SBI).................................................................... 4-16
(2)
4.9.3 External Interrupt (EI) ............................................................................... 4-18
4.10 Trap Processing............................................................................................4-20
4.10.1 Trap (TRAP) ........................................................................................... 4-20
4.11 EIT Priority Levels......................................................................................... 4-22
4.12 Example of EIT Processing..........................................................................4-23
CHAPTER 5 INTERRUPT CONTROLLER (ICU)
5.1 Outline of Interrupt Controller (ICU)................................................................ 5-2
5.2 Interrupt Sources of Internal Peripheral I/Os ................................................. 5-4
5.3 ICU-Related Registers ...................................................................................... 5-6
5.3.1 Interrupt Vector Register.............................................................................5-7
5.3.2 Interrupt Mask Register .............................................................................. 5-8
5.3.3 SBI (System Break Interrupt) Control Register...........................................5-9
5.3.4 Interrupt Control Registers........................................................................5-10
5.4 ICU Vector Table ............................................................................................. 5-14
5.5 Description of Interrupt Operation ................................................................ 5-17
5.5.1 Acceptance of Internal Peripheral I/O Interrupts....................................... 5-17
5.5.2 Processing of Internal Peripheral I/O Interrupts by Handlers ................... 5-20
5.6 Description of System Break Interrupt (SBI) Operation..............................5-22
5.6.1 Acceptance of SBI .................................................................................... 5-22
5.6.2 SBI Processing by Handler.......................................................................5-22
CHAPTER 6 INTERNAL MEMORY
6.1 Outline of the Internal Memory ........................................................................ 6-2
6.2 Internal RAM......................................................................................................6-2
6.3 Internal Flash Memory......................................................................................6-2
6.4 Registers Associated with the Internal Flash Memory.................................. 6-3
6.4.1 Flash Mode Register...................................................................................6-4
6.4.2 Flash Status Registers................................................................................6-5
6.4.3 Flash Controle Registers ............................................................................ 6-8
(3)
6.4.4 Virtual Flash L Bank Registers .................................................................6-14
6.4.5 Virtual Flash S Bank Registers .................................................................6-15
6.5 Programming of the Internal Flash Memory................................................. 6-16
6.5.1 Outline of Programming Flash Memory ....................................................6-16
6.5.2 Controlling Operation Mode during Programming Flash .......................... 6-22
6.5.3 Programming Procedure to the Internal Flash Memory............................ 6-25
6.5.4 Flash Write Time (for Reference) ............................................................. 6-40
6.6 Boot ROM ........................................................................................................ 6-42
6.7 Virtual Flash Emulation Function..................................................................6-43
6.7.1 Virtual Flash Emulation Area ....................................................................6-45
6.7.2 Entering Virtual Flash Emulation Mode .................................................... 6-52
6.7.3 Application Example of Virtual Flash Emulation Mode .............................6-53
6.8 Connecting to A Serial Programmer ............................................................. 6-55
6.9 Precautions to Be Taken When Rewriting Flash Memory........................... 6-57
CHAPTER 7 RESET
7.1 Outline of Reset ................................................................................................ 7-2
7.2 Reset Operation ................................................................................................ 7-2
7.2.1 Reset at Power-on ......................................................................................7-2
7.2.2 Reset during Operation...............................................................................7-2
7.2.3 Reset Vector Relocation during Flash Rewrite ...........................................7-2
7.3 Internal State Immediately after Reset Release ............................................. 7-3
7.4 Things To Be Considered after Reset Release .............................................. 7-4
CHAPTER 8 INPUT/OUTPUT PORTS AND PIN FUNCTIONS
8.1 Outline of Input/Output Ports .......................................................................... 8-2
8.2 Selecting Pin Functions ................................................................................... 8-4
8.3 Input/Output Port Related Registers...............................................................8-6
8.3.1 Port Data Registers ....................................................................................8-8
8.3.2 Port Direction Registers............................................................................ 8-10
8.3.3 Port Operation Mode Registers ................................................................8-12
(4)
8.4 Port Peripheral Circuits..................................................................................8-31
CHAPTER 9 DMAC
9.1 Outline of the DMAC ......................................................................................... 9-2
9.2 DMAC Related Registers..................................................................................9-4
9.2.1 DMA Channel Control Register .................................................................. 9-6
9.2.2 DMA Software Request Generation Registers ......................................... 9-17
9.2.3 DMA Source Address Registers ...............................................................9-18
9.2.4 DMA Destination Address Registers ........................................................ 9-19
9.2.5 DMA Transfer Count Registers.................................................................9-20
9.2.6 DMA Interrupt Request Status Registers..................................................9-21
9.2.7 DMA Interrupt Mask Registers..................................................................9-23
9.3 Functional Description of the DMAC ............................................................ 9-27
9.3.1 Cause of DMA Request ............................................................................9-27
9.3.2 DMA Transfer Processing Procedure .......................................................9-31
9.3.3 Starting DMA ............................................................................................ 9-32
9.3.4 Channel Priority ........................................................................................9-32
9.3.5 Gaining and Releasing Control of the Internal Bus...................................9-32
9.3.6 Transfer Units ...........................................................................................9-33
9.3.7 Transfer Counts ........................................................................................9-33
9.3.8 Address Space ......................................................................................... 9-33
9.3.9 Transfer Operation....................................................................................9-33
9.3.10 End of DMA and Interrupt .......................................................................9-37
9.3.11 Status of Each Register after Completion of DMA Transfer ................... 9-37
9.4 Precautions about the DMAC ........................................................................ 9-38
CHAPTER 10 MULTIJUNCTION TIMERS
10.1 Outline of Multijunction Timers ................................................................... 10-2
10.2 Common Units of Multijunction Timer........................................................10-9
10.2.1 Timer Common Register Map.................................................................10-9
10.2.2 Prescaler Unit .......................................................................................10-12
10.2.3 Clock Bus/Input-Output Event Bus Control Unit ................................... 10-13
(5)
10.2.4 Input Processing Control Unit ...............................................................10-18
10.2.5 Output Flip-Flop Control Unit ................................................................10-26
10.2.6 Interrupt Control Unit ............................................................................10-37
10.3 TOP (Output-related 16-bit Timer) ............................................................. 10-63
10.3.1 Outline of TOP ......................................................................................10-63
10.3.2 Outline of Each Mode of TOP...............................................................10-65
10.3.3 TOP Related Register Map...................................................................10-67
10.3.4 TOP Control Registers..........................................................................10-70
10.3.5 TOP Counters (TOP0CT-TOP10CT).................................................... 10-77
10.3.6 TOP Reload Registers (TOP0RL-TOP10RL) .......................................10-78
10.3.7 TOP Correction Registers (TOP0CC-TOP10CC)................................ 10-79
10.3.8 TOP Enable Control Register ...............................................................10-80
10.3.9
10.3.10
10.3.11
10.4 TIO (Input/Output-related 16-bit Timer)................................................... 10-100
10.4.1 Outline of TIO .....................................................................................10-100
10.4.2 Outline of Each Mode of TIO ..............................................................10-102
10.4.3 TIO Related Register Map ..................................................................10-105
10.4.4 TIO Control Registers .........................................................................10-108
10.4.5 TIO Counter (TIO0CT-TIO9CT).......................................................... 10-119
10.4.6 TIO Reload 0/ Measure Register (TIO0RL0-TIO9RL0) ......................10-120
10.4.7 TIO Reload 1 Registers (TIO0RL1-TIO9RL1) ....................................10-121
10.4.8 TIO Enable Control Registers............................................................. 10-122
10.4.9 Operation in TIO Measure Free-run/Clear Input Modes .....................10-125
10.4.10 Operation in TIO Noise Processing Input Mode ................................10-129
10.4.11 Operation in TIO PWM Output Mode.................................................10-130
Operation in TOP Single-shot Output Mode (with Correction Function) ..
Operation in TOP Delayed Single-shot Output Mode (With Correction Function)
Operation in TOP Continuous Output Mode (Without Correction Function) .
10-84
10-91
10-96
10.4.12
10.4.13
10.4.14
10.5 TMS (Input-related 16-bit Timer)..............................................................10-140
10.5.1 Outline of TMS.................................................................................... 10-140
10.5.2 Outline of TMS Operation ...................................................................10-140
Operation in TIO Single-shot Output Mode (without Correction Function)..
Operation in TIO Delayed Single-shot Output Mode (without Correction Function)..
Operation in TIO Continuous Output Mode (Without Correction Function).
10-134
10-136
10-138
(6)
10.5.3 TMS Related Register Map ................................................................ 10-142
10.5.4 TMS Control Registers ....................................................................... 10-143
10.5.5 TMS Counters (TMS0CT, TMS1CT) .................................................. 10-145
10.5.6 TMS Measure Registers (TMS0MR3-0, TMS1MR3-0)....................... 10-146
10.5.7 Operation of TMS Measure Input ....................................................... 10-147
10.6 TML (Input-related 32-bit Timer) ..............................................................10-149
10.6.1 Outline of TML ....................................................................................10-149
10.6.2 Outline of TML Operation ................................................................... 10-150
10.6.3 TML Related Register Map.................................................................10-151
10.6.4 TML Control Registers........................................................................10-152
10.6.5 TML Counters .....................................................................................10-154
10.6.6 TML Measure Registers ..................................................................... 10-156
10.6.7 Operation of TML Measure Input........................................................10-158
10.7 TID (Input-related 16-bit Timer)................................................................ 10-160
10.7.1 Outline of TID......................................................................................10-160
10.7.2 TID Related Register Map ..................................................................10-162
10.7.3 TID Control &Prescaler Enable Registers .......................................... 10-163
10.7.4 TID Counters (TID0CT, TID1CT, TID2CT) .........................................10-166
10.7.5 TID Reload Registers (TID0RL, TID1RL, TID2RL)............................. 10-167
10.7.6 Outline of Each Mode of TID .............................................................. 10-168
10.8 TOD (Output-related 16-bit Timer)...........................................................10-173
10.8.1 Outline of TOD....................................................................................10-173
10.8.2 Outline of Each Mode of TOD.............................................................10-175
10.8.3 TOD Related Register Map ................................................................ 10-177
10.8.4 TOD Control Registers (TOD0CR) .....................................................10-180
10.8.5 TOD Counters.....................................................................................10-182
10.8.6 TOD Reload 0 Registers.....................................................................10-184
10.8.7 TOD Reload 1 Registers.....................................................................10-186
10.8.8 TOD Enable Protect Registers ...........................................................10-188
10.8.9 TOD Cout Enable Registers ...............................................................10-190
10.8.10 Operation in TOD PWM Output Mode ..............................................10-193
10.8.11
10.8.12
Operation in TOD Single-shot Output Mode (without Correction Function)
Operation in TOD Delayed Single-shot Output Mode (without Correction Function)
10-197
10-199
(7)
10.8.13
10.9 TOM (Output-related 16-bit Timer) .......................................................... 10-203
10.9.1 Outline of TOM ...................................................................................10-203
10.9.2 Outline of Each Mode of TOM ............................................................ 10-205
10.9.3 TOM Related Register Map ................................................................10-207
10.9.4 TOM Control Registers .......................................................................10-209
10.9.5 TOM Counters ....................................................................................10-210
10.9.6 TOM Reload 0 Registers ....................................................................10-211
10.9.7 TOM Reload 1 Registers ....................................................................10-212
10.9.8 TOM Enable Protect Registers ...........................................................10-213
10.9.9 TOM Count Enable Registers............................................................. 10-214
10.9.10 Operation in TOM PWM Output Mode...............................................10-216
Operation in TOD Continuous Output Mode (Without Correction Function) .
10-201
10.9.11
10.9.12
10.9.13
10.9.14 Example Application for Using the 32170 in Motor Control ...............10-226
Operation in TOM Single-shot Output Mode (without Correction Function)
Operation in TOM Single-shot PWM Output Mode (without Correction Function) ....
Operation in TOM Continuous Output Mode (Without Correction Function) ...
10-220
10-222
10-224
CHAPTER 11 A-D CONVERTERS
11.1 Outline of A-D Converter..............................................................................11-2
11.1.1 Conversion Modes.................................................................................. 11-6
11.1.2 Operation Modes ....................................................................................11-7
11.1.3 Special Operation Modes ..................................................................... 11-11
11.1.4 A-D Converter Interrupt and DMA Transfer Requests.......................... 11-14
11.2 A-D Converter Related Registers .............................................................. 11-15
11.2.1 A-D Single Mode Register 0 .................................................................11-19
11.2.2 A-D Single Mode Register 1 .................................................................11-23
11.2.3 A-D Scan Mode Register 0 ...................................................................11-26
11.2.4 A-D Scan Mode Register 1 ...................................................................11-30
11.2.5 A-D Successive Approximation Register ..............................................11-33
11.2.6 A-D0 Comparate Data Register............................................................. 11-35
11.2.7 10-bit A-D Data Registers..................................................................... 11-37
11.2.8 8-bit A-D Data Registers.......................................................................11-39
(8)
11.3 Functional Description of A-D Converters ............................................... 11-41
11.3.1 How to Find Along Input Voltages ........................................................ 11-41
11.3.2 A-D Conversion by Successive Approximation Method ....................... 11-42
11.3.3 Comparator Operation ..........................................................................11-44
11.3.4 Calculation of the A-D Conversion Time...............................................11-45
11.3.5 Definition of the A-D Conversion Accuracy...........................................11-48
11.4 Precautions on Using A-D Converters...................................................... 11-51
CHAPTER 12 SERIAL I/O
12.1 Outline of Serial I/O....................................................................................... 12-2
12.2 Serial I/O Related Registers ......................................................................... 12-6
12.2.1 SIO Interrupt Related Registers..............................................................12-7
12.2.2 SIO Interrupt Control Registers .............................................................. 12-9
12.2.3 SIO Transmit Control Registers............................................................ 12-16
12.2.4 SIO Transmit/Receive Mode Registers ................................................12-18
12.2.5 SIO Transmit Buffer Registers.............................................................. 12-21
12.2.6 SIO Receive Buffer Registers............................................................... 12-22
12.2.7 SIO Receive Control Registers............................................................. 12-23
12.2.8 SIO Baud Rate Registers ..................................................................... 12-26
12.3 Transmit Operation in CSIO Mode ............................................................ 12-28
12.3.1 Setting the CSIO Baud Rate.................................................................12-28
12.3.2 Initial Settings for CSIO Transmission ..................................................12-29
12.3.3 Starting CSIO Transmission .................................................................12-31
12.3.4 Successive CSIO Transmission ........................................................... 12-31
12.3.5 Processing at End of CSIO Transmission ............................................ 12-32
12.3.6 Transmit Interrupt ................................................................................. 12-32
12.3.7 Transmit DMA Transfer Request ..........................................................12-32
12.3.8 Typical CSIO Transmit Operation......................................................... 12-34
12.4 Receive Operation in CSIO Mode .............................................................. 12-36
12.4.1 Initial Settings for CSIO Reception ....................................................... 12-36
12.4.2 Starting CSIO Reception ...................................................................... 12-38
12.4.3 Processing at End of CSIO Reception..................................................12-38
(9)
12.4.4 About Successive Reception ................................................................12-39
12.4.5 Flags Indicating the Status of CSIO Receive Operation....................... 12-40
12.4.6 Typical CSIO Receive Operation.......................................................... 12-41
12.5 Precautions on Using CSIO Mode.............................................................12-43
12.6 Transmit Operation in UART Mode ........................................................... 12-45
12.6.1 Setting the UART Baud Rate................................................................ 12-45
12.6.2 UART Transmit/Receive Data Formats ................................................12-46
12.6.3 Initial Settings for UART Transmission .................................................12-48
12.6.4 Starting UART Transmission ................................................................12-50
12.6.5 Successive UART Transmission ..........................................................12-50
12.6.6 Processing at End of UART Transmission ........................................... 12-51
12.6.7 Transmit Interrupt ................................................................................. 12-51
12.6.8 Transmit DMA Transfer Request ..........................................................12-51
12.6.9 Typical UART Transmit Operation........................................................ 12-53
12.7 Receive Operation in UART Mode.............................................................12-55
12.7.1 Initial Settings for UART Reception ......................................................12-55
12.7.2 Starting UART Reception ..................................................................... 12-57
12.7.3 Processing at End of UART Reception.................................................12-57
12.7.4 Typical UART Receive Operation......................................................... 12-59
12.8 Fixed Period Clock Output Function......................................................... 12-61
12.9 Precautions on Using UART Mode............................................................ 12-62
CHAPTER 13 CAN MODULE
13.1 Outline of the CAN Module .......................................................................... 13-2
13.2 CAN Module Related Registers ................................................................... 13-4
13.2.1 CAN Control Register .............................................................................13-8
13.2.2 CAN Status Register.............................................................................13-11
13.2.3 CAN Extended ID Register ...................................................................13-15
13.2.4 CAN Configuration Register ................................................................. 13-16
13.2.5 CAN Time Stamp Count Register......................................................... 13-19
13.2.6 CAN Error Count Registers ..................................................................13-20
13.2.7 CAN Baud Rate Prescaler ....................................................................13-21
(10)
13.2.8 CAN Interrupt Related Registers .......................................................... 13-22
13.2.9 CAN Mask Registers ............................................................................ 13-30
13.2.10 CAN Message Slot Control Registers.................................................13-34
13.2.11 CAN Message Slots............................................................................13-38
13.3 CAN Protocol............................................................................................... 13-53
13.3.1 CAN Protocol Frame.............................................................................13-53
13.4 Initializing the CAN Module........................................................................ 13-56
13.4.1 Initialization of the CAN Module............................................................13-56
13.5 Transmitting Data Frames.......................................................................... 13-59
13.5.1 Data Frame Transmit Procedure .......................................................... 13-59
13.5.2 Data Frame Transmit Operation ...........................................................13-61
13.5.3 Transmit Abort Function ....................................................................... 13-62
13.6 Receiving Data Frames .............................................................................. 13-63
13.6.1 Data Frame Receive Procedure ...........................................................13-63
13.6.2 Data Frame Receive Operation ............................................................13-65
13.6.3 Reading Out Received Data Frames.................................................... 13-67
13.7 Transmitting Remote Frames .................................................................... 13-69
13.7.1 Remote Frame Transmit Procedure ..................................................... 13-69
13.7.2 Remote Frame Transmit Operation ......................................................13-71
13.7.3
13.8 Receiving Remote Frames ......................................................................... 13-76
13.8.1 Remote Frame Receive Procedure ......................................................13-76
13.8.2 Remote Frame Receive Operation .......................................................13-78
Reading Out Received Data Frames when Set for Remote Frame Transmission ..
13-74
CHAPTER 14 REAL-TIME DEBUGGER (RTD)
14.1 Outline of the Real-Time Debugger (RTD) ..................................................14-2
14.2 Pin Function of the RTD ...............................................................................14-3
14.3 Functional Description of the RTD..............................................................14-4
14.3.1 Outline of RTD Operation ....................................................................... 14-4
14.3.2 Operation of RDR (Real-time RAM Content Output) ..............................14-5
14.3.3 Operation of WRR (RAM Content Forcible Rewrite) .............................. 14-7
14.3.4 Operation of VER (Continuous Monitor) .................................................14-9
(11)
14.3.5 Operation of VEI (Interrupt Request) ....................................................14-10
14.3.6 Operation of RCV (Recover from Runaway) ........................................ 14-11
14.3.7 Method to Set a Specified Address when Using the RTD ....................14-12
14.3.8 Resetting the RTD ................................................................................14-13
14.4 Typical Connection with the Host ............................................................. 14-14
CHAPTER 15 EXTERNAL BUS INTERFACE
15.1 External Bus Interface Related Signals ...................................................... 15-2
15.2 Read/Write Operations ................................................................................. 15-6
15.3 Bus Arbitration............................................................................................15-12
15.4 Typical Connection of External Extension Memory ................................ 15-14
CHAPTER 16 WAIT CONTROLLER
16.1 Outline of the Wait Controller ...................................................................... 16-2
16.2 Wait Controller Related Registers...............................................................16-4
16.2.1 Wait Cycles Control Register.................................................................. 16-5
16.3 Typical Operation of the Wait Controller .................................................... 16-6
CHAPTER 17 RAM BACKUP MODE
17.1 Outline............................................................................................................ 17-2
17.2 Example of RAM Backup when Power is Down.........................................17-2
17.2.1 Normal Operating State ..........................................................................17-3
17.2.2 RAM Backup State .................................................................................17-4
17.3 Example of RAM Backup for Saving Power Consumption ....................... 17-5
17.3.1 Normal Operating State ..........................................................................17-6
17.3.2 RAM Backup State .................................................................................17-7
17.3.3 Precautions to Be Observed at Power-on ..............................................17-8
17.4 Exiting RAM Backup Mode (Wakeup) ......................................................... 17-9
(12)
CHAPTER 18 OSCILLATION CIRCUIT
18.1 Oscillator Circuit ........................................................................................... 18-2
18.1.1 Example of an Oscillator Circuit..............................................................18-2
18.1.2 System Clock Output Function ...............................................................18-3
18.1.3 Oscillation Stabilization Time at Power-on ............................................. 18-4
18.2 Clock Generator Circuit................................................................................ 18-5
CHAPTER 19 JTAG
19.1 Outline of JTAG............................................................................................. 19-2
19.2 Configuration of the JTAG Circuit............................................................... 19-3
19.3 JTAG Registers .............................................................................................19-4
19.3.1 Instruction Register (JTAGIR).................................................................19-4
19.3.2 Data Registers ........................................................................................19-5
19.4 Basic Operation of JTAG ............................................................................. 19-6
19.4.1 Outline of JTAG Operation ..................................................................... 19-6
19.4.2 IR Path Sequence...................................................................................19-8
19.4.3 DR Path Sequence ...............................................................................19-10
19.4.4 Examining and Setting Data Registers .................................................19-12
19.5 Boundary Scan Description Language.....................................................19-14
19.6 Precautions about Board Design when Connecting JTAG..................... 19-34
CHAPTER 20 POWER-UP/POWER-SHUTDOWN SEQUENCE
20.1 Configuration of the Power Supply Circuit ................................................ 20-2
20.2 Power-On Sequence .....................................................................................20-3
20.2.1 Power-On Sequence When Not Using RAM Backup .............................20-3
20.2.2 Power-On Sequence When Using RAM Backup.................................... 20-4
20.3 Power-Shutdown Sequence......................................................................... 20-5
20.3.1 Power-Shutdown Sequence When Not Using RAM Backup ..................20-5
20.3.2 Power-Shutdown Sequence When Using RAM Backup.........................20-6
(13)
CHAPTER 21 ELECTRICAL CHARACTERISTICS
21.1 Absolute Maximum Ratings.........................................................................21-2
21.2 Recommended Operating Conditions ........................................................ 21-3
21.3 DC Characteristics........................................................................................21-5
21.3.1 Electrical Characteristics ........................................................................21-5
21.3.2 Flash Related Electrical Characteristics ...............................................21-10
21.4 A-D Conversion Characteristics................................................................21-11
21.5 AC Characteristics......................................................................................21-12
21.5.1 Timing Requirements............................................................................21-12
21.5.2 Switching Characteristics......................................................................21-15
21.5.3 AC Characteristics ................................................................................21-18
CHAPTER 22 TYPICAL CHARACTERISTICS
22.1 A-D Conversion Characteristics..................................................................22-2
APPENDIX 1 MECHANICAL SPECIFICATIONS
Appendix 1.1 Dimensional Outline Drawing....................................... Appendix 1-2
APPENDIX 2 INSTRUCTION PROCESSING TIME
Appendix 2.1 32170 Instruction Processing Time ............................. Appendix 2-2
APPENDIX 3 PRECAUTIONS ABOUT NOISE
Appendix 3.1 Precautions about Noise .............................................. Appendix 3-2
Appendix 3.1.1 Reduction of Wiring Length ........................................Appendix 3-2
Appendix 3.1.2
Appendix 3.1.3 Processing Analog Input Pin Wiring ...........................Appendix 3-5
Inserting a Bypass Capacitor between VSS and VCC Lines ......
Appendix 3-4
Appendix 3.1.4 Consideration about the Oscillator..............................Appendix 3-6
Appendix 3.1.5 Processing Input/Output Ports.................................... Appendix 3-8
(14)
CHAPTER 1CHAPTER 1
OVERVIEW
1.1 Outline of the 32170
1.2 Block Diagram
1.3 Pin Function
1.4 Pin Layout
1
1.1 Outline of the 32170
1.1.1 M32R Family CPU Core
(1) Based on RISC architecture
• The 32170 is a 32-bit RISC single-chip microcomputer which is built around the M32R family
CPU core (hereafter referred to as the M32R) and incorporates flash memory, RAM, and
various other peripheral functions-all integrated into a single chip.
• The M32R is based on RISC architecture. Memory access is performed using load and store
instructions, and various arithmetic operations are executed using register-to-register
operation instructions. The M32R internally contains sixteen 32-bit general-purpose registers
and has 83 distinct instructions.
• The M32R supports compound instructions such as Load & Address Update and Store &
Address Update, in addition to ordinary load and store instructions. These compound
instructions help to speed up data transfers.
OVERVIEW
1.1 Outline of the 32170
(2) 5-stage pipelined processing
• The M32R uses 5-stage pipelined instruction processing consisting of Instruction Fetch,
Decode, Execute, Memory Access, and Write Back. Not just load and store instructions or
register-to-register operation instructions, compound instructions such as Load & Address
Update and Store & Address Update also are executed in one cycle.
• Instructions are entered into the execution stage in the order they are fetched, but this does not
always mean that the first instruction entered is executed first. If the execution of a load or
store instruction entered earlier is delayed by one or more wait cycles inserted in memory
access, a register-to-register operation instruction entered later may be executed before said
load or store instruction. By using "out-of-order-completion" like this, the M32R controls
instruction execution without wasting clock cycles.
(3) Compact instruction code
• The M32R instructions come in two types: one consisting of 16 bits in length, and the other
consisting of 32 bits in length. Use of the 16-bit length instruction format especially helps to
suppress the program code size.
• Some 32-bit long instructions can branch directly to a location 32 Mbytes forward or backward
from the instruction address being executed. Compared to architectures where address space
is segmented, this direct jump allows for easy programming.
1-2 Ver.0.10
1
1.1.2 Built-in Multiply-Accumulate Operation Function
(1) Built-in high-speed multiplier
• The M32R incorporates a 32-bit × 16-bit high-speed multiplier which enables it to execute a
32-bit × 32-bit integral multiplication instruction in three cycles (1 cycle = 25 ns when using a 40
MHz internal CPU clock).
(2) Supports Multiply-Accumulate operation instructions comparable to DSP
• The M32R supports the following four modes of Multiply-Accumulate operation instructions (or
multiplication instructions) using a 56-bit accumulator. Any of these operations can be
executed in one cycle.
➀ 16 high-order register bits × 16 high-order register bits
➁ 16 low-order register bits × 16 low-order register bits
➂ Entire 32 register bits × 16 high-order register bits
➃ Entire 32 register bits × 16 low-order register bits
OVERVIEW
1.1 Outline of the 32170
• The M32R has instructions to round off the value stored in the accumulator to 16 or 32 bits, as
well as instructions to shift the accumulator value to adjust digits and store the digit-adjusted
value in a register. These instructions also can be executed in one cycle, so that when
combined with high-speed data transfer instructions such as Load & Address Update and
Store & Address Update, they enable the M32R to exhibit high data processing capability
comparable to that of DSP.
1.1.3 Built-in Flash Memory and RAM
• The 32170 contains flash memory and RAM which can be accessed with no wait states,
allowing you to build a high-speed embedded system.
• The internal flash memory allows for on-board programming (you can write to it while being
mounted on the printed circuit board). Use of flash memory means the chip engineered at the
development phase can be used directly in mass-production, so that you can smoothly
migrate from prototype to mass-production without changing the printed circuit board.
• The internal flash memory can be rewritten 100 times.
• The internal flash memory has a pseudo-flash emulation function, allowing the internal RAM to
be artificially mapped into part of the internal flash memory. This function, when combined with
the internal Real-Time Debugger (RTD), facilitates data tuning on ROM tables.
• The internal RAM can be accessed for read or rewrite from an external device independently
of the M32R by using RTD (real-time debugger). It is communicated with external devices by
RTD's exclusive clock-synchronized serial I/O.
1-3 Ver.0.10
1
1.1.4 Built-in Clock Frequency Multiplier
• The 32170 internally multiplies the input clock signal frequency by 4 and the internal peripheral
clock by 2. If the input clock frequency is 10.0 MHz, the CPU clock frequency will be 40 MHz
and the internal clock frequency 20 MHz.
1.1.5 Built-in Powerful Peripheral Functions
(1) Built-in multijunction timer (MJT)
• The multijunction timer is configured with the following timers:
➀ 16-bit output-related timer × 35 channels
➁ 16-bit input/output-related timer × 10 channels
➂ 16-bit input-related timer × 11 channels (incorporating three channels of multiply-by-4
counter)
32-bit input-related timer × 8 channels
➃
OVERVIEW
1.1 Outline of the 32170
Each timer has multiple modes of operation, which can be selected according of the purpose of use.
• The multijunction timer has internal clock bus, input event bus, and output event bus, allowing
multiple timers to be combined for use internally. This provides a flexible way to make use of
timer functions.
• The output-related timers (TOP) have a correction function. This function allows the timer's
count value in progress to be increased or reduced as desired, thus materializing real-time
output control.
(2) Built-in 10-channel DMA
• The 10-channel DMA is built-in, supporting data transfers between internal peripheral I/Os or
between internal peripheral I/O and internal RAM. Not only can DMA transfer requests be
generated in software, but can also be triggered by a signal generated by an internal
peripheral I/O (e.g., A-D converter, MJT, or serial I/O).
• Cascaded connection between DMA channels (DMA transfer in a channel is started by
completion of transfer in another) is also supported, allowing for high-speed transfer
processing without imposing any extra load on the CPU.
(3) Built-in 16-channel A-D converters
• The 32170 contains two 16-channel A-D converters which can convert data in 10-bit
resolution. In addition to single A-D conversion in each channel, successive A-D conversion in
four, eight, or 16 channels combined into one unit is possible.
• In addition to ordinary A-D conversion, a comparator mode is supported in which the A-D
conversion result is compared with a given set value to determine the relative magnitudes of
two quantities.
• When A-D conversion is completed, the 32170 can generate not only an interrupt, but can also
generate a DMA transfer request.
• The 32170 supports two read out modes, so that A-D conversion results can be read out in 8
bits or 10 bits.
1-4 Ver.0.10
1
(4) High-speed serial I/O
• The 32170 incorporates 6 channels of serial I/O, which can be set for clock-synchronized
serial I/O or UART.
• When set for clock-synchronized serial I/O, the data transfer rate is a high 2 Mbits per second.
• When data reception is completed or the transmit buffer becomes empty, the serial I/O can
generate a DMA transfer request signal.
(5) Built-in Real-Time Debugger (RTD)
• The Real-Time Debugger (RTD) provides a function for the M32R/E's internal RAM to be
accessed directly from an external device. The debugger communicates with external devices
through its exclusive clock-synchronized serial I/O.
• By using the RTD, you can read the contents of the internal RAM or rewrite its data from an
external device independently of the M32R.
• The debugger can generate an RTD interrupt to notify that RTD-based data transmission or
reception is completed.
OVERVIEW
1.1 Outline of the 32170
(6) Eight-level interrupt controller
• The interrupt controller manages interrupt requests from each internal peripheral I/O by
resolving interrupt priority in eight levels including an interrupt-disabled state. Also, it can
accept external interrupt requests due to power-down detection or generated by a watchdog
timer as a System Break Interrupt (SBI).
(7) Three operation modes
• The M32R/E has three operation modes-single-chip mode, extended external mode, and
processor mode. The address space and external pin functions of the M32R/E are switched
over according to a mode in which it operates. The MOD0 and MOD1 pins are used to set a
mode.
(8) Wait controller
• The wait controller supports access to external devices by the M32R. In all but single-chip
mode, the extended external area provides 4 Mbytes of space.
1-5 Ver.0.10
1
1.1.6 Built-in Full-CAN Function
• The 32170 contains CAN Specification V2.0B-compliant CAN module, thereby providing 16
message slots.
1.1.7 Built-in Debug Function
• The 32170 supports JTAG interface. Boundary scan test can be performed using this JTAG
interface.
OVERVIEW
1.1 Outline of the 32170
1-6 Ver.0.10
1
1.2 Block Diagram
1.2 Block Diagram
Figure 1.2.1 shows a block diagram of the 32170. Features of each block are shown in Tables 1.2.1
through 1.2.3.
32170
OVERVIEW
M32R CPU core
(max 40MHz)
Multiplier-
accumulator
(32 X 16 + 56)
Internal flash memory
(M32170F6:768KB)
(M32170F4:512KB)
(M32170F3:384KB)
Internal RAM
(M32170F6:40KB)
(M32170F4:32KB)
(M32170F3:32KB)
Internal bus interface
(10-bit resolution, 16 channels) x 2
bus
Internal 32-bit
Internal 16-bit bus
DMAC
(10 channels)
Multijunction timer
(MJT: 64 channels)
A-D converter
Serial I/O
(6 channels)
Interrupt controller
(31 sources, 8 levels)
Wait controller
Real-time debugger (RTD)
PLL clock generator circuit
Figure 1.2.1 Block Diagram of the 32170
Full CAN
(1 channel)
External bus
interface
AddressData
Input/output port (JTAG), 157 lines
1-7 Ver.0.10
1
Table 1.2.1 Features of the M32R Family CPU Core
Functional Block Features
M32R family • Bus specifications
CPU core Basic bus cycle: 25 ns (when operating with 40 MHz CPU clock)
Logical address space: 4Gbytes, linear
Extended external area: Maximum 4 Mbytes
External data bus: 16 bits
• Implementation: Five-stage pipeline
• Internal 32-bit architecture for the core
• Register configuration
General-purpose register: 32 bits × 16 registers
Control register: 32 bits × 5 registers
• Instruction set
16-bit and 32-bit instruction formats
83 distinct instructions and 9 addressing modes
• Built-in multiplier/accumulator (32 × 16 + 56)
OVERVIEW
1.2 Block Diagram
Table 1.2.2 Features of Internal Memory
Functional Block Features
RAM • Capacity
M32170F6 : 40 Kbytes
M32170F4, M32170F3 : 32 Kbytes
• No-wait access (when operating with 40 MHz CPU clock)
• By using RTD (real-time debugger), the internal RAM can be accessed for read or
rewrite from external devices independently of the M32R.
Flash memory • Capacity
M32170F6 : 768 Kbytes
M32170F4 : 512 Kbytes
M32170F3 : 384 Kbytes
• No-wait access (when operating with 40 MHz CPU clock)
• Durability: Can be rewritten 100 times
1-8 Ver.0.10
1
Table 1.2.3 Features of Internal Peripheral I/O
Functional Block Features
DMA • 10-channel DMA
• Supports transfer between internal peripheral I/Os and between internal peripheral I/O
and internal RAM.
• Capable of advanced DMA transfer when operating in combination with internal
peripheral I/O
• Capable of cascaded connection between DMA channels (DMA transfer in a channel
is started by completion of transfer in another)
Multijunction • 64-channel multifunction timer
• Contains output-related timer × 35 channels, input/output-related timer × 10 channels,
16-bit input-related timer × 11 channels, and 32-bit input-related timer × 8 channels.
• Capable of flexible timer configuration by mutual connection between each channel.
OVERVIEW
1.2 Block Diagram
A-D converter • 16-channel, 10-bit resolution A-D converter × 2 units
• Incorporates comparator mode
•
Can generate interrupt or start DMA transfer upon completion of A-D conversion.
• Can read out conversion results in 8 or 10 bits.
Serial I/O • 6-channel serial I/O
• Can be set for clock-synchronized serial I/O or UART.
• Capable of high-speed data transfer at 2 Mbits per second when clock synchronized or
156 Kbits per second during UART.
Real-time debugger • Can rewrite or monitor the internal RAM independently of the CPU by command input
from an external source.
• Has its exclusive clock-synchronized serial port.
Interrupt controller • Accepts and manages interrupt requests from internal peripheral I/O.
• Resolves interrupt priority in 8 levels including interrupt-disabled state.
Wait controller • Controls wait state for access to extended external areas.
• Can insert 1 to 4 wait cycles by setting in software and extend wait period by external
WAIT signal.
Clock PLL • Multiply-by-4 clock generator circuit
• Maximum 40 MHz of CPU clock (CPU, internal ROM, internal RAM access)
• Maximum 20 MHz of internal peripheral clock (peripheral module access)
• Maximum external input clock frequency=10 MHz
CAN • Sixteen message slots
JTAG • Capable of boundary scan
1-9 Ver.0.10
1
1.3 Pin Function
Figure 1.3.1 shows a pin function diagram of the 32170 in 240QFP package. Figure 1.3.2
shows a pin function diagram of the 32170 in 255FBGA package. Table 1.3.1 explains the
function of each pin of the 32170. Table 1.3.2 explains the function of the dedicated debug pins
of the 32170 in 255FBGA package.
OVERVIEW
1.3 Pin Function
Port 7
Port 22
Port 19
Port 17
Port 15
Port 14
Port 13
Port 12
Port 21
Port 18
Port 16
Port 11
Port 10
Port 9
Port 6
Port 6
Clock
Reset
Mode
CAN
Multi-
junction
timer
A-D
converter
Port 22
Interrupt
controller
XIN
XOUT
VCNT
OSC-VCC
OSC-VSS
P70/BCLK/WR
RESET
MOD0
MOD1
FP
P220/CTX
P221/CRX
P190 – P197/TIN26 – TIN33
P172, P173/TIN24, TIN25
P150 – P157/TIN0 – TIN7
– P147/TIN8 – TIN15
P140
P130 – P137/TIN16 – TIN23
P124 – P127/
TCLK0 – TCLK 3
-P217/TO37-TO44
P210
P180-P187/TO29 -TO36
-P167/TO21-TO28
P160
P110-P117/TO0- TO7
-P107/TO8-TO15
P100
P93-P97/TO16 -TO20
– AD0IN15
AD0IN0
AD1IN0
– AD1IN15
P67/ADTRG
AVCC0, AVCC1
AVSS0, AVSS1
AVREF0, AVREF1
P61-P63Port 6
P222, P223
P64/SBI
VCCE
P45/CS1
P44/CS0
3.3V
34
4
45
5V
16
16
2
2
2
3
7
5V
M32170F6VFP , M32170F4VFP , M32170F3VFP
P43/RD
P42/BHW/BHE
P41/BLW/BLE
P71/WAIT
P72/HREQ
P73/HACK
P224/A11(Note2)
P225/A12(Note2)
20
P20 – P27/A23 – A30
P30 – P37/A15 – A22
P46, P47/A13, A14
16
– P07/DB0 – DB7
P00
P10 – P17/DB8 – DB15
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
P174/TXD2
P175/RXD2
P176/TXD3
P177/RXD3
P200/TXD4
P201/RXD4
P202/TXD5
P203/RXD5
P65/SCLKI4/SCLKO4
P66/SCLKI5/SCLKO5
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK
JTMS
JTCK
JTRST
JTDO
JTDI
Bus
control
Address
bus
Data
bus
Serial
I/O
Real-time
debugger
JTAG
Port 4
Port 7
Port 22
Port 2
Port 3
Port 4
Port 0
Port 1
Port 6
Port 8
Port 17
Port 20
Port 7
6
3.3V
Note1.
VCCI
:
3.3V
5V
denotes blocks operating with a 3.3 V power supply.
: denotes blocks operating with a 5 V power supply.
Note2. Use caution when using this port because it has a debug event function.
Figure 1.3.1 Pin Function Diagram of 240QFP
1-10 Ver.0.10
VSS
VDD
3.3V
16
FVCC
1
OVERVIEW
1.3 Pin Function
Port 7
Port 22
Port 19
Port 17
Port 15
Port 14
Port 13
Port 12
Port 21
Port 18
Port 16
Port 11
Port 10
Port 9
Port 6
Port 6
Clock
Reset
Mode
CAN
Multi-
junction
timer
A-D
converter
Port 22
Interrupt
controller
DBGUG
XIN
XOUT
VCNT
OSC-VCC
OSC-VSS
P70/BCLK/WR
RESET
MOD0
MOD1
FP
P220/CTX
P221/CRX
P190–P197/TIN26–TIN33
P172, P173/TIN24, TIN25
–
P157/TIN0–TIN7
P150
P140
–
P147/TIN8–TIN15
–
P137/TIN16–TIN23
P130
P124–P127/
TCLK0
–
TCLK 3
–
P217/TO37–TO44
P210
–
P187/TO29–TO36
P180
–
P167/TO21–TO28
P160
P110
–
P117/TO0–TO7
–
P107/TO8–TO15
P100
–
P97/TO16–TO20
P93
–
AD0IN15
AD0IN0
AD1IN0
–
AD1IN15
P67/ADTRG
AVCC0, AVCC1
AVSS0, AVSS1
AVREF0, AVREF1
P61–P63Port 6
P222, P223
P64/SBI
TRCLK
TRSYNC
TRDATA
JDBI
JEVENTO
JEVENT1
VCCE
VCCI
P45/CS1
P44/CS0
20
16
5V
P43/RD
P42/BHW/BHE
P41/BLW/BLE
P71/WAIT
P72/HREQ
P73/HACK
P224/A11 (Note2)
P225/A12 (Note2)
P20–P27/A23–A30
–
P37/A15–A22
P30
P46, P47/A13, A14
–
P07/DB0–DB7
P00
P10
–
P17/DB8–DB15
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
P174/TXD2
P175/RXD2
P176/TXD3
P177/RXD3
P200/TXD4
P201/RXD4
P202/TXD5
P203/RXD5
P65/SCLKI4/SCLKO4
P66/SCLKI5/SCLKO5
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK
JTMS
JTCK
JTRST
JTDO
JTDI
VDD
FVCC
Bus
control
Address
bus
Data
bus
Serial
I/O
Real-time
debugger
JTAG
3.3V
34
4
45
5V
VWG
16
16
2
2
2
3
8
7
6
M32170F6VWG , M32170F4VWG , M32170F3
3.3V
3.3V
Port 4
Port 7
Port 22
Port 2
Port 3
Port 4
Port 0
Port 1
Port 6
Port 8
Port17
Port 20
Port 7
VSS
Note1.
Note2.
Note3.
3.3V
Use caution when using this port because it has a debug event function.
255FBGA is currently under development.
denotes blocks operating with a 3.3 V power supply
:
:
5V
denotes blocks operating with a 5 V power supply.
Figure 1.3.2 Pin Function Diagram of 255FBGA
1-11 Ver.0.10
16
1
Table 1.3.1 Description of the 32170 Pin Function (1/6)
OVERVIEW
1.3 Pin Function
Type Pin Name Signal Name
Power VCCE Power supply — Power supply to external I/O ports (5 V).
supply
Clock XIN, Clock Input Clock input/output pins. These pins contains a PLL-based
VCCI Power supply — Power supply to internal logic (3.3 V).
VDD
FVCC
VSS Ground — Connect all VSS to ground (GND).
XOUT Output frequency multiplier circuit. Apply a clock whose frequency
BCLK/WR System clock Output This pin outputs a clock whose frequency is twice that of
OSC-VCC Power supply — Power supply for PLL circuit. Connect OSC-VCC to the
RAM power supply
FLASH power supply
Input/Output
— Power supply for internal RAM backup (3.3 V).
— Power supply for internal flash memory (3.3 V).
Function
is 1/4 the operating frequency. (When using 40 MHz CPU
clock, XIN input = 10.0 MHz)
external input clock. (When using 10 MHz external input
clock, BCLK output = 20 MHz). Use this output when
external operation needs to be synchronized.
power supply rail.
OSC-VSS Ground —
VCNT PLL control Input This pin controls the PLL circuit. Connect a resistor and
Reset RESET Reset Input This pin resets the internal circuit.
Mode MOD0 Mode Input These pins set operation mode.
MOD1 MOD0 MOD1 Mode
Address A11 – A30 Address Output The device has 20 address lines (A11-A30) to allow two
Bus Bus channels of up to 2 MB of memory space to be added
Note: For boot mode, refer to Chapter 6, "Internal Memory."
Connect OSC-VSS to ground.
capacitor to it. (For external circuits, refer to Section 18.1.1,
"Example of an Oscillator Circuit.")
0 0 Single-chip mode
0 1 Extended external mode
1 0 Processor mode
0 0 (Boot mode) (Note)
1 1 (Reserved)
external to the chip. A31 is not output.
1-12 Ver.0.10
1
Table 1.3.1 Description of the 32170 Pin Function (2/6)
OVERVIEW
1.3 Pin Function
Type Pin Name Signal Name
Data DB0-DB15 Data bus
bus
Bus
control
___
CS0, Chip select Output These pins comprise external device chip select signal. For
___
CS1 areas for which a chip select signal is output, refer to
__
RD Read Output This signal is output when reading an external device.
___ ___
BHW/BHE Byte high Output Indicates the byte position to which valid data is transferred
write/enable
___
___
BLW/BLE Byte low Output
write/enable corresponds to the lower address (D8-D15 is valid).
____
WAIT Wait Input When the M32R accesses an external device, a low on this
____
HREQ Hold request Input This pin is used by an external device to request control of
Multijunction
timer
____
HACK Hold Output This signal is used to notify that the M32R has entered a
acknowledge hold state and relinquished control of the external bus.
Input/Output
Input/Output
Function
These pins comprise 16-bit data bus to connect external devices. In write
cycles, the valid byte positions to be written on the 16-bit data bus are
output as BHW/BHE and BLW/BLE. In read cycles, data is always read
from the 16-bit data bus. However, when transferring to the internal circuit
of the M32R, only data at the valid byte positions are transferred.
Chapter 3, "Address Space."
when writing to an external device. BHW/BHE corresponds
___ ___
___
___
to the upper address (D0-D7 is valid); BLW/BLE
____
WAIT input extends the wait cycle.
the external bus. A low on this HREQ input causes the
____
M32R to enter a hold state.
TIN 0–TIN 33
TO 0– TO 44
TCLK 0– TCLK 3
A-D AVCC0,
converter
AVCC1 is the power supply for the A-D1 converter. Connect AVCC0
AVSS0,
AVSS1 — analog ground for the A-D1 converter. Connect AVSS0 and
AD0IN0
– AD0IN15
AD1IN0 16-channel analog input pins for the A-D1 converter.
– AD1IN15
Timer input Input Input pins for multijunction timer.
Timer output Output Output pins for the multijunction timer.
Timer clock Input Clock input pins for the multijunction timer.
Analog power supply
— AVCC0 is the power supply for the A-D0 converter. AVCC1
and 1 to the power supply rail.
Analog ground — AVSS0 is analog ground for the A-D0 converter. AVSS1 is
1 to the ground.
Analog input Input 16-channel analog input pins for the A-D0 converter.
1-13 Ver.0.10
1
Table 1.3.1 Description of the 32170 Pin Function (3/6)
OVERVIEW
1.3 Pin Function
Type Pin Name Signal Name
A-D VREF0, Reference Input
converter
Interrupt
controller interrupt controller
Serial I/O SCLKI0 /
VREF1 voltage input
_____
ADTRG Conversion Input Hardware trigger input pin to start A-D conversion.
trigger
___
SBI System break Input System break interrupt (SBI) input pin for the interrupt
UART transmit/
SCLKO0
SCLKI1 /
SCLKO1
receive clock
output
or
transmit/receive
clock input/output
UART transmit/
receive clock
output
or
transmit/receive
clock input/output
CSIO
CSIO
Input/Output
Input/output
Input/output
Function
VREF0 is the reference voltage input pin for the A-D0 converter.
VREF1 is the reference voltage input pin for the A-D1 converter.
When channel 0 is in UART mode:
This pin outputs a clock derived from BRG output by halving it
When channel 0 is in CSIO mode:
This pin accepts as its input a transmit/receive clock when external clock
source is selected or outputs a transmit/receive clock when internal clock
source is selected.
When channel 1 is in UART mode:
This pin outputs a clock derived from BRG output by halving it
When channel 1 is in CSIO mode:
This pin accepts as its input a transmit/receive clock when external clock
source is selected or outputs a transmit/receive clock when internal clock
source is selected.
.
.
SCLKI4 /
SCLKO4
SCLKI5 /
SCLKO5
TXD0 Transmit data output Transmit data output pin for serial I/O channel 0
RXD0 Receive data Input Receive data input pin for serial I/O channel 0
UART transmit/
receive clock
output
or
transmit/receive
clock input/output
UART transmit/
receive clock
output
or
transmit/receive
clock input/output
Input/output
CSIO
Input/output
CSIO
When channel 4 is in UART mode:
This pin outputs a clock derived from BRG output by halving it
When channel 4 is in CSIO mode:
This pin accepts as its input a transmit/receive clock when external clock
source is selected or outputs a transmit/receive clock when internal clock
source is selected.
When channel 5 is in UART mode:
This pin outputs a clock derived from BRG output by halving it
When channel 5 is in CSIO mode:
This pin accepts as its input a transmit/receive clock when external clock
source is selected or outputs a transmit/receive clock when internal clock
source is selected.
.
.
1-14 Ver.0.10
1
Table 1.3.1 Description of the 32170 Pin Function (4/6)
OVERVIEW
1.3 Pin Function
Type Pin Name Signal Name
TXD1 Transmit data Output Transmit data output pin for serial I/O channel 1.
RXD1 Receive data Input Receive data input pin for serial I/O channel 1.
TXD2 Transmit data Output Transmit data output pin for serial I/O channel 2.
RXD2 Receive data Input Receive data input pin for serial I/O channel 2.
TXD3 Transmit data Output Transmit data output pin for serial I/O channel 3.
RXD3 Receive data Input Receive data input pin for serial I/O channel 3.
TXD4 Transmit data Output Transmit data output pin for serial I/O channel 4.
RXD4 Receive data Input Receive data input pin for serial I/O channel 4.
TXD5 Transmit data Output Transmit data output pin for serial I/O channel 5.
RXD5 Receive data Input Receive data input pin for serial I/O channel 5.
Real-time
debugger
RTDTXD Transmit data Output Serial data output pin for the real-time debugger.
RTDRXD Receive data Input Serial data input pin for the real-time debugger.
RTDCLK Clock input Input Serial data transmit/receive clock input pin for the
Input/Output
Function
real-time debugger.
RTDACK Acknowledge Output
Flash FP Flash Protect Input This mode pin has a function to protect the flash
-only memory against E/W in hardware.
CAN CTX Data output Output This pin outputs data from the CAN module.
CRX Data input Input This pin is used to input data to the CAN module.
JTAG JTMS Test mode Input Test mode select input to control state transition of the
JTCK clock Input Clock input for the debug module and test circuit.
JTRST Test reset Input Test reset input to initialize the test circuit
JTDI Serial input Input This pin is used to input test instruction code or test
This pin outputs a low pulse synchronously with the beginning
clock of the real-time debugger's serial data output word. The
duration of this low pulse indicates the type of command/data
that the real-time debugger has received.
test circuit.
asynchronously.
data serially.
JTDO Serial output Output This pin outputs test instruction code or test data
serially.
1-15 Ver.0.10
1
Table 1.3.1 Description of the 32170 Pin Function (5/6)
OVERVIEW
1.3 Pin Function
Type Pin Name Signal Name
Input/
output
port
(Note)
P00 – P07 Input/output
port 0
P10 – P17 Input/output
port 1
P20 – P27 Input/output
port 2
P30 – P37 Input/output
port 3
P41 – P47 Input/output
port 4
P61 – P67 Input/output
port 6 (However, P64 is an input-only port.)
P70 – P77 Input/output
port 7
P82 – P87 Input/output
port 8
Input/Output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Function
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
P93 – P97 Input/output
port 9
P100 Input/output
– P107 port 10
P110 Input/output
– P117 port 11
P124 Input/output
– P127 port 12
P130 Input/output
– P137 port 13
P140 Input/output
– P147 port 14
P150 Input/output
– P157 port 15
P160 Input/output
– P167 port 16
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Note: Input/output port 5 is reserved for future use.
1-16 Ver.0.10
1
Table 1.3.1 Description of the 32170 Pin Function (6/6)
OVERVIEW
1.3 Pin Function
Type Pin Name Signal Name
Input/
output
port
Note: Use caution when using P224 and P225 because they have a debug event function.
P172 Input/output
– P177 port 17
P180 Input/output
– P187 port 18
P190 Input/output
– P197 port 19
P200 Input/output
– P203 port 20
P210 Input/output
– P217 port 21
P220 Input/output
– P225 port 22 (However, P221 is an input only port.)
Input/Output
Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Function
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port.
Programmable input/output port. (Note)
Table 1.3.2 Description of the Debug-only Pin Function of 255FBGA
Type Pin Name Signal Name
DEBOG JDBI
JEVENT0, Event output Output Output synchronously with TRCLK. When an event occurs,
JEVENT1 this output is driven high for a 1 TRCLK period.
TRCLK Trace clock Output Clock output pin for trace operation. Trace data is output
TRSYNC
TRDATA0
-
TRDATA7
Note: 255FBGA is currently under development.
Debug interrupt
request requests a debug interrupt.
output synchronously with this clock.
Trace packet
output start signal
Trace packet Output Trace packet output pin.
output
Input/Output
Input Debug interrupt request input pin. A low on this input
Output This is a trace packet output start signal. When the device
Function
starts outputting a trace packet, this signal is driven high for
a 1 TRCLK period.
1-17 Ver.0.10
1
1.4 Pin Layout
Figure 1.4.1 shows a pin layout diagram of the 32170 in 240QFP package. Figure 1.4.2 shows
a pin layout diagram of the 32170 in 255FBGA package. Table 1.4.1 lists pin assignments of the
240QFP. Table 1.4.2 lists pin assignments of the 255FBGA.
VCCI
P102/TO10
P216/TO43
P215/TO42
P214/TO41
P217/TO44
P211/TO38
P213/TO40
P212/TO39
VSS
P210/TO37
VDD
P100/TO8
P117/TO7
P101/TO9
P114/TO4
P116/TO6
P115/TO5
P113/TO3
P112/TO2
P111/TO1
VSS
VCCE
P110/TO0
P96/TO19
P76/RTDACK
P93/TO16
P97/TO20
RESET
FP
MOD0
MOD1
P95/TO18
P94/TO17
P75/RTDRXD
P77/RTDCLK
P74/RTDTXD
P73/ HACK
P72/ HREQ
P70/BCLK/WR
P71/WAIT
VCCE
VSS
VCCI
P64/SBI
P61
P65/SCLKI4/SCLKO4
P62
P63
P67/ADTRG
P66/SCLKI5/SCLKO5
VSS
FVCC
VSS
VCCI
P201/RXD4
P202/TXD5
P203/RXD5
P200/TXD4
P87/SCLKI1/SCLKO1
OVERVIEW
1.4 Pin Layout
JTMS
JTCK
JTRST
JTDO
JTDI
P103/TO11
P104/TO12
P105/TO13
P106/TO14
P107/TO15
P124/TCLK0
P125/TCLK1
P126/TCLK2
P127/TCLK3
VCCI
VSS
P130/TIN16
P131/TIN17
P132/TIN18
P133/TIN19
P134/TIN20
P135/TIN21
P136/TIN22
P137/TIN23
VCCE
VSS
P140/TIN8
P141/TIN9
P142/TIN10
P143/TIN11
P144/TIN12
P145/TIN13
P146/TIN14
P147/TIN15
P150/TIN0
P151/TIN1
P152/TIN2
P153/TIN3
P154/TIN4
P155/TIN5
P156/TIN6
P157/TIN7
P41/BLW/BLE
P42/BHW/BHE
VCCI
VSS
VREF1
AVCC1
AD1IN0
AD1IN1
AD1IN2
AD1IN3
AD1IN4
AD1IN5
AD1IN6
AD1IN7
AD1IN8
AD1IN9
AD1IN10
AD1IN11
172
169
177
179
178
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
4
3
2
1
171
174
173
176
175
9
8
7
5
6
166
168
170
10
11
163
165
167
164
14
181920
15
12
13
16
17
156
158
161
155
160
157
162
159
M32170F3VFP
M32170F4VFP
M32170F6VFP
25
22
23
26
21
24
148
153
150
145
147
152
154
151
30
28
29
27
144
149
146
33
36
31
34
37
32
35
137
143
140
142
136
138
139
141
44
41
39
45
42
43
40
38
129
134
128
131
130
133
135
132
49
50
51
47
48
52
46
123
124
122
127
126
125
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
55
60
58
53
56
59
57
54
P86/RXD1
P85/TXD1
P84/SCLKI0/SCLKO0
P83/RXD0
P82/TXD0
VSS
VCCE
P177/RXD3
P176/TXD3
P175/RXD2
P174/TXD2
P173/TIN25
P172/TIN24
P167/TO28
P166/TO27
P165/TO26
P164/TO25
P163/TO24
P162/TO23
P161/TO22
P160/TO21
VSS
VCCI
P197/TIN33
P196/TIN32
P195/TIN31
P194/TIN30
P193/TIN29
P192/TIN28
P191/TIN27
P190/TIN26
P187/TO36
P186/TO35
P185/TO34
P184/TO33
P183/TO32
P182/TO31
P181/TO30
P180/TO29
VSS
VCCE
AVSS0
AD0IN15
AD0IN14
AD0IN13
AD0IN12
AD0IN11
AD0IN10
AD0IN9
AD0IN8
AD0IN7
AD0IN6
AD0IN5
AD0IN4
AD0IN3
AD0IN2
AD0IN1
AD0IN0
AVCC0
VREF0
XIN
VSS
AD1IN13
AD1IN12
AVSS1
AD1IN15
AD1IN14
P43/RD
P44/CS0
P46/A13
P45/CS1
P47/A14
P220/CTX
P222
P223
P221/CRX
VSS
OSC-VSS
(Note) P224/A11
(Note) P225/A12
XOUT
OSC-VCC
VCNT
VSS
P31/A16
P30/A15
P32/A17
P33/A18
P35/A20
P34/A19
P37/A22
P36/A21
P21/A24
P20/A23
P23/A26
P22/A25
VCCE
VSS
P24/A27
P25/A28
P26/A29
P27/A30
P00/DB0
P01/DB1
P04/DB4
P03/DB3
P02/DB2
P07/DB7
P06/DB6
P05/DB5
Package: 240P6Y-A (0.5 mm pitch)
Note: Use caution when using these pins because they have a debug event function.
Figure 1.4.1 Pin Layout Diagram of the 240QFP (Top View)
1-18 Ver.0.10
VCCE
VSS
P11/DB9
P10/DB8
P12/DB10
P13/DB11
P14/DB12
P15/DB13
P16/DB14
P17/DB15
1
1.4 Pin Layout
Table 1.4.1 Pin Assignments of the 240QFP (1/2)
No. Pin Name No. Pin Name No. Pin Name No. Pin Name
1 AD1IN12 41 P26 / A29 81 VSS 121 P87 / SCLKI1 / SCLKO1
2 AD1IN13 42 P27 / A30 82 P180 / TO29 122 P200 / TXD4
3 AD1IN14 43 P00 / DB0 83 P181 / TO30 123 P201 / RXD4
4 AD1IN15 44 P01 / DB1 84 P182 / TO31 124 P202 / TXD5
5 AVSS1 45 P02 / DB2 85 P183 / TO32 125 P203 / RXD5
6
7
8
9 P46 / A13 49 P06 / DB6 89 P187 / TO36 129 VSS
10 P47 / A14 50 P07 / DB7 90 P190 / TIN26 130 P61
11 P220 / CTX 51 VCCE 91 P191 / TIN27 131 P62
12 P221 / CRX 52 VSS 92 P192 / TIN28 132 P63
13 P222 53 P10 / DB8 93 P193 / TIN29 133
14 P223 54 P11 / DB9 94 P194 / TIN30 134
15 P224 / A11 55 P12 / DB10 95 P195 / TIN31 135 P66 / SCLKI5 / SCLKO5
16 P225 / A12 56 P13 / DB11 96 P196 / TIN32 136
17 VSS 57 P14 / DB12 97 P197 / TIN33 137 VCCI
18 OSC-VSS 58 P15 / DB13 98 VCCI 138 VSS
19 XIN 59 P16 / DB14 99 VSS 139 VCCE
20 XOUT 60 P17 / DB15 100 P160 / TO21 140
21 OSC-VCC 61 VREF0 101 P161 / TO22 141
22 VSS 62 AVCC0 102 P162 / TO23 142
23 VCNT 63 AD0IN0 103 P163 / TO24 143
24 VSS 64 AD0IN1 104 P164 / TO25 144 P74 / RTDTXD
25 P30 / A15 65 AD0IN2 105 P165 / TO26 145 P75 / RTDRXD
26 P31 / A16 66 AD0IN3 106 P166 / TO27 146 P76 / RTDACK
27 P32 / A17 67 AD0IN4 107 P167 / TO28 147 P77 / RTDCLK
28 P33 / A18 68 AD0IN5 108 P172 / TIN24 148 P93 / TO16
29 P34 / A19 69 AD0IN6 109 P173 / TIN25 149 P94 / TO17
30 P35 / A20 70 AD0IN7 110 P174 / TXD2 150 P95 / TO18
31 P36 / A21 71 AD0IN8 111 P175 / RXD2 151 P96 / TO19
32 P37 / A22 72 AD0IN9 112 P176 / TXD3 152 P97 / TO20
33 P20 / A23 73 AD0IN10 113 P177 / RXD3 153
34 P21 / A24 74 AD0IN11 114 VCCE 154 MOD0
35 P22 / A25 75 AD0IN12 115 VSS 155 MOD1
36 P23 / A26 76 AD0IN13 116 P82 / TXD0 156 FP
37 VCCE 77 AD0IN14 117 P83 / RXD0 157 VCCE
38 VSS 78 AD0IN15 118
39 P24 / A27 79 AVSS0 119 P85 / TXD1 159 P110 / TO0
40 P25 / A28 80 VCCE 120 P86 / RXD1 160 P111 / TO1
__
P43 / RD 46 P03 / DB3 86 P184 / TO33 126 VCCI
___
P44 / CS0 47 P04 / DB4 87 P185 / TO34 127 VSS
___
P45 / CS1 48 P05 / DB5 88 P186 / TO35 128 FVCC
P64 / SBI
P65 / SCLKI4 / SCLKO4
P67 / ADTRG
P70 / BCLK / WR
P71 / WAIT
P72 / HREQ
P73 / HACK
_____
RESET
P84 / SCLKI0 / SCLKO0 158 VSS
___
____
OVERVIEW
_____
___
____
____
1-19 Ver.0.10
1
Table 1.4.1 Pin Assignments of the 240QFP (2/2)
No. Pin Name No. Pin Name No. Pin Name No. Pin Name
161 P112 / TO2 181 JTMS 201 P134 / TIN20 221 P156 / TIN6
162 P113 / TO3 182 JTCK 202 P135 / TIN21 222 P157 / TIN7
163 P114 / TO4 183 JTRST 203 P136 / TIN22 223
164 P115 / TO5 184 JTDO 204 P137 / TIN23 224
165 P116 / TO6 185 JTDI 205 VCCE 225 VCCI
166 P117 / TO7 186 P103 / TO11 206 VSS 226 VSS
167 P100 / TO8 187 P104 / TO12 207 P140 / TIN8 227 VREF1
168 P101 / TO9 188 P105 / TO13 208 P141 / TIN9 228 AVCC1
169 P102 / TO10 189 P106 / TO14 209 P142 / TIN10 229 AD1IN0
170 VDD 190 P107 / TO15 210 P143 / TIN11 230 AD1IN1
171 VCCI 191 P124 / TCLK0 211 P144 / TIN12 231 AD1IN2
172 VSS 192 P125 / TCLK1 212 P145 / TIN13 232 AD1IN3
173 P210 / TO37 193 P126 / TCLK2 213 P146 / TIN14 233 AD1IN4
174 P211 / TO38 194 P127 / TCLK3 214 P147 / TIN15 234 AD1IN5
175 P212 / TO39 195 VCCI 215 P150 / TIN0 235 AD1IN6
176 P213 / TO40 196 VSS 216 P151 / TIN1 236 AD1IN7
177 P214 / TO41 197 P130 / TIN16 217 P152 / TIN2 237 AD1IN8
178 P215 / TO42 198 P131 / TIN17 218 P153 / TIN3 238 AD1IN9
179 P216 / TO43 199 P132 / TIN18 219 P154 / TIN4 239 AD1IN10
180 P217 / TO44 200 P133 / TIN19 220 P155 / TIN5 240 AD1IN11
OVERVIEW
1.4 Pin Layout
___ ___
P41 / BLW / BLE
___ ___
P42 / BHW / BHE
1-20 Ver.0.10
1
OVERVIEW
1.4 Pin Layout
JTMS
20
JTCK
19
JEVENT
18
0
JEVENT
17
1
P104
16
/TO12
P124
15
/TCLK0
VCCI VSS
14
P132
13
/TIN18
P136
12
/TIN22
P140
11
/TIN8
P144
10
/TIN12
P150
9
/TIN0
P154
8
/TIN4
P41
7
/BLW
P216
/TO43
P217
/TO44
JDBI
JTRST
P103
/TO11
P107
/TO15
P127
/TCLK3
P131
/TIN17
P135
/TIN21
P145
/TIN13
P151
/TIN1
P155
/TIN5
P42
/BHW
P214
/TO41
P215
/TO42
P213
/TO40
JTDO
P105
/TO13
P125
/TCLK1
P133
/TIN19
P137
/TIN23
P141
/TIN9
P143
/TIN11
P147
/TIN15
P153
/TIN3
P157
/TIN7
P210
/TO37
P211
/TO38
P212
/TO39
VSS
JTDI
P106
/TO14
P126
/TCLK2
P130
/TIN16
P134
/TIN20
VCCEVSS
P142
/TIN10
P146
/TIN14
P152
/TIN2
P156
/TIN6
P102
/TO10
VDD
VCCI
P101
/TO9
P116
/TO6
P117
/TO7
P100
/TO8
P115
/TO5
TRDATA
6
TRDATA
7
P114
/TO4
TRDATA
5
P112
/TO2
P113
/TO3
TRDATA
4
P111
/TO1
VCCE
VSS
P110
/TO0
FP
RESET
MOD0
MOD1
P97
/TO20
P96
/TO19
P95
/TO18
P94
/TO17
P93
/TO16
M32170F3VWG
M32170F4VWG
M32170F6VWG
P77/
RTDCLK
P76/
RTDACK
P75/
RTDRXD
P74/
RTDTXD
P73
/HACK
P72
/HREQ
P71
/WAIT
P70
/BCLK
VCCE
VSS
VCCI
P67
/ADTRG
P66
/SCLK5
P65
/SCLK4
P64
/SBI
P63
P62
P61
VSS
FVCC
P202
VSS
/TXD5
P200
VCCI
/TXD4
P87
P203
/SCLK1
/RXD5
P84
P83
/SCLK0
/RXD0
P177
VCCE VSS
/RXD3
P173
P174
/TIN25
/TXD2
P165
P166
/TO26
/TO27
P161
P162
/TO22
/TO23
P197
VCCI VSS
/TIN33
P193
P194
/TIN29
/TIN30
P187
P192
/TO36
/TIN28
P183
P186
/TO32
/TO35
P182
VSS
/TO31
AD0IN14 AD0IN15 AVSS0VCCE
P201
/RXD4
N.C
TRDATA
2
P86
/RXD1
P82
/TXD0
P176
/TXD3
P172
/TIN24
P164
/TO25
P160
/TO21
P196
/TIN32
P190
/TIN26
P184
/TO33
P180
/TO29
TRDATA
3
TRDATA
1
TRDATA
0
P85
/TXD1
P175
/RXD2
P167
/TO28
P163
/TO24
P195
/TIN31
P191
/TIN27
P185
/TO34
P181
/TO30
6
5
4
AD1IN8 AD1IN10
3
AD1IN9 AD1IN11
2
1
AD1IN12
AD1IN5AD1IN6 AD1IN7
AD1IN4
AD1IN13
AD1IN14
VCCIVSSVREF1 AVCC1
AD1IN0AD1IN1AD1IN2 AD1IN3
AD1IN15
AVSS1
P43
/RD
P44
/CS0
P45
/CS1
P46
/A13
P47
/A14
P220
/CTX
P221
/CRX
P222
P223
P224
/A11
P225
/A12
VSS
OSC-
VSS
XIN
XOUT
OSC-
VCC
VSS
VCNT
VSS
P30
/A15
P31
/A16
P32
/A17
P33
/A18
P34
/A19
P35
/A20
TRCLK
TRSYNC
P20
/A23
P37
/A22
P36
/A21
P21
/A24
VCCE
P23
/A26
P22
/A25
VSS
P26
/A29
P25
/A28
P24
/A27
P27
/A30
P02
/DB2
P01
/DB1
P00
/DB0
P03
/DB3
P06
/DB6
P05
/DB5
P04
/DB4
P07
/DB7
P10
/DB8
VSS
VCCE
AD0IN10 AD0IN11 AD0IN12AD0IN13
AD0IN6 AD0IN7 AD0IN8AD0IN9
P11
/DB9
P14
/DB12
P13
P17
/DB11
/DB15
P12
P15
/DB10
/DB13
AD0IN3 AD0IN4AD0IN5
AD0IN0AD0IN1 AD0IN2
VREF0 AVCC0
AB CDE FGH JKL MNPR T UVWY
Package: 255F7F (0.8 mm pitch)
Note 1: NC pins (W19, Y1) are not internally connected. Leave them open.
Note 2: Use caution when using P224/A11 and P225/A12 because they have a debug event
function.
Note 3: 255FBGA is currently under development.
Figure 1.4.2 Pin Layout Diagram of the 255FBGA (Top View)
P16
/DB14
N.C
1-21 Ver.0.10
1
Table 1.4.2 Pin Assignments of the 255FBGA (1/2)
No. Pin Name No. Pin Name No. Pin Name No. Pin Name
OVERVIEW
1.4 Pin Layout
A1 — C1 AD1IN14 E1 P220 / CTX H1 VCNT
A2 AD1IN9 C2 AD1IN13 E2
A3 AD1IN8 C3 AD1IN4 E3
A4 AD1IN6 C4 AD1IN5 E4
A5 AD1IN2 C5 AD1IN1 E17 P101 / TO9 H17 P111 / TO1
A6 VERF1 C6 VSS E18 VCCI H18 TRDATA4
A7
A8 P154 / TIN4 C8 P153 / TIN3 E20 P102 / TO10 H20 P112 / TO2
A9 P150 / TIN0 C9 P147 / TIN15 F1 P224 / A11 J1 P32 / A17
A10 P144 / TIN12 C10 P143 / TIN11 F2 P223 J2 P31 / A16
A11 P140 / TIN8 C11 P141 / TIN9 F3 P222 J3 P30 / A15
A12 P136 / TIN22 C12 P137 / TIN23 F4 P221 / CRX J4 VSS
A13 P132 / TIN18 C13 P133 / TIN19 F17 P115 / TO5 J17 FP
A14 VCCI C14 VSS F18 P100 / TO8 J18 P110 / TO0
A15 P124 / TCLK0 C15 P125 / TCLK1 F19 P117 / TO7 J19 VSS
A16 P104 / TO12 C16 P105 / TO13 F20 P116 / TO6 J20 VCCE
A17 JEVENT1 C17 JTDO G1 XIN K1 TRCLK
A18 JEVENT0 C18 P213 / TO40 G2 OSC-VSS K2 P35 / A20
A19 JTCK C19 P215 / TO42 G3 VSS K3 P34 / A19
A20 JTMS C20 P214 / TO41 G4 P225 / A12 K4 P33 / A18
B1 AD1IN12 D1
B2 AD1IN11 D2
B3 AD1IN10 D3 AVSS1 G19 TRADATA7 K19 MOD0
B4 AD1IN7 D4 AD1IN15 G20 TRADATA6 K20
B5 AD1IN3 D5 AD1IN0
B6 AVCC1 D6 VCCI
B7
B8 P155 / TIN5 D8 P152 / TIN2
B9 P151 / TIN1 D9 P146 / TIN14
B10 P145 / TIN13 D10 P142 / TIN10
B11 VSS D11 VCCE
B12 P135 / TIN21 D12 P134 / TIN20
B13 P131 / TIN17 D13 P130 / TIN16
B14 P127 / TCLK3 D14 P126 / TCLK2
B15 P102 / TO15 D15 P106 / TO4
B16 P103 / TO11 D16 JTDI
B17 JTRST D17 VSS
B18 JDBI D18 P212 / TO39
B19 P217 / TO44 D19 P211 / TO38
B20 P216 / TO43 D20 P210 / TO37
_______
P41 / BLW C7 P157 / TIN7 E19 VDD H19 P113 / TO3
_________
P44 / CS0 G17 TRADATA5 K17 P97 / TO20
_____
P43 / RD G18 P114 / TO4 K18 MOD1
________
P42 / BHW D7 P156 / TIN6
______
P47 / A14 H2 VSS
_____
P46 / A13 H3 OSC-VOC
_____
P45 / CS1 H4 XOUT
____________
RESET
1-22 Ver.0.10
1
Table 1.4.2 Pin Assignments of the 255FBGA (2/2)
No. Pin Name No. Pin Name No. Pin Name No. Pin Name
L1 P36 / A21 P1 P00 / DB0 U1 P12 / DB10 W1 P16 / DB14
L2 P37 / A22 P2 P01 / DB1 U2 P13 / DB11 W2 VREF0
L3 P20 / A23 P3 P02 / DB2 U3 P14 / DB12 W3 AD0IN0
L4 TRSYNC P4 P27 / A30 U4 P11 / DB9 W4 AD0IN3
______
L17 P93 / TO16 P17
L18 P94 / TO17 P18 VCCI U6 AD0IN10 W6 AD0IN11
L19 P95 / TO18 P19 VSS U7 AD0IN14 W7 AD0IN15
L20 P96 / TO19 P20 VCCE U8 VSS W8 P180 / TO29
M1 P22 / A25 R1 P04 / DB4 U9 P183 / TO32 W9 P184 / TO33
M2 P23 / A26 R2 P05 / DB5 U10 P187 / TO36 W10 P190 / TIN26
M3 VCCE R3 P06 / DB6 U11 P193 / TIN29 W11 P196 / TIN32
M4 P21 / A24 R4 P03 / DB3 U12 P197 / TIN33 W12 P160 / TO21
P67 / ADTRG U5 AD0IN6 W5 AD0IN7
OVERVIEW
1.4 Pin Layout
M17 P74 / RTDTXD R17 P63 U13 P161 / TO22 W13 P164 / TO25
M18 P75 / RTDRXD R18
M19 P76 / RTDACK R19 P65 / SCLK4 U15 P173 / TIN25 W15 P176 / TXD3
M20 P77 / RTDCLK R20 P66 / SCLK5 U16 P177 / RXD3 W16 P82 / TXD0
N1 P24 / A27 T1 VCCE U17 P83 / RXD0 W17 P86 / RXD1
N2 P25 / A28 T2 VSS U18 P203 / RXD5 W18 TRDATA2
N3 P26 / A29 T3 P10 / DB8 U19 VCCI W19 N.C
N4 VSS T4 P07 / DB7 U20 VSS W20 P201 / RXD4
N17 P70 / BCLK T17 FVCC V1 P15 / DB13 Y1 N.C
N18
N19
N20
_____
P71 / WAIT T18 VSS V2 P17 / DB15 Y2 AVCC0
_____
P72 / HREQ T19 P61 V3 AD0IN1 Y3 AD0IN2
_____
P73 / HACK T20 P62 V4 AD0IN5 Y4 AD0IN4
___
P64 / SBI U14 P165 / TO26 W14 P172 / TIN24
V5 AD0IN9 Y5 AD0IN8
V6 AD0IN13 Y6 AD0IN12
V7 VCCE Y7 AVSS0
V8 P182 / TO31 Y8 P181 / TO30
V9 P186 / TO35 Y9 P185 / TO34
V10 P192 / TIN28 Y10 P191 / TIN27
V11 P194 / TIN30 Y11 P195 / TIN31
V12 VCCI Y12 VSS
V13 P162 / TO23 Y13 P163 / TO24
V14 P166 / TO27 Y14 P167 / TO28
V15 P174 / TXD2 Y15 P175 / RXD2
V16 VCCE Y16 VSS
V17 P84 / SCLK0 Y17 P85 / TXD1
V18 P87 / SCLK1 Y18 TRDATA0
V19 P200 / TXD4 Y19 TRDATA1
V20 P202 / TXD5 Y20 TRDATA3
1-23 Ver.0.10
1
OVERVIEW
1.4 Pin Layout
❊ This is a blank page. ❊
1-24 Ver.0.10
CHAPTER 2CHAPTER 2
CPU
2.1 CPU Registers
2.2 General-purpose Registers
2.3 Control Registers
2.4 Accumulator
2.5 Program Counter
2.6 Data Formats
2
2.1 CPU Registers
2.1 CPU Registers
The M32R has sixteen general-purpose registers, five control registers, an accumulator, and a
program counter. The accumulator is a 56-bit configuration, and all other registers are a 32-bit
configuration.
2.2 General-purpose Registers
General-purpose registers are 32 bits in width and there are sixteen of them (R0 to R15), which are
used to hold data and base addresses. Especially, R14 is used as a link register, and R15 is used
as a stack pointer. The link register is used to store the return address when executing a subroutine
call instruction. The stack pointer is switched between an interrupt stack pointer (SPI) and a user
stack pointer (SPU) depending on the value of the Processor Status Word register (PSW)'s stack
mode (SM) bit.
CPU
00
Note: The stack pointer is switched between an interrupt stack pointer (SPI) and a user stack pointer
(SPU) depending on the value of the PSW's SM bit.
Figure 2.2.1 General-purpose Registers
31 31
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14 (Link register)
R15 (Stack pointer) (Note)
2-2 Ver.0.10
2
2.3 Control Registers
2.3 Control Registers
There are five control registers-Processor Status Word Register (PSW), Condition Bit Register
(CBR), Interrupt Stack Pointer (SPI), User Stack Pointer (SPU), and Backup PC (BPC).
Dedicated "MVTC" and "MVFC" instructions are used to set and read these control registers.
CPU
CRn
CR0
CR1
CR2
CR3
CR6 Backup PC
Notes 1: CRn (n = 0-3, 6) denotes control register numbers.
2: Dedicated "MVTC" and "MVFC" instructions are used to set and read the control registers.
Figure 2.3.1 Control Registers
0 31
Control Registers
PSW
CBR
SPI
SPU
BPC
Processor status Word Register
Condition Bit Register
Interrupt Stack Pointer
User Stack Pointer
2-3 Ver.0.10
2
2.3 Control Registers
2.3.1 Processor Status Word Register: PSW (CR0)
The Processor Status Word Register (PSW) is used to indicate the status of the M32R. It consists
of a regularly used PSW field and a special BPSW field which is used to save the PSW field when
an EIT occurs.
The PSW field consists of several bits labeled Stack Mode (SM), Interrupt Enable (IE), and
Condition bit (C). The BPSW field consists of backup bits of the foregoing, i.e., Backup SM bit
(BSM), Backup IE bit (BIE), and Backup C bit (BC).
BPSW field PSW field
CPU
0(MSB)
16 17 23 24 25
1587
PSW
SM IE CBCBSM BIE
(Note 1)
D Bit Name Function Initial R W
16 BSM (Backup SM) Holds the value of SM bit when EIT
is accepted.
17 BIE (Backup IE) Holds the value of IE bit when EIT
is accepted.
23 BC (Backup C) Holds the value of C bit when EIT
is accepted.
24 SM (Stack Mode) 0: Interrupt stack pointer is used. 0
1: User stack pointer is used.
Indeterminate
Indeterminate
Indeterminate
31(LSB)
00000000000000000000000000
25 IE (Interrupt Enable) 0: No interrupt is accepted. 0
1: Interrupt is accepted.
31 C (Condition bit)
Notes 1: "Initial" shows the state immediately after reset, R = O means the register is readable, W = O
means the register is writable.
2: For changes of the state of each bit when an EIT event occurs, refer to Chapter 4, "EIT.”
Depending on instruction execution, it indicates
whether operation resulted in a carry, borrow, or overflow.
0
2-4 Ver.0.10
2
2.3 Control Registers
2.3.2 Condition Bit Register: CBR (CR1)
The Condition Bit Register (CBR) is created as a separate register from the PSW by extracting the
Condition bit (C) from it. The value written to the PSW C bit is reflected in this register. This register
is a read-only register (writes to this register by "MVTC" instruction are ignored).
0(MSB) 31(LSB)
0000000000000000000000000000000
CBR
2.3.3 Interrupt Stack Pointer: SPI (CR2) User Stack Pointer: SPU (CR3)
CPU
C
The Interrupt Stack Pointer (SPI) and User Stack Pointer (SPU) hold the current address of the
stack pointer. These registers can be accessed as general-purpose register R15. In this case,
whether R15 is used as SPI or as SPU depends on the PSW's Stack Mode (SM) bit.
SPI
SPU
0(MSB)
SPI
0(MSB)
SPU
31(LSB)
31(LSB)
2.3.4 Backup PC: BPC (CR6)
The Backup PC (BPC) is a register used to save the value of the Program Counter (PC) when an
EIT occurs. Bit 31 is fixed to 0.
When an EIT occurs, the value held in the PC immediately before the EIT occurred or the value of
the next instruction is set in this register. When the "RTE" instruction is executed, the saved value
is returned from the BPC to the PC. However, the two low-order bits of the PC when thus returned
are always fixed to "00" (control always returns to word boundaries.)
BPC
31(LSB)0(MSB)
BPC
0
2-5 Ver.0.10
2
2.4 Accumulator
2.4 Accumulator
The accumulator (ACC) is a 56-bit register used by DSP function instructions. When read out or
written to, it is handled as a 64-bit register. When reading, the value of bit 8 is sign-extended. When
writing, bits 0--7 are ignored. Also, the accumulator is used by the multiplication instruction "MUL."
Note that when executing this instruction, the value of the accumulator is destroyed.
The "MVTACHI" and "MVTACLO" instructions are used to write to the accumulator. The
"MVTACHI" instruction writes data to the 32 high-order bits (bits 0-31), and the "MVTACLO"
instruction writes data to the 32 low-order bits (bits 32-63).
The "MVFACHI," "MVFACLO," and "MVFACMI" instructions are used to read data from the
accumulator. The "MVFACHI" instruction reads data from the 32 high-order bits (bits 0-31), the
"MVFACLO" instruction reads data from the 32 low-order bits (bits 32-63), and the "MVFACHI"
instruction reads data from the 32 middle bits (bits 16-47).
CPU
(Note)
ACC
Range of bits read/written to by
MVFACHI/MVTACHI instructions
Note: Bits 0-7 always show the sign-extended value of bit 8. Writes to this bit field are ignored.
Range of bits read by MVFACMI
instruction
32 48 63(LSB)3116150(MSB) 4778
Range of bits read/written to by
MVFACLO/MVTACLO instructions
2.5 Program Counter
The Program Counter (PC) is a 32-bit counter used to hold the address of the currently executed
instruction. Because M32R instructions each start from an even address, the LSB (bit 31) is always
0.
PC
31(LSB)0(MSB)
PC
0
2-6 Ver.0.10
2
2.6 Data Formats
2.6 Data Formats
2.6.1 Data Types
There are several data types that can be handled by the M32R's instruction set. These include
signed and unsigned 8, 16, and 32-bit integers. Values of signed integers are represented by
2's complements.
CPU
Signed byte (8-bit)
integer
Unsigned byte (8-bit)
integer
Signed halfword (16-bit)
integer
Unsigned halfword
(16-bit) integer
Signed word (32-bit)
integer
Unsigned word (32-bit)
integer
0(MSB)
S
0(MSB)
0(MSB)
S
0(MSB)
0(MSB)
S
0(MSB)
7(LSB)
7(LSB)
15(LSB)
15(LSB)
31(LSB)
31(LSB)
Figure 2.6.1 Data Types
S : Sign bit
2-7 Ver.0.10
2
2.6.2 Data Formats
(1) Data formats in register
Data sizes in M32R registers are always words (32 bits).
When loading byte (8-bit) or halfword (16-bit) data from memory into a register, the data is signextended (LDB, LDH instructions) or zero-extended (LDUB, LDUH instructions) into word (32-bit)
data before being stored in the register. When storing data from M32R register into memory, the
register data is stored in memory in different sizes depending on the instructions used. The ST
instruction stores the entire 32-bit data of the register, the STH instruction stores the least
significant 16-bit data, and the STB instruction stores the least significant 8-bit data.
CPU
2.6 Data Formats
<When loading>
0(MSB) 31(LSB)
Rn
Sign-extended (LDH instruction) or
zero-extended (LDUH instruction)
0(MSB) 31(LSB)
Rn
0(MSB) 31(LSB)
Rn
<When storing>
0(MSB) 31(LSB)
Rn
Sign-extended (LDB instruction) or
zero-extended (LDUB instruction)
From memory (LDH, LDUH instructions)
16
From memory (LD instructions)
Word
From memory (LDB,
LDUB instructions)
24
Halfword
24
Byte
Byte
0(MSB) 31(LSB)
Rn
0(MSB) 31(LSB)
Rn
To memory (ST instruction)
Figure 2.6.2 Data Formats in Register
To memory (STB instruction)
16
Halfword
To memory (STH instruction)
Word
2-8 Ver.0.10
2
(2) Data formats in memory
Data sizes in memory are either byte (8 bits), halfword (16 bits), or word (32 bits). Byte data can
be located at any address. However, halfword data must be located at halfword boundaries
(where the LSB address bit = "0"), and word data must be located at word boundaries (where two
LSB address bits = "00"). If an attempt is made to access memory data across these halfword or
word boundaries, an address exception is generated.
CPU
2.6 Data Formats
Address
+ 0 address + 1 address + 2 address + 3 address
031
Byte
Byte
(MSB) (LSB)
Halfword
(MSB)
Word
Figure 2.6.3 Data Formats in Memory
7 8 15 16 23 24
Halfword
Byte
Byte
Byte
Halfword
(LSB)
Word
2-9 Ver.0.10
2
CPU
2.6 Data Formats
(3) Endian
The following shows the generally used endian methods and the M32R family endian.
Bit endian Byte endian
(H'01) (H'01234567)
MSB LSB
Big endian
Little endian
B'0000001
D0 D7
MSB LSB
B'0000001
D7 D0
Note: Even for bit big endian, H'01 is not B'10000000.
Figure 2.6.4 Endian Methods
MPU name
Endian
(Bit/Byte)
Address
Data
arrangement
7700 family
M16C family
Little/Little
+0 +1 +2 +3 +0 +1 +2 +3+0 +1 +2 +3
MSB LSB MSB LSB MSB LSB
LL LH HL HH
HH HL LH LL
MSB LSB
H'01
HH HL LH LL
MSB LSB
H'67
LL LH HL HH
Competition
Little/Big
H'23 H'45 H'67
H'45 H'23 H'01
M32R family
M16 family
HH HL LH LL
Big/Big
Bit number
Ex:0x01234567
Note: The M32R's endian method is big endian for both bit and byte.
.byte 67,45,23,01 .byte 01,23,45,67 .byte 01,23,45,67
7-031-24 15-823-16 0-7 24-318-15 16-23
Figure 2.6.5 M32R Family Endian
7-031-24 15-823-16
2-10 Ver.0.10
2
(4) Transfer instructions
CPU
2.6 Data Formats
• Constant transfer
LD24 Rdest, #imm24
LDI Rdest, #imm16
LDI Rdest, #imm8
SETH Rdest, #imm16
• Register to register transfer
MV Rdest, Rsrc
• Control register transfer
MVFC Rdest, CRsrc
MVTC Rsrc, CRdest
LD24 Rdest, #imm24
imm24
SETH Rdest, #imm16
imm16
MV Rdest, Rsrc
Rsrc
MVTC Rsrc, CRdest
Rsrc
Rdest
Rdest
Rdest
CRdest
230
00
8
150
00 00
15
310
310
310
310
310
310
Note: For the MVTC instruction, the condition bit C does not change unless CRdest is CR0 (PSW).
Figure 2.6.6 Transfer instructions
2-11 Ver.0.10
2
(5) Memory (signed) to register transfer
CPU
2.6 Data Formats
• Signed 32 bits
Memory Register
LD24 Rsrc, #label
label
LD Rdest, @Rsrc
+0 +1 +2 +3
• Signed 16 bits
LD24 Rsrc, #label
label
LDH Rdest, @Rsrc
+0 +1 +2 +3
Check the MSB
0 = positive
1 = negative
• Signed 8 bits
label
LD24 Rsrc, #label
LDB Rdest, @Rsrc
+0 +1 +2 +3
Check the MSB
0 = positive
1 = negative
Figure 2.6.7 Memory (signed) to register transfer
Rdest
310
Rdest
00 00
FF FF
310
Rdest
00 00 00
FF FF FF
310
(6) Memory (unsigned) to register transfer
• Unsigned 32 bits
LD24 Rsrc, #label
LD Rdest, @Rsrc
• Unsigned 16 bits
LD24 Rsrc, #label
LDUH Rdest, @Rsrc
• Unsigned 8 bits
LD24 Rsrc, #label
LDUB Rdest, @Rsrc
label
label
label
Memory Register
+0 +1 +2 +3
+0 +1 +2 +3
+0 +1 +2 +3
Figure 2.6.8 Memory (unsigned) to register transfer
Rdest
310
Rdest
00 00
310
Rdest
00 00 00
310
2-12 Ver.0.10
2
(7) Things to be noted for data transfer
Note that in data transfer, data arrangements in registers and those in memory are different.
CPU
2.6 Data Formats
Data in register
(R0-R15)
Word data (32 bits)
HH HL LH LL
D0 D31
MSB LSB
(R0-R15)
Half-word data (16 bits)
D0 D31
MSB LSB
(R0-R15)
Byte data (8 bits)
D0 D31
MSB LSB
Figure 2.6.9 Difference in Data Arrangements
H L
Data in memory
+0 +1 +2 +3
HH HL LH LL
D0 D31
MSB LSB
+0 +1 +2 +3
H L
D0 D15
MSB LSB
+0 +1 +2 +3
D0 D7
MSB LSB
2-13 Ver.0.10
2
❊ This is a blank page. ❊
2-14 Ver.0.10
CHAPTER 3CHAPTER 3
ADDRESS SPACE
3.1 Outline of Address Space
3.2 Operation Modes
3.3 Internal ROM Area and Extended
External Area
3.4 Internal RAM Area and SFR Area
3.5 EIT Vector Entry
3.6 ICU Vector Table
3.7 Note about Address Space
ADDRESS SPACE
3
3.1 Outline of Address Space
3.1 Outline of Address Space
The M32R's logical addresses are always handled in 32 bits, providing 4 Gbytes of linear address space. The M32R/E's address space consists of the following:
(1) User space
• Internal ROM area
• Extended external area
• Internal RAM area
• Special Function Register (SFR) area
(2) Boot program space
(3) System space (areas not open to the user)
(1) User space
A 2 Gbytes of address space from H'0000 0000 to H'7FFF FFFF is the user space. Located in
this space are the internal ROM area, extended external area, internal RAM area, and Special Function Register (SFR) area, an area containing a group of internal peripheral I/O registers. Of these, the internal ROM and extended external areas are located differently depending on mode settings which will be described later.
(2) Boot program space
A 1 Gbyte of address space from H'8000 0000 to H'BFFF FFFF is the boot program space.
This space stores a program (boot program) which enables on-board programming when the
internal flash area is blank.
(3) System space
A 1 Gbyte of address space from H'C000 0000 to H'FFFF FFFF is the system space. This
space is reserved for use by development tools such as an in-circuit emulator or a debug
monitor, and cannot be used by the user.
3-2 Ver.0.10
3
A
A
ADDRESS SPACE
3.1 Outline of Address Space
<Logical address space of M32170F6>
Logical address
H'0000 0000
2 Gbytes
H'7FFF FFFF
H'8000 0000
1 Gbyte
H'BFFF FFFF
H'C000 0000
User space
Boot
program
space
(16 Mbytes)
BOOT ROM area
(8 Kbytes)
Reserved area
(8 Kbytes)
Extended external
Ghost area
in units of
16 Mbytes
H'8000 0000
H'8000 1FFF
H'8000 2000
H'8000 3FFF
H'8000 4000
Ghost area
in units of
16 Mbytes
H'BFFF FFFF
area
(4 Mbytes)
EIT vector entry
Internal ROM area
(768 Kbytes)
(Note 1)
Reserved area
(256 Kbytes)
CS0 area
CS1 area
SFR area
(16 Kbytes)
Internal RAM area
(40 Kbytes)
Reserved area
AA
(72 Kbytes)
AA
H'0000 0000
H'000B FFFF
H'000F FFFF
H'0010 0000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Ghost area in
4 Mbytes
H'007F FFFF
H'0080 0000
H'0080 3FFF
H'0080 4000
H'0080 DFFF
H'0080 E000
H'0081 FFFF
H'0082 0000
1 Gbyte
H'FFFF FFFF
Notes1: This location varies with chip mode settings.
System space
2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0.
Figure 3.1.1 Address Space of the M32170F6
Ghost area in
units of 128
Kbytes
H'00FF FFFF
3-3 Ver.0.10
3
A
A
ADDRESS SPACE
3.1 Outline of Address Space
<Logical address space of M32170F4>
Logical address
H'0000 0000
2 Gbytes
H'7FFF FFFF
H'8000 0000
1 Gbyte
H'BFFF FFFF
H'C000 0000
User space
Boot
program
space
(16 Mbytes)
BOOT ROM area
(8 Kbytes)
Reserved area
(8 Kbytes)
Extended external
Ghost area
in units of
16 Mbytes
H'8000 0000
H'8000 1FFF
H'8000 2000
H'8000 3FFF
H'8000 4000
Ghost area
in units of
16 Mbytes
H'BFFF FFFF
area
(4 Mbytes)
EIT vector entry
Internal ROM area
(512 Kbytes)
(Note 1)
Reserved area
(512 Kbytes)
CS0 area
CS1 area
SFR area
(16 Kbytes)
Internal RAM area
(32 Kbytes)
Reserved area
AA
(80 Kbytes)
AA
H'0000 0000
H'0007 FFFF
H'000F FFFF
H'0010 0000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Ghost area in
4 Mbytes
H'007F FFFF
H'0080 0000
H'0080 3FFF
H'0080 4000
H'0080 BFFF
H'0080 C000
H'0081 FFFF
H'0082 0000
1 Gbyte
H'FFFF FFFF
Notes1: This location varies with chip mode settings.
System space
2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0.
Figure 3.1.2 Address Space of the M32170F4
Ghost area in
units of 128
Kbytes
H'00FF FFFF
3-4 Ver.0.10
3
A
A
ADDRESS SPACE
3.1 Outline of Address Space
<Logical address space of M32170F3>
Logical address
H'0000 0000
2 Gbytes
H'7FFF FFFF
H'8000 0000
1 Gbyte
H'BFFF FFFF
H'C000 0000
User space
Boot
program
space
(16 Mbytes)
BOOT ROM area
(8 Kbytes)
Reserved area
(8 Kbytes)
Extended external
Ghost area
in units of
16 Mbytes
H'8000 0000
H'8000 1FFF
H'8000 2000
H'8000 3FFF
H'8000 4000
Ghost area
in units of
16 Mbytes
H'BFFF FFFF
area
(4 Mbytes)
EIT vector entry
Internal ROM area
(384 Kbytes)
(Note 1)
Reserved area
(640 Kbytes)
CS0 area
CS1 area
SFR area
(16 Kbytes)
Internal RAM area
(32 Kbytes)
Reserved area
AA
(80 Kbytes)
AA
H'0000 0000
H'0005 FFFF
H'000F FFFF
H'0010 0000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Ghost area in
4 Mbytes
H'007F FFFF
H'0080 0000
H'0080 3FFF
H'0080 4000
H'0080 BFFF
H'0080 C000
H'0081 FFFF
H'0082 0000
1 Gbyte
H'FFFF FFFF
Notes1: This location varies with chip mode settings.
System space
2: The boot program space can read out only when FP = 1, MOD0 = 1, and MOD1 = 0.
Figure 3.1.3 Address Space of the M32170F3
Ghost area in
units of 128
Kbytes
H'00FF FFFF
3-5 Ver.0.10
ADDRESS SPACE
3
3.2 Operation Modes
3.2 Operation Modes
The 32170 is placed in one of the following modes by setting its operation mode (using MOD0 and
MOD1 pins). For details about the mode used to rewrite the internal flash memory, refer to Section
6.5, "Programming of Internal Flash Memory."
Table 3.2.1 Setting Operation Modes
MOD0 MOD1 (Note 1) Operation Mode (Note 2)
VSS VSS Single-chip mode
VSS VCC Extended external mode
VCC VSS Processor mode (FP = VSS)
VCC VCC Reserved (cannot be used)
Notes 1:VCC connects to +5 V, and VSS connects to GND.
2:
For flash rewrite mode (FP = VCC) not listed in the above table, refer to Section 6.5, "Programming
of Internal Flash Memory."
The internal ROM and extended external areas are located differently depending on the 32170's
operation mode. (All other areas in address space are located the same way.) The address maps of
internal ROM and extended external areas in each mode are shown below. (For flash rewrite mode
(FP = VCC) not listed in the above table, refer to Section 6.5, "Programming of Internal Flash
Memory.")
Non-CS0 area
H'0000 0000
H'000B FFFF
H'000C 0000
H'000F FFFF
H'0010 0000
H'001F FFFF
H'0020 0000
Internal ROM
area
(768 Kbytes)
Internal ROM
area
(768 Kbytes)
Reserved area
(256 Kbytes)
CS0 area
(1 Mbyte)
CS1 area
(2 Mbytes)
Extended external area
CS0 area
(2 Mbytes)
Extended external area
CS1 area
(2 Mbytes)
H'003F FFFF
<Single-chip mode> <Processor mode>
<Extended external mode>
Figure 3.2.1 M32170F6 Operation Mode and Internal ROM/Extended External Areas
3-6 Ver.0.10
3
ADDRESS SPACE
3.2 Operation Modes
Non-CS0 area
H'0000 0000
H'0007 FFFF
H'0008 0000
H'000F FFFF
H'0010 0000
H'001F FFFF
H'0020 0000
H'003F FFFF
Internal ROM
area
(512 Kbytes)
<Single-chip mode> <Processor mode>
Internal ROM
area
(512 Kbytes)
Reserved area
(512 Kbytes)
CS0 area
(1 Mbyte)
CS1 area
(2 Mbytes)
Extended external area
<Extended external mode>
CS0 area
(2 Mbytes)
Extended external area
CS1 area
(2 Mbytes)
Figure 3.2.2 M32170F4 Operation Mode and Internal ROM/Extended External Areas
H'0000 0000
H'0005 FFFF
H'0006 0000
H'000F FFFF
H'0010 0000
H'001F FFFF
H'0020 0000
H'003F FFFF
Non-CS0 area
Internal ROM
area
(384 Kbytes)
<Single-chip mode> <Processor mode>
Internal ROM
area
(384 Kbytes)
Reserved area
(640 Kbytes)
CS0 area
(1 Mbyte)
CS1 area
(2 Mbytes)
Extended external area
<Extended external mode>
CS0 area
(2 Mbytes)
Extended external area
CS1 area
(2 Mbytes)
Figure 3.2.3 M32170F3 Operation Mode and Internal ROM/Extended External Areas
3-7 Ver.0.10
ADDRESS SPACE
3
3.3 Internal ROM/Extended External Area
3.3 Internal ROM Area and Extended External Area
The 8 Mbyte area at addresses H'0000 0000 to H'007F FFFF in the user space accommodates the
internal ROM and extended external areas. Of this, a 4 Mbytes of address space from H'0000 0000
to H'0003 FFFF is the area that the user can actually use. All other areas here comprise a 4 Mbytes
of ghost area. (When programming, do not use this ghost area intentionally.)
For details on how the internal ROM and extended external areas are located differently depending
on the 32170's operation modes set, refer to Section 3.2, "Operation Modes."
3.3.1 Internal ROM Area
The internal ROM is located in the area shown below. Also, this area has an EIT vector entry
(and ICU vector table) located in it at the beginning.
Table 3.3.1 Addresses at Which the 32170's Internal ROM is Located
Type Name Size Located address
MF32170F6 768 Kbytes H'0000 0000 - H'000B FFFF
MF32170F4 512 Kbytes H'0000 0000 - H'0007 FFFF
MF32170F3 384 Kbytes H'0000 0000 - H'0005 FFFF
3.3.2 Extended External Area
An extended external area is provided only when extended external mode or processor mode has
been selected when setting the 32170's operation mode. For access to this extended external area,
the 32170 outputs the control signals necessary to access external devices.
The 32170's CS0 and CS1 signals are output corresponding to the address mapping of the extended external area. The CS0 signal is output for the CS0 area, and the CS1 signal is output for
the CS1 area.
Table 3.3.2 Address Mapping of the Extended External Area in Each Operation Mode of the
32170
________ _______
________ _______
Operation Mode Address mapping of the extended external area
Single-chip mode None
Extended external mode Addresses H'0010 0000 to H'001F FFFF (CS0 area: 1 Mbytes)
Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes)
Processor mode Addresses H'0000 0000 to H'001F FFFF (CS0 area: 2 Mbytes)
Addresses H'0020 0000 to H'003F FFFF (CS1 area: 2 Mbytes)
3-8 Ver.0.10
ADDRESS SPACE
3
3.4 Internal ROM/SFR Area
3.4 Internal RAM Area and SFR Area
The 8 Mbyte area at addresses H'0080 0000 to H'00FF FFFF in the user space accommodates the
internal RAM area and Special Function Register (SFR) area. Of this, a 128 Kbytes of address
space from H'0080 0000 to H'0081 FFFF is the area that the user can actually use. All other areas
here comprise a ghost area in units of 128 Kbytes. (When programming, do not use this ghost area
intentionally.)
3.4.1 Internal RAM Area
The internal RAM is located in the area shown below.
Table 3.4.1 Addresses at Which the 32170's Internal ROM is Located
Type Name Size Located address
MF32170F6 40 Kbytes H'0080 4000 - H'0080 DFFF
MF32170F4 32 Kbytes H'0080 4000 - H'0080 BFFF
MF32170F3
3.4.2 Special Function Register (SFR) Area
Addresses H'0080 0000 to H'0080 3FFFF are the Special Function Register (SFR) area. This area
has registers for internal peripheral I/O located in it.
H'0080 0000
SFR area
(16 Kbytes)
H'0080 3FFF
H'0080 4000
Pseudo-flash emulation
Internal RAM
(40 Kbytes)
areas separated in units of
8 Kbytes or 4 Kbytes can
be allocated here. For
details, refer to Section 6.7.
H'0080 DFFF
Figure 3.4.1 Internal RAM Area and Special Function Register (SFR) Area of the M32170F6
3-9 Ver.0.10
3
H'0080 0000
H'0080 3FFF
H'0080 4000
SFR area
(16 Kbytes)
Internal RAM
(32 Kbytes)
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Pseudo-flash emulation
areas separated in units of
8 Kbytes or 4 Kbytes can
be allocated here. For details,
refer to Section 6.7.
H'0080 BFFF
Figure 3.4.2 Internal RAM Area and Special Function Register (SFR) Area of the M32170F4
and M32170F3
3-10 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
H'0080 0000
H'0080 007E
H'0080 0080
H'0080 00EE
H'0080 0100
H'0080 0146
H'0080 0180
H'0080 0200
H'0080 023E
H'0080 0240
H'0080 02FE
H'0080 0300
H'0080 03BE
H'0080 03C0
H'0080 03D8
H'0080 03E0
H'0080 03FE
H'0080 0400
H'0080 0478
H'0080 0700
H'0080 0756
0 7 8 15
+0 address +1 address
Interrupt
controller (ICU)
A-D0 converter
Serial I/O0-3
Wait controller
MJT (common part)
MJT (TOP)
MJT (TIO)
MJT (TMS)
MJT (TML0)
DMAC
Input/output port
Multijunction timer
(MJT)
H'0080 078C
H'0080 078E
H'0080 0790
H'0080 07DE
H'0080 07E0
H'0080 07F2
H'0080 0A00
H'0080 0A26
H'0080 0A80
H'0080 0AEE
H'0080 0B8C
H'0080 0B8E
H'0080 0B90
H'0080 0BDE
H'0080 0C8C
H'0080 0C8E
H'0080 0C90
H'0080 0CDE
H'0080 0FE0
H'0080 0FFE
H'0080 1000
H'0080 11FE
0 7 8 15
+0 address +1 address
MJT (TID0)
MJT (TOD0)
Flash control
Serial I/O4, 5
A-D1 converter
MJT (TID1)
MJT (TOD1)
MJT (TID2)
MJT (TOM0)
MJT (TML1)
CAN0
Multijunction timer
(MJT)
Multijunction timer
(MJT)
H'0080 0760
H'0080 3FFE
Note: The Real-time Debugger (RTD) is designed to be an independent module
operated from an external source, and is transparent to the CPU.
Figure 3.4.3 Outline Address Mapping of the SFR Area
3-11 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Address
H'0080 0000
H'0080 0002
H'0080 0004
H'0080 0006
H'0080 0060
H'0080 0062
H'0080 0064
H'0080 0066
H'0080 0068
H'0080 006A
H'0080 006C
H'0080 006E
H'0080 0070
H'0080 0072
H'0080 0074
H'0080 0076
H'0080 0078
H'0080 007A
H'0080 007C
H'0080 007E
H'0080 0080
H'0080 0082
H'0080 0084
H'0080 0086
H'0080 0088
H'0080 008A
H'0080 008C
H'0080 0090
H'0080 0092
H'0080 0094
H'0080 0096
H'0080 0098
H'0080 009A
H'0080 009C
H'0080 009E
H'0080 00A0
H'0080 00A2
H'0080 00A4
H'0080 00A6
H'0080 00A8
H'0080 00AA
H'0080 00AC
H'0080 00AE
H'0080 00D0
Blank addresses are reserved areas
D0 D7 D8 D15
~
~
CAN0 Transmit/Receive & Error Interrupt Control Register (ICAN0CR)
TID2 Output Interrupt Control Register (ITID2CR)
SIO4,5 Transmit/Receive Interrupt Control Register (ISIO45CR)
TID1 Output Interrupt Control Register (ITID1CR)
SIO2,3 Transmit/Receive Interrupt Control Register (ISO23CR)
TOD0 Output Interrupt Control Register (ITOD0CR)
A-D0 Conversion Interrupt Control Register (IAD0CCR)
SIO0 Receive Interrupt Control Register (ISIO0RXCR)
SIO1 Receive Interrupt Control Register (ISIO1RXCR)
MJT Output Interrupt Control Register 0 (IMJTOCR0)
MJT Output Interrupt Control Register 2 (IMJTOCR2)
MJT Output Interrupt Control Register 4 (IMJTOCR4)
MJT Output Interrupt Control Register 6 (IMJTOCR6)
MJT Input Interrupt Control Register 0 (IMJTICR0)
MJT Input Interrupt Control Register 2 (IMJTICR2)
MJT Input Interrupt Control Register 4 (IMJTICR4)
A-D0 Single Mode Register 0 (AD0SIM0)
A-D0 Scan Mode Register 0 (AD0SCM0)
~
~
~
~
+0 Address +1 Address
Interrupt Mask Register (IMASK)
SBI Control Register (SBICR)
A-D0 Successive Approximation Register (AD0SAR)
A-D0 Comparate Data Register (AD0CMP)
10-bit A-D0 Data Register 0 (AD0DT0)
10-bit A-D0 Data Register 1 (AD0DT1)
10-bit A-D0 Data Register 2 (AD0DT2)
10-bit A-D0 Data Register 3 (AD0DT3)
10-bit A-D0 Data Register 4 (AD0DT4)
10-bit A-D0 Data Register 5 (AD0DT5)
10-bit A-D0 Data Register 6 (AD0DT6)
10-bit A-D0 Data Register 7 (AD0DT7)
10-bit A-D0 Data Register 8 (AD0DT8)
10-bit A-D0 Data Register 9 (AD0DT9)
10-bit A-D0 Data Register 10 (AD0DT10)
10-bit A-D0 Data Register 11 (AD0DT11)
10-bit A-D0 Data Register 12 (AD0DT12)
10-bit A-D0 Data Register 13 (AD0DT13)
10-bit A-D0 Data Register 14 (AD0DT14)
10-bit A-D0 Data Register 15 (AD0DT15)
Interrupt Vector Register (IVECT)
TML1 Input Interrupt Control Register (ITML1CR)
A-D1 Conversion Interrupt Control Register (IAD1CCR)
TOD1-TOM0 Output Interrupt Control Register (ITOM0CR)
RTD Interrupt Control Register (IRTDCR)
DMA5-9 Interrupt Control Register (IDMA59CR)
TID0 Output Interrupt Control Register (ITID0CR)
SIO0 Transmit Interrupt Control Register (ISIO0TXCR)
SIO1 Transmit Interrupt Control Register (ISIO1TXCR)
DMA0-4 Interrupt Control Register (IDMA04CR)
MJT Output Interrupt Control Register 1 (IMJTOCR1)
MJT Output Interrupt Control Register 3 (IMJTOCR3)
MJT Output Interrupt Control Register 5 (IMJTOCR5)
MJT Output Interrupt Control Register 7 (IMJTOCR7)
MJT Input Interrupt Control Register 1 (IMJTICR1)
MJT Input Interrupt Control Register 3 (IMJTICR3)
A-D0 Single Mode Register 1 (AD0SIM1)
A-D0 Scan Mode Register 1 (AD0SCM1)
8-bit A-D0 Data Register 0 (AD08DT0)
~
~
~
~
~
~
Figure 3.4.4 Register Mapping of the SFR Area (1)
3-12 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Address
H'0080 00D2
H'0080 00D4
H'0080 00D6
H'0080 00D8
H'0080 00DA
H'0080 00DC
H'0080 00DE
H'0080 00E0
H'0080 00E2
H'0080 00E4
H'0080 00E6
H'0080 00E8
H'0080 00EA
H'0080 00EC
H'0080 00EE
H'0080 0100
H'0080 0102
H'0080 0110
H'0080 0112
H'0080 0114
H'0080 0116
H'0080 0120
H'0080 0122
H'0080 0124
H'0080 0126
H'0080 0130
H'0080 0132
H'0080 0134
H'0080 0136
H'0080 0140
H'0080 0142
H'0080 0144
H'0080 0146
H'0080 0180
H'0080 0200
H'0080 0202
H'0080 0204
H'0080 0210
H'0080 0212
H'0080 0214
Blank addresses are reserved areas.
D0 D7 D8 D15
~
~
SIO23 Interrupt Status Register (SI23STAT)
SIO03 Receive Interrupt Cause Select Register (SI03SEL)
~
~
SIO0 Transmit Control Register (S0TCNT) SIO0 Transmit/Receive Mode Register (S0MOD)
SIO0 Receive Control Register (S0RCNT)
~
~
SIO1 Transmit Control Register (S1TCNT) SIO0 Transmit/Receive Mode Register (S1MOD)
SIO1 Receive Control Register (S1RCNT)
~
~
~
~
~
~
~
~
~
~
SIO2 Transmit Control Register (S2TCNT) SIO2 Transmit/Receive Mode Register (S2MOD)
SIO2 Receive Control Register (S2RCNT)
SIO3 Transmit Control Register (S3TCNT) SIO3 Transmit/Receive Mode Register (S3MOD)
SIO3 Receive Control Register (S3RCNT)
Wait Cycles Control Register (WTCCR)
+0 Address +1 Address
8-bit A-D0 Data Register 1 (AD08DT1)
8-bit A-D0 Data Register 2 (AD08DT2)
8-bit A-D0 Data Register 3 (AD08DT3)
8-bit A-D0 Data Register 4 (AD08DT4)
8-bit A-D0 Data Register 5 (AD08DT5)
8-bit A-D0 Data Register 6 (AD08DT6)
8-bit A-D0 Data Register 7 (AD08DT7)
8-bit A-D0 Data Register 8 (AD08DT8)
8-bit A-D0 Data Register 9 (AD08DT9)
8-bit A-D0 Data Register 10 (AD08DT10)
8-bit A-D0 Data Register 11 (AD08DT11)
8-bit A-D0 Data Register 12 (AD08DT12)
8-bit A-D0 Data Register 13 (AD08DT13)
8-bit A-D0 Data Register 14 (AD08DT14)
8-bit A-D0 Data Register 15 (AD08DT15)
SIO03 Interrupt Mask Register (SI03MASK)
SIO0 Transmit Buffer Register (S0TXB)
SIO0 Receive Buffer Register (S0RXB)
SIO1 Baud Rate Register (S1BAUR)
SIO1 Transmit Buffer Register (S1TXB)
SIO1 Receive Buffer Register (S1RXB)
SIO1 Baud Rate Register (S1BAUR)
SIO2 Transmit Buffer Register (S2TXB)
SIO2 Receive Buffer Register (S2RXB)
SIO2 Baud Rate Register (S2BAUR)
SIO3 Transmit Buffer Register (S3TXB)
SIO3 Receive Buffer Register (S3RXB)
SIO3 Baud Rate Register (S3BAUR)
Clock Bus & Input Event Bus Control Register (CKIEBCR)
Prescaler Register 0 (PRS0)
Prescaler Register 2 (PRS2)
TCLK Input Processing Control Register (TCLKCR)
TIN Input Processing Control Register 0 (TINCR0)
TIN Input Processing Control Register 1 (TINCR1)
Output Event Bus Control Register (OEBCR)
Prescaler Register 1 (PRS1)
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
Figure 3.4.5 Register Mapping of the SFR Area (2)
3-13 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Address
H'0080 0216
H'0080 0218
H'0080 021A
H'0080 021C
H'0080 021E
H'0080 0220
H'0080 0222
H'0080 0224
H'0080 0226
H'0080 0228
H'0080 022A
H'0080 0230
H'0080 0232
H'0080 0234
H'0080 0236
H'0080 0238
H'0080 023A
H'0080 023C
H'0080 023E
H'0080 0240
H'0080 0242
H'0080 0244
H'0080 0246
H'0080 0250
H'0080 0252
H'0080 0254
H'0080 0256
H'0080 0260
H'0080 0262
H'0080 0264
H'0080 0266
H'0080 0270
H'0080 0272
H'0080 0274
H'0080 0276
H'0080 0280
H'0080 0282
H'0080 0284
H'0080 0286
H'0080 0290
H'0080 0292
H'0080 0294
Blank addresses are reserved areas.
D0 D7 D8 D15
~
~
TOP Interrupt Control Register 0 (TOPIR0)
TOP Interrupt Control Register 2 (TOPIR2)
TIO Interrupt Control Register 0 (TIOIR0)
TIO Interrupt Control Register 2 (TIOIR2)
TIN Interrupt Control Register 0 (TINIR0)
TIN Interrupt Control Register 2 (TINIR2)
TIN Interrupt Control Register 4 (TINIR4)
TIN Interrupt Control Register 6 (TINIR6)
~
~
~
~
~
~
~
~
~
~
+0 Address +1 Address
TIN Input Processing Control Register 2 (TINCR2)
TIN Input Processing Control Register 3 (TINCR3)
TIN Input Processing Control Register 4 (TINCR4)
F/F Source Select Register 0 (FFS0)
F/F Source Select Register 1 (FFS1)
F/F Protect Register 0 (FFP0)
F/F Data Register 0 (FFD0)
F/F Protect Register 1 (FFP1)
F/F Data Register 1 (FFD1)
TOP Interrupt Control Register 1 (TOPIR1)
TOP Interrupt Control Register 3 (TOPIR3)
TIO Interrupt Control Register 1 (TIOIR1)
TMS Interrupt Control Register (TMSIR)
TIN Interrupt Control Register 1 (TINIR1)
TIN Interrupt Control Register 3 (TINIR3)
TIN Interrupt Control Register 5 (TINIR5)
TIN Interrupt Control Register 7 (TINIR7)
TOP0 Counter (TOP0CT)
TOP0 Reload Register (TOP0RL)
TOP0 Correction Register (TOP0CC)
TOP1 Counter (TOP1CT)
TOP1 Reload Register (TOP1RL)
TOP1 Correction Register (TOP1CC)
TOP2 Counter (TOP2CT)
TOP2 Reload Register (TOP2RL)
TOP2 Correction Register (TOP2CC)
TOP3 Counter (TOP3CT)
TOP3 Reload Register (TOP3RL)
TOP3 Correction Register (TOP3CC)
TOP4 Counter (TOP4CT)
TOP4 Reload Register (TOP4RL)
TOP4 Correction Register (TOP4CC)
TOP5 Counter (TOP5CT)
TOP5 Reload Register (TOP5RL)
~
~
~
~
~
~
~
~
~
~
~
~
Figure 3.4.6 Register Mapping of the SFR Area (3)
3-14 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Address
H'0080 0296
H'0080 0298
H'0080 029A
H'0080 029C
H'0080 029E
H'0080 02A0
H'0080 02A2
H'0080 02A4
H'0080 02A6
H'0080 02A8
H'0080 02AA
H'0080 02B0
H'0080 02B2
H'0080 02B4
H'0080 02B6
H'0080 02C0
H'0080 02C2
H'0080 02C4
H'0080 02C6
H'0080 02D0
H'0080 02D2
H'0080 02D4
H'0080 02D6
H'0080 02E0
H'0080 02E2
H'0080 02E4
H'0080 02E6
H'0080 02E8
H'0080 02EA
H'0080 02FA
H'0080 02FC
H'0080 02FE
H'0080 0300
H'0080 0302
H'0080 0304
H'0080 0306
H'0080 0310
H'0080 0312
H'0080 0314
H'0080 0316
H'0080 0318
H'0080 031A
Blank addresses are reserved areas.
D0 D7 D8 D15
~
~
~
~
~
~
~
~
~
~
~
~
+0 Address +1 Address
TOP5 Correction Register (TOP5CC)
TOP0-5 Control Register 0 (TOP05CR0)
TOP0-5 Control Register 1 (TOP05CR1)
TOP6 Counter (TOP6CT)
TOP6 Reload Register (TOP6RL)
TOP6 Correction Register (TOP6CC)
TOP6, 7 Control Register (TOP67CR)
TOP7 Counter (TOP7CT)
TOP7 Reload Register (TOP7RL)
TOP7 Correction Register (TOP7CC)
TOP8Counter (TOP8CT)
TOP8 Reload Register (TOP8RL)
TOP8 Correction Register (TOP8CC)
TOP9 Counter (TOP9CT)
TOP9 Reload Register (TOP9RL)
TOP9 Correction Register (TOP9CC)
TOP10 Counter (TOP10CT)
TOP10 Reload Register (TOP10RL)
TOP10 Correction Register (TOP10CC)
TOP8-10 Control Register (TOP810CR)
TOP0-10 External Enable Register (TOPEEN)
TOP0-10 Enable Protect Register (TOPPRO)
TOP0-10 Count Enable Register (TOPCEN)
TIO0 Counter (TIO0CT)
TIO0 Reload Register (TIO0RL)
TIO0 Reload 0/Measure Register (TIO0RL0)
TIO1 Counter (TIO1CT)
TIO1 Reload Register (TIO1RL)
TIO1 Reload 0/Measure Register (TIO1RL0)
TIO0-3 Control Register 0 (TIO03CR0)
~
~
~
~
~
~
~
~
~
~
~
~
Figure 3.4.7 Register Mapping of the SFR Area (4)
3-15 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Address
H'0080 031C
H'0080 0320
H'0080 0322
H'0080 0324
H'0080 0326
H'0080 0330
H'0080 0332
H'0080 0334
H'0080 0336
H'0080 0340
H'0080 0342
H'0080 0344
H'0080 0346
H'0080 0348
H'0080 034A
H'0080 0350
H'0080 0352
H'0080 0354
H'0080 0356
H'0080 0360
H'0080 0362
H'0080 0364
H'0080 0366
H'0080 0368
H'0080 036A
H'0080 0370
H'0080 0372
H'0080 0374
H'0080 0376
H'0080 0380
H'0080 0382
H'0080 0384
H'0080 0386
H'0080 0388
H'0080 038A
H'0080 0390
H'0080 0392
H'0080 0394
H'0080 0396
Blank addresses are reserved areas.
D0 D7 D8 D15
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
+0 Address +1 Address
TIO0-3 Control Register 1 (TIO03CR1)
TIO2 Counter (TIO2CT)
TIO2 Reload 1 Register (TIO2RL1)
TIO2 Reload 0/Measure Register (TIO2RL0)
TIO3 Counter (TIO3CT)
TIO3 Reload 1 Register (TIO3RL1)
TIO3 Reload 0/Measure Register (TIO3RL0)
TIO4 Counter (TIO4CT)
TIO4 Reload 1 Register (TIO4RL1)
TIO4 Reload 0/Measure Register (TIO4RL0)
TIO4 Control Register (TIO4CR)
TIO5 Counter (TIO5CT)
TIO5 Reload 1 Register (TIO5RL1)
TIO5 Reload 0/Measure Register (TIO5RL0)
TIO6 Counter (TIO6CT)
TIO6 Reload 1 Register (TIO6RL1)
TIO6 Reload 0/Measure Register (TIO6RL0)
TIO6 Control Register (TIO6CR) TIO7 Control Register (TIO7CR)
TIO7 Counter (TIO7CT)
TIO7 Reload 1 Register (TIO7RL1)
TIO7 Reload 0/Measure Register (TIO7RL0)
TIO8 Counter (TIO8CT)
TIO8 Reload 1 Register (TIO8RL1)
TIO8 Reload 0/Measure Register (TIO8RL0)
TIO8 Control Register (TIO8CR) TIO9 Control Register (TIO9CR)
TIO9 Counter (TIO9CT)
TIO9 Reload 1 Register (TIO9RL1)
TIO9 Reload 0/Measure Register (TIO9RL0)
TIO5 Control Register (TIO5CR)
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
Figure 3.4.8 Register Mapping of the SFR Area (5)
3-16 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
D0 D7 D8 D15
H'0080 03BC
H'0080 03BE
H'0080 03C0
H'0080 03C2
H'0080 03C4
H'0080 03C6
H'0080 03C8
H'0080 03CA
~
H'0080 03D0
H'0080 03D2
H'0080 03D4
H'0080 03D6
H'0080 03D8
H'0080 03E0
H'0080 03E2
H'0080 03EA
H'0080 03F0
H'0080 03F2
H'0080 03F4
H'0080 03F6
H'0080 03F8
H'0080 03FA
H'0080 03FC
H'0080 03FE
H'0080 0400
H'0080 0408
H'0080 0410
H'0080 0412
H'0080 0414
H'0080 0416
H'0080 0418
H'0080 041A
H'0080 041C
H'0080 041E
H'0080 0420
H'0080 0422
H'0080 0424
H'0080 0426
H'0080 0428
H'0080 042A
H'0080 042C
H'0080 042E
~
~
~
~
~
~
~
DMA0-4 Interrupt Request Status Register (DM04ITST)
~
~
~
~
DMA0 Channel Control Register (DM0CNT)
DMA5 Channel Control Register (DM5CNT)
DMA1 Channel Control Register (DM1CNT)
DMA6 Channel Control Register (DM6CNT)
Blank addresses are reserved areas.
+0 Address +1 AddressAddress
TIO0-9 Enable Protect Register (TIOPRO)
TIO0-9 Count Enable Register (TIOCEN)
TMS0 Measure 3 Register (TMS0MR3)
TMS0 Measure 2 Register (TMS0MR2)
TMS0 Measure 1 Register (TMS0MR1)
TMS0 Measure 0 Register (TMS0MR0)
TMS0 Control Register (TMS0CR)
TMS1 Measure 3 Register (TMS1MR3)
TMS1 Measure 2 Register (TMS1MR2)
TMS1 Measure 1 Register (TMS1MR1)
TMS1 Measure 0 Register (TMS1MR0)
TML0 Measure 3 Register, High (TML0MR3H)
TML0 Measure 3 Register, Low (TML0MR3L)
TML0 Measure 2 Register, High (TML0MR2H)
TML0 Measure 2 Register, Low (TML0MR2L)
TML0 Measure 1 Register, High (TML0MR1H)
TML0 Measure 1 Register, Low (TML0MR1L)
TML0 Measure 0 Register, High (TML0MR0H)
TML0 Measure 0 Register, Low (TML0MR0L)
DMA0 Source Address Register (DM0SA)
DMA0 Destination Address Register (DM0DA)
DMA5 Source Address Register (DM5SA)
DMA5 Destination Address Register (DM5DA)
DMA1 Source Address Register (DM1SA)
DMA1 Destination Address Register (DM1DA)
DMA6 Source Address Register (DM6SA)
DMA6 Destination Address Register (DM6DA)
TMS0 Counter (TMS0CT)
TMS1 Counter (TMS1CT)
TML0 Counter, High (TML0CTH)
TML0 Counter, Low (TML0CTL)
DMA0-4 Interrupt Mask Register (DM04ITMK)
DMA5-9 Interrupt Mask Register (DM59ITMK)DMA5-9 Interrupt Request Status Register (DM59ITST)
DMA0 Transfer Count Register (DM0TCT)
DMA5 Transfer Count Register (DM5TCT)
DMA1 Transfer Count Register (DM1TCT)
DMA6 Transfer Count Register (DM6TCT)
TMS1 Control Register (TMS1CR)
TML0 Control Register (TML0CR)
~
~
~
~
~
~
~
~
~
~
~
~
Figure 3.4.9 Register Mapping of the SFR Area (6)
3-17 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
D0 D7 D8 D15
H'0080 0430
H'0080 0432
H'0080 0434
H'0080 0436
H'0080 0438
H'0080 043A
H'0080 043C
H'0080 043E
H'0080 0440
H'0080 0442
H'0080 0444
H'0080 0446
H'0080 0448
H'0080 044A
H'0080 044C
H'0080 044E
H'0080 0450
H'0080 0452
H'0080 0454
H'0080 0456
H'0080 0458
H'0080 045A
H'0080 045C
H'0080 045E
H'0080 0460
H'0080 0462
H'0080 0464
H'0080 0466
H'0080 0468
~
~
H'0080 0470
H'0080 0472
H'0080 0474
H'0080 0476
H'0080 0478
~
~
H'0080 0700
H'0080 0702
H'0080 0704
H'0080 0706
H'0080 0708
H'0080 070A
H'0080 070C
H'0080 070E
H'0080 0710
H'0080 0712
H'0080 0714
Blank addresses are reserved areas.
DMA2 Channel Control Register (DM2CNT)
DMA7 Channel Control Register (DM7CNT)
DMA3 Channel Control Register (DM3CNT)
DMA8 Channel Control Register (DM8CNT)
DMA4 Channel Control Register (DM4CNT)
DMA9 Channel Control Register (DM9CNT)
+0 Address +1 AddressAddress
DMA2 Source Address Register (DM2SA)
DMA2 Destination Address Register (DM2DA)
DMA7 Source Address Register (DM7SA)
DMA7 Destination Address Register (DM7DA)
DMA3 Source Address Register (DM3SA)
DMA3 Destination Address Register (DM3DA)
DMA8 Source Address Register (DM8SA)
DMA8 Destination Address Register (DM8DA)
DMA4 Source Address Register (DM4SA)
DMA4 Destination Address Register (DM4DA)
DMA9 Source Address Register (DM9SA)
DMA9 Destination Address Register (DM9DA)
DMA0 Software Request Generation Register (DM0SRI)
DMA1 Software Request Generation Register (DM1SRI)
DMA2 Software Request Generation Register (DM2SRI)
DMA3 Software Request Generation Register (DM3SRI)
DMA4 Software Request Generation Register (DM4SRI)
DMA5 Software Request Generation Register (DM5SRI)
DMA6 Software Request Generation Register (DM6SRI)
DMA7 Software Request Generation Register (DM7SRI)
DMA8 Software Request Generation Register (DM8SRI)
DMA9 Software Request Generation Register (DM9SRI)
P0 Data Register (P0DATA)
P2 Data Register (P2DATA)
P4 Data Register (P4DATA)
P6 Data Register (P6DATA)
P8 Data Register (P8DATA)
P10 Data Register (P10DATA)
P12 Data Register (P12DATA)
P14 Data Register (P14DATA)
P16 Data Register (P16DATA)
P18 Data Register (P18DATA)
P20 Data Register (P20DATA)
DMA2 Transfer Count Register (DM2TCT)
DMA7 Transfer Count Register (DM7TCT)
DMA3 Transfer Count Register (DM3TCT)
DMA8 Transfer Count Register (DM8TCT)
DMA4 Transfer Count Register (DM4TCT)
DMA9 Transfer Count Register (DM9TCT)
P1 Data Register (P1DATA)
P3 Data Register (P3DATA)
P7 Data Register (P7DATA)
P9 Data Register (P9DATA)
P11Data Register (P11DATA)
P13 Data Register (P13DATA)
P15 Data Register (P15DATA)
P17 Data Register (P17DATA)
P19 Data Register (P19DATA)
P21 Data Register (P21DATA)
~
~
~
~
Figure 3.4.10 Register Mapping of the SFR Area (7)
3-18 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Address
H'0080 0716
H'0080 0720
H'0080 0722
H'0080 0724
H'0080 0726
H'0080 0728
H'0080 072A
H'0080 072C
H'0080 072E
H'0080 0730
H'0080 0732
H'0080 0734
H'0080 0736
H'0080 0744
H'0080 0746
H'0080 0748
H'0080 074A
H'0080 074C
H'0080 074E
H'0080 0750
H'0080 0752
H'0080 0754
H'0080 0756
H'0080 077E
H'0080 078C
H'0080 078E
H'0080 0790
H'0080 0792
H'0080 0794
H'0080 0796
H'0080 0798
H'0080 079A
H'0080 079C
H'0080 079E
H'0080 07A0
H'0080 07A2
H'0080 07A4
H'0080 07A6
H'0080 07A8
H'0080 07AA
H'0080 07AC
H'0080 07AE
Blank addresses are reserved areas.
D0 D7 D8 D15
~
~
~
~
P6 Operation Mode Register (P6MOD)
P8 Operation Mode Register (P8MOD)
P10 Operation Mode Register (P10MOD)
P12 Operation Mode Register (P12MOD)
P14 Operation Mode Register (P14MOD)
P16 Operation Mode Register (P16MOD)
P18 Operation Mode Register (P18MOD)
P20 Operation Mode Register (P20MOD)
P22 Operation Mode Register (P22MOD)
~
~
~
~
+0 Address +1 Address
P22 Data Register (P22DATA)
P0 Direction Register (P0DIR)
P2 Direction Register (P2DIR)
P4 Direction Register (P4DIR)
P6 Direction Register (P6DIR)
P8 Direction Register (P8DIR)
P10 Direction Register (P10DIR)
P12 Direction Register (P12DIR)
P14 Direction Register (P14DIR)
P16 Direction Register (P16DIR)
P18 Direction Register (P18DIR)
P20 Direction Register (P20DIR)
P22 Direction Register (P22DIR)
P1 Direction Register (P1DIR)
P3 Direction Register (P3DIR)
P7 Direction Register (P7DIR)
P9 Direction Register (P9DIR)
P11 Direction Register (P11DIR)
P13 Direction Register (P13DIR)
P15 Direction Register (P15DIR)
P17 Direction Register (P17DIR)
P19 Direction Register (P19DIR)
P21 Direction Register (P21DIR)
Port Input Function Enable Register (PIEN)
P7 Operation Mode Register (P7MOD)
P9 Operation Mode Register (P9MOD)
P11 Operation Mode Register (P11MOD)
P13 Operation Mode Register (P13MOD)
P15 Operation Mode Register (P15MOD)
P17 Operation Mode Register (P17MOD)
P19 Operation Mode Register (P19MOD)
P21 Operation Mode Register (P21MOD)
Bus Mode Control Register (BUSMODC)
TID0 Counter (TID0CT)
TID0 Reload Register (TID0RL)
TOD0_0 Counter (TOD00CT)
TOD0_0 Reload 1 Register (TOD00RL1)
TOD0_0 Reload 0 Register (TOD00RL0)
TOD0_1 Counter (TOD01CT)
TOD0_1 Reload 1 Register (TOD01RL1)
TOD0_0 Reload 0 Register (TOD01RL0)
TOD0_2 Counter (TOD02CT)
TOD0_2 Reload 1 Register (TOD02RL1)
TOD0_2 Reload 0 Register (TOD02RL0)
TOD0_3 Counter (TOD03CT)
TOD0_3 Reload 1 Register (TOD03RL1)
TOD0_3 Reload 0 Register (TOD03RL0)
~
~
~
~
~
~
~
~
Figure 3.4.11 Register Mapping of the SFR Area (8)
3-19 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
D0 D7 D8 D15
H'0080 07B0
H'0080 07B2
H'0080 07B4
H'0080 07B6
H'0080 07B8
H'0080 07BA
H'0080 07BC
H'0080 07BE
H'0080 07C0
H'0080 07C2
H'0080 07C4
H'0080 07C6
H'0080 07C8
H'0080 07CA
H'0080 07CC
H'0080 07CE
H'0080 07D0
H'0080 07D2
H'0080 07D4
H'0080 07D6
H'0080 07D8
H'0080 07DA
H'0080 07DC
H'0080 07DE
H'0080 07E0
H'0080 07E2
H'0080 07E4
H'0080 07E6
H'0080 07E8
H'0080 07EA
H'0080 07EC
H'0080 07EE
H'0080 07F0
H'0080 07F2
~
H'0080 0A00
H'0080 0A02
H'0080 0A10
H'0080 0A12
H'0080 0A14
H'0080 0A16
H'0080 0A20
H'0080 0A22
H'0080 0A24
H'0080 0A26
~
~
~
~
~
Blank addresses are reserved areas.
TOD0 Interrupt Mask Register (TOD0IMA)
SIO45 Interrupt Status Register (SI45STAT)
SIO45 Receive Interrupt Cause Select Register (SI45SEL)
SIO4 Transmit Control Register (S4TCNT)
SIO4 Receive Control Register (S4RCNT)
SIO5 Transmit Control Register (S5RCNT)
SIO5 Receive Control Register (S5RCNT)
+0 Address +1 AddressAddress
TOD0_4 Counter (TOD04CT)
TOD0_4 Reload 1 Register (TOD04RL1)
TOD0_4 Reload 0 Register (TOD04RL0)
TOD0_5 Counter (TOD05CT)
TOD0_5 Reload 1 Register (TOD05RL1)
TOD0_5 Reload 0 Register (TOD05RL0)
TOD0_6 Counter (TOD06CT)
TOD0_6 Reload 1 Register (TOD06RL1)
TOD0_6 Reload 0 Register (TOD06RL0)
TOD0_7 Counter (TOD07CT)
TOD0_7 Reload 1 Register (TOD07RL1)
TOD0_7 Reload 0 Register (TOD07RL0)
Prescaler Register 3 (PRS3) TID0 Control & Prescaler 3 Enable Register (TID0PRES3EN)
TOD0 Interrupt Status Register (TOD0IST)
F/F Protect Register 2 (FFP2)
F/F Data Register 2 (FFD2)
TOD0 Control Register (TOD0CR)
TOD0 Enable Protect Register (TOD0PRO)
TOD0 Count Enable Register (TOD0CEN)
Flash Mode Register (FMOD)
Flash Control Register 1 (FCNT1)
Flash Control Register 3 (FCNT3)
Pseudo-flash L Bank Register 0 (FELBANK0)
Pseudo-flash L Bank Register 1 (FELBANK1)
Pseudo-flash L Bank Register 2 (FELBANK2)
Pseudo-flash L Bank Register 3 (FELBANK3)
Pseudo-flash S Bank Register 0 (FESBANK0)
Pseudo-flash S Bank Register 1 (FESBANK1)
SIO4 Transmit Buffer Register (S4TXB)
SIO4 Receive Buffer Register (S4RXB)
SIO5 Transmit Buffer Register (S5TXB)
SIO5 Receive Buffer Register (S5RXB)
Flash Status Register 1 (FSTAT1)
Flash Control Register 2 (FCNT2)
Flash Control Register 4 (FCNT4)
SIO45 Interrupt Mask Register (SI45MASK)
SIO4 Transmit/Receive Mode Register (S4MOD)
SIO4 Baud Rate Register (S4BAUR)
SIO5 Transmit/Receive Mode Register (S5MOD)
SIO5 Baud Rate Register (S5BAUR)
~
~
~
~
~
~
Figure 3.4.12 Register Mapping of the SFR Area (9)
3-20 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
D0 D7 D8 D15
H'0080 0A80
H'0080 0A82
H'0080 0A84
H'0080 0A86
H'0080 0A88
H'0080 0A8A
H'0080 0A8C
~
~
H'0080 0A90
H'0080 0A92
H'0080 0A94
H'0080 0A96
H'0080 0A98
H'0080 0A9A
H'0080 0A9C
H'0080 0A9E
H'0080 0AA0
H'0080 0AA2
H'0080 0AA4
H'0080 0AA6
H'0080 0AA8
H'0080 0AAA
H'0080 0AAC
H'0080 0AAE
~
~
H'0080 0AD0
H'0080 0AD2
H'0080 0AD4
H'0080 0AD6
H'0080 0AD8
H'0080 0ADA
H'0080 0ADC
H'0080 0ADE
H'0080 0AE0
H'0080 0AE2
H'0080 0AE4
H'0080 0AE6
H'0080 0AE8
H'0080 0AEA
H'0080 0AEC
H'0080 0AEE
~
H'0080 0B8C
H'0080 0B8E
H'0080 0B90
H'0080 0B92
H'0080 0B94
~
Blank addresses are reserved areas.
A-D1 Single Mode Register 0 (AD1SIM0)
A-D1 Scan Mode Register 0 (AD1SCM0)
+0 Address +1 AddressAddress
A-D1 Successive Approximation Register (AD1SAR)
A-D1 Comparate Data Register (AD1CMP)
10-bit A-D1 Data Register 0 (AD1DT0)
10-bit A-D1 Data Register 1 (AD1DT1)
10-bit A-D1 Data Register 2 (AD1DT2)
10-bit A-D1 Data Register 3 (AD1DT3)
10-bit A-D1 Data Register 4 (AD1DT4)
10-bit A-D1 Data Register 5 (AD1DT5)
10-bit A-D1 Data Register 6 (AD1DT6)
10-bit A-D1 Data Register 7 (AD1DT7)
10-bit A-D1 Data Register 8 (AD1DT8)
10-bit A-D1 Data Register 9 (AD1DT9)
10-bit A-D1 Data Register 10 (AD1DT10)
10-bit A-D1 Data Register 11 (AD1DT11)
10-bit A-D1 Data Register 12 (AD1DT12)
10-bit A-D1 Data Register 13 (AD1DT13)
10-bit A-D1 Data Register 14 (AD1DT14)
10-bit A-D1 Data Register 15 (AD1DT15)
TID1 Counter (TID1CT)
TID1 Reload Register (TID1RL)
TOD1_0 Counter (TOD10CT)
TOD1_0 Reload 1 Register (TOD10RL1)
A-D1 Single Mode Register 1 (AD1SIM1)
A-D1 Scan Mode Register 1 (AD1SCM1)
8-bit A-D1 Data Register 0 (AD18DT0)
8-bit A-D1 Data Register 1 (AD18DT1)
8-bit A-D1 Data Register 2 (AD18DT2)
8-bit A-D1 Data Register 3 (AD18DT3)
8-bit A-D1 Data Register 4 (AD18DT4)
8-bit A-D1 Data Register 5 (AD18DT5)
8-bit A-D1 Data Register 6 (AD18DT6)
8-bit A-D1 Data Register 7 (AD18DT7)
8-bit A-D1 Data Register 8 (AD18DT8)
8-bit A-D1 Data Register 9 (AD18DT9)
8-bit A-D1 Data Register 10 (AD18DT10)
8-bit A-D1 Data Register 11 (AD18DT11)
8-bit A-D1 Data Register 12 (AD18DT12)
8-bit A-D1 Data Register 13 (AD18DT13)
8-bit A-D1 Data Register 14 (AD18DT14)
8-bit A-D1 Data Register 15 (AD18DT15)
~
~
~
~
~
~
Figure 3.4.13 Register Mapping of the SFR Area (10)
3-21 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
Address
H'0080 0B96
H'0080 0B98
H'0080 0B9A
H'0080 0B9C
H'0080 0B9E
H'0080 0BA0
H'0080 0BA2
H'0080 0BA4
H'0080 0BA6
H'0080 0BA8
H'0080 0BAA
H'0080 0BAC
H'0080 0BAE
H'0080 0BB0
H'0080 0BB2
H'0080 0BB4
H'0080 0BB6
H'0080 0BB8
H'0080 0BBA
H'0080 0BBC
H'0080 0BBE
H'0080 0BC0
H'0080 0BC2
H'0080 0BC4
H'0080 0BC6
H'0080 0BC8
H'0080 0BCA
H'0080 0BCC
H'0080 0BCE
H'0080 0BD0
H'0080 0BD2
H'0080 0BD4
H'0080 0BD6
H'0080 0BD8
H'0080 0BDA
H'0080 0BDC
H'0080 0BDE
H'0080 0C8C
H'0080 0C8E
H'0080 0C90
H'0080 0C92
H'0080 0C94
H'0080 0C96
H'0080 0C98
H'0080 0C9A
H'0080 0C9C
Blank addresses are reserved areas.
D0 D7 D8 D15
TOD1 Interrupt Mask Register (TOD1IMA)
~
~
+0 Address +1 Address
TOD1_0 Reload 0 Register (TOD10RL0)
TOD1_1 Counter (TOD11CT)
TOD1_1 Reload 1 Register (TOD11RL1)
TOD1_1 Reload 0 Register (TOD11RL0)
TOD1_2 Counter (TOD12CT)
TOD1_2 Reload 1 Register (TOD12RL1)
TOD1_2 Reload 0 Register (TOD12RL0)
TOD1_3 Counter (TOD13CT)
TOD1_3 Reload 1 Register (TOD13RL1)
TOD1_3 Reload 0 Register (TOD13RL0)
TOD1_4 Counter (TOD14CT)
TOD1_4 Reload 1 Register (TOD14RL1)
TOD1_4 Reload 0 Register (TOD14RL0)
TOD1_5 Counter (TOD15CT)
TOD1_5 Reload 1 Register (TOD15RL1)
TOD1_5 Reload 0 Register (TOD15RL0)
TOD1_6 Counter (TOD16CT)
TOD1_6 Reload 1 Register (TOD16RL1)
TOD1_6 Reload 0 Register (TOD16RL0)
TOD1_7 Counter (TOD17CT)
TOD1_7 Reload 1 Register (TOD17RL1)
TOD1_7 Reload 0 Register (TOD17RL0)
Prescaler Register 4 (PRS4)
TOD1 Control Register (TOD1CR)
TID2 Counter (TID2CT)
TID2 Reload Register (TID2RL)
TOM0_0 Counter (TOM00CT)
TOM0_0 Reload 1 Register (TOM00RL1)
TOM0_0 Reload 0 Register (TOM00RL0)
TOM0_1 Counter (TOM01CT)
TOM0_1 Reload 1 Register (TOM01RL1)
TID1 Control & Prescaler 4 Enable Register (TID1PRS4EN)
TOD1 Interrupt Status Register (TOD1IST)
TOD1 Enable Protect Register (TOD1PRO)
TOD1 Count Enable Register (TOD1CEN)
F/F Protect Register 3 (FFP3)
F/F Data Register 3 (FFD3)
~
~
Figure 3.4.14 Register Mapping of the SFR Area (11)
3-22 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
D0 D7 D8 D15
H'0080 0C9E
H'0080 0CA0
H'0080 0CA2
H'0080 0CA4
H'0080 0CA6
H'0080 0CA8
H'0080 0CAA
H'0080 0CAC
H'0080 0CAE
H'0080 0CB0
H'0080 0CB2
H'0080 0CB4
H'0080 0CB6
H'0080 0CB8
H'0080 0CBA
H'0080 0CBC
H'0080 0CBE
H'0080 0CC0
H'0080 0CC2
H'0080 0CC4
H'0080 0CC6
H'0080 0CC8
H'0080 0CCA
H'0080 0CCC
H'0080 0CCE
H'0080 0CD0
H'0080 0CD2
H'0080 0CD4
H'0080 0CD6
H'0080 0CD8
H'0080 0CDA
H'0080 0CDC
H'0080 0CDE
~
H'0080 0FE0
H'0080 0FE2
H'0080 0FEA
H'0080 0FF0
H'0080 0FF2
H'0080 0FF4
H'0080 0FF6
H'0080 0FF8
H'0080 0FFA
H'0080 0FFC
H'0080 0FFE
~
~
~
~
~
Blank addresses are reserved areas.
TOM0 Interrupt Mask Register (TOM0IMA)
+0 Address +1 AddressAddress
Prescaler Register 5 (PRS5)
TOM0_1 Reload 0 Register (TOM01RL0)
TOM0_2 Counter (TOM02CT)
TOM0_2 Reload 1 Register (TOM02RL1)
TOM0_2 Reload 0 Register (TOM02RL0)
TOM0_3 Counter (TOM03CT)
TOM0_3 Reload 1 Register (TOM03RL1)
TOM0_3 Reload 0 Register (TOM03RL0)
TOM0_4 Counter (TOM04CT)
TOM0_4 Reload 1 Register (TOM04RL1)
TOM0_4 Reload 0 Register (TOM04RL0)
TOM0_5 Counter (TOM05CT)
TOM0_5 Reload 1 Register (TOM05RL1)
TOM0_5 Reload 0 Register (TOM05RL0)
TOM0_6 Counter (TOM06CT)
TOM0_6 Reload 1 Register (TOM06RL1)
TOM0_6 Reload 0 Register (TOM06RL0)
TOM0_7 Counter (TOM07CT)
TOM0_7 Reload 1 Register (TOM07RL1)
TOM0_7 Reload 0 Register (TOM07RL0)
TID2 Control & Prescaler 5 Enable Register (TID2PRS5EN)
TOM0 Interrupt Status Register (TOM0IST)
F/F Protect Register 4 (FFP4)
F/F Data Register 4 (FFD4)
TOM0 Control Register (TOM0CR)
TOM0 Enable Protect Register (TOM0PRO)
TOM0 Count Enable Register (TOM0CEN)
TML1 Counter, High (TML1CTH)
TML1 Counter, Low (TML1CTL)
TML1 Control Register (TML1CR)
TML1 Measure 3 Register, High (TML1MR3H)
TML1 Measure 3 Register, Low (TML1MR3L)
TML1 Measure 2 Register, High (TML1MR2H)
TML1 Measure 2 Register, Low (TML1MR2L)
TML1 Measure 1 Register, High (TML1MR1H)
TML1 Measure 1 Register, Low (TML1MR1L)
TML1 Measure 0 Register, High (TML1MR0H)
TML1 Measure 0 Register, Low (TML1MR0L)
~
~
~
~
~
~
Figure 3.4.15 Register Mapping of the SFR Area (12)
3-23 Ver.0.10
3
D0 D7 D8 D15
H'0080 1000
H'0080 1002
H'0080 1004
H'0080 1006
H'0080 1008
H'0080 100A
H'0080 100C
H'0080 100E
H'0080 1010
H'0080 1012
H'0080 1014
H'0080 1016
H'0080 1028
H'0080 102A
H'0080 102C
H'0080 102E
H'0080 1030
H'0080 1032
H'0080 1034
H'0080 1036
H'0080 1038
H'0080 103A
H'0080 103C
H'0080 1050
H'0080 1052
H'0080 1054
H'0080 1056
H'0080 1058
H'0080 105A
H'0080 105C
H'0080 105E
Blank addresses are reserved areas.
CAN0 Receive Error Count Register (CAN0REC)
CAN0 Error Interrupt Status Register (CAN0ERIST)
CAN0 Baud Rate Prescaler (CAN0BRP)
~
~
CAN0 Global Mask Register Standard ID0 (C0GMSKS0)
CAN0 Global Mask Register Extended ID0 (C0GMSKE0) CAN0 Global Mask Register Extended ID1 (C0GMSKE1)
CAN0 Global Mask Register Extended ID2 (C0GMSKE2)
CAN0 Local Mask Register A Standard ID0 (C0LMSKAS0)
CAN0 Local Mask Register A Extended ID0 (C0LMSKAE0) CAN0 Local Mask Register A Extended ID1 (C0LMSKAE1)
CAN0 Local Mask Register A Extended ID2 (C0LMSKAE2)
CAN0 Local Mask Register B Standard ID0 (C0LMSKBS0) CAN0 Local Mask Register B Standard ID0 (C0LMSKBS1)
CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0) CAN0 Local Mask Register B Extended ID0 (C0LMSKBE1)
CAN0 Local Mask Register B Extended ID0 (C0LMSKBE0)
~
~
CAN0 Message Slot 0 Control Register (C0MSL0CNT)
CAN0 Message Slot 4 Control Register (C0MSL4CNT)
CAN0 Message Slot 6 Control Register (C0MSL6CNT)
CAN0 Message Slot 8 Control Register (C0MSL8CNT)
CAN0 Message Slot 10 Control Register (C0MSL10CNT)
CAN0 Message Slot 12 Control Register (C0MSL12CNT)
CAN0 Message Slot 14 Control Register (C0MSL14CNT)
+0 Address +1 AddressAddress
CAN0 Control Register (CAN0CNT)
CAN0 Status Register (CAN0STAT)
CAN0 Extension ID Register (CAN0EXTID)
CAN0 Configuration Register (CAN0CONF)
CAN0 Time Stamp Count Register (CAN0TSTMP)
CAN0 Slot Interrupt Status Register (CAN0SLIST)
CAN0 Slot Interrupt Mask Register (CAN0SLIMK)
ADDRESS SPACE
3.4 Internal ROM/SFR Area
CAN0 Transmit Error Count Register (CAN0TEC)
CAN0 Error Interrupt Mask Register (CAN0ERIMK)
CAN0 Global Mask Register Standard ID1 (C0GMSKS1)
CAN0 Local Mask Register A Standard ID1 (C0LMSKAS1)
CAN0 Message Slot 1 Control Register (C0MSL1CNT)
CAN0 Message Slot 3 Control Register (C0MSL3CNT)CAN0 Message Slot 2 Control Register (C0MSL2CNT)
CAN0 Message Slot 5 Control Register (C0MSL5CNT)
CAN0 Message Slot 7 Control Register (C0MSL7CNT)
CAN0 Message Slot 9 Control Register (C0MSL9CNT)
CAN0 Message Slot 11 Control Register (C0MSL11CNT)
CAN0 Message Slot 13 Control Register (C0MSL13CNT)
CAN0 Message Slot 15 Control Register (C0MSL15CNT)
~
~
~
~
Figure 3.4.16 Register Mapping of the SFR Area (13)
3-24 Ver.0.10
3
D0 D7 D8 D15
H'0080 1100
H'0080 1102
H'0080 1104
H'0080 1106
H'0080 1108
H'0080 110A
H'0080 110C
H'0080 110E
H'0080 1110
H'0080 1112
H'0080 1114
H'0080 1116
H'0080 1118
H'0080 111A
H'0080 111C
H'0080 111E
H'0080 1120
H'0080 1122
H'0080 1124
H'0080 1126
H'0080 1128
H'0080 112A
H'0080 112C
H'0080 112E
H'0080 1130
H'0080 1132
H'0080 1134
H'0080 1136
H'0080 1138
H'0080 113A
H'0080 113C
H'0080 113E
H'0080 1140
H'0080 1142
H'0080 1144
H'0080 1146
H'0080 1148
H'0080 114A
H'0080 114C
H'0080 114E
H'0080 1150
H'0080 1152
Blank addresses are reserved areas.
CAN0 Message Slot 0 Standard ID0 (C0MSL0SID0)
CAN0 Message Slot 0 Extended ID0 (C0MSL0EID0)
CAN0 Message Slot 0 Extended ID2 (C0MSL0EID2)
CAN0 Message Slot 0 Data 0 (C0MSL0DT0)
CAN0 Message Slot 0 Data 2 (C0MSL0DT2)
CAN0 Message Slot 0 Data 4 (C0MSL0DT4)
CAN0 Message Slot 0 Data 6 (C0MSL0DT6)
CAN0 Message Slot 1 Standard ID0 (C0MSL1SID0)
CAN0 Message Slot 1 Extended ID0 (C0MSL1EID0)
CAN0 Message Slot 1 Extended ID2 (C0MSL1EID2)
CAN0 Message Slot 1 Data 0 (C0MSL1DT0)
CAN0 Message Slot 1 Data 2 (C0MSL1DT2)
CAN0 Message Slot 1 Data 4 (C0MSL1DT4)
CAN0 Message Slot 1 Data 6 (C0MSL1DT6)
CAN0 Message Slot 2 Standard ID0 (C0MSL2SID0)
CAN0 Message Slot 2 Extended ID0 (C0MSL2EID0)
CAN0 Message Slot 2 Extended ID2 (C0MSL2EID2)
CAN0 Message Slot 2 Data 0 (C0MSL2DT0)
CAN0 Message Slot 2 Data 2 (C0MSL2DT2)
CAN0 Message Slot 2 Data 4 (C0MSL2DT4)
CAN0 Message Slot 2 Data 6 (C0MSL2DT6)
CAN0 Message Slot 3 Standard ID0 (C0MSL3SID0)
CAN0 Message Slot 3 Extended ID0 (C0MSL3EID0)
CAN0 Message Slot 3 Extended ID2 (C0MSL3EID2)
CAN0 Message Slot 3 Data 0 (C0MSL3DT0)
CAN0 Message Slot 3 Data 2 (C0MSL3DT2)
CAN0 Message Slot 3 Data 4 (C0MSL3DT4)
CAN0 Message Slot 3 Data 6 (C0MSL3DT6)
CAN0 Message Slot 4 Standard ID0 (C0MSL4SID0)
CAN0 Message Slot 4 Extended ID0 (C0MSL4EID0)
CAN0 Message Slot 4 Extended ID2 (C0MSL4EID2)
CAN0 Message Slot 4 Data 0 (C0MSL4DT0)
CAN0 Message Slot 4 Data 2 (C0MSL4DT2)
CAN0 Message Slot 4 Data 4 (C0MSL4DT4)
CAN0 Message Slot 4 Data 6 (C0MSL4DT6)
CAN0 Message Slot 5 Standard ID0 (C0MSL5SID0)
CAN0 Message Slot 5 Extended ID0 (C0MSL5EID0)
ADDRESS SPACE
3.4 Internal ROM/SFR Area
+0 Address +1 AddressAddress
CAN0 Message Slot 0 Standard ID1 (C0MSL0SID1)
CAN0 Message Slot 0 Extended ID1 (C0MSL0EID1)
CAN0 Message Slot 0 Data Length Register (C0MSL0DLC)
CAN0 Message Slot 0 Data 1 (C0MSL0DT1)
CAN0 Message Slot 0 Data 3 (C0MSL0DT3)
CAN0 Message Slot 0 Data 5 (C0MSL0DT5)
CAN0 Message Slot 0 Data 7 (C0MSL0DT7)
CAN0 Message Slot 0 Time Stamp (C0MSL0TSP)
CAN0 Message Slot 1 Standard ID1 (C0MSL1SID1)
CAN0 Message Slot 1 Extended ID1 (C0MSL1EID1)
CAN0 Message Slot 1 Data Length Register (C0MSL1DLC)
CAN0 Message Slot 1 Data 1 (C0MSL1DT1)
CAN0 Message Slot 1 Data 3 (C0MSL1DT3)
CAN0 Message Slot 1 Data 5 (C0MSL1DT5)
CAN0 Message Slot 1 Data 7 (C0MSL1DT7)
CAN0 Message Slot 1 Time Stamp (C0MSL1TSP)
CAN0 Message Slot 2 Standard ID1 (C0MSL2SID1)
CAN0 Message Slot 2 Extended ID1 (C0MSL2EID1)
CAN0 Message Slot 2 Data Length Register (C0MSL2DLC)
CAN0 Message Slot 2 Data 1 (C0MSL2DT1)
CAN0 Message Slot 2 Data 3 (C0MSL2DT3)
CAN0 Message Slot 2 Data 5 (C0MSL2DT5)
CAN0 Message Slot 2 Data 7 (C0MSL2DT7)
CAN0 Message Slot 2 Time Stamp (C0MSL2TSP)
CAN0 Message Slot 3 Standard ID1 (C0MSL3SID1)
CAN0 Message Slot 3 Extended ID1 (C0MSL3EID1)
CAN0 Message Slot 3 Data Length Register (C0MSL3DLC)
CAN0 Message Slot 3 Data 1 (C0MSL3DT1)
CAN0 Message Slot 3 Data 3 (C0MSL3DT3)
CAN0 Message Slot 3 Data 5 (C0MSL3DT5)
CAN0 Message Slot 3 Data 7 (C0MSL3DT7)
CAN0 Message Slot 3 Time Stamp (C0MSL3TSP)
CAN0 Message Slot 4 Standard ID1 (C0MSL4SID1)
CAN0 Message Slot 4 Extended ID1 (C0MSL4EID1)
CAN0 Message Slot 4 Data Length Register (C0MSL4DLC)
CAN0 Message Slot 4 Data 1 (C0MSL4DT1)
CAN0 Message Slot 4 Data 3 (C0MSL4DT3)
CAN0 Message Slot 4 Data 5 (C0MSL4DT5)
CAN0 Message Slot 4 Data 7 (C0MSL4DT7)
CAN0 Message Slot 4 Time Stamp (C0MSL4TSP)
CAN0 Message Slot 5 Standard ID1 (C0MSL5SID1)
CAN0 Message Slot 5 Extended ID1 (C0MSL5EID1)
Figure 3.4.17 Register Mapping of the SFR Area (14)
3-25 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
+0 Address +1 AddressAddress
D0 D7 D8 D15
H'0080 1154
H'0080 1156
H'0080 1158
H'0080 115A
H'0080 115C
H'0080 115E
H'0080 1160
H'0080 1162
H'0080 1164
H'0080 1166
H'0080 1168
H'0080 116A
H'0080 116C
H'0080 116E
H'0080 1170
H'0080 1172
H'0080 1174
H'0080 1176
H'0080 1178
H'0080 117A
H'0080 117C
H'0080 117E
H'0080 1180
H'0080 1182
H'0080 1184
H'0080 1186
H'0080 1188
H'0080 118A
H'0080 118C
H'0080 118E
H'0080 1190
H'0080 1192
H'0080 1194
H'0080 1196
H'0080 1198
H'0080 119A
H'0080 119C
H'0080 119E
H'0080 11A0
H'0080 11A2
H'0080 11A4
H'0080 11A6
Blank addresses are reserved areas.
CAN0 Message Slot 5 Extended ID2 (C0MSL5EID2)
CAN0 Message Slot 5 Data 0 (C0MSL5DT0)
CAN0 Message Slot 5 Data 2 (C0MSL5DT2)
CAN0 Message Slot 5 Data 4 (C0MSL5DT4)
CAN0 Message Slot 5 Data 6 (C0MSL5DT6)
CAN0 Message Slot 6 Standard ID0 (C0MSL6SID0)
CAN0 Message Slot 6 Extended ID0 (C0MSL6EID0)
CAN0 Message Slot 6 Extended ID2 (C0MSL6EID2)
CAN0 Message Slot 6 Data 0 (C0MSL6DT0)
CAN0 Message Slot 6 Data 2 (C0MSL6DT2)
CAN0 Message Slot 6 Data 4 (C0MSL6DT4)
CAN0 Message Slot 6 Data 6 (C0MSL6DT6)
CAN0 Message Slot 7 Standard ID0 (C0MSL7SID0)
CAN0 Message Slot 7 Extended ID0 (C0MSL7EID0)
CAN0 Message Slot 7 Extended ID2 (C0MSL7EID2)
CAN0 Message Slot 7 Data 0 (C0MSL7DT0)
CAN0 Message Slot 7 Data 2 (C0MSL7DT2)
CAN0 Message Slot 7 Data 4 (C0MSL7DT4)
CAN0 Message Slot 7 Data 6 (C0MSL7DT6)
CAN0 Message Slot 8 Standard ID0 (C0MSL8SID0)
CAN0 Message Slot 8 Extended ID0 (C0MSL8EID0)
CAN0 Message Slot 8 Extended ID2 (C0MSL8EID2)
CAN0 Message Slot 8 Data 0 (C0MSL8DT0)
CAN0 Message Slot 8 Data 2 (C0MSL8DT2)
CAN0 Message Slot 8 Data 4 (C0MSL8DT4)
CAN0 Message Slot 8 Data 6 (C0MSL8DT6)
CAN0 Message Slot 9 Standard ID0 (C0MSL9SID0)
CAN0 Message Slot 9 Extended ID0 (C0MSL9EID0)
CAN0 Message Slot 9 Extended ID2 (C0MSL9EID2)
CAN0 Message Slot 9 Data 0 (C0MSL9DT0)
CAN0 Message Slot 9 Data 2 (C0MSL9DT2)
CAN0 Message Slot 9 Data 4 (C0MSL9DT4)
CAN0 Message Slot 9 Data 6 (C0MSL9DT6)
CAN0 Message Slot 10 Standard ID0 (C0MSL10SID0)
CAN0 Message Slot 10 Extended ID0 (C0MSL10EID0)
CAN0 Message Slot 10 Extended ID2 (C0MSL10EID2)
CAN0 Message Slot 10 Data 0 (C0MSL10DT0)
CAN0 Message Slot 5 Data Length Register (C0MSL5DLC)
CAN0 Message Slot 5 Data 1 (C0MSL5DT1)
CAN0 Message Slot 5 Data 3 (C0MSL5DT3)
CAN0 Message Slot 5 Data 5 (C0MSL5DT5)
CAN0 Message Slot 5 Data 7 (C0MSL5DT7)
CAN0 Message Slot 5 Time Stamp (C0MSL5TSP)
CAN0 Message Slot 6 Standard ID1 (C0MSL6SID1)
CAN0 Message Slot 6 Extended ID1 (C0MSL6EID1)
CAN0 Message Slot 6 Data Length Register (C0MSL6DLC)
CAN0 Message Slot 6 Data 1 (C0MSL6DT1)
CAN0 Message Slot 6 Data 3 (C0MSL6DT3)
CAN0 Message Slot 6 Data 5 (C0MSL6DT5)
CAN0 Message Slot 6 Data 7 (C0MSL6DT7)
CAN0 Message Slot 6 Time Stamp (C0MSL6TSP)
CAN0 Message Slot 7 Standard ID1 (C0MSL7SID1)
CAN0 Message Slot 7 Extended ID1 (C0MSL7EID1)
CAN0 Message Slot 7 Data Length Register (C0MSL7DLC)
CAN0 Message Slot 7 Data 1 (C0MSL7DT1)
CAN0 Message Slot 7 Data 3 (C0MSL7DT3)
CAN0 Message Slot 7 Data 5 (C0MSL7DT5)
CAN0 Message Slot 7 Data 7 (C0MSL7DT7)
CAN0 Message Slot 7 Time Stamp (C0MSL7TSP)
CAN0 Message Slot 8 Standard ID1 (C0MSL8SID1)
CAN0 Message Slot 8 Extended ID1 (C0MSL8
CAN0 Message Slot 8 Data Length Register (C0MSL8DLC)
CAN0 Message Slot 8 Data 1 (C0MSL8DT1)
CAN0 Message Slot 8 Data 3 (C0MSL8DT3)
CAN0 Message Slot 8 Data 5 (C0MSL8DT5)
CAN0 Message Slot 8 Data 7 (C0MSL8DT7)
CAN0 Message Slot 8 Time Stamp (C0MSL8TSP)
CAN0 Message Slot 9 Standard ID1 (C0MSL9SID1)
CAN0 Message Slot 9 Extended ID1 (C0MSL9EID1)
CAN0 Message Slot 9 Data Length Register (C0MSL9DLC)
CAN0 Message Slot 9 Data 1 (C0MSL9DT1)
CAN0 Message Slot 9 Data 3 (C0MSL9DT3)
CAN0 Message Slot 9 Data 5 (C0MSL9DT5)
CAN0 Message Slot 9 Data 7 (C0MSL9DT7)
CAN0 Message Slot 9 Time Stamp (C0MSL9TSP)
CAN0 Message Slot 10 Standard ID1 (C0MSL10SID1)
CAN0 Message Slot 10 Extended ID1 (C0MSL10EID1)
CAN0 Message Slot 10 Data Length Register (C0MSL10DLC)
CAN0 Message Slot 10 Data 1 (C0MSL10DT1)
EID1)
Figure 3.4.18 Register Mapping of the SFR Area (15)
3-26 Ver.0.10
3
ADDRESS SPACE
3.4 Internal ROM/SFR Area
D0 D7 D8 D15
H'0080 11A8
H'0080 11AA
H'0080 11AC
H'0080 11AE
H'0080 11B0
H'0080 11B2
H'0080 11B4
H'0080 11B6
H'0080 11B8
H'0080 11BA
H'0080 11BC
H'0080 11BE
H'0080 11C0
H'0080 11C2
H'0080 11C4
H'0080 11C6
H'0080 11C8
H'0080 11CA
H'0080 11CC
H'0080 11CE
H'0080 11D0
H'0080 11D2
H'0080 11D4
H'0080 11D6
H'0080 11D8
H'0080 11DA
H'0080 11DC
H'0080 11DE
H'0080 11E0
H'0080 11E2
H'0080 11E4
H'0080 11E6
H'0080 11E8
H'0080 11EA
H'0080 11EC
H'0080 11EE
H'0080 11F0
H'0080 11F2
H'0080 11F4
H'0080 11F6
H'0080 11F8
H'0080 11FA
H'0080 11FC
H'0080 11FE
~
~
H'0080 3FFE
Blank addresses are reserved areas.
CAN0 Message Slot 10 Data 2 (C0MSL10DT2)
CAN0 Message Slot 10 Data 4 (C0MSL10DT4)
CAN0 Message Slot 10 Data 6 (C0MSL10DT6)
CAN0 Message Slot 11 Standard ID0 (C0MSL11SID0)
CAN0 Message Slot 11 Extended ID0 (C0MSL11EID0)
CAN0 Message Slot 11 Extended ID2 (C0MSL11EID2)
CAN0 Message Slot 11 Data 0 (C0MSL11DT0)
CAN0 Message Slot 11 Data 2 (C0MSL11DT2)
CAN0 Message Slot 11 Data 4 (C0MSL11DT4)
CAN0 Message Slot 11 Data 6 (C0MSL11DT6)
CAN0 Message Slot 12 Standard ID0 (C0MSL12SID0)
CAN0 Message Slot 12 Extended ID0 (C0MSL12EID0)
CAN0 Message Slot 12 Extended ID2 (C0MSL12EID2)
CAN0 Message Slot 12 Data 0 (C0MSL12DT0)
CAN0 Message Slot 12 Data 2 (C0MSL12DT2)
CAN0 Message Slot 12 Data 4 (C0MSL12DT4)
CAN0 Message Slot 12 Data 6 (C0MSL12DT6)
CAN0 Message Slot 13 Standard ID0 (C0MSL13SID0)
CAN0 Message Slot 13 Extended ID0 (C0MSL13EID0)
CAN0 Message Slot 13 Extended ID2 (C0MSL13EID2)
CAN0 Message Slot 13 Data 0 (C0MSL13DT0)
CAN0 Message Slot 13 Data 2 (C0MSL13DT2)
CAN0 Message Slot 13 Data 4 (C0MSL13DT4)
CAN0 Message Slot 13 Data 6 (C0MSL13DT6)
CAN0 Message Slot 14 Standard ID0 (C0MSL14SID0)
CAN0 Message Slot 14 Extended ID0 (C0MSL14EID0)
CAN0 Message Slot 14 Extended ID2 (C0MSL14EID2)
CAN0 Message Slot 14 Data 0 (C0MSL14DT0)
CAN0 Message Slot 14 Data 2 (C0MSL14DT2)
CAN0 Message Slot 14 Data 4 (C0MSL14DT4)
CAN0 Message Slot 14 Data 6 (C0MSL14DT6)
CAN0 Message Slot 15 Standard ID0 (C0MSL15SID0)
CAN0 Message Slot 15 Extended ID0 (C0MSL15EID0)
CAN0 Message Slot 15 Extended ID2 (C0MSL15EID2)
CAN0 Message Slot 15 Data 0 (C0MSL15DT0)
CAN0 Message Slot 15 Data 2 (C0MSL15DT2)
CAN0 Message Slot 15 Data 4 (C0MSL15DT4)
CAN0 Message Slot 15 Data 6 (C0MSL15DT6)
+0 Address +1 AddressAddress
CAN0 Message Slot 10 Time Stamp (C0MSL10TSP)
CAN0 Message Slot 11 Data Length Register (C0MSL11DLC)
CAN0 Message Slot 11 Time Stamp (C0MSL11TSP)
CAN0 Message Slot 12 Data Length Register (C0MSL12DLC)
CAN0 Message Slot 12 Time Stamp (C0MSL12TSP)
CAN0 Message Slot 13 Data Length Register (C0MSL13DLC)
CAN0 Message Slot 13 Time Stamp (C0MSL13TSP)
CAN0 Message Slot 14 Data Length Register (C0MSL14DLC)
CAN0 Message Slot 14 Time Stamp (C0MSL14TSP)
CAN0 Message Slot 15 Data Length Register (C0MSL15DLC)
CAN0 Message Slot 15 Time Stamp (C0MSL11TSP)
CAN0 Message Slot 10 Data 3 (C0MSL10DT3)
CAN0 Message Slot 10 Data 5 (C0MSL10DT5)
CAN0 Message Slot 10 Data 7 (C0MSL10DT7)
CAN0 Message Slot 11 Standard ID1 (C0MSL11SID1)
CAN0 Message Slot 11 Extended ID1 (C0MSL11EID1)
CAN0 Message Slot 11 Data 1 (C0MSL11DT1)
CAN0 Message Slot 11 Data 3 (C0MSL11DT3)
CAN0 Message Slot 11 Data 5 (C0MSL11DT5)
CAN0 Message Slot 11 Data 7 (C0MSL11DT7)
CAN0 Message Slot 12 Standard ID1 (C0MSL12SID1)
CAN0 Message Slot 12 Extended ID1 (C0MSL12EID1)
CAN0 Message Slot 12 Data 1 (C0MSL12DT1)
CAN0 Message Slot 12 Data 3 (C0MSL12DT3)
CAN0 Message Slot 12 Data 5 (C0MSL12DT5)
CAN0 Message Slot 12 Data 7 (C0MSL12DT7)
CAN0 Message Slot 13 Standard ID1 (C0MSL13SID1)
CAN0 Message Slot 13 Extended ID1 (C0MSL13EID1)
CAN0 Message Slot 13 Data 1 (C0MSL13DT1)
CAN0 Message Slot 13 Data 3 (C0MSL13DT3)
CAN0 Message Slot 13 Data 5 (C0MSL13DT5)
CAN0 Message Slot 13 Data 7 (C0MSL13DT7)
CAN0 Message Slot 14 Standard ID1 (C0MSL14SID1)
CAN0 Message Slot 14 Extended ID1 (C0MSL14EID1)
CAN0 Message Slot 14 Data 1 (C0MSL14DT1)
CAN0 Message Slot 14 Data 3 (C0MSL14DT3)
CAN0 Message Slot 14 Data 5 (C0MSL14DT5)
CAN0 Message Slot 14 Data 7 (C0MSL14DT7)
CAN0 Message Slot 15 Standard ID1 (C0MSL15SID1)
CAN0 Message Slot 15 Extended ID1 (C0MSL15EID1)
CAN0 Message Slot 15 Data 1 (C0MSL15DT1)
CAN0 Message Slot 15 Data 3 (C0MSL15DT3)
CAN0 Message Slot 15 Data 5 (C0MSL15DT5)
CAN0 Message Slot 15 Data 7 (C0MSL15DT7)
~
~
Figure 3.4.19 Register Mapping of the SFR Area (16)
3-27 Ver.0.10
ADDRESS SPACE
3
3.5 EIT Vector Entry
3.5 EIT Vector Entry
The EIT vector entry is located at the beginning of the internal ROM/extended external areas.
Instructions for branching to the start addresses of respective EIT event handlers are written here.
Note that it is
to Chapter 4, "EIT."
branch instructions and not the jump addresses that are written here. For details, refer
031
H'0000 0000
H'0000 0004
H'0000 0008
H'0000 000C
H'0000 0010
H'0000 0014
H'0000 0018
H'0000 001C
H'0000 0020
H'0000 0024
H'0000 0028
H'0000 002C
H'0000 0030
H'0000 0034
H'0000 0038
H'0000 003C
H'0000 0040
H'0000 0044
H'0000 0048
H'0000 004C
H'0000 0050
H'0000 0054
H'0000 0058
H'0000 005C
H'0000 0060
H'0000 0064
H'0000 0068
H'0000 006C
H'0000 0070
H'0000 0074
H'0000 0078
H'0000 007C
H'0000 0080
RI (Reset Interrupt)
SBI (System Break Interrupt)
(Reserved Instruction Exception)
EI (External Interrupt) (Note)
RIE
AE (Address Exception)
TRAP0
TRAP1
TRAP2
TRAP3
TRAP4
TRAP5
TRAP6
TRAP7
TRAP8
TRAP9
TRAP10
TRAP11
TRAP12
TRAP13
TRAP14
TRAP15
~~
Note: When flash entry bit = 1 (i.e., flash enable mode), the EI vector entry is at H'0080 4000.
Figure 3.5.1 EIT Vector Entry
3-28 Ver.0.10
ADDRESS SPACE
3
3.6 ICU Vector Table
3.6 ICU Vector Table
The ICU vector table is used by the internal interrupt controller. The start addresses of interrupt
handlers for the interrupt requests from respective internal peripheral I/Os are set at the addresses shown below. For details, refer to Chapter 5, "Interrupt Controller."
The 32170's ICU vector table is shown in Figures 3.6.1 and 3.6.2.
Address
H'0000 0094
H'0000 0096
H'0000 0098
H'0000 009A
H'0000 009C
H'0000 009E
H'0000 00A0
H'0000 00A2
H'0000 00A4
H'0000 00A6
H'0000 00A8
H'0000 00AA
H'0000 00AC
H'0000 00AE
H'0000 00B0
D0 D7
+0 Address +1 Address
MJT Input Interrupt 4 Handler Start Address (A0-A15)
MJT Input Interrupt 4 Handler Start Address (A16-A31)
MJT Input Interrupt 3 Handler Start Address (A0-A15)
MJT Input Interrupt 3 Handler Start Address (A16-A31)
MJT Input Interrupt 2 Handler Start Address (A0-A15)
MJT Input Interrupt 2 Handler Start Address (A16-A31)
MJT Input Interrupt 1 Handler Start Address (A0-A15)
MJT Input Interrupt 1 Handler Start Address (A16-A31)
MJT Input Interrupt 0 Handler Start Address (A0-A15)
MJT Input Interrupt 0 Handler Start Address (A16-A31)
MJT Output Interrupt 7 Handler Start Address (A0-A15)
MJT Output Interrupt 7 Handler Start Address (A16-A31)
MJT Output Interrupt 6 Handler Start Address (A0-A15)
MJT Output Interrupt 6 Handler Start Address (A16-A31)
MJT Output Interrupt 5 Handler Start Address (A0-A15)
D8 D15
H'0000 00B2
H'0000 00B4
H'0000 00B6
H'0000 00B8
H'0000 00BA
H'0000 00BC
H'0000 00BE
H'0000 00C0
H'0000 00C2
H'0000 00C4
H'0000 00C6
MJT Output Interrupt 5 Handler Start Address (A16-A31)
MJT Output Interrupt 4 Handler Start Address (A0-A15)
MJT Output Interrupt 4 Handler Start Address (A16-A31)
MJT Output Interrupt 3 Handler Start Address (A0-A15)
MJT Output Interrupt 3 Handler Start Address (A16-A31)
MJT Output Interrupt 2 Handler Start Address (A0-A15)
MJT Output Interrupt 2 Handler Start Address (A16-A31)
MJT Output Interrupt 1 Handler Start Address (A0-A15)
MJT Output Interrupt 1 Handler Start Address (A16-A31)
MJT Output Interrupt 0 Handler Start Address (A0-A15)
MJT Output Interrupt 0 Handler Start Address (A16-A31)
~
Figure 3.6.1 ICU Vector Table of the 32170 (1/2)
~
3-29 Ver.0.10
3
ADDRESS SPACE
3.6 ICU Vector Table
Address
H'0000 00C8
H'0000 00CA
H'0000 00CC
H'0000 00CE
H'0000 00D0
H'0000 00D2
H'0000 00D4
H'0000 00D6
H'0000 00D8
H'0000 00DA
H'0000 00DC
H'0000 00DE
H'0000 00E0
H'0000 00E2
H'0000 00E4
H'0000 00E6
D0 D7
DMA0-4 Interrupt Handler Start Address (A0-A15)
SIO1 Receive Interrupt Handler Start Address (A0-A15)
SIO1 Transmit Interrupt Handler Start Address (A0-A15)
SIO1 Transmit Interrupt Handler Start Address (A16-A31)
SIO0 Receive Interrupt Handler Start Address (A0-A15)
SIO0 Transmit Interrupt Handler Start Address (A0-A15)
SIO0 Transmit Interrupt Handler Start Address (A16-A31)
A-D0 Conversion Interrupt Handler Start Address (A0-A15)
TID0 Output Interrupt Handler Start Address (A0-A15)
TID0 Output Transmit Interrupt Handler Start Address (A16-A31)
TOD0 Output Interrupt Handler Start Address (A0-A15)
+0 Address +1 Address
DMA0-4 Interrupt Handler Start Address (A16-A31)
SIO1 Receive Interrupt Handler Start Address (A16-A31)
SIO0 Receive Interrupt Handler Start Address (A16-A31)
A-D0 Conversion Interrupt Handler Start Address (A16-A31)
TOD0 Output Interrupt Handler Start Address (A16-A31)
D8 D15
H'0000 00E8
H'0000 00EA
H'0000 00EC
H'0000 00EE
H'0000 00F0
H'0000 00F2
H'0000 00F4
H'0000 00F6
H'0000 00F8
H'0000 00FA
H'0000 00FC
H'0000 00FE
H'0000 0100
H'0000 0102
H'0000 0104
H'0000 0106
H'0000 0108
H'0000 010A
H'0000 010C
DMA5-9 Interrupt Handler Start Address (A0-A15)
DMA5-9 Interrupt Handler Start Address (A16-A31)
SIO2,3 Transmit/Receive Interrupt Handler Start Address (A0-A15)
SIO2,3 Transmit/Receive Interrupt Handler Start Address (A16-A31)
RTD Interrupt Handler Start Address (A0-A15)
RTD Interrupt Handler Start Address (A16-A31)
TID1 Output Interrupt Handler Start Address (A0-A15)
TID1 Output Interrupt Handler Start Address (A16-A31)
TOD1+TOM0 Output Interrupt Handler Start Address (A0-A15)
TOD1+TOM0 Output Interrupt Handler Start Address (A16-A31)
SIO4,5 Transmit/Receive Interrupt Handler Start Address (A0-A15)
SIO4,5 Transmit/Receive Interrupt Handler Start Address (A16-A31)
A-D1 Conversion Interrupt Handler Start Address (A0-A15)
A-D1 Conversion Interrupt Handler Start Address (A16-A31)
TID2 Output Interrupt Handler Start Address (A0-A15)
TID2 Output Interrupt Handler Start Address (A16-A31)
TML1 Input Interrupt Handler Start Address (A0-A15)
TML1 Input Interrupt Handler Start Address (A16-A31)
CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A0-A15)
H'0000 010E
CAN0 Transmit/Receive & Error Interrupt Handler Start Address (A16-A31)
Figure 3.6.2 ICU Vector Table of the 32170 (2/2)
3-30 Ver.0.10
ADDRESS SPACE
3
3.7 Notes on Address Space
3.7 Note about Address Space
• Virtual flash emulation function
The 32170 has a special function, called the "Virtual Flash Emulation Function," which allows the
internal RAM to be mapped in blocks of 8 Kbytes from the beginning (up to four blocks for the
M32170F6, up to three blocks for the M32170F4 and M32170F3) into internal flash memory areas
divided in 8 Kbytes (L banks). Similarly, this function allows the internal RAM to be mapped in
blocks of 4 Kbytes, for the M32170F6 (up to two blocks) starting from the RAM address H'0080
C000, for the M32170F4 and M32170F3 (up to two blocks) starting from the RAM address H'0080
A000 into internal flash memory areas divided in 4 Kbytes (S banks). For details about this function,
refer to Section 6.7, "Pseudo-Flash Emulation Function."
3-31 Ver.0.10
3
ADDRESS SPACE
3.7 Notes on Address Space
❊ This is a blank page. ❊
3-32 Ver.0.10
CHAPTER 4CHAPTER 4
EIT
4.1 Outline of EIT
4.2 EIT Event
4.3 EIT Processing Procedure
4.4 EIT Processing Mechanism
4.5 Acceptance of EIT Events
4.6 Saving and Restoring the PC
and PSW
4.7 EIT Vector Entry
4.8 Exception Processing
4.9 Interrupt Processing
4.10 Trap Processing
4.11 EIT Priority Levels
4.12 Example of EIT Processing
4
4.1 Outline of EIT
4.1 Outline of EIT
If some event occurs when the CPU is executing an ordinary program, it may become necessary to
suspend the program being executed and execute another program. Events like this one are
referred to by a generic name as EIT (Exception, Interrupt, and Trap).
(1) Exception
This is an event related to the context being executed. It is generated by an error or violation
during instruction execution. In the M32R/E, this type of event includes Address Exception (AE)
and Reserved Instruction Exception (RIE).
(2) Interrupt
This is an event generated irrespective of the context being executed. It is generated in hardware
by a signal from an external source. In the M32R/E, this type of event includes External Interrupt
(EI), System Break Interrupt (SBI), and Reset Interrupt (RI).
EIT
(3) Trap
This refers to a software interrupt generated by executing a TRAP instruction. This type of event
is intentionally generated in a program as in the OS's system call by the programmer.
EIT
Exception Reserved Instruction Exception (RIE)
Address Exception (AE)
Interrupt Reset Interrupt (RI)
System Break Interrupt (SBI)
External Interrupt (EI)
Trap TRAP
Figure 4.1.1 Classification of EITs
4-2 Ver.0.10
4
4.2 EIT Event
4.2.1 Exception
(1) Reserved Instruction Exception (RIE)
Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction
(unimplemented instruction) is detected.
(2) Address Exception (AE)
Address Exception (AE) is generated when an attempt is made to access a misaligned address
in Load or Store instructions.
EIT
4.2 EIT Event
4.2.2 Interrupt
(1) Reset Interrupt (RI)
Reset Interrupt (RI) is always accepted by entering the RESET signal. The reset interrupt is
assigned the highest priority.
(2) System Break Interrupt (SBI)
System Break Interrupt (SBI) is an emergency interrupt which is used when power outage is
detected or a fault condition is notified by an external watchdog timer. This interrupt can only be
used in cases when after interrupt processing, control will not return to the program that was
being executed when the interrupt occurred.
(3) External Interrupt (EI)
External Interrupt (EI) is requested from internal peripheral I/Os managed by the interrupt
controller. The 32170's internal interrupt controller manages these interrupts by assigning each
one of eight priority levels including an interrupt-disabled state.
____________
4.2.3 Trap
Traps are software interrupts which are generated by executing the TRAP instruction. Sixteen
distinct vector addresses are provided corresponding to TRAP instruction operands 0-15.
4-3 Ver.0.10
4
4.3 EIT Processing Procedure
4.3 EIT Processing Procedure
EIT processing consists of two parts, one in which they are handled automatically by hardware, and
one in which they are handled by user-created programs (EIT handlers). The procedure for
processing EITs when accepted, except for a rest interrupt, is shown below.
EIT request
generated
Program execution restarted
Program
InstructionAInstructionBInstruction
C
suspended
EIT request
accepted
processing-
canceled type
InstructionCInstruction
Instruction
(RIE, AE)
D
••••
Instruction processing
-completed type
(EI, TRAP)
EIT
PC BPC
PSW (B)PSW
EIT vector
entry
Branch
instruc
-tion
Hardware
preprocessing
Hardware
postprocessing
User-created EIT handler
EIT handlers except for SBI
General-purpose
registers, (B)PSW,
and BPC restored
from stack
(SBI)
BPC, (B)PSW,
and general-purpose
registers saved to
stack
(System Break Interrupt
SBI
processing)
Processing
by
handler
Program terminated or
system is reset
Note: (B)PSW denotes the BPSW field of the PSW register.
(B)PSW PSW
RTE
instruc-
tion
BPC PC
Figure 4.3.1 Outline of EIT Processing Procedure
4-4 Ver.0.10
4
When an EIT is accepted, the M32R/E saves the PC and PSW (as will be described later) and
branches to the EIT vector. The EIT vector has an entry address assigned for each EIT.
where the BRA (branch) instruction (note that these are not branch address) for the EIT handler is
written.
In the M32R/E's hardware preprocessing, only the contents of the PC and PSW registers are
transferred to the backup registers (BPC register and the BPSW field of the PSW register), and no
other operations are performed. Therefore, please make sure the BPC register, the PSW register
(including the BPSW field), and the general-purpose registers to be used in the EIT handler are
saved to the stack by the EIT handler you write.
the stack in a program by the user.)
When processing by the EIT handler is completed, restore the saved registers from the stack and
finally execute the "RTE" instruction. Control is thereby returned from EIT processing to the
program that was being executed when the EIT occurred. (This does not apply to the System Break
Interrupt, however.)
In the M32R/E's hardware postprocessing, the contents of the backup registers (BPC register and
the BPSW field of the PSW register) are moved back to the PC and PSW registers.
(Remember that these registers must be saved to
4.3 EIT Processing Procedure
EIT
This is
4-5 Ver.0.10
4
4.4 EIT Processing Mechanism
4.4 EIT Processing Mechanism
The M32R/E's EIT processing mechanism consists of the M32R CPU core and the interrupt
controller for internal peripheral I/Os. It also has the backup registers for the PC and PSW (BPC
register and the BPSW field of the PSW register). The M32R/E's internal EIT processing
mechanism is shown below.
M32R/E
M32R CPU core
EIT
RESET
SBI
Internal
peripheral
I/O
•
•
•
•
•
•
Interrupt
controller
(ICU)
RI
SBI
EI
IE flag
(PSW)
RI
AE, RIE, TRAP
SBI
High
Priority
EI
Low
BPC register
BPSW
PSW register
Figure 4.4.1 The M32R/E's EIT Processing Mechanism
4-6 Ver.0.10
PSW
PC register
4
4.5 Acceptance of EIT Events
4.5 Acceptance of EIT Event
When an EIT event occurs, the M32R/E suspends the program it has hitherto been executing and
branches to EIT processing by the relevant handler. Conditions under which each EIT event occurs
and the timing at which they are accepted are shown below.
Table 4.5.1 Acceptance of EIT Events
EIT Event Type of Processing Acceptance Timing Values Set in BPC Register
Reserved Instruction Instruction processing- During instruction PC value of the instruction
Exception (RIE) canceled type execution which generated RIE
Address Exception (AE) Instruction processing- During instruction PC value of the instruction
canceled type execution which generated AE
EIT
Reset Interrupt (RI) Instruction processing- Each machine cycle Indeterminate value
aborted type
System Break Instruction processing- Break in instructions PC value of the next instruction
Interrupt (SBI) completed type (only word boundaries)
External Interrupt (EI) Instruction processing- Break in instructions PC value of the next instruction
completed type (only word boundaries)
Trap (TRAP) Instruction processing- Break in instructions PC value of TRAP
completed type instruction + 4
4-7 Ver.0.10
4
4.6 Saving and Restoring the PC and PSW
4.6 Saving and Restoring the PC and PSW
The following describes operation of the M32R at the time when it accepts an EIT and when it
executes the "RTE" instruction.
(1) Hardware preprocessing when an EIT is accepted
Save the SM, IE, and C bits of the PSW register
➀
BSM ← SM
BIE ← IE
BC ← C
Update the SM, IE, and C bits of the PSW register
➁
SM ← Remains unchanged (RIE, AE, TRAP)
or set to 0 (SBI, EI, RI)
IE ← Set to 0
C ← Set to 0
EIT
Save the PC register
➂
BPC ← PC
Set the vector address in the PC register
➃
Branches to the EIT vector and executes the branch instruction ("BRA" instruction) written
in it, thereby transferring control to the user-created EIT handler.
(2) Hardware postprocessing when the "RTE" instruction is executed
Restore the SM, IE, and C bits of the PSW register from their backup bits.
❶
SM ← BSM
IE ← BIE
C ← BC
Restore the value of the PC register from the BPC register
❷
PC ← BPC
Note: The value of the BPC register and those of the BSM, BIE, and BC bits of the PSW register
after execution of the "RTE" instruction are indeterminate.
4-8 Ver.0.10
4
A
A
Save SM, IE, and C bits
1
BSM
BIE
BC
Update SM, IE, and C bits
2
SM
IE
C
SM
IE
C
Unchanged/0
0
0
EIT
4.6 Saving and Restoring the PC and PSW
Save PC
3
BPC
Set vector address in PC
4
PC
PC
Vector address
Restore BSM, BIE, and BC bits
from backup bits
SM
IE
C
The values of BSM, BIE, and BC
bits after execution of the "RTE"
instruction are indeterminate.
When EIT is accepted
Restore PC value from BPC
21
BSM
BIE
BC
PSW BPC PC
1
2
The value of BPC after
execution of the "RTE"
instruction is indeterminate.
3
4
When "RTE" instruction is executed
Figure 4.6.1 Saving and Restoring the PC and PSW
1 2
4-9 Ver.0.10
BPSW field PSW field
16 17 23 24 25 31(LSB)15870(MSB)
00000000000000000000000000PSW
SM IE CBCBSM BIE
4
4.7 EIT Vector Entry
4.7 EIT Vector Entry
The EIT vector entry is located in the user space starting from address H'0000 0000. The table
below lists the EIT vector entry.
Table 4.7.1 EIT Vector Entry
EIT
Name
Reset Interrupt RI H'0000 0000 (Note 1) 0 0 Indeterminate
System Break Interrupt SBI H'0000 0010 0 0 PC of the next instruction
Reserved Instruction RIE H'0000 0020 Indeterminate 0 PC of the instruction that
Exception generated EIT
Address Exception AE H'0000 0030 Indeterminate 0 PC of the instruction that
Trap TRAP0 H'0000 0040 Indeterminate 0 PC of TRAP instruction + 4
Abbreviation
TRAP1 H'0000 0044 Indeterminate 0 PC of TRAP instruction + 4
TRAP2 H'0000 0048 Indeterminate 0 PC of TRAP instruction + 4
TRAP3 H'0000 004C Indeterminate 0 PC of TRAP instruction + 4
TRAP4 H'0000 0050 Indeterminate 0 PC of TRAP instruction + 4
TRAP5 H'0000 0054 Indeterminate 0 PC of TRAP instruction + 4
TRAP6 H'0000 0058 Indeterminate 0 PC of TRAP instruction + 4
TRAP7 H'0000 005C Indeterminate 0 PC of TRAP instruction + 4
TRAP8 H'0000 0060 Indeterminate 0 PC of TRAP instruction + 4
TRAP9 H'0000 0064 Indeterminate 0 PC of TRAP instruction + 4
Vector Address SM IE BPC
generated RIE
TRAP10 H'0000 0068 Indeterminate 0 PC of TRAP instruction + 4
TRAP11 H'0000 006C Indeterminate 0 PC of TRAP instruction + 4
TRAP12 H'0000 0070 Indeterminate 0 PC of TRAP instruction + 4
TRAP13 H'0000 0074 Indeterminate 0 PC of TRAP instruction + 4
TRAP14 H'0000 0078 Indeterminate 0 PC of TRAP instruction + 4
TRAP15 H'0000 007C Indeterminate 0 PC of TRAP instruction + 4
External Interrupt EI H'0000 0080 (Note 2) 0 0 PC of the next instruction
Note 1: During boot mode, this vector address is moved to the beginning of the boot ROM (address H'8000
0000). For details, refer to Section 6.5, "Programming of Internal Flash Memory."
Note 2: During flash E/W enable mode, this vector address is moved to the beginning of the internal RAM
(address H'0080 4000). For details, refer to Section 6.5, "Programming of Internal Flash Memory."
4-10 Ver.0.10
4
4.8 Exception Processing
4.8.1 Reserved Instruction Exception (RIE)
[Occurrence Conditions]
Reserved Instruction Exception (RIE) is generated when execution of a reserved instruction
(unimplemented instruction) is detected. Instruction check is performed on the op-code part of
the instruction.
When a reserved instruction exception occurs, the instruction which generated it is not executed.
If an external interrupt is requested at the same time a reserved instruction exception is detected,
it is the reserved instruction exception that is accepted.
[EIT Processing]
(1) Saving SM, IE, and C bits
EIT
4.8 Exception Processing
The SM, IE, and C bits of the PSW register are saved to their backup bits – the BSM, BIE,
and BC bits.
BSM ← SM
BIE ← IE
BC ← C
(2) Updating SM, IE, and C bits
The SM, IE, and C bits of the PSW register are updated as shown below.
SM ← Unchanged
BIE ← 0
BC ← 0
(3) Saving PC
The PC value of the instruction that generated the reserved instruction exception is set in
the BPC register. For example, if the instruction that generated the reserved instruction
exception is at address 4, the value 4 is set in the BPC register. Similarly, if the instruction
is at address 6, the value 6 is set in the BPC register. In this case, the value of the BPC
register bit 30 indicates whether the instruction that generated the reserved instruction
exception resides on a word boundary (BPC[30] = 0) or not on a word boundary (BPC[30]
= 1).
However, in either case of the above, the address to which the "RTE" instruction returns
after completion of processing by the EIT handler is address 4. (This is because the two
low-order bits are cleared to "00" when returning to the PC.)
4-11 Ver.0.10
4
EIT
4.8 Exception Processing
+0 +1 +2 +3
H'00
H'04
H'08
H'0C
~
RIE occurred
Address
Return
address
~
BPC
Figure 4.8.1 Example of a Return Address for Reserved Instruction Exception (RIE)
(4) Branching to the EIT vector entry
Control branches to the address H'0000 0020 in the user space. This is the last operation
performed in hardware preprocessing by the M32R/E.
(5) Jumping from the EIT vector entry to the user-created handler
H'04
~
address
Return
Address
H'00
H'04
H'08
H'0C
~
+0 +1 +2 +3
~
RIE occurred
~
BPC
H'06
~
~
The M32R/E executes the "BRA" instruction written at address H'0000 0020 of the EIT
vector entry by the user to jump to the start address of the user-created handler. At the
beginning of the EIT handler you created, first save the BPC and PSW registers and the
necessary general-purpose registers to the stack.
(6) Returning from the EIT handler
At the end of the EIT handler, restore the general-purpose registers and the BPC and PSW
registers from the stack and then execute the "RTE" instruction. As you execute the "RTE"
instruction, hardware postprocessing is automatically performed by the M32R/E.
4-12 Ver.0.10
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