Mitsubishi M306V2ME-XXXFP, M306V2EEFS, M306V2EEFP Datasheet
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
1. DESCRIPTION
The M306V2ME-XXXFP and M306V2EEFP are single-chip microcomputers using the high-performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic
molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high
level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at
high speed. They also feature a built-in OSD display function and data slicer, making them ideal for controlling TV with a closed caption decoder.
The features of the M306V2EEFP are similar to those of the M306V2ME-XXXFP except that this chip has
a built-in PROM which can be written electrically.
1.1 Features
• Memory size ........................................<ROM>192K bytes
<RAM> 5K bytes
<OSD ROM> 61K bytes
<OSD RAM> 2.2K bytes
• Shortest instruction execution time......100 ns (f(XIN)=10 MHz)
• Power sourse voltage ..........................4.5 V to 5.5V
• Power consumption .............................250 mW
• Interrupts..............................................21 internal and 3 external interrupt sources, 4 software
interrupt sources; 7 levels
• Multifunction 16-bit timer......................2 output timers + 3 input timers + 3 timers
• Serial I/O..............................................3 units
UART/clock synchronous: 2
Multi-master I2C-BUS interface 0 (2 systems): 1
Multi-master I2C-BUS interface 1 (1 system): 1
• DMAC ..................................................2 channels (trigger: 23 sources)
• A-D converter.......................................8 bits ✕ 6 channels
• D-A converter.......................................8 bits ✕ 2 channels
• Data slicer............................................1 circuit
• HSYNC counter .....................................1 circuit (2 systems)
• OSD function .......................................1 circuit
• Watchdog timer....................................1 circuit
• Programmable I/O ...............................78 lines
• Memory expansion ..............................Available
• Chip select output ................................4 lines
• Clock generating circuit .......................3 built-in clock generation circuits
and ON-SCREEN DISPLAY CONTROLLER
M306V2EEFP
1.2 Applications
TV with a closed caption decoder
Rev. 1.0
1
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
------Table of Contents------
1. DESCRIPTION ..............................................1
1.1 Features...................................................1
1.2 Applications .............................................1
1.3 Pin Configuration ..................................... 3
1.4 Block Diagram .........................................4
1.5 Performance Outline................................5
2. OPERATION OF FUNCTIONAL BLOCKS .... 9
2.1 Memory....................................................9
2.2 Central Processing Unit (CPU) .............. 15
2.3 Reset .....................................................18
2.4 Processor Mode..................................... 23
2.5 Clock Generating Circuit........................36
2.6 Protection............................................... 46
2.7 Interrupts................................................ 47
2.8 Watchdog Timer ....................................67
2.9 DMAC .................................................... 69
2.10 Timer.................................................... 79
2.11 Serial I/O..............................................99
2.12 A-D Converter....................................149
2.13 D-A Converter....................................164
2.14 Data Slicer ......................................... 166
2.15 HSYNC Counter ..................................176
2.16 OSD Function .................................... 177
2.16.1 Triple Layer OSD ........................183
2.16.2 Display Position .......................... 185
2.16.3 Dot Size ...................................... 189
2.16.4 Clock for OSD.............................190
2.16.5 Field Determination Display........191
2.16.6 Memory for OSD.........................193
2.16.7 Character Color ..........................206
2.16.8 Character Background Color ...... 206
2.16.9 OUT1, OUT2 Signals..................211
2.16.10 Attribute ....................................212
2.16.11
2.16.12 Particular OSD Mode Block ...... 218
2.16.13 Multiline Display........................220
2.16.14 SPRITE OSD Function ............. 221
2.16.15 Window Function ...................... 224
2.16.16 Blank Function .......................... 225
2.16.17 Raster Coloring Function ..........228
Automatic Solid Space Function.....
217
2.16.18 Scan Mode................................230
2.16.19 R, G, B Signal Output Control... 230
2.16.20 OSD Reserved Register ........... 231
2.17 Programmable I/O Ports .................... 232
3. USAGE PRECAUTION..............................245
3.1 Timer A (timer mode)...........................245
3.2 Timer A (event counter mode) ............. 245
3.3 Timer A (one-shot timer mode)............245
3.4 Timer A
3.5 Timer B
3.6 Timer B (pulse period/pulse width
measurement mode) ...........................246
3.7 A-D Converter......................................246
3.8 Stop Mode and Wait Mode .................. 246
3.9 Interrupts..............................................247
3.10 Built-in PROM version .......................248
4. ITEM TO BE SUBMITTED WHEN ORDERING
MASKED ROM VERSION ......................... 249
5. ELECTRICAL CHARACTERISTICS..........250
5.1 Absolute Maximum Ratings ................. 250
5.2 Recommended Operating Conditions..251
5.3 Electrical Characteristics .....................252
5.4 A-D Conversion Characteristics........... 253
5.5 D-A Conversion Characteristics........... 253
5.6 Analog R, G, B Output Characteristics 253
5.7 Timing Requirements...........................254
5.8 Switching Characteristics.....................255
5.9 Measurement Circuit............................259
5.10 Timing Diagram .................................260
6. MASK ROM CONFIRMATION FORM ....... 265
7. MARK SPECIFICATION FORM ................269
8.ONE TIME PROM VERSION
M306V2EEFP MARKING...........................270
9. PACKAGE OUTLINE ................................. 271
(pulse width modulation mode)....
(timer mode, event counter mode) .....
245
246
Rev. 1.0
2
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
C
1.3 Pin Configuration
Figure 1.3.1 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
)
)
0
1
)
D
D
/
/
/
0
1
2
D
D
0
1
2
3
8
9
1
D
D
D
/
/
/
0
1
2
1
1
1
P
P
P
8
0
9
8
7
07/ D
1
1
1
1
1
1
1
1
V S E T
7
06/ D
6
05/ D
5
04/ D
4
03/ D
3
02/ D
2
01/ D
1
00/ D
0
07/ A N
5
06/ A N
4
05/ A N
3
04/ A N
2
03/ A N
1
02/ A N
0
01/ V
S Y N
. C
. 3
00/ H
S Y N C
B 3
V c
c 3
V
I N
1P
2P
3P
4P
5P
6P
7P
8P
9P
0P
1P
9 2P
9 3P
9 4P
9 5P
9 6N
7P
8T
9 9A
0
0C
1
2
37
4
1
1
1
1
D
D
D
D
/
/
/
/
3
4
5
6
1
1
1
1
P
P
P
P
7
6
5
4
7
7
7
47
5
6
7
D
5
(
(
(
1
0
1
2
D
A
A
A
/
/
/
/
7
0
1
2
1
2
2
2
P
P
P
P
-
/
/
/
3
2
1
0
7
7
7
7
M 3 0 6 V 2 M E - X X X F P
M 3 0 6 V 2 E E F P
0
1
8
9
1
1
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
and ON-SCREEN DISPLAY CONTROLLER
)1
)
)1
)1
2
D
/
3
D
(
3
A
/
3
2
P
/
/
9
6
2
)1
3
4
5
6
D
D
/
/
4
5
D
D
(
(
4
5
A
A
/
/
4
5
2
2
P
P
/
/
8
7
6
6
3
4
1
)1
D
D
7
/
/
6
7
D
D
D
(
(
(
6
7
8
A
A
A
/
/
/
6
7
0
c
s1
2
2
3
V
c
P
P
/
6
5
6
6
5
6
V
s
P
/ - /
4
3
2
6
6
6
7
8
9
1
2
3
4
5
1
0
9
1
1
1
1
A
A
A
A
A
/
/
/
/
/
1
3
4
5
2
3
3
3
3
3
P
P
P
P
P
1
0
9
8
6
0
2
7
6
5
5
5
1
2
3
4
2
2
2
2
7
6
8
1
1
A
A
/
/
6
7
3
3
P
P
6
5
5
5
5
6
2
2
9
1
1
1
1
A
A
A
A
/
/
/
/
1
0
2
3
4
4
4
4
P
P
P
P
4
3
2
1
5
5
5
5
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
5
3 4
3
2
3 1
7
8
9
0
2
2
2
3
P 44/ C S 08
P 45/ C S 18
P 46/ C S 28
P 47/ C S 38
P 50/ W R L / W R8
P 51/ W R H / B H E8
P 52/ R D8
P 53/ B C L K8
P 54/ H L D A8
P 55/ H O L D9
P 56/ A L E9
P 57/ R D Y / C L K
P 60/ C T S0/ R T S
P 61/ C L K
0
P 62/ R x D
0
P 63/ TXD
0
B9
G9
R
P 67/ S D A 21
O U T
0
D
H
V
L
O L
N
N
N
3
3
F
I
I
I
2
1
H
/
1
A
/D
4
9
P
S D A
S C L
0
/
/
/
/
2
1
0
0
A
/D
3
9
P
Y T
9
9
9
P
P
P
T B
T B
T B
Figure 1.3.1 Pin configuration (top view)
Rev. 1.0
1
s
N
E
C
X
/
B
7
C
8
P
N V s
I
O U
S
C
N
T
I
S
C
X
O
V
C
X
/
R
U
6
8
P
E S E
V
X
S C
T
T
0
1
2
T
T
/
/
3
2
O
O
8
8
P
P
S C
U T
I N
I N
T
1
1
2
O
3
/
7
O
O
7
/
P
U T
6
7
P
H C
H C
T A
U
2
2
2
T
0
/
5
7
P
T A
U
2
K
S
D
D
O
2
/
4
7
P
C T
R T
X
X
T
R
,
2
S
/
/
/
/
2
0
1
3
7
7
7
7
P
P
P
P
S D A 1 /
S C L 1 /
S C L 2 / C L
Package: 100P6S-A
3
1.4 Block Diagram
0
Figure 1.4.1 is a block diagram.
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
5
I / O p o r t s
I n t e r n a l p e r i p h e r a l f u n c t i o n s
T i m e r T A 0 ( 1 6 b i t s )
T i m e r T A 1 ( 1 6 b i t s )
T i m e r T A 2 ( 1 6 b i t s )
T i m e r T A 3 ( 1 6 b i t s )
T i m e r T A 4 ( 1 6 b i t s )
T i m e r T B 0 ( 1 6 b i t s )
T i m e r T B 1 ( 1 6 b i t s )
T i m e r T B 2 ( 1 6 b i t s )
W a t c h d o g t i m e r
( 2 c h a n n e l s )
D - A c o n v e r t e r
( 8 b i t s X 2 c h a n n e l s )
P o r t P 08P o r t P 18P o r t P 28P o r t P 38P o r t P 48P o r t P 58P o r t P 6
T i m e r
( 1 5 b i t s )
D M A C
A - D c o n v e r t e r
O S D
D a t a s l i c e r
H
S Y N C
c o u n t e r
M 1 6 C / 6 0 s e r i e s 1 6 - b i t C P U c o r e
R e g i s t e r s
R 0 LR 0 H
R 0 LR 0 H
R 1 HR 1 L
R 1 HR 1 L
R 2
R 2
R 3
R 3
A
A 0
A 1
A 1
F B
F B
S B F L G
P r o g r a m c o u n t e r
V e c t o r t a b l e
S t a c k p o i n t e r
S y s t e m c l o c k g e n e r a t o r
I N
– X
X
U A R T / c l o c k s y n c h r o n o u s S I / O
U A R T / c l o c k s y n c h r o n o u s S I / O
M u l t i - m a s t e r I2C - b u s
i n t e r f a c e 0
M u l t i - m a s t e r I2C - b u s
i n t e r f a c e 1
P C
I N T B
I S P
U S P
O U T
M e m o r y
R O M
1 9 2 K
R A M
5 K
M u l t i p l i e r
o r t P
P
7
o r t P
P
8 4
8
o r t P
P
9
5 8
o r t P 1
P
0
Figure 1.4.1 Block diagram
Rev. 1.0
4
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
1.5 Performance Outline
Table 1.5.1 is a performance outline.
Table 1.5.1 Performance outline
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time 100 ns(f(XIN)=10 MHz)
Memory ROM 192K bytes
size RAM 5K bytes
OSD ROM 61K bytes
OSD RAM 2.2K bytes
I/O port P0 to P10 8 bits ✕ 8, 5 bits ✕ 2, 4 bits ✕ 1
Multifunction TA0, TA1, TA2, TA3, TA4 16 bits ✕ 5
timer TB0, TB1, TB2 16 bits ✕ 3
Serial I/O UART0 1 unit: UART or clock synchronous
UART2 1 unit: UART or clock synchronous
Multi-master I2C-BUS interface 0 1 unit (2 channels)
Multi-master I2C-BUS interface 1 1 unit (1 channel)
A-D converter 8 bits ✕ 6 channels
D-A converter 8 bits ✕ 2 channels
DMAC 2 channels (trigger: 23 sources)
OSD function
Data slicer 32-bit buffer
HSYNC counter 8 bits ✕ 2 channels
Watchdog timer 15 bits ✕ 1 (with prescaler)
Interrupt
Clock generating circuit 3 built-in clock generation circuits
Power source voltage 4.5 V to 5.5V (f(XIN ) = 10 MHz)
Power consumption
I/O I/O withstand voltage 5 V
characteristics Output current 5 mA
Memory expansion Available
Operating ambient temperature –10 o C to 70 o C
Device configuration CMOS high performance silicon gate
Package 100-pin plastic molded QFP
Triple layer, 890 kinds of fonts, 42 character ✕ 16 lines
21 internal and 3 external sources, 4 software sources, 7 levels
250 mW
M306V2EEFP
Rev. 1.0
5
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Currently supported products are listed below.
Table 1.5.2 List of supported products
R A M c a p a c i t yR O M c a p a c i t y
M 3 0 6 V 2 M E - X X X F P
1 9 2 K b y t e s
1 9 2 K b y t e s
1 9 2 K b y t e s
5 K b y t e s
5 K b y t e s
5 K b y t e s
Note: Since EPROM version is for development support tool (for evaluation), do not use for mass produc-
tion.
P a c k a g e t y p e
1 0 0 P 6 S - A
1 0 0 P 6 S - A
1 0 0 D 0
R e m a r k sT y p e N o
M a s k R O M v e r s i o n
O n e T i m e P R O M v e r s i o nM 3 0 6 V 2 E E F P
E P R O M v e r s i o nM 3 0 6 V 2 E E F S
T y p e N o . M 3 0 6 V 2 M E – X X X F P
P a c k a g e t y p e :
F P : P a c k a g e1 0 0 P 6 S - A
F S : P a c k a g e1 0 0 D 0
R O M N o .
O m i t t e d f o r O n e T i m e P R O M v e r s i o n
a n d E P R O M v e r s i o n
R O M c a p a c i t y :
E : 1 9 2 K b y t e s
M e m o r y t y p e :
M : M a s k R O M v e r s i o n
E : O n e T i m e P R O M v e r s i o n o r E P R O M
v e r s i o n
S h o w s R A M c a p a c i t y , p i n c o u n t , e t c
( T h e v a l u e i t s e l f h a s n o s p e c i f i c m e a n i n g )
Figure 1.5.1 Type No., memory size, and package
6
M 1 6 C / 6 V G r o u p
M 1 6 C F a m i l y
Rev. 1.0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Table 1.5.3 Pin description (1)
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
and ON-SCREEN DISPLAY CONTROLLER
P i n n a m e
VC
C,
VS
S
C N VS
S
R E S E T
XI
N
U
XO
T
B Y T E
C C
A V
P 00 t o P 07
D0 t o D7
S i g n a l n a m e
P o w e r s u p p l y
i n p u t
S S
C N V
R e s e t i n p u t
C l o c k i n p u t
C l o c k o u t p u t
E x t e r n a l d a t a
b u s w i d t h
s e l e c t i n p u t
A n a l o g p o w e r
s u p p l y i n p u t
I / O p o r t P 0
I / O t y p e
I n p u t
I n p u t
I n p u t
O u t p u t
I n p u t
I n p u t / o u t p u t
I n p u t / o u t p u t
F u n c t i o n
p i n . S u p p l y 0 V t o t h e
p i n
S u p p l y 4 . 5 V t o 5 . 5 V t o t h e V
p i n w h e n o p e r a t i n g i n s i n g l e - c h i p o r m e m o r y e x p a n s i o n m o d e .
p i n w h e n i n m i c r o p r o c e s s o r m o d e
T h i s p i n s w i t c h e s b e t w e e n p r o c e s s o r m o d e s . C o n n e c t i t t o t h e
S S
V
C o n n e c t i t t o t h e V
C C
C C
VS
.
S
.
A “ L ” o n t h i s i n p u t r e s e t s t h e m i c r o c o m p u t e r .
p i n o p e n
p i n a n d l e a v e t h e
a n d t h e
p i n s .
U
T h e s e p i n s a r e p r o v i d e d f o r t h e m a i n c l o c k g e n e r a t i n g c i r c u i t . C o n n e c t
a c e r a m i c r e s o n a t o r o r c r y s t a l b e t w e e n t h e X
u s e a n e x t e r n a l l y d e r i v e d c l o c k , i n p u t i t t o t h e X
X
O U T
.
I N
I N
XO
T
To
T h i s p i n s e l e c t s t h e w i d t h o f a n e x t e r n a l d a t a b u s . A 1 6 - b i t w i d t h i s
s e l e c t e d w h e n t h i s i n p u t i s “ L ” ; a n 8 - b i t w i d t h i s s e l e c t e d w h e n t h i s
i n p u t i s “ H ” . T h i s i n p u t m u s t b e f i x e d t o e i t h e r “ H ” o r “ L . ” W h e n
o p e r a t i n g i n s i n g l e - c h i p m o d e , c o n n e c t t h i s p i n t o V
S S.
T h i s p i n i s a p o w e r s u p p l y i n p u t f o r t h e A - D c o n v e r t e r . C o n n e c t t h i s
C C.
p i n t o V
T h i s i s a n 8 - b i t C M O S I / O p o r t . I t h a s a n i n p u t / o u t p u t p o r t d i r e c t i o n
r e g i s t e r t h a t a l l o w s t h e u s e r t o s e t e a c h p i n f o r i n p u t o r o u t p u t
i n d i v i d u a l l y . W h e n s e t f o r i n p u t i n s i n g l e - c h i p m o d e , t h e u s e r c a n s p e c i f y
i n u n i t s o f f o u r b i t s v i a s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a p u l l - u p
r e s i s t o r . I n m e m o r y e x p a n s i o n a n d m i c r o p r o c e s s o r m o d e s , t h e u s e r
c a n n o t s p e c i f y t h a t .
W h e n s e t a s a s e p a r a t e b u s , t h e s e p i n s i n p u t a n d o u t p u t d a t a ( D
0–
D7) .
P 10 t o P 17 I / O p o r t P 1
t o
8
D1
D
P 20 t o P 27
5
I / O p o r t P 2
A0 t o A7
A0/ D0 t o
7/
A
o
A0
A1/ D0
P 30 t o P 37
A8 t o A1
t o
A8/ D7,
A
P 40 t o P 47
t o C
t o
C S
A
D7
t
A7/ D6
I / O p o r t P 3
5
9
A1
5
I / O p o r t P 4
0
S3,
1 6
A1
9
I n p u t / o u t p u t
I n p u t / o u t p u t
O u t p u t
I n p u t / o u t p u t
O u t p u t
I n p u t / o u t p u t
I n p u t / o u t p u t
O u t p u t
I n p u t / o u t p u t
O u t p u t
I n p u t / o u t p u t
O u t p u t
O u t p u t
T h i s i s a n 8 - b i t I / O p o r t e q u i v a l e n t t o P 0 . I n p u t / o u t p u t
W h e n s e t a s a s e p a r a t e b u s , t h e s e p i n s i n p u t a n d o u t p u t d a t a
( D8– D
T h i s i s a n 8 - b i t I / O p o r t e q u i v a l e n t t o P 0 .
T h e s e p i n s o u t p u t 8 l o w - o r d e r a d d r e s s b i t s ( A
I f t h e e x t e r n a l b u s i s s e t a s a n 8 - b i t w i d e m u l t i p l e x e d b u s , t h e s e p i n s
i n p u t a n d o u t p u t d a t a ( D
( A
0–
A7) s e p a r a t e d i n t i m e b y m u l t i p l e x i n g .
I f t h e e x t e r n a l b u s i s s e t a s a 1 6 - b i t w i d e m u l t i p l e x e d b u s , t h e s e p i n s
i n p u t a n d o u t p u t d a t a ( D
0–
D7) a n d o u t p u t 8 l o w - o r d e r a d d r e s s b i t s
0–
D6) a n d o u t p u t a d d r e s s ( A1– A7) s e p a r a t e d
i n t i m e b y m u l t i p l e x i n g . T h e y a l s o o u t p u t a d d r e s s ( A
0
– A7) .
0)
.
T h i s i s a n 8 - b i t I / O p o r t e q u i v a l e n t t o P 0 .
T h e s e p i n s o u t p u t 8 m i d d l e - o r d e r a d d r e s s b i t s ( A
a n d o u t p u t a d d r e s s (
I f t h e e x t e r n a l b u s i s s e t a s a 1 6 - b i t w i d e m u l t i p l e x e d b u s , t h e s e p i n s
i n p u t a n d o u t p u t d a t a ( D
7)
b y m u l t i p l e x i n g . T h e y a l s o o u t p u t a d d r e s s ( A
8–
A1
5)
.
A8) s e p a r a t e d i n t i m e
9–
A1
5)
.
T h i s i s a n 8 - b i t I / O p o r t e q u i v a l e n t t o P 0 .
a r e 4 h i g h -
C
T h e s e p i n s o u t p u t C S0– C S3 s i g n a l s a n d A1
s e l e c t s i g n a l s u s e d t o s p e c i f y a n a c c e s s s p a c e . A
6–
A1
9.
S0– C S3 a r e c h i p
1 6–
A1
9
o r d e r a d d r e s s b i t s .
1 5
) .
Rev. 1.0
7
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Table 1.5.4 Pin description (continued) (2)
S i g n a l n a m eF
P 50 t o P 5
7
W R L / W R ,
W R H / B H E ,
R D ,
B C L K ,
H L D A ,
H O L D ,
A L E ,
R D Y
P 60 t o P 63,
P 6
7
P 70 t o P 77
2
, P 83,
P 8
P 86, P 8
7
P 90 t o P 9
4
P 1 00 t o P 1 0
I / O p o r t P 5
I / O p o r t P 7
I / O p o r t P 8
I / O p o r t P 9
7
I / O p o r t P 1 0
I n p u t / o u t p u t
O u t p u t
O u t p u t
O u t p u t
O u t p u t
O u t p u t
I n p u t
O u t p u t
I n p u t
I n p u t / o u t p u tI / O p o r t P 6
I n p u t / o u t p u t
I n p u t / o u t p u t
I n p u t / o u t p u t
I n p u t / o u t p u t
T h i s i s a n 8 - b i t I / O p o r t e q u i v a l e n t t o P 0 . I n s i n g l e - c h i p m o d e , P 57 i n
t h i s p o r t o u t p u t s a d i v i d e - b y - 8 o r d i v i d e - b y - 3 2 c l o c k o f X
t h e s a m e f r e q u e n c y a s X
O u t p u t W R L , W R H ( W R a n d B H E ) , R D , B C L K , H L D A , a n d A L E
s i g n a l s . W R L a n d W R H , a n d B H E a n d W R c a n b e s w i t c h e d u s i n g
s o f t w a r e c o n t r o l .
■ W R L , W R H , a n d R D s e l e c t e d
W i t h a 1 6 - b i t e x t e r n a l d a t a b u s , d a t a i s w r i t t e n t o e v e n a d d r e s s e s
w h e n t h e W R L s i g n a l i s “ L ” a n d t o t h e o d d a d d r e s s e s w h e n t h e W R H
s i g n a l i s “ L ” . D a t a i s r e a d w h e n R D i s “ L ” .
■ W R , B H E , a n d R D s e l e c t e d
D a t a i s w r i t t e n w h e n W R i s “ L ” . D a t a i s r e a d w h e n R D i s “ L ” . O d d
a d d r e s s e s a r e a c c e s s e d w h e n B H E i s “ L ” . U s e t h i s m o d e w h e n u s i n g
a n 8 - b i t e x t e r n a l d a t a b u s .
W h i l e t h e i n p u t l e v e l a t t h e H O L D p i n i s “ L ” , t h e m i c r o c o m p u t e r i s
p l a c e d i n t h e h o l d s t a t e . W h i l e i n t h e h o l d s t a t e , H L D A o u t p u t s a “ L ”
l e v e l . A L E i s u s e d t o l a t c h t h e a d d r e s s . W h i l e t h e i n p u t l e v e l o f t h e
R D Y p i n i s “ L ” , t h e m i c r o c o m p u t e r i s i n t h e r e a d y s t a t e .
T h i s i s a n 5 - b i t I / O p o r t e q u i v a l e n t t o P 0 . W h e n s e t f o r i n p u t i n s i n g l e c h i p , m i c r o p r o c e s s o r a n d m e m o r y e x p a n s i o n m o d e s , t h e u s e r c a n
s p e c i f y i n u n i t s o f f o u r b i t s v i a s o f t w a r e w h e t h e r o r n o t t h e y a r e t i e d t o a
p u l l - u p r e s i s t o r . P i n s i n t h i s p o r t a l s o f u n c t i o n a s U A R T 0 , U A R T 2 a n d
m u l t i - m a s t e r I
T h i s i s a n 8 - b i t I / O p o r t e q u i v a l e n t t o P 6 ( P 70 a n d P 71 a r e N - c h a n n e l
o p e n - d r a i n o u t p u t ) . P i n s i n t h i s p o r t a l s o f u n c t i o n a s t i m e r s A 2 a n d A 3 ,
U A R T 2 , m u l t i - m a s t e r I
s e l e c t e d b y s o f t w a r e .
P 82, P 83, P 86 a n d P 87 a r e I / O p o r t s w i t h t h e s a m e f u n c t i o n s a s P 6 .
U s i n g s o f t w a r e , P 82 a n d P 83 c a n b e m a d e t o f u n c t i o n a s t h e I / O p i n s f o r
t h e i n p u t p i n s f o r e x t e r n a l i n t e r r u p t s . P 8
s o f t w a r e t o f u n c t i o n a s t h e I / O p i n s f o r a s u b - c l o c k g e n e r a t i o n c i r c u i t . I n
t h i s c a s e , c o n n e c t a q u a r t z o s c i l l a t o r b e t w e e n P 8
( X
T h i s i s a n 5 - b i t I / O p o r t e q u i v a l e n t t o P 6 . P i n s i n t h i s p o r t a l s o f u n c t i o n
a s T i m e r B 0 t o B 2 i n p u t p i n s , D - A c o n v e r t e r o u t p u t p i n s , o r m u l t i - m a s t e r
2
I
T h i s i s a n 8 - b i t I / O p o r t e q u i v a l e n t t o P 6 . P i n s i n t h i s p o r t a l s o f u n c t i o n
a s A - D c o n v e r t e r i n p u t p i n s . F u r t h e r m o r e , P 1 0
a s i n p u t p i n s f o r O S D f u n c t i o n .
C I N
2
C - B U S i n t e r f a c e 0 I / O p i n s a s s e l e c t e d b y s o f t w a r e .
2
C - B U S i n t e r f a c e 0 , o r H
C I N
p i n ) .
C - B U S i n t e r f a c e 1 I / O p i n s .
u n c t i o
nP i n n a m e I / O t y p e
a s s e l e c t e d b y s o f t w a r e .
S Y N C
6
a n d P 87 c a n b e s e t u s i n g
6
( X
0
a n d P 1 01 a l s o f u n c t i o n
I N
o r a c l o c k o f
c o u n t e r I / O p i n s a s
C O U T
p i n ) a n d P 87
R , G , B
O U T 1 , O U T 2
O S C 1
O S C 2
C V
V
H L F
T V S E T B
8
I N
H O L D
O S D o u t p u t
O u t p u t
O S D o u t p u tO u t p u t
C l o c k i n p u t
I n p u t
f o r O S D
C l o c k o u t p u t
O u t p u t
f o r O S D
I / O f o r d a t a
I n p u t
s l i c e r
I n p u t
I n p u t / o u t p u t
T e s t i n p u t
I n p u t
T h e s e a r e O S D o u t p u t p i n s ( a n a l o g o u t p u t ) .
T h e s e a r e O S D o u t p u t p i n s ( d i g i t a l o u t p u t ) .
T h i s i s a n O S D c l o c k i n p u t p i n .
T h i s i s a n O S D c l o c k o u t p u t p i n .
I n p u t c o m p o s i t e v i d e o s i g n a l t h r o u g h a c a p a c i t o r .
C o n n e c t a c a p a c i t o r b e t w e e n V
H O L D
a n d V s s .
C o n n e c t a f i l t e r u s i n g o f a c a p a c i t o r a n d a r e s i s t o r
b e t w e e n H L F a n d V s s .
T h i s i s a t e s t i n p u t p i n . F i x i t t o “ L . ”
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2. OPERATION OF FUNCTIONAL BLOKS
This microcomputer accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, OSD circuit, data slicer,
A-D converter, and I/O ports.
The following explains each unit.
2.1 Memory
Figure 2.1.1 is a memory map. The address space extends the 1M bytes from address 0000016 to
FFFFF16. From FFFFF16 down is ROM. There is 192K bytes of internal ROM from D000016 to FFFFF16.
The vector table for fixed interrupts such as the reset mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be
set as desired using the internal register (INTB). See the section on interrupts for details.
5K bytes of internal RAM is mapped to the space from 02C0016 to 03FFF16. In addition to storing data, the
RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 2.1.2 to 2.1.5 are location
of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be
used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines
or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions
can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. The following spaces cannot be used.
• The space between 0100016 and 02BFF16 (in memory expansion and microprocessor modes)
• The space between B000016 and CFFFF16 (in memory expansion mode)
Rev. 1.0
9
00000
003FF
00400
013FF
01400
02BFF
02C00
03FFF
04000
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
16
16
16
SFR area
(Refer to Figures 2.1.2 to 2.1.5)
OSD RAM area
16
16
Internal reserved
area (See note 1)
16
16
Internal RAM area
16
16
FFE00
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
and ON-SCREEN DISPLAY CONTROLLER
16
8FFFF
16
90000
16
AFFFF
16
B0000
16
CFFFF
16
D0000
16
FFFFF
16
Notes 1: During memory expansion and microprocessor modes, cannot be used.
2: During memory expansion mode, cannot be used.
Figure 2.1.1 Memory map
External area
OSD ROM area
Internal reserved
area (See note 2)
Internal ROM area
FFFDC
FFFFF
Special page
vector table
16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
16
DBC
Reset
10
Rev. 1.0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
0 0 0 01
6
0 0 0 11
6
0 0 0 21
6
0 0 0 31
6
0 0 0 41
6
P r o c e s s o r m o d e r e g i s t e r 0 ( P M 0 )
0 0 0 51
6
P r o c e s s o r m o d e r e g i s t e r 1 ( P M 1 )
0 0 0 61
6
S y s t e m c l o c k c o n t r o l r e g i s t e r 0 ( C M 0 )
0 0 0 71
6
S y s t e m c l o c k c o n t r o l r e g i s t e r 1 ( C M 1 )
0 0 0 81
6
C h i p s e l e c t c o n t r o l r e g i s t e r ( C S R )
0 0 0 91
6
A d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r ( A I E R )
0 0 0 A1
6
P r o t e c t r e g i s t e r ( P R C R )
0 0 0 B1
6
0 0 0 C1
6
0 0 0 D1
6
0 0 0 E1
6
W a t c h d o g t i m e r s t a r t r e g i s t e r ( W D T S )
0 0 0 F1
6
W a t c h d o g t i m e r c o n t r o l r e g i s t e r ( W D C )
0 0 1 01
6
0 0 1 11
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0 ( R M A D 0 )
0 0 1 21
6
0 0 1 31
6
0 0 1 41
6
A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1 ( R M A D 1 )
0 0 1 51
6
0 0 1 61
6
0 0 1 71
6
0 0 1 81
6
0 0 1 91
6
0 0 1 A1
6
0 0 1 B1
6
0 0 1 C1
6
0 0 1 D1
6
0 0 1 E1
6
0 0 1 F1
6
0 0 2 01
6
0 0 2 11
6
D M A 0 s o u r c e p o i n t e r ( S A R 0 )
0 0 2 21
6
0 0 2 31
6
0 0 2 41
6
0 0 2 51
6
D M A 0 d e s t i n a t i o n p o i n t e r ( D A R 0 )
0 0 2 61
6
0 0 2 71
6
0 0 2 81
6
D M A 0 t r a n s f e r c o u n t e r ( T C R 0 )
0 0 2 91
6
0 0 2 A1
6
0 0 2 B1
6
0 0 2 C1
6
D M A 0 c o n t r o l r e g i s t e r ( D M 0 C O N )
0 0 2 D1
6
0 0 2 E1
6
0 0 2 F1
6
0 0 3 01
6
0 0 3 11
6
D M A 1 s o u r c e p o i n t e r ( S A R 1 )
0 0 3 21
6
0 0 3 31
6
0 0 3 41
6
D M A 1 d e s t i n a t i o n p o i n t e r ( D A R 1 )
0 0 3 51
6
0 0 3 61
6
0 0 3 71
6
0 0 3 81
6
D M A 1 t r a n s f e r c o u n t e r ( T C R 1 )
0 0 3 91
6
0 0 3 A1
6
0 0 3 B1
6
0 0 3 C1
6
D M A 1 c o n t r o l r e g i s t e r ( D M 1 C O N )
0 0 3 D1
6
0 0 3 E1
6
0 0 3 F1
6
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
and ON-SCREEN DISPLAY CONTROLLER
0 0 4 01
6
0 0 4 11
6
0 0 4 21
6
0 0 4 31
6
0 0 4 41
6
O S D 1 i n t e r r u p t c o n t r o l r e g i s t e r ( O S D 1 I C )
0 0 4 51
6
I n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 0 ( R E 0 I C )
0 0 4 61
6
I n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 1 ( R E 1 I C )
0 0 4 71
6
I n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 2 ( R E 2 I C )
0 0 4 81
6
O S D 2 i n t e r r u p t c o n t r o l r e g i s t e r ( O S D 2 I C )
0 0 4 91
6
M u l t i - m a s t e r I2C - B U S i n t e r f a c e 1 i n t e r r u p t c o n t r o l r e g i s t e r ( I I C 1 I C )
0 0 4 A1
6
B u s c o l l i s i o n d e t e c t i o n i n t e r r u p t c o n t r o l r e g i s t e r ( B C N I C )
0 0 4 B1
6
D M A 0 i n t e r r u p t c o n t r o l r e g i s t e r ( D M 0 I C )
0 0 4 C1
6
D M A 1 i n t e r r u p t c o n t r o l r e g i s t e r ( D M 1 I C )
0 0 4 D1
6
M u l t i - m a s t e r I2C - B U S i n t e r f a c e 0 i n t e r r u p t c o n t r o l r e g i s t e r ( I I C 0 I C )
0 0 4 E1
6
A - D c o n v e r s i o n i n t e r r u p t c o n t r o l r e g i s t e r ( A D I C )
0 0 4 F1
6
U A R T 2 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r ( S 2 T I C )
0 0 5 01
6
U A R T 2 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( S 2 R I C )
0 0 5 11
6
U A R T 0 t r a n s m i t i n t e r r u p t c o n t r o l r e g i s t e r ( S 0 T I C )
0 0 5 21
6
U A R T 0 r e c e i v e i n t e r r u p t c o n t r o l r e g i s t e r ( S 0 R I C )
0 0 5 31
6
D a t a s l i c e r i n t e r r u p t c o n t r o l r e g i s t e r ( D S I C )
i n t e r r u p t c o n t r o l r e g i s t e r ( V S Y N C I C
0 0 5 41
6
V
0 0 5 51
0 0 5 61
0 0 5 71
0 0 5 81
0 0 5 91
0 0 5 A1
0 0 5 B1
0 0 5 C1
0 0 5 D1
0 0 5 E1
0 0 5 F1
0 0 6 01
0 1 F F1
S Y N C
6
T i m e r A 0 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 0 I C )
6
T i m e r A 1 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 1 I C )
6
T i m e r A 2 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 2 I C )
6
T i m e r A 3 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 3 I C )
6
T i m e r A 4 i n t e r r u p t c o n t r o l r e g i s t e r ( T A 4 I C )
6
T i m e r B 0 i n t e r r u p t c o n t r o l r e g i s t e r ( T B 0 I C )
6
T i m e r B 1 i n t e r r u p t c o n t r o l r e g i s t e r ( T B 1 I C )
6
T i m e r B 2 i n t e r r u p t c o n t r o l r e g i s t e r ( T B 2 I C )
6
I N T 0 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 0 I C )
6
I N T 1 i n t e r r u p t c o n t r o l r e g i s t e r ( I N T 1 I C )
6
I n t e r r u p t c o n t r o l r e s e r v e d r e g i s t e r 3 ( R E 3 I C )
6
6
)
Figure 2.1.2 Location of peripheral unit control registers (1)
Rev. 1.0
11
0 2 0 0
1 6
0 2 0 1
1 6
S P R I T E O S D c o n t r o l r e g i s t e r ( S C )
0 2 0 2
1 6
O S D c o n t r o l r e g i s t e r 1 ( O C 1 )
0 2 0 3
1 6
O S D c o n t r o l r e g i s t e r 2 ( O C 2 )
0 2 0 4
1 6
H o r i z o n t a l p o s i t i o n r e g i s t e r ( H P )
0 2 0 5
1 6
C l o c k c o n t r o l r e g i s t e r ( C S )
0 2 0 6
1 6
I / O p o l a r i t y c o n t r o l r e g i s t e r ( P C )
0 2 0 7
1 6
O S D c o n t r o l r e g i s t e r 3 ( O C 3 )
0 2 0 8
1 6
R a s t e r c o l o r r e g i s t e r ( R S C )
0 2 0 9
1 6
0 2 0 A
1 6
0 2 0 B
1 6
0 2 0 C
1 6
T o p b o r d e r c o n t r o l r e g i s t e r ( T B R )
0 2 0 D
1 6
0 2 0 E
1 6
B o t t o m b o r d e r c o n t r o l r e g i s t e r ( B B R )
0 2 0 F
1 6
0 2 1 0
1 6
B l o c k c o n t r o l r e g i s t e r 1 ( B C 1)
0 2 1 1
1 6
B l o c k c o n t r o l r e g i s t e r 2 ( B C 2)
0 2 1 2
1 6
B l o c k c o n t r o l r e g i s t e r 3 ( B C 3)
0 2 1 3
1 6
B l o c k c o n t r o l r e g i s t e r 4 ( B C 4)
0 2 1 4
1 6
B l o c k c o n t r o l r e g i s t e r 5 ( B C 5)
0 2 1 5
1 6
B l o c k c o n t r o l r e g i s t e r 6 ( B C 6)
0 2 1 6
1 6
B l o c k c o n t r o l r e g i s t e r 7 ( B C 7)
0 2 1 7
1 6
B l o c k c o n t r o l r e g i s t e r 8 ( B C 8)
0 2 1 8
1 6
B l o c k c o n t r o l r e g i s t e r 9 ( B C 9)
0 2 1 9
1 6
B l o c k c o n t r o l r e g i s t e r 1 0 ( B C 1 0)
0 2 1 A
1 6
B l o c k c o n t r o l r e g i s t e r 1 1 ( B C 1 1)
0 2 1 B
1 6
B l o c k c o n t r o l r e g i s t e r 1 2 ( B C 1 2)
0 2 1 C
1 6
B l o c k c o n t r o l r e g i s t e r 1 3 ( B C 1 3)
0 2 1 D
1 6
B l o c k c o n t r o l r e g i s t e r 1 4 ( B C 1 4)
0 2 1 E
1 6
B l o c k c o n t r o l r e g i s t e r 1 5 ( B C 1 5)
0 2 1 F
1 6
B l o c k c o n t r o l r e g i s t e r 1 6 ( B C 1 6)
0 2 2 0
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 ( V P 1 )
0 2 2 1
1 6
0 2 2 2
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 2 ( V P 2 )
0 2 2 3
1 6
0 2 2 4
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 3 ( V P 3 )
0 2 2 5
1 6
0 2 2 6
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 4 ( V P 4 )
0 2 2 7
1 6
0 2 2 8
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 5 ( V P 5 )
0 2 2 9
1 6
0 2 2 A
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 6 ( V P 6 )
0 2 2 B
1 6
0 2 2 C
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 7 ( V P 7 )
0 2 2 D
1 6
0 2 2 E
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 8 ( V P 8 )
0 2 2 F
1 6
0 2 3 0
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 9 ( V P 9 )
0 2 3 1
1 6
0 2 3 2
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 0 ( V P 1 0 )
0 2 3 3
1 6
0 2 3 4
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 1 ( V P 1 1 )
0 2 3 5
1 6
0 2 3 6
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 2 ( V P 1 2 )
0 2 3 7
1 6
0 2 3 8
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 3 ( V P 1 3 )
0 2 3 9
1 6
0 2 3 A
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 4 ( V P 1 4 )
0 2 3 B
1 6
0 2 3 C
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 5 ( V P 1 5 )
0 2 3 D
1 6
0 2 3 E
1 6
V e r t i c a l p o s i t i o n r e g i s t e r 1 6 ( V P 1 6 )
0 2 3 F
1 6
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
0 2 4 0
1 6
C o l o r p a l e t t e r e g i s t e r 1 ( C R 1 )
0 2 4 1
1 6
0 2 4 2
1 6
C o l o r p a l e t t e r e g i s t e r 2 ( C R 2 )
0 2 4 3
1 6
0 2 4 4
1 6
C o l o r p a l e t t e r e g i s t e r 3 ( C R 3 )
0 2 4 5
1 6
0 2 4 6
1 6
C o l o r p a l e t t e r e g i s t e r 4 ( C R 4 )
0 2 4 7
1 6
0 2 4 8
1 6
C o l o r p a l e t t e r e g i s t e r 5 ( C R 5 )
0 2 4 9
1 6
0 2 4 A
1 6
C o l o r p a l e t t e r e g i s t e r 6 ( C R 6 )
0 2 4 B
1 6
0 2 4 C
1 6
C o l o r p a l e t t e r e g i s t e r 7 ( C R 7 )
0 2 4 D
1 6
0 2 4 E
1 6
C o l o r p a l e t t e r e g i s t e r 9 ( C R 9 )
0 2 4 F
1 6
0 2 5 0
1 6
C o l o r p a l e t t e r e g i s t e r 1 0 ( C R 1 0 )
0 2 5 1
1 6
0 2 5 2
1 6
C o l o r p a l e t t e r e g i s t e r 1 1 ( C R 1 1 )
0 2 5 3
1 6
0 2 5 4
1 6
C o l o r p a l e t t e r e g i s t e r 1 2 ( C R 1 2 )
0 2 5 5
1 6
0 2 5 6
1 6
C o l o r p a l e t t e r e g i s t e r 1 3 ( C R 1 3 )
0 2 5 7
1 6
0 2 5 8
1 6
C o l o r p a l e t t e r e g i s t e r 1 4 ( C R 1 4 )
0 2 5 9
1 6
0 2 5 A
1 6
C o l o r p a l e t t e r e g i s t e r 1 5 ( C R 1 5 )
0 2 5 B
1 6
0 2 5 C
1 6
0 2 5 D
1 6
O S D r e s e r v e d r e g i s t e r 1 ( O R 1 )
0 2 5 E
1 6
0 2 5 F
1 6
O S D c o n t r o l r e g i s t e r 4 ( O C 4 )
0 2 6 0
1 6
D a t a s l i c e r c o n t r o l r e g i s t e r 1 ( D S C 1 )
0 2 6 1
1 6
D a t a s l i c e r c o n t r o l r e g i s t e r 2 ( D S C 2 )
0 2 6 2
1 6
C a p t i o n d a t a r e g i s t e r 1 ( C D 1 )
0 2 6 3
1 6
0 2 6 4
1 6
C a p t i o n d a t a r e g i s t e r 2 ( C D 2 )
0 2 6 5
1 6
0 2 6 6
1 6
C a p t i o n p o s i t i o n r e g i s t e r ( C P S )
0 2 6 7
1 6
D a t a s l i c e r r e s e r v e d r e g i s t e r 2 ( D R 2 )
0 2 6 8
1 6
D a t a s l i c e r r e s e r v e d r e g i s t e r 1 ( D R 1 )
0 2 6 9
1 6
C l o c k r u n - i n d e t e c t r e g i s t e r ( C R D )
0 2 6 A
1 6
D a t a c l o c k p o s i t i o n r e g i s t e r ( D P S )
0 2 6 B
1 6
0 2 6 F
1 6
0 2 7 0
1 6
L e f t b o r d e r c o n t r o l r e g i s t e r ( L B R )
0 2 7 1
1 6
0 2 7 2
1 6
R i g h t b o r d e r c o n t r o l r e g i s t e r ( R B R )
0 2 7 3
1 6
0 2 7 4
1 6
S P R I T E v e r t i c a l p o s i t i o n r e g i s t e r 1 ( V S 1 )
0 2 7 5
1 6
0 2 7 6
1 6
S P R I T E v e r t i c a l p o s i t i o n r e g i s t e r 2 ( V S 2 )
0 2 7 7
1 6
0 2 7 8
1 6
S P R I T E h o r i z o n t a l p o s i t i o n r e g i s t e r ( H S )
0 2 7 9
1 6
0 2 7 A
1 6
O S D r e s e r v e d r e g i s t e r 4 ( O R 4 )
0 2 7 B
1 6
O S D r e s e r v e d r e g i s t e r 3 ( O R 3 )
0 2 7 C
1 6
O S D r e s e r v e d r e g i s t e r 2 ( O R 2 )
0 2 7 D
1 6
P e r i p h e r a l m o d e r e g i s t e r ( P M )
0 2 7 E
1 6
H
S Y N C
0 2 7 F
0 2 8 0
0 2 D F
1 6
1 6
1 6
c o u n t e r r e g i s t e r ( H C )
H
S Y N C
c o u n t e r l a t c h
Figure 2.1.3 Location of peripheral unit control registers (2)
12
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
02E0
02E1
02E2
02E3
02E4
02E5
02E6
02E7
02E8
02E9
02EA
02EB
02EC
02ED
02EE
02EF
0339
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349
035E
035F
0360
0361
0362
0363
0364
0365
0366
0367
0368
0369
036A
036B
036C
036D
036E
036F
0370
0371
0372
0373
0374
0375
0376
0377
0378
0379
037A
037B
037C
037D
037E
037F
2
I
C0 data shift register (IIC0S0)
16
2
I
C0 address register (IIC0S0D)
16
2
16
I
C0 status register (IIC0S1)
2
16
C0 control register (IIC0S1D)
I
2
16
I
C0 clock control register (IIC0S2)
2
16
C0 port selection register (IIC0S2D)
I
2
16
C0 transmit buffer register (IIC0S0S)
I
16
2
16
I
C1 data shift register (IIC1S0)
2
16
I
C1 address register (IIC1S0D)
16
I2C1 status register (IIC1S1)
2
16
C1 control register (IIC1S1D)
I
2
I
C1 clock control register (IIC1S2)
16
2
16
C1 port selection register (IIC1S2D)
I
2
16
C1 transmit buffer register (IIC1S0S)
I
16
16
16
Reserved register 1 (INVC1)
16
16
16
16
16
16
16
Reserved register 0 (INVC0)
16
16
16
Interrupt request cause select register (IFSR)
16
16
16
Reserved register 3 (INVC3)
16
16
16
16
Reserved register 4 (INVC4)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Reserved register 5 (INVC5)
16
UART2 special mode register (U2SMR)
16
UART2 transmit/receive mode register (U2MR)
16
16
UART2 bit rate generator (U2BRG)
16
UART2 transmit buffer register (U2TB)
16
16
UART2 transmit/receive control register 0 (U2C0)
16
UART2 transmit/receive control register 1 (U2C1)
16
UART2 receive buffer register (U2RB)
16
0380
0381
0382
0383
0384
0385
0386
0387
0388
0389
038A
038B
038C
038D
038E
038F
0390
0391
0392
0393
0394
0395
0396
0397
0398
0399
039A
039B
039C
039D
039E
039F
03A0
03A1
03A2
03A3
03A4
03A5
03A6
03A7
03A8
03A9
03AA
03AB
03AC
03AD
03AE
03AF
03B0
03B1
03B2
03B3
03B4
03B5
03B6
03B7
03B8
03B9
03BA
03BB
03BC
03BD
03BE
03BF
16
Count start flag (TABSR)
16
Clock prescaler reset flag (CPSRF)
16
One-shot start flag (ONSF)
16
Trigger select register (TRGSR)
16
Up-down flag (UDF)
16
16
Timer A0 register (TA0)
16
16
Timer A1 register (TA1)
16
16
Timer A2 register (TA2)
16
16
Timer A3 register (TA3)
16
16
Timer A4 register (TA4)
16
16
Timer B0 register (TB0)
16
16
Timer B1 register (TB1)
16
16
Timer B2 register (TB2)
16
16
Timer A0 mode register (TA0MR)
16
Timer A1 mode register (TA1MR)
16
Timer A2 mode register (TA2MR)
16
Timer A3 mode register (TA3MR)
16
Timer A4 mode register (TA4MR)
16
Timer B0 mode register (TB0MR)
16
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
16
16
16
16
UART0 transmit/receive mode register (U0MR)
16
UART0 bit rate generator (U0BRG)
16
UART0 transmit buffer register (U0TB)
16
16
UART0 transmit/receive control register 0 (U0C0)
16
UART0 transmit/receive control register 1 (U0C1)
16
UART0 receive buffer register (U0RB)
16
16
Reserved register 2 (INVC2)
16
16
16
16
16
16
16
UART transmit/receive control register 2 (UCON)
16
16
16
16
16
16
16
16
16
DMA0 request cause select register (DM0SL)
16
DMA1 request cause select register (DM1SL)
16
16
16
16
16
16
Figure 2.1.4 Location of peripheral unit control registers (3)
Rev. 1.0
13
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
A-D register 0 (AD0)
03C5
16
03C6
16
A-D register 1 (AD1)
03C7
16
03C8
16
A-D register 2 (AD2)
03C9
16
03CA
16
A-D register 3 (AD3)
03CB
16
03CC
16
A-D register 4 (AD4)
03CD
16
03CE
16
A-D register 5 (AD5)
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
A-D control register 2 (ADCON2)
03D5
16
03D6
16
A-D control register 0 (ADCON0)
03D7
16
A-D control register 1 (ADCON1)
03D8
16
D-A register 0 (DA0)
03D9
16
03DA
16
D-A register 1 (DA1)
03DB
16
03DC
16
D-A control register (DACON)
03DD
16
03DE
16
03DF
16
03E0
16
Port P0 register(P0)
03E1
16
Port P1 register (P1)
03E2
16
Port P0 direction register (PD0)
03E3
16
Port P1 direction register (PD1)
03E4
16
Port P2 register (P2)
03E5
16
Port P3 register (P3)
03E6
16
Port P2 direction register (PD2)
03E7
16
Port P3 direction register (PD3)
03E8
16
Port P4 register (P4)
03E9
16
Port P5 register (P5)
03EA
16
Port P4 direction register (PD4)
03EB
16
Port P5 direction register (PD5)
03EC
16
Port P6 register (P6)
03ED
16
Port P7 register (P7)
03EE
16
Port P6 direction register (PD6)
03EF
16
Port P7 direction register (PD7)
03F0
16
Port P8 register (P8)
Port P9 register (P9)
03F1
16
Port P8 direction register (PD8)
03F2
16
Port P9 direction register (PD9)
03F3
16
03F4
16
Port P10 register (P10)
03F5
16
Port P10 direction register (PD10)
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
Pull-up control register 0 (PUR0)
03FC
16
Pull-up control register 1 (PUR1)
03FD
16
Pull-up control register 2 (PUR2)
03FE
16
Port control register (PCR)
03FF
16
Figure 2.1.5 Location of peripheral unit control registers (4)
14
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.2 Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 2.2.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, and FB) come in two sets; therefore, these have two register banks.
b15 b8 b7 b0
(Note)
R0
H
L
R1
R2
R3
A0
A1
FB
b15
(Note)
b15
(Note)
b15 b0
(Note)
b15 b0
(Note)
b15
(Note)
b15 b0
(Note)
b8 b7 b0
H
b19
L
PC
b0
Program counter
Data
b0
registers
INTB
b0 b19
HL
Interrupt table
register
b15 b0
USP
b15 b0
ISP
User stack pointer
Interrupt stack
pointer
Address
b0
registers
Frame base
registers
b15
SB
b15 b0
FLG
b0
Static base
register
Flag register
Note: These registers consist of two register banks.
Figure 2.2.1 Central processing unit register
Rev. 1.0
IPL
CDZSBOIU
15
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.2.1 Data Registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
2.2.2 Address Registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.2.3 Frame Base Register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
2.2.4 Program Counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
2.2.5 Interrupt Table Register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector
table.
2.2.6 Stack Pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
2.2.7 Static Base Register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
2.2.8 Flag Register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 2.2.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
“1”
when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”
.
16
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
g
r
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for
details.
b0b15
IPL
Flag register (FLG)
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select fla
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt prio
Reserved area
Figure 2.2.2 Flag register (FLG)
Rev. 1.0
17
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.3 Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 2.3.1 shows the example reset circuit. Figure 2.3.2 shows the reset sequence.
RESET
5V
V
CC
0V
V
CC
5V
RESET
0V
4.5V
0.9V
Example when f(XIN) = 10 MHz and VCC = 5V.
Figure 2.3.1 Example reset circuit
2.3.1 Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal
RAM are preserved.
18
Rev. 1.0
X
IN
Microprocessor
mode BYTE = “H”
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
More than 20 cycles are needed
RESET
BCLK
Address
RD
WR
CS0
Microprocessor
mode BYTE = “L”
Address
RD
WR
CS0
Single chip
mode
Address
BCLK 24cycles
FFFFC
FFFFC
FFFFC
16
16
16
FFFFE
FFFFD
16
FFFFE
16
Content of reset vector
16
Content of reset vector
FFFFE
16
Content of reset vector
Figure 2.3.2 Reset sequence
Rev. 1.0
19
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
____________
2.3.2 Pin Status When RESET Pin Level is “L”
Table 2.3.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 2.3.3 and 2.3.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 2.3.1 Pin status when RESET pin level is “L”
____________
Pin name
P0
P1
P2, P3, P4
P4
4
P45 to P4
P5
0
P5
1
P5
2
P5
3
P5
4
0
7
to P4
Input port (floating)
Input port (floating)
Input port (floating)
3
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
CNVSS = V
SS
Data input (floating)
Data input (floating)
Address output (undefined)
CS0 output (“H” level is output)
Input port (floating)
(pull-up resistor is on)
WR output (“H” level is output)
BHE output (undefined)
RD output (“H” level is output)
BCLK output
HLDA output (The output value
depends on the input to the
HOLD pin)
Status
BYTE = V
SS
CNVSS = V
CC
BYTE = V
Data input (floating)
Input port (floating)
Address output (undefined)
CS0 output (“H” level is output)
Input port (floating)
(pull-up resistor is on)
WR output (“H” level is output)
BHE output (undefined)
RD output (“H” level is output)
BCLK output
HLDA output (The output value
depends on the input to the
HOLD pin)
CC
P5
5
P5
6
P5
7
P60 to P63, P67,
2
P7, P8
P8
, P83,
6
, P87, P9, P10
R, G, B, OUT1,
OUT2
CV
IN
, V
HOLD
,
HLF
OSC1
OSC2
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Output port
Input/output port
Input port
Output port
HOLD input (floating)
ALE output (“L” level is output)
RDY input (floating)
HOLD input (floating)
ALE output (“L” level is output)
RDY input (floating)
Input port (floating) Input port (floating)
Rev. 1.0
20
MITSUBISHI MICROCOMPUTERS
6
·
r
6
6
6
6
6
6
·
r
r
·
·
·
·
6
r
r
·
·
6
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
· ·
( 0 0 0 4
1 6)
· ·
( 0 0 0 51
6)
· ·
1 6)
( 0 0 0 6
· ·
( 0 0 0 7
1 6)
· ·
1 6)
( 0 0 0 8
A d d r e s s m a t c h i n t e r r u p t
e n a b l e r e g i s t e r
P r o t e c t r e g i s t e r(
2
M u l t i - m a s t e r I
i n t e r r u p t c o n t r o l r e g i s t e r
B u s c o l l i s i o n d e t e c t i o n i n t e r r u p t
c o n t r o l r e g i s t e r
D M A 0 i n t e r r u p t c o n t r o l r e g i s t e
C - B U S i n t e r f a c e 1
M u l t i - m a s t e r I
i n t e r r u p t c o n t r o l r e g i s t e r
A - D c o n v e r s i o n i n t e r r u p t
c o n t r o l r e g i s t e r
U A R T 2 t r a n s m i t i n t e r r u p t
c o n t r o l r e g i s t e r
U A R T 2 r e c e i v e i n t e r r u p t
c o n t r o l r e g i s t e r
U A R T 0 t r a n s m i t i n t e r r u p t
c o n t r o l r e g i s t e r
U A R T 0 r e c e i v e i n t e r r u p t
c o n t r o l r e g i s t e r
2
C - B U S i n t e r f a c e 0
D a t a s l i c e r i n t e r r u p t c o n t r o l r e g i s t e r
i n t e r r u p t c o n t r o l r e g i s t e
V
S Y N C
T i m e r A 0 i n t e r r u p t c o n t r o l r e g i s t e r
T i m e r A 1 i n t e r r u p t c o n t r o l r e g i s t e r
T i m e r A 2 i n t e r r u p t c o n t r o l r e g i s t e r
T i m e r A 3 i n t e r r u p t c o n t r o l r e g i s t e r
T i m e r A 4 i n t e r r u p t c o n t r o l r e g i s t e r
· ·
( 0 0 0 9
1 6)
· ·
0 0 0
1 6)
A
· ·
( 0 0 0 F1
6)
· ·
( 0 0 1 0
1 6)
· ·
1 6)
( 0 0 1 1
· ·
1 6)
( 0 0 1 2
· ·
( 0 0 1 4
1 6)
· ·
1 6)
( 0 0 1 5
· ·
1 6)
( 0 0 1 6
· ·
( 0 0 2 C
1 6)
· ·
1 6)
( 0 0 3 C
· ·
1 6)
( 0 0 4 4
· ·
( 0 0 4 81
6)
· ·
( 0 0 4 91
6)
· ·
( 0 0 4 A
1 6)
· ·
( 0 0 4 B1
6)
· ·
1 6)
( 0 0 4 C
· ·
( 0 0 4 D
1 6)
· ·
1 6)
( 0 0 4 E
· ·
( 0 0 4 F
1 6)
· ·
1 6)
( 0 0 5 0
· ·
1 6)
( 0 0 5 1
· ·
( 0 0 5 2
1 6)
· ·
1 6)
( 0 0 5 3
· ·
r
( 0 0 5 4
1 6)
· ·
1 6)
( 0 0 5 5
· ·
( 0 0 5 6
1 6)
· ·
1 6)
( 0 0 5 7
· ·
1 6)
( 0 0 5 8
· ·
( 0 0 5 9
1 6)
·P r o c e s s o r m o d e r e g i s t e r 0 ( N o t e ) 0 01
·P r o c e s s o r m o d e r e g i s t e r 1
4 81
·S y s t e m c l o c k c o n t r o l r e g i s t e r 0
2 01
·S y s t e m c l o c k c o n t r o l r e g i s t e r 1
0 11
·C h i p s e l e c t c o n t r o l r e g i s t e r
·
·W a t c h d o g t i m e r c o n t r o l r e g i s t e
00?0 ????
·A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 0
0 01
·
0 01
· 0
·A d d r e s s m a t c h i n t e r r u p t r e g i s t e r 1
0 01
·
0 01
· 0
·D M A 0 c o n t r o l r e g i s t e r 00000?00
·D M A 1 c o n t r o l r e g i s t e r 00000?00
·O S D 1 i n t e r r u p t c o n t r o l r e g i s t e r ?000
·O S D 2 i n t e r r u p t c o n t r o l r e g i s t e r
·
·D M A 1 i n t e r r u p t c o n t r o l r e g i s t e
· ? 0 0 0
· ? 0 0 0
·
·
·
·
·
·
·
·
·
·
·
l e v e l i s a p p l i e d t o t h e C N
p i n , i t i s 0
a t a r e s e t
T h e c o n t e n t o f o t h e r r e g i s t e r s a n d R A M i s u n d e f i n e d w h e n t h e m i c r o c o m p u t e r i s r e s e t . T h e i n i t i a l v a l u e s
m u s t t h e r e f o r e b e s e t .
N o t e : W h e n t h e VC
00 0
000
0 0 0
0 0 0
?000
?00000
0 0 0?
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
T i m e r B 0 i n t e r r u p t c o n t r o l r e g i s t e r
0
000
T i m e r B 1 i n t e r r u p t c o n t r o l r e g i s t e r
T i m e r B 2 i n t e r r u p t c o n t r o l r e g i s t e r
I N T 0 i n t e r r u p t c o n t r o l r e g i s t e r
I N T 1 i n t e r r u p t c o n t r o l r e g i s t e r
00
S P R I T E O S D c o n t r o l r e g i s t e r
O S D c o n t r o l r e g i s t e r 1
O S D c o n t r o l r e g i s t e r 2
H o r i z o n t a l p o s i t i o n r e g i s t e r
C l o c k c o n t r o l r e g i s t e r
I / O p o l a r i t y c o n t r o l r e g i s t e r
O S D c o n t r o l r e g i s t e r 3
R a s t e r c o l o r r e g i s t e r
O S D r e s e r v e d r e g i s t e r 1(
O S D c o n t r o l r e g i s t e r 4
D a t a s l i c e r c o n t r o l r e g i s t e r 1
D a t a s l i c e r c o n t r o l r e g i s t e r 2
C a p t i o n p o s i t i o n r e g i s t e r
D a t a s l i c e r r e s e r v e d r e g i s t e r 2(
D a t a s l i c e r r e s e r v e d r e g i s t e r 1(
C l o c k r u n - i n d e t e c t r e g i s t e r
D a t a c l o c k p o s i t i o n r e g i s t e r
L e f t b o r d e r c o n t r o l r e g i s t e r
R i g h t b o r d e r c o n t r o l r e g i s t e r
S P R I T E h o r i z o n t a l p o s i t i o n r e g i s t e r
( h i g h - o r d e r )
O S D r e s e r v e d r e g i s t e r 4
O S D r e s e r v e d r e g i s t e r 3
O S D r e s e r v e d r e g i s t e r 2
P e r i p h e r a l m o d e r e g i s t e
c o u n t e r r e g i s t e
H
S Y N C
X : N o t h i n g i s m a p p e d t o t h i s b i t
? : U n d e f i n e d
C
VS
S
31
6
· ·
( 0 0 5 A
· ·
( 0 0 5 B1
· ·
( 0 0 5 C
· ·
( 0 0 5 D
· ·
( 0 0 5 E
· ·
( 0 2 0 1
· ·
( 0 2 0 21
· ·
( 0 2 0 31
· ·
( 0 2 0 41
· ·
( 0 2 0 5
· ·
( 0 2 0 61
· ·
( 0 2 0 71
· ·
( 0 2 0 8
· ·
( 0 2 0 9
0 2 5
· ·
· ·
( 0 2 5 F
· ·
( 0 2 6 01
· ·
( 0 2 6 11
· ·
( 0 2 6 6
· ·
0 2 6
0 2 6
· ·
· ·
( 0 2 6 9
· ·
( 0 2 6 A1
· ·
( 0 2 7 0
· ·
( 0 2 7 11
· ·
( 0 2 7 2
· ·
( 0 2 7 3
· ·
( 0 2 7 9
· ·
( 0 2 7 A
· ·
( 0 2 7 B1
· ·
( 0 2 7 C
· ·
( 0 2 7 D1
· ·
( 0 2 7 E1
1 6)
6)
1 6)
1 6)
1 6)
1 6)
6)
6)
6)
1 6)
6)
6)
1 6)
1 6)
D1
6)
1 6)
6)
6)
1 6)
1 6)
7
81
6)
1 6)
6)
1 6)
6)
1 6)
1 6)
1 6)
1 6)
6)
1 6)
6)
6)
· ? 0 0 0
·
· 00000
·
· 0 01
·
· 0 01
·
·
·
·
· 0 01
·
· 0 01
· 000
?
0000
·
· 0 01
· 0 01
· 0 01
·
·
·
·
·
·
·
·
00000
·
? 0 0 0
? 0 0 0
? 00000
? 00000
0 01
6
6
0 01
6
6
00000010
0 01
6
0 01
6
0 01
6
6
00
6
????
?
000
6
6
6
00 010
0 11
6
000
0 01
000
000
00 00000
0 01
6
0 01
6
0
00 00
.
Figure 2.3.3 Device’s internal status after a reset is cleared (1)
Rev. 1.0
21
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
I
C0 address register
2
I
C0 status register
I2C0 control register
I2C0 clock control register
2
C0 port selection register
I
2
C1 address register
I
2
I
C1 status register
I2C1 control register
I2C1 clock control register
2
C1 port selection register
I
Reserved register 1
Reserved register 0
Interrupt request cause select register
Reserved register 3
Reserved register 4
Reserved register 5
UART2 special mode register
UART2 transmit/receive mode register
UART2 transmit/receive control register 0
UART2 transmit/receive control register 1
Count start flag
Reserved register 2
(02E1
16
)···
(02E216)···
16
(02E3
(02E4
16
16
(02E5
(02E9
16
(02EA
16
16
(02EB
(02EC
16
16
(02ED
(0340
16
16
(0348
16
(035F
(0362
16
16
(0366
16
(0376
000
)··· 00
)··· 00
)···
?00
)···
)···
000
)··· 00
)··· 00
)···
?00
000
)···
)··· 00
)··· 00
)··· 40
)··· 40
)··· 00
(037716)··· 00
(037816)··· 00
(037C
16
)···
(037D
16
)···
16
)··· 00
(0380
(0381
(0382
(0383
(0384
(0396
(0397
(0398
(0399
(039A
(039B
(039C
(039D
(03A0
(03A4
(03A5
(03A8
0
16
)···Clock prescaler reset flag
16
)···One-shot start flag
0000 000
16
)···Trigger select register
16
)···Up-down flag
16
)···Timer A0 mode register
16
)···Timer A1 mode register
16
)···Timer A2 mode register
16
)···Timer A3 mode register
16
)···Timer A4 mode register
16
)···Timer B0 mode register
0
0? 0000
16
)···Timer B1 mode register
00? 0000
16
)···Timer B2 mode register
00? 0000
16
)···UART0 transmit/receive mode register
16
)···UART0 transmit/receive control register 0
16
)···UART0 transmit/receive control register 1
16
)··· 00
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the V
00
16
000
1?
16
16
000
?0
00
16
000
1?
16
16
000
?0
???
??
16
16
16
16
16
16
16
08
16
02
16
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
08
16
02
16
16
CC
level is applied to the CNVSS pin, it is 0216 at a reset.
A-D control register 0
A-D control register 1
D-A control register
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Port P8 direction register
Port P9 direction register
Port P10 direction register
Pull-up control register 0
Pull-up control register 1(Note)
Pull-up control register 2
Port control register
Data registers (R0/R1/R2/R3)
Address registers (A0/A1)
Frame base register (FB)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
x : Nothing is mapped to this bit
? : Undefined
(03B0
16
)···UART transmit/receive control register 2
(03B816)···DMA0 request cause select register
16
)···DMA1 request cause select register
(03BA
(03D416)···A-D control register 2 0???
(03D616)···
16
)···
(03D7
(03DC
16
)··· 00
(03E2
16
)···
16
)···
(03E3
16
)···
(03E6
16
)···
(03E7
16
)···
(03EA
16
)···
(03EB
16
)···
(03EE
16
)···
(03EF
16
)···
(03F2
16
)···
(03F3
16
)···
(03F6
16
)···
(03FC
16
)···
(03FD
16
)···
(03FE
16
)··· 00
(03FF
00
00
0000
000 0???0
00
00
00
00
00
00
00
00
00
00 00000
00
00
00
00
00
0000
0000
0000
00000
0000
0000
0000
0000
0000000
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Figure 2.3.4 Device’s internal status after a reset is cleared (2)
22
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.4 Processor Mode
2.4.1 Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and microprocessor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
(1) Single-chip mode
In single-chip mode, only internal memory space (SFR, OSD RAM, internal RAM, and internal ROM)
can be accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the
internal peripheral functions.
(2) Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, OSD RAM, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “2.4.3 Bus
Settings” for details.)
(3) Microprocessor mode
In microprocessor mode, the SFR, OSD RAM, internal RAM, and external memory space can be
accessed. The internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “2.4.3 Bus
Settings” for details.)
2.4.2 Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
(1) Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
(2) Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figures 2.4.1 and 2.4.2 show the processor mode register 0 and 1.
Figure 2.4.3 shows the memory maps applicable for each of the modes.
Rev. 1.0
23
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
P r o c e s s o r m o d e r e g i s t e r 0 ( N o t e 1 )
d d r e s
h e n r e s e
0 0
b 7b 6b 5b 4b 3b 2b 1b 0
S y m b o lA
P M 00
P M 0 0
P M 0 1
P M 0 2
P M 0 3
P M 0 4
P M 0 5
P M 0 6
P M 0 7
N o t e s 1 : S e t b i t 1 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 A
v a l u e s t o t h i s r e g i s t e r .
2 : I f t h e V
r e s e t i s 0 3
3 : V a l i d i n m i c r o p r o c e s s o r a n d m e m o r y e x p a n s i o n m o d e s .
4 : I f t h e e n t i r e s p a c e i s o f m u l t i p l e x e d b u s i n m e m o r y e x p a n s i o n m o d e , c h o o s e a n 8 -
b i t w i d t h .
T h e p r o c e s s o r o p e r a t e s u s i n g t h e s e p a r a t e b u s a f t e r r e s e t i s r e v o k e d , s o t h e
e n t i r e s p a c e m u l t i p l e x e d b u s c a n n o t b e c h o s e n i n m i c r o p r o c e s s o r m o d e .
T h e h i g h e r - o r d e r a d d r e s s b e c o m e s a p o r t i f t h e e n t i r e s p a c e m u l t i p l e x e d b u s i s
c h o s e n , s o o n l y 2 5 6 b y t e s c a n b e u s e d i n e a c h c h i p s e l e c t .
sW
4
1 6
0 0
1 6
B i t n a m eF
P r o c e s s o r m o d e b i t
R / W m o d e s e l e c t b i t
S o f t w a r e r e s e t b i t
M u l t i p l e x e d b u s s p a c e
s e l e c t b i t
P o r t P 40 t o P 43 f u n c t i o n
s e l e c t b i t ( N o t e 3 )
B C L K o u t p u t d i s a b l e b i t
T h e d e v i c e i s r e s e t w h e n t h i s b i t i s s e t
t o “ 1 ” . T h e v a l u e o f t h i s b i t i s “ 0 ” w h e n
r e a d .
b 5 b 4
0 : A d d r e s s o u t p u t
1 : P o r t f u n c t i o n
( A d d r e s s i s n o t o u t p u t )
0 : B C L K i s o u t p u t
t
( N o t e 2 )
u n c t i o
b 1 b 0
0 0 : S i n g l e - c h i p m o d e
0 1 : M e m o r y e x p a n s i o n m o d e
1 0 : I n h i b i t e d
1 1 : M i c r o p r o c e s s o r m o d e
0 : R D , B H E , W R
1 : R D , W R H , W R L
0 0 : M u l t i p l e x e d b u s i s n o t u s e d
0 1 : A l l o c a t e d t o C S 2 s p a c e
1 0 : A l l o c a t e d t o C S 1 s p a c e
1 1 : A l l o c a t e d t o e n t i r e s p a c e ( N o t e 4 )
1 : B C L K i s n o t o u t p u t
( P i n i s l e f t f l o a t i n g )
1 6
) t o “ 1 ” w h e n w r i t i n g n e w
C C
v o l t a g e i s a p p l i e d t o t h e C N V
1 6
. ( P M 0 0 a n d P M 0 1 b o t h a r e s e t t o “ 1 ” . )
S S
, t h e v a l u e o f t h i s r e g i s t e r w h e n
nB i t s y m b o l
WR
Figure 2.4.1 Processor mode register 0
24
Rev. 1.0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
P r o c e s s o r m o d e r e g i s t e r 1 ( N o t e 1 )
d d r e s
h e n r e s e
0 0
b 7b 6b 5b 4b 3b 2b 1b 0
0
000
1
0
0 0 0 0 X 0
S y m b o lA
P M 10
and ON-SCREEN DISPLAY CONTROLLER
sW
5
1 6 0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
t
02
R e s e r v e d b i t
R e s e r v e d b i t ( N o t e 2 )
N o t h i n g i s a s s i g n e d .
I n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e “ 0 . ” T h e v a l u e , i f r e a d , t u r n s o u t t o b e
i n d e t e r m i n a t e .
R e s e r v e d b i t s
P M 1 7
t o “ 1 ” w h e n w r i t i n g n e w
N o t e s 1 : S e t b i t 1 o f t h e p r o t e c t r e g i s t e r ( a d d r e s s 0 0 0 A
v a l u e s t o t h i s r e g i s t e r .
2: A s t h i s b i t b e c o m e s “ 0 ” a t r e s e t , m u s t a l w a y s b e s e t t o “ 1 ” a f t e r r e s e t
r e l e a s e .
Figure 2.4.2 Processor mode register 1
W a i t b i t
1 6)
u n c t i o
nB i t s y m b o l
B i t n a m eF
M u s t a l w a y s b e s e t t o “ 0 ”
M u s t a l w a y s b e s e t t o “ 1 ”
M u s t a l w a y s b e s e t t o “ 0 ”
0 : N o w a i t s t a t e
1 : W a i t s t a t e i n s e r t e d
WR
Rev. 1.0
25
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
00000
003FF
00400
013FF
01400
02BFF
02C00
03FFF
04000
8FFFF
90000
AFFFF
B0000
Single-chip mode
16
SFR area
16
16
OSD RAM
16
16
Internal
reserved area
16
16
Internal
RAM area
16
16
Not used
16
16
OSD ROM
16
16
Memory expansion mode Microprocessor mode
SFR area
OSD RAM
Internal
reserved area
Internal RAM
area
External area
OSD ROM OSD ROM
SFR area
OSD RAM
Internal
reserved area
Internal RAM
area
External area
Internal
reserved area
Internal
ROM area
CFFFF
D0000
FFFFF
Internal
reserved area
16
16
Internal
ROM area
16
External area : Accessing this area allows you to
Figure 2.4.3 Memory maps in each processor mode
External area
access a device connected external
to the microcomputer.
26
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.4.3 Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the
bus settings.
Table 2.4.1 shows the factors used to change the bus settings.
Table 2.4.1 Factors for switching bus settings
Bus setting Switching factor
Switching external address bus width Bit 6 of processor mode register 0
Switching external data bus width BYTE pin
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K
bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register
0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the
address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode
register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43
become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can
be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The
internal bus width is permanently set to 16 bits.)
While operating, fix the BYTE pin either to “H” or to “L.”
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode
register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16
bits and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before using the multiplex bus for access, be sure to insert a software wait.
Rev. 1.0
27
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
In memory expansion mode, select a 8-bit multiplex bus.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed
bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256
bytes can be used in each chip select.
Table 2.4.2 Pin functions for each processor mode
P r o c e s s o r m o d e
M u l t i p l e x e d b u s
s p a c e s e l e c t b i t
D a t a b u s w i d t h
B Y T E p i n l e v e l
a t a b u
a t a b u
a t a b u
a t a b u
/ O p o r
P 00 t o P 0
/ O p o r
a t a b u
/ O p o r
a t a b u
/ O p o r
P 1
P 2
d d r e s s b u
P 2
d d r e s s b u
P 3
d d r e s s b u
P 3
/ O p o r
/ O p o r
O p o r
/ O p o r
/ O p o r
P 4
P o r t P 40 t o P 4
f u n c t i o n s e l e c t b i t = 1
d d r e s s b u
P 4
P o r t P 40 t o P 4
f u n c t i o n s e l e c t b i t = 0
P 4
P 5
L D
L D
L D
L D
L D
P 5
0
t o P 1
0
1
t o P 2
0
1
t o P 3
0
t o P 4
0
t o P 4
4
t o P 4
0
t o P 5
4
7
7
7
7
3
3
3
3
7
3
S i n g l e - c h i p
m o d e
M e m o r y e x p a n s i o n m o d e / m i c r o p r o c e s s o r m o d e s
E i t h e r C S 1 o r C S 2 i s f o r
m u l t i p l e x e d b u s a n d o t h e r s
a r e f o r s e p a r a t e b u s
8 b i t s
= “ H ”
I / O p o r tD
I / O p o r tI
I / O p o r t
I / O p o r t
A d d r e s s b u s
/ d a t a b u s
A d d r e s s b u sA
I / O p o r tA
/ d a t a b u s
I / O p o r tA
I / O p o r tI
I / O p o r tA
I / O p o r t
I / O p o r t
I / O p o r tH
C S ( c h i p s e l e c t ) o r p r o g r a m m a b l e I / O p o r t
O u t p u t s R D , W R L , W R H , a n d B C L K o r R D , B H E , W R , a n d B C L K
AH
e x p a n s i o n m o d e
“ 0 1 ” , “ 1 0 ”“
0 0
”“
( s e p a r a t e b u s )
1 6 b i t s
= “ L ”
sD
tD
sD
sI
8 b i t s
= “ H ”
sD
tD
1 6 b i t s
= “ L ”
sI
sI
A d d r e s s b u sA d d r e s s b u sA d d r e s s b u sA d d r e s s b u s
( N o t e 3 )
s
A d d r e s s b u sA d d r e s s b u sA d d r e s s b u s
/ d a t a b u s
( N o t e 3 )
A d d r e s s b u sA d d r e s s b u sA8/ D
s
( N o t e 3 )
/ d a t a b u s
A d d r e s s b u s
( N o t e 3 )
sA d d r e s s b u sA d d r e s s b u sA d d r e s s b u sI / O p o r t
tI
t/
tI
tI
sA d d r e s s b u sA d d r e s s b u sA d d r e s s b u sI / O p o r t
( F o r d e t a i l s , r e f e r t o “ 2 . 4 . 4 B u s c o n t r o l ” )
( F o r d e t a i l s , r e f e r t o “ 2 . 4 . 4 B u s c o n t r o l ” )
AH
AH
AH
M e m o r y
1 1 ” ( N o t e 1
M u l t i p l e x e d
b u s f o r t h e
e n t i r e
s p a c e
8 b i t s
= “ H ”
t
t
/ d a t a b u s
/ d a t a b u s
7
t
A
)
O L
O L
O L
O L
O L
P 5
D
D
D
D
D
L
L
L
L
L
P 5
P 5
5
6
7
I / O p o r tH
I / O p o r tA
I / O p o r tR
DH
EA
YR
N o t e s 1 : I n m e m o r y e x p a n s i o n m o d e , s e l e c t a 8 - b i t m u l t i p l e x b u s .
T h e p r o c e s s o r o p e r a t e s u s i n g t h e s e p a r a t e b u s a f t e r r e s e t i s r e v o k e d , s o t h e e n t i r e s p a c e m u l t i p l e x e d b u s c a n n o t b e
c h o s e n i n m i c r o p r o c e s s o r m o d e .
T h e h i g h e r - o r d e r a d d r e s s b e c o m e s a p o r t i f t h e e n t i r e s p a c e m u l t i p l e x e d b u s i s c h o s e n , s o o n l y 2 5 6 b y t e s c a n b e
u s e d i n e a c h c h i p s e l e c t .
2 : A d d r e s s b u s w h e n i n s e p a r a t e b u s m o d e .
28
DH
EA
YR
DH
EA
YR
DH
EA
YR
D
E
Y
Rev. 1.0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
M306V2EEFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2.4.4 Bus Control
The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory
expansion mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
When a change is made from single-chip mode to memory expansion mode, the value of the address
bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-
_______ _______
celled. CS1 to CS3 function as input ports. Figure 2.4.4 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 2.4.4
shows the external memory areas specified using the chip select signal.
_______
Table 2.4.3 External areas specified by the chip select signals
Chip select
CS0
CS1
CS2
CS3
Memory expansion mode Microprocessor mode
16
30000
2800016 to 2FFFF16 (32K)
08000
04000
to 8FFFF16 (384K)
16
to 27FFF16 (128K)
16
to 07FFF16 (16K)
Specified address range
30000
16
to 8FFFF16 (384K), B000016 to FFFFF16 (320K)
16
28000
08000
04000
to 2FFFF16 (32K)
16
to 27FFF16 (128K)
16
to 07FFF16 (16K)
Rev. 1.0
29
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
MITSUBISHI MICROCOMPUTERS
M306V2ME-XXXFP
and ON-SCREEN DISPLAY CONTROLLER
Symbol Address When reset
CSR 0008
16
01
16
M306V2EEFP
Bit symbol
CS0
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
Bit name
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Function
Figure 2.4.4 Chip select control register
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select
the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus
_____ ________ ______ _____ ________ _________
_____ ______ _______
(BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode
register 0 (address 000416) to “0”.) Tables 2.4.4 and 2.4.5 show the operation of these signals.
_____ ______ ________
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
_____ _________ _________
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of
the processor mode register 0 (address 000416) has been set (Note).
W
R
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of
the protect register (address 000A16) to “1”.
Table 2.4.4 Operation of RD, WRL, and WRH signals
_____ ________ _________
Data bus width
16-bit
(BYTE = “L”)
L
H
H
H
_____ ______ ________
H
L
H
L
WRHWRLRD
H
H
L
L
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
Status of external data bus
Table 2.4.5 Operation of RD, WR, and BHE signals
Data bus width A0
16-bit
(BYTE = “L”)
RD
BHEWR
HLL
LHL
HLH
LHH
H
H
HLLL
LHLL
8-bit
(BYTE = “H”)
H L H / L
L H H / L
Not used
Not used
Write 1 byte of data to odd address
Read 1 byte of data from odd address
L
L
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
Status of external data bus
30
Rev. 1.0
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