Mitsubishi M306N0MCT-XXXFP, M306N0FGTFP Datasheet
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Description
Description
The M16C/6NT group of single-chip microcomputers are built using the high-performance silicon gate CMOS
process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP. These singlechip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency.
With 1M bytes of address space, they are capable of executing instructions at high speed. They also feature
a built-in multiplier and DMAC, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications.
Being equipped with two CAN (Controller Area Network) modules, the microcomputer is suited to drive
automotive and industrial control systems. The CAN modules comply with the 2.0B specification.
Features
• Memory capacity.................................ROM 128K/256K bytes
RAM 5K/10K bytes
• Shortest instruction execution time...... 62.5 ns (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
100 ns (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
• Supply voltage..................................... 4.2 to 5.5V (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
4.2 to 5.5V (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
• Low power consumption ...................... TBD (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
TBD (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
• Interrupts ............................................. 29 internal and 9 external interrupt sources, 4 software
interrupt sources; 7 priority levels (including key input interrupt)
• Multifunction 16-bit timer ..................... 5 output timers + 6 input timers
• Serial I/O ............................................. 4 channels
(3 for UART or clock synchronous, 1 for clock synchronous)
• DMAC ................................................. 2 channels (trigger: 23 sources)
• CAN module ........................................ 2 channels, 2.0B active
• A-D converter ...................................... 10 bits X 26 analog inputs
• D-A converter ...................................... 8 bits X 2 analog outputs
• CRC calculation circuit ........................ 1 circuit
• Watchdog timer ................................... 1 15-bit timer
• Programmable I/O ............................... 87 lines
• Input port ............................................. 1 line (P85 shared with NMI pin)
• Chip select output................................ 4 lines
Specifications written in this
manual are believed to be accurate, but are not guaranteed
to be entirely free of error.
Specifications in this manual
may be changed for functional
or performance improvements.
Please make sure your manual
is the latest edition.
• Memory expansion .............................. Available (to a maximum of 1M bytes)
• Clock generating circuit ....................... 2 built-in clock generation circuits
(built-in feedback resistor, and external ceramic or quartz oscillator)
Applications
Automotive and industrial control systems
------Table of Contents------
Description...................................................... 1
Memory .......................................................... 9
Central Processing Unit (CPU) ...................... 1 8
Processor Mode............................................ 21
Protection ..................................................... 3 2
Reset ............................................................ 33
Clock Generating Circuit ............................... 38
Interrupts ...................................................... 52
DMAC ........................................................... 72
WD T ............................................................. 79
Tim er ............................................................ 81
Serial I/O .....................................................11 1
- UART0-2 ..............................................127
- SIO3.....................................................141
A-D Converter ..............................................144
D-A Converter ..............................................154
CRC Calculation Circuit................................156
CAN module ................................................158
Programmable I/O Ports ..............................17 8
Usage Precaution ........................................188
Electrical Characteristics (Vcc = 5 V) ..........190
Flash Memory Description ...........................20 6
CPU Rewrite Mode.......................................209
Parallel I/O Mode .........................................22 4
Standard Serial I/O Mode.............................239
1
Preliminary Specifications REV.B
Under
development
Specifications in this manual are tentative and subject to change.
Description
Pin Configuration
Figure 1-1 shows the pin configuration (top view).
PIN CONFIGURATION (top view)
)
0
/-)
/D
0
1
/(D
/(D
0
1
/A
/A
/INT5
/INT4
/INT3
20
10
8
11
12
9
/D
/D
0
1
P1
P1
13
/D
/D
/D
/D
2
3
4
5
P1
P1
P1
P1
21
15
14
/D
/D
/AN
/AN
7
6
0
1
P1
P1
P2
P2
)
1
/D
2
/(D
2
/A
22
/AN
2
P2
)
2
/D
3
/(D
3
/A
23
/AN
3
P2
)
3
/D
4
/(D
4
/A
24
/AN
4
P2
)
4
/D
5
/(D
5
/A
25
/AN
5
P2
)
5
/D
6
/(D
6
/A
26
/AN
6
P2
)
6
/D
7
/(D
7
/A
27
/AN
7
P2
Vss
)
7
(/-/D
8
/A
0
P3
Vcc
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
9
10
11
/A
/A
/A
1
2
3
P3
P3
P3
15
16
17
12
13
14
/A
/A
/A
4
5
6
P3
P3
P3
18
/A
7
P3
19
/A
/A
/A
/A
0
1
2
3
P4
P4
P4
P4
P07/AN07/D
P06/AN06/D
P05/AN05/D
P04/AN04/D
P03/AN03/D
P02/AN02/D
P01/AN01/D
P00/AN00/D
P107/AN7/KI
P106/AN6/KI
P105/AN5/KI
P104/AN4/KI
P103/AN
P102/AN
P101/AN
AV
P100/AN
V
AVcc
P97/AD
REF
TRG
/W
OUT
/TA2
4
P7
/V
IN
/TA1
2
/RTS
2
/CTS
3
P7
515253545556575859606162636465666768697071727374757677787980
IN
/V
OUT
/TB5
IN
/TA1
2
/CLK
2
/SCL/TA0
2
P7
/RxD
1
P7
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
OUT
/SDA/TA0
2
D
X
/T
0
P7
7
81
6
82
5
83
4
84
3
85
2
86
1
87
0
88
3
89
2
90
1
91
92
0
93
3
94
2
95
1
SS
96
97
0
98
99
00
1
123456789101112131415161718192021222324252627282930
0
0
/ANEX1/CTX
/ANEX0/CRX
6
5
P9
P9
M16C/6N Group
3
IN
/TB4
1
/DA
4
P9
IN
/TB3
0
/DA
3
P9
3
OUT
/S
IN
/TB2
2
P9
IN
/S
IN
/TB1
1
P9
BYTE
/CLK3
IN
/TB0
0
P9
CIN
/X
7
CNVss
P8
COUT
/X
6
P8
OUT
X
RESET
IN
SS
CC
X
V
V
/NMI
5
P8
2
/INT
4
P8
1
/INT
3
P8
0
/INT
2
P8
/U
IN
/TA4
1
P8
/U
OUT
/TA4
0
P8
1
/CRX
IN
/TA3
7
P7
1
/CTX
OUT
/TA3
6
P7
/W
IN
/TA2
5
P7
P44/CS0
P45/CS1
P46/CS2
P47/CS3
P50/WRL/WR
P51/WRH/BHE
P5
2
/RD
P53/BCLK
P54/HLDA
P5
5
/HOLD
P56/ALE
P57/RDY/CLK
P60/CTS0/RTS
P61/CLK
P62/RxD
P6
3/TXD0
P64/CTS1/RTS1/CTS0/CLKS
P65/CLK
P66/RxD
P67/TXD
OUT
0
0
0
1
1
1
1
Figure 1-1. Pin configuration (top view)
Package: 100P6S-A
2
Preliminary Specifications REV.B
Under
development
Specifications in this manual are tentative and subject to change.
Description
Block Diagram
Figure 1-2 is a block diagram of the M16C/6N group.
Block diagram of the M16C/6N group
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
8
I/O ports
Internal peripheral functions
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Port P08Port P18Port P28Port P38Port P48Port P58Port P6
Timer
A-D converter
(10 bits X 26 inputs)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits x 2 outputs)
UART/clock synchronous SI/O
(8 bits X 3 channels)
CRC arithmetic circuit (CCITT)
(Polynomial : X
M16C/60 series16-bit CPU core
Registers
R1H R1L
R1H R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
SB FLG
Note 1: Memory sizes depend on MCU type.
16+X12+X5
R0LR0H
R0LR0H
+1)
Program counter
PC
Vector table
INTB
Stack pointer
ISP
USP
System clock generator
X
IN-XOUT
X
CIN-XCOUT
Clock synchronous SI/O
(8 bits X 1 channel)
CAN module
(2 channels)
Memory
ROM
(Note 1)
RAM
(Note 1)
Multiplier
Port P7
8
Port P8
7
Port P8
5
Port P9
8
Port P10
8
Figure 1-2. Block diagram of M16C/6N group
3
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Description
Performance Outline
Table 1-1 is a performance outline of the M16C/6N group.
Table 1-1. Performance outline of M16C/6N group
Item Performance
Number of basic instructions 91 instructions
Shortest instruction execution time
Memory ROM 128K to 256K byte
capacity RAM 5K to 10K byte
I/O ports P0 to P10 (except P85) 8 bit x 10, 7 bit x 1
Input port P85 1 bit x 1
Multifunction TA0, TA1, TA2, TA3, TA4 16 bit x 5
timer TB0, TB1, TB2, TB3, TB4, TB5 16 bit x 6
Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3
SI/O3 Clock synchronous
A-D converter 10 bits x (8 + 8 + 8 + 2) inputs
D-A converter 8 bits x 2 channels
CRC calculation circuit CRC-CCITT
DMAC 2 channels (trigger: 23 sources)
CAN module 2 channels, 2.0B active
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 29 internal and 9 external sources, 4 software sources,
Clock generating circuit 2 built-in clock generation circuits (built-in feedback
Supply voltage
Power consumption
I/O I/O withstand voltage 5V
characteristics Output current 5mA
Operating ambient temperature –40 to 85oC
Device configuration CMOS high performance silicon gate
Package 100-pin plastic mold QFP
62.5 ns (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
100ns (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
7 priority levels
resistor, and external ceramic or quartz oscillator)
4.2 to 5.5V (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
4.2 to 5.5V (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
TBD (f(XIN) = 16MHz, 1/1 prescaler, without software wait)
TBD (f(XIN) = 20MHz, 1/2 prescaler, without software wait)
4
Under
development
Description
ROM Size
(Byte)
External
ROM
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
256K
128K
M306N0MCT-XXXFP
96K
64K
32K
Mask ROM version
Figure 1-3. ROM expansion
Table 1-2. M16C/6N group
Type No
M306N0MCT-XXXFP
M306N0FGTFP
One-time PROM version EPROM version Flash version
ROM size
128K byte
256K byte
RAM size
5K byte
10K byte
Package type
M306N0FGTFP
100P6S-A
100P6S-A
External ROM version
Apr. 1998
Remarks
Mask ROM version
Flash 5V version
5
Under
development
Description
Type No. M 3 0 6 N 0 M C T – X X X F P
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Package type:
FP : Package 100P6S-A
ROM No.
Omitted for Flash version
Temperature Range
ROM capacity:
1 : 8K bytes 7 : 56K bytes
2 : 16K bytes 8 : 64K bytes
3 : 24K bytes 9 : 80K bytes
4 : 32K bytes A : 96K bytes
5 : 40K bytes C : 128K bytes
6 : 48K bytes G : 256K bytes
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
T : Automotive 85oC version
Figure 1-4. Type No., memory size, and package
Memory type:
M : Mask ROM version
F : Flash ROM version
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
M16C/6N Group
M16C Family
6
Preliminary Specifications REV.B
Under
development
Pin Description
Description
Specifications in this manual are tentative and subject to change.
Table 1-3. Pin Description of M16C/6N group (1)
Pin name
Signal name
I/O type
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Function
VCC, V
SS
CNV
SS
RESET
X
IN
X
OUT
BYTE
CC
AV
AV
SS
V
REF
P00 to P0
D0 to D
7
Power supply
input
SS
CNV
Reset input
Clock input
Clock output
External data
bus width
select input
Analog power
supply input
Analog power
supply input
Reference
voltage input
I/O port P0
Input
Input
Input
Output
Input
Input
Input/output
Supply 4.0 to 5.5 V to the V
CC
pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect it to the
SS
pin to operate in single-chip or memory expansion mode.
V
Connect it to the V
CC
pin to operate in microprocessor mode.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the X
use an externally derived clock, input it to the X
X
OUT
pin open.
and the X
IN
pin and leave the
OUT
pins. To
IN
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. When
SS
operating in single-chip mode,connect this pin to V
.
This pin is a power supply input for the A-D converter. Connect this
CC
pin to V
.
This pin is a power supply input for the A-D converter. Connect this
SS
pin to V
.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input, the user can specify in units of four
bits via software whether or not they are tied to a pull-up resistor.
Pins in this port also function as A-D converter input pins.
7
Input/output
When set as a separate bus, these pins input and output data (D
0–D7
).
P10 to P1
D8 to D
15
P20 to P2
A0 to A
7
A0/D0 to
7/D7
A
A0, A1/D
to A7/D
P30 to P3
A8 to A
15
A8/D7,
9
to A
A
P40 to P4
0
to CS3,
CS
A
16
to A
7
7
0
7
15
7
6
19
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Input/output
Input/output
Input/output
Output
Input/output
Output
Input/output
Input/output
Output
Input/output
Output
Input/output
Output
Output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as external interrupt pins as selected by software.
When set as a separate bus, these pins input and output data
(D8–D15).
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins.
These pins output 8 low-order address bits (A0–A7).
If the external bus is set as an 8-bit wide multiplexed bus, these pins
0–D7
input and output data (D
0–A7
) separated in time by multiplexing.
(A
) and output 8 low-order address bits
If the external bus is set as a 16-bit wide multiplexed bus, these pins
0–D6
input and output data (D
in time by multiplexing. They also output address (A
) and output address (A1–A7) separated
0
).
This is an 8-bit I/O port equivalent to P0.
8–A15
These pins output 8 middle-order address bits (A
).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
7
input and output data (D
by multiplexing. They also output address (A
) and output address (A8) separated in time
9–A15
).
This is an 8-bit I/O port equivalent to P0.
These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip
16–A19
select signals used to specify an access space. A
are 4 high-
order address bits.
7
Preliminary Specifications REV.B
Under
development
Pin Description
Description
Specifications in this manual are tentative and subject to change.
Table 1-4. Pin Description of M16C/6N group (2)
Signal name FunctionPin name I/O type
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0
to P5
P5
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
P60 to P6
7
P70 to P77
0
to P84,
P8
P86,
P87,
P8
5
I/O port P5 Input/output
7
I/O port P6
I/O port P7
I/O port P8
Input port P8
5
Output
Output
Output
Output
Output
Input
Output
Input
Input/output
Input/output
Input/output
Input/output
Input/output
Input
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in
this port outputs a divide-by-8 or divide-by-32 clock of XIN or a clock of
the same frequency as X
CIN
as selected by software.
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is L and to the odd addresses when the WRH
signal is L . Data is read when RD is L .
WR, BHE, and RD selected
Data is written when WR is L . Data is read when RD is L . Odd
addresses are accessed when BHE is L . Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is L , the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a L
level. ALE is used to latch the address. While the input level of the
RDY pin is L , the microcomputer is in the ready state. BCLK outputs
a clock with the same cycle as the internal clock φ.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as UART0 and UART1 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as timer A
0
- A3, timer B5, UART2 I/O or CAN1 transmit/receive data
pins as selected by software.
P80 to P84, P86 and P87 are I/O ports with the same functions as P0.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8
6
and P87 can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P86 (X
pin) and P8
7
(X
CIN
pin). P85 is an input-only port that also functions
COUT
for NMI. The NMI interrupt is generated when the input at this pin
changes from H to L . The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.
P90 to P9
7
P100 to P10
I/O port P9
I/O port P10
7
Input/output
Input/output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as SI/O3 I/O pins, Timer B0 - B4 input pins, D-A converter output pins,
A-D converter extended input pins, A-D trigger input pins or CAN0
transmit/receive data pins as selected by software.
This is an 8-bit I/O port equivalent to P0. Pins in this port also function
as A-D converter input pins. Furthermore, P10
4
- P107 also function as
input pins for the key input interrupt function.
8
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Memory
Operation of Functional Blocks
The M16C/6N group accommodates several units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also
included are peripheral units such as CAN module, timers, serial I/O, D-A converter, DMAC, CRC calculation
circuit, A-D converter, and I/O ports.
Each unit is explained in the following.
Memory
Figure 2-1 depicts the memory map of the M16C/6N group. The address space extends the 1M bytes from
address 0000016 to FFFFF16. ROM is located from FFFFF16 down. For example, in the M306N0MCTXXXFP, there is 128K byte of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts
such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting addresses of the interrupt
routines are stored here. The address of the vector table for timer interrupts, etc., can be set as desired using
the internal register (INTB). See the section on interrupts for details.
RAM is located from 0040016 up. For example, in the M306N0MCT-XXXFP, 5K bytes of internal RAM are
mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack
used when calling subroutines and when interrupts are generated.
The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, CAN controller and timers, etc. Figure 2-2 to 2-9 are
locations of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and
cannot be used for other purposes.
The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or
the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be
implemented as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the space is reserved and cannot be used.
For example, in the M306N0MCT-XXXFP, the following space cannot be used.
• The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes)
• The space between D000016 and DFFFF16 (Memory expansion mode)
Type No. Address XXXXX16 Address YYYYY
M306N0MC 017FF16 E0000
M306N0FG
Figure 2-1. Memory map
02BFF
00000
16
SFR area
FFE00
16
00400
16
Internal RAM area
XXXXX
16
Internal reserved
16
area (Note 1)
04000
External area
Internal reserved
D0000
16
YYYYY
FFFFF
16
Note 1: During memory expansion and microprocessor modes, can not be used.
16
C0000
16
16
Note 2: In memory expansion mode, can not be used.
area (Note 2)
16
Internal ROM area
16
Special page
vector table
FFFDC
16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
FFFFF
DBC
NMI
Reset
16
9
ent
nder
U
developm
Memory
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
0040
16
0041
16
0042
16
0043
Processor mode register 0 (PM0)
Processor mode register 1(PM1)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Chip select control register (CSR)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Oscillation stop detection register (CM2)
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
DMA0 source pointer (SAR0)
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA1 source pointer (SAR1)
DMA1 destination pointer (DAR1)
DMA1 transfer counter (TCR1)
DMA1 control register (DM1CON)
0044
0045
0046
0047
0048
0049
004A
004B
004C
004D
004E
004F
0050
0051
0052
0053
0054
0055
0056
0057
0058
0059
005A
005B
005C
005D
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069
006A
006B
006C
006D
006E
006F
0070
0071
0072
0073
0074
0075
0076
0077
0078
0079
007A
007B
007C
007D
007E
007F
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CAN0/1 Wake Up interrupt control register (C01WKPIC)
CAN0 receive successful interrupt control register (C0RECIC)
CAN0 transmit successful interrupt control register (C0TRMIC)
INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
CAN1 receive successful interrupt control register (C1RECIC)
INT5 interrupt control register (INT5IC)
CAN1 transmit successful interrupt control register (C1TRMIC)
SIO3 interrupt control register (S3IC)
INT4 interrupt control register (INT4IC)
Bus collision detection interrupt control register (BCNIC)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
CAN0/1 error interrupt control register (C01ERRIC)
A-D conversion interrupt control register (ADIC)
Key input interrupt control register (KUPIC)
UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)
UART0 transmit interrupt control register (S0TIC)
UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)
Timer A0 interrupt control register (TA0IC)
Timer A1 interrupt control register (TA1IC)
Timer A2 interrupt control register (TA2IC)
Timer A3 interrupt control register (TA3IC)
Timer A4 interrupt control register (TA4IC)
Timer B0 interrupt control register (TB0IC)
Timer B1 interrupt control register (TB1IC)
Timer B2 interrupt control register (TB2IC)
INT0 interrupt control register (INT0IC)
INT1 interrupt control register (INT1IC)
INT2 interrupt control register (INT2IC)
CAN0 Slot 0: Message Identifier / DLC
CAN0 Slot 0: Data Field
CAN0 Slot 0: Time Stamp
CAN0 Slot 1: Message Identifier / DLC
CAN0 Slot 1: Data Field
CAN0 Slot 1: Time Stamp
Figure 2-2. Location of peripheral unit control registers (1)
10
Under
development
Memory
0080
0081
0082
0083
0084
0085
0086
0087
0088
0089
008A
008B
008C
008D
008E
008F
0090
0091
0092
0093
0094
0095
0096
0097
0098
0099
009A
009B
009C
009D
009E
009F
00A0
00A1
00A2
00A3
00A4
00A5
00A6
00A7
00A8
00A9
00AA
00AB
00AC
00AD
00AE
00AF
00B0
00B1
00B2
00B3
00B4
00B5
00B6
00B7
00B8
00B9
00BA
00BB
00BC
00BD
00BE
00BF
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
16
16
16
CAN0 Slot 2: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 2: Data Field
16
16
16
16
16
CAN0 Slot 2: Time Stamp
16
16
16
16
CAN0 Slot 3: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 3: Data Field
16
16
16
16
16
CAN0 Slot 3: Time Stamp
16
16
16
16
CAN0 Slot 4: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 4: Data Field
16
16
16
16
16
CAN0 Slot 4: Time Stamp
16
16
16
16
CAN0 Slot 5: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 5: Data Field
16
16
16
16
CAN0 Slot 5: Time Stamp
16
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
00C0
16
00C1
16
00C2
16
CAN0 Slot 6: Message Identifier / DLC
00C3
16
00C4
16
00C5
16
00C6
16
00C7
16
00C8
16
00C9
16
CAN0 Slot 6: Data Field
00CA
16
00CB
16
00CC
16
00CD
16
00CE
16
CAN0 Slot 6: Time Stamp
00CF
16
00D0
16
00D1
16
00D2
16
CAN0 Slot 7: Message Identifier / DLC
00D3
16
00D4
16
00D5
16
00D6
16
00D7
16
00D8
16
00D9
16
CAN0 Slot 7: Data Field
00DA
16
00DB
16
00DC
16
00DD
16
00DE
16
CAN0 Slot 7: Time Stamp
00DF
16
00E0
16
00E1
16
00E2
16
CAN0 Slot 8: Message Identifier / DLC
00E3
16
00E4
16
00E5
16
00E6
16
00E7
16
00E8
16
00E9
16
CAN0 Slot 8: Data Field
00EA
16
00EB
16
00EC
16
00ED
16
00EE
16
CAN0 Slot 8: Time Stamp
00EF
16
00F0
16
00F1
16
00F2
16
CAN0 Slot 9: Message Identifier / DLC
00F3
16
00F4
16
00F5
16
00F6
16
00F7
16
00F8
16
00F9
16
CAN0 Slot 9: Data Field
00FA
16
00FB
16
00FC
16
00FD
16
00FE
16
CAN0 Slot 9: Time Stamp
00FF
16
Mitsubishi microcomputers
M16C / 6N Group
Figure 2-3. Location of peripheral unit control registers (2)
11
ent
nder
U
developm
Memory
0100
0101
0102
0103
0104
0105
0106
0107
0108
0109
010A
010B
010C
010D
010E
010F
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119
011A
011B
011C
011D
011E
011F
0120
0121
0122
0123
0124
0125
0126
0127
0128
0129
012A
012B
012C
012D
012E
012F
0130
0131
0132
0133
0134
0135
0136
0137
0138
0139
013A
013B
013C
013D
013E
013F
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
16
16
16
CAN0 Slot 10: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 10: Data Field
16
16
16
16
16
CAN0 Slot 10: Time Stamp
16
16
16
16
CAN0 Slot 11: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 11: Data Field
16
16
16
16
16
CAN0 Slot 11: Time Stamp
16
16
16
16
CAN0 Slot 12: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 12: Data Field
16
16
16
16
16
CAN0 Slot 12: Time Stamp
16
16
16
16
CAN0 Slot 13: Message Identifier / DLC
16
16
16
16
16
16
16
CAN0 Slot 13: Data Field
16
16
16
16
CAN0 Slot 13: Time Stamp
16
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0140
16
0141
16
0142
16
CAN0 Slot 14: Message Identifier / DLC
0143
16
0144
16
0145
16
0146
16
0147
16
0148
16
0149
16
CAN0 Slot 14: Data Field
014A
16
014B
16
014C
16
014D
16
014E
16
CAN0 Slot 14: Time Stamp
014F
16
0150
16
0151
16
0152
16
CAN0 Slot 15: Message Identifier / DLC
0153
16
0154
16
0155
16
0156
16
0157
16
0158
16
0159
16
CAN0 Slot 15: Data Field
015A
16
015B
16
015C
16
015D
16
015E
16
CAN0 Slot 15: Time Stamp
015F
16
0160
16
CAN0 global mask (C0GMR)
0161
16
0162
16
0163
16
0164
16
0165
16
0166
16
CAN0 local mask A (C0LMAR)
0167
16
0168
16
0169
16
016A
16
016B
16
016C
16
CAN0 local mask B (C0LMBR)
016D
16
016E
16
016F
16
0170
16
0171
16
0172
16
0173
16
0174
16
0175
16
0176
16
0177
16
16
01B9
01BA
16
01BB
16
01BC
16
01BD
16
01BE
16
01BF
16
Mitsubishi microcomputers
M16C / 6N Group
Figure 2-4. Location of peripheral unit control registers (3)
12
Under
development
Memory
01C0
01C1
01C2
01C3
01C4
01C5
01C6
01C7
01C8
01C9
01CA
01CB
01CC
01CD
01CE
01CF
01D0
01D1
01D2
01D3
01D4
01D5
01D6
01D7
01D8
01D9
01DA
01DB
01DC
01DD
01DE
01DF
01E0
01E1
01E2
01E3
01E4
01E5
01E6
01E7
01E8
01E9
01EA
01EB
01EC
01ED
01EE
01EF
01F0
01F1
01F2
01F3
01F4
01F5
01F6
01F7
01F8
01F9
01FA
01FB
01FC
01FD
01FE
01FF
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
16
Timer B3,4,5 count start flag (TBSR)
16
Timer A1-1 register (TA11)
16
16
Timer A2-1 register (TA21)
16
16
Timer A4-1 register (TA41)
16
16
Three-phase PWM control register 0 (INVC0)
16
Three-phase PWM control register 1 (INVC1)
16
Three-phase output buffer register 0 (IDB0)
16
Three-phase output buffer register 1 (IDB1)
16
Dead time timer (DTT)
16
Timer B2 interrupt occurrence frequency set counter (ICTB2)
16
16
16
Timer B3 register (TB3)
16
16
Timer B4 register (TB4)
16
16
Timer B5 register (TB5)
16
16
16
16
16
16
16
Timer B3 mode register (TB3MR)
16
Timer B4 mode register (TB4MR)
16
Timer B5 mode register (TB5MR)
16
Interrupt cause select register 0 (IFSR0)
16
Interrupt cause select register 1 (IFSR1)
16
SI/O3 transmit/receive register (S3TRR)
16
16
SI/O3 control register (S3C)
16
SI/O3 bit rate generator (S3BRG)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
UART2 special mode register 2 (U2SMR2)
16
UART2 special mode register (U2SMR)
16
UART2 transmit/receive mode register (U2MR)
16
UART2 bit rate generator (U2BRG)
16
UART2 transmit buffer register (U2TB)
16
16
UART2 transmit/receive mode register 0 (U2C0)
16
UART2 transmit/receive mode register 1 (U2C1)
16
UART2 receive buffer register (U2RB)
16
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0200
16
CAN0 message control register 0 (C0MCTL0)
CAN0 message control register 1 (C0MCTL1)
0201
16
CAN0 message control register 2 (C0MCTL2)
0202
16
CAN0 message control register 3 (C0MCTL3)
0203
16
CAN0 message control register 4 (C0MCTL4)
0204
16
CAN0 message control register 5 (C0MCTL5)
0205
16
CAN0 message control register 6 (C0MCTL6)
0206
16
CAN0 message control register 7 (C0MCTL7)
0207
16
CAN0 message control register 8 (C0MCTL8)
0208
16
CAN0 message control register 9 (C0MCTL9)
0209
16
CAN0 message control register 10 (C0MCTL10)
020A
16
CAN0 message control register 11 (C0MCTL11)
020B
16
CAN0 message control register 12 (C0MCTL12)
020C
16
CAN0 message control register 13 (C0MCTL13)
020D
16
CAN0 message control register 14 (C0MCTL14)
020E
16
CAN0 message control register 15 (C0MCTL15)
020F
16
CAN0 control register (C0CTLR)
0210
16
0211
16
CAN0 status register (C0STR)
0212
16
0213
16
CAN0 slot status register (C0SSTR)
0214
16
0215
16
CAN0 slot interrupt control register (C0SICR)
0216
16
0217
16
CAN0 ExtID register (C0IDR)
0218
16
0219
16
CAN0 configuration register (C0CONR)
021A
16
021B
16
CAN0 REC register (C0RECR)
021C
16
CAN0 TEC register (C0TECR)
021D
16
CAN0 time stamp register (C0STR)
021E
16
021F
16
CAN1 message control register 0 (C1MCTL0)
0220
16
CAN1 message control register 1 (C1MCTL1)
0221
16
CAN1 message control register 2 (C1MCTL2)
0222
16
CAN1 message control register 3 (C1MCTL3)
0223
16
CAN1 message control register 4 (C1MCTL4)
0224
16
CAN1 message control register 5 (C1MCTL5)
0225
16
CAN1 message control register 6 (C1MCTL6)
0226
16
CAN1 message control register 7 (C1MCTL7)
0227
16
CAN1 message control register 8 (C1MCTL8)
0228
16
CAN1 message control register 9 (C1MCTL9)
0229
16
CAN1 message control register 10 (C1MCTL10)
022A
16
CAN1 message control register 11 (C1MCTL11)
022B
16
CAN1 message control register 12 (C1MCTL12)
022C
16
CAN1 message control register 13 (C1MCTL13)
022D
16
CAN1 message control register 14 (C1MCTL14)
022E
16
CAN1 message control register 15 (C1MCTL15)
022F
16
CAN1 control register (C1CTLR)
0230
16
0231
16
CAN1 status register (C1STR)
0232
16
0233
16
CAN1 slot status register (C1SSTR)
0234
16
0235
16
CAN1 slot interrupt control register (C1SICR)
0236
16
0237
16
CAN1 ExtID register (C1IDR)
0238
16
0239
16
CAN1 configuration register (C1CONR)
023A
16
023B
16
CAN1 REC register (C1RECR)
023C
16
CAN1 TEC register (C1TECR)
023D
16
CAN1 time stamp register (C1STR)
023E
16
023F
16
Mitsubishi microcomputers
M16C / 6N Group
Figure 2-5. Location of peripheral unit control registers (4)
13
ent
nder
U
developm
Memory
0240
0241
0242
0243
0244
0245
0246
0247
0248
0249
024A
024B
024C
024D
024E
024F
0250
0251
0252
0253
0254
0255
0256
0257
0258
0259
025A
025B
025C
025D
025E
025F
0260
0261
0262
0263
0264
0265
0266
0267
0268
0269
026A
026B
026C
026D
026E
026F
0270
0271
0272
0273
0274
0275
0276
0277
0278
0279
027A
027B
027C
027D
027E
027F
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
16
16
16
CAN0 acceptance filter support register (C0AFS)
16
16
CAN1 acceptance filter support register (C1AFS)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Peripheral function clock select register (PCLKR)
16
CAN0/1 clock select register (C01CLKR)
16
16
16
CAN1 Slot 0: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 0: Data Field
16
16
16
16
16
CAN1 Slot 0: Time Stamp
16
16
16
16
CAN1 Slot 1: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 1: Data Field
16
16
16
16
16
CAN1 Slot 1: Time Stamp
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0280
16
0281
16
CAN1 Slot 2: Message Identifier / DLC
0282
16
0283
16
0284
16
0285
16
0286
16
0287
16
0288
16
CAN1 Slot 2: Data Field
0289
16
028A
16
028B
16
028C
16
028D
16
CAN1 Slot 2: Time Stamp
028E
16
028F
16
0290
16
0291
16
CAN1 Slot 3: Message Identifier / DLC
0292
16
0293
16
0294
16
0295
16
0296
16
0297
16
0298
16
CAN1 Slot 3: Data Field
0299
16
029A
16
029B
16
029C
16
029D
16
CAN1 Slot 3: Time Stamp
029E
16
029F
16
02A0
16
02A1
16
CAN1 Slot 4: Message Identifier / DLC
02A2
16
02A3
16
02A4
16
02A5
16
02A6
16
02A7
16
02A8
16
CAN1 Slot 4: Data Field
02A9
16
02AA
16
02AB
16
02AC
16
02AD
16
CAN1 Slot 4: Time Stamp
02AE
16
02AF
16
02B0
16
02B1
16
CAN1 Slot 5: Message Identifier / DLC
02B2
16
02B3
16
02B4
16
02B5
16
02B6
16
02B7
16
02B8
16
CAN1 Slot 5: Data Field
02B9
16
02BA
16
02BB
16
02BC
16
02BD
16
CAN1 Slot 5: Time Stamp
02BE
16
02BF
16
Mitsubishi microcomputers
M16C / 6N Group
Figure 2-6. Location of peripheral unit control registers (5)
14
Under
development
Memory
02C0
02C1
02C2
02C3
02C4
02C5
02C6
02C7
02C8
02C9
02CA
02CB
02CC
02CD
02CE
02CF
02D0
02D1
02D2
02D3
02D4
02D5
02D6
02D7
02D8
02D9
02DA
02DB
02DC
02DD
02DE
02DF
02E0
02E1
02E2
02E3
02E4
02E5
02E6
02E7
02E8
02E9
02EA
02EB
02EC
02ED
02EE
02EF
02F0
02F1
02F2
02F3
02F4
02F5
02F6
02F7
02F8
02F9
02FA
02FB
02FC
02FD
02FE
02FF
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
16
16
16
CAN1 Slot 6: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 6: Data Field
16
16
16
16
16
CAN1 Slot 6: Time Stamp
16
16
16
CAN1 Slot 7: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 7: Data Field
16
16
16
16
16
CAN1 Slot 7: Time Stamp
16
16
16
16
CAN1 Slot 8: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 8: Data Field
16
16
16
16
16
CAN1 Slot 8: Time Stamp
16
16
16
16
CAN1 Slot 9: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 9: Data Field
16
16
16
16
16
CAN1 Slot 9: Time Stamp
16
16
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
0300
16
0301
16
0302
16
CAN1 Slot 10: Message Identifier / DLC
0303
16
0304
16
0305
16
0306
16
0307
16
0308
16
CAN1 Slot 10: Data Field
0309
16
030A
16
030B
16
030C
16
030D
16
CAN1 Slot 10: Time Stamp
030E
16
030F
16
0310
16
0311
16
CAN1 Slot 11: Message Identifier / DLC
0312
16
0313
16
0314
16
0315
16
0316
16
0317
16
0318
16
CAN1 Slot 11: Data Field
0319
16
031A
16
031B
16
031C
16
031D
16
CAN1 Slot 11: Time Stamp
031E
16
031F
16
0320
16
0321
16
CAN1 Slot 12: Message Identifier / DLC
0322
16
0323
16
0324
16
0325
16
0326
16
0327
16
0328
16
CAN1 Slot 12: Data Field
0329
16
032A
16
032B
16
032C
16
032D
16
CAN1 Slot 12: Time Stamp
032E
16
032F
16
0330
16
0331
16
CAN1 Slot 13: Message Identifier / DLC
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
CAN1 Slot 13: Data Field
0339
16
033A
16
033B
16
033C
16
033D
16
CAN1 Slot 13: Time Stamp
033E
16
033F
16
Mitsubishi microcomputers
M16C / 6N Group
Figure 2-7. Location of peripheral unit control registers (6)
15
ent
nder
U
developm
Memory
0340
0341
0342
0343
0344
0345
0346
0347
0348
0349
034A
034B
034C
034D
034E
034F
0350
0351
0352
0353
0354
0355
0356
0357
0358
0359
035A
035B
035C
035D
035E
035F
0360
0361
0362
0363
0364
0365
0366
0367
0368
0369
036A
036B
036C
036D
036E
036F
0370
0371
0372
0373
0374
0375
0376
0377
0378
0379
037A
037B
037C
037D
037E
037F
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
16
16
16
CAN1 Slot 14: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 14: Data Field
16
16
16
16
16
CAN1 Slot 14: Time Stamp
16
16
16
16
CAN1 Slot 15: Message Identifier / DLC
16
16
16
16
16
16
16
CAN1 Slot 15: Data Field
16
16
16
16
16
CAN1 Slot 15: Time Stamp
16
16
CAN1 global mask (C1GMR)
16
16
16
16
16
16
CAN1 local mask A (C1LMAR)
16
16
16
16
16
16
CAN1 local mask B (C1LMBR)
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Count start flag (TABSR)
0380
16
Clock prescaler reset flag (CPSRF)
0381
16
One-shot start flag (ONSF)
0382
16
Trigger select register (TRGSR)
0383
16
Up-down flag (UDF)
0384
16
0385
16
Timer A0 (TA0)
0386
16
0387
16
Timer A1 (TA1)
0388
16
0389
16
Timer A2 (TA2)
038A
16
038B
16
Timer A3 (TA3)
038C
16
038D
16
Timer A4 (TA4)
038E
16
038F
16
Timer B0 (TB0)
0390
16
0391
16
Timer B1 (TB1)
0392
16
0393
16
Timer B2 (TB2)
0394
16
0395
16
Timer A0 mode register (TA0MR)
0396
16
Timer A1 mode register (TA1MR)
0397
16
Timer A2 mode register (TA2MR)
0398
16
Timer A3 mode register (TA3MR)
0399
16
Timer A4 mode register (TA4MR)
039A
16
Timer B0 mode register (TB0MR)
039B
16
Timer B1 mode register (TB1MR)
039C
16
Timer B2 mode register (TB2MR)
039D
16
039E
16
039F
16
UART0 transmit/receive mode register (U0MR)
03A0
16
UART0 bit rate generator (U0BRG)
03A1
16
UART0 transmit buffer register (U0TB)
03A2
16
03A3
16
UART0 transmit/receive control register 0 (U0C0)
03A4
16
UART0 transmit/receive control register 1 (U0C1)
03A5
16
UART0 receive buffer register (U0RB)
03A6
16
03A7
16
UART1 transmit/receive mode register (U1MR)
03A8
16
UART1 bit rate generator (U1BRG)
03A9
16
UART1 transmit buffer register (U1TB)
03AA
16
03AB
16
UART1 transmit/receive control register 0 (U1C0)
03AC
16
UART1 transmit/receive control register 1 (U1C1)
03AD
16
UART1 receive buffer register (U1RB)
03AE
16
03AF
16
UART transmit/receive control register 2 (UCON)
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
Flash memory control register 2 (FMCR2)
03B6
16
Flash memory control register (FMCR)
03B7
16
DMA0 cause select register (DM0SL)
03B8
16
03B9
16
DMA1 cause select register (DM1SL)
03BA
16
03BB
16
CRC data register (CRCD)
03BC
16
03BD
16
CRC input register (CRCIN)
03BE
16
03BF
16
Mitsubishi microcomputers
Figure 2-8. Location of peripheral unit control registers (7)
16
Under
development
Memory
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
03C0
16
A-D register 0 (AD0)
03C1
16
03C2
16
A-D register 1 (AD1)
03C3
16
03C4
16
A-D register 2 (AD2)
03C5
16
03C6
16
A-D register 3 (AD3)
03C7
16
03C8
16
A-D register 4 (AD4)
03C9
16
03CA
16
A-D register 5 (AD5)
03CB
16
03CC
16
A-D register 6 (AD6)
03CD
16
03CE
16
A-D register 7 (AD7)
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
A-D control register 2 (ADCON2)
03D5
16
03D6
16
A-D control register 0 (ADCON0)
03D7
16
A-D control register 1 (ADCON1)
03D8
16
D-A register 0 (DA0)
03D9
16
03DA
16
D-A register 1 (DA1)
03DB
16
03DC
16
D-A control register (DACON)
03DD
16
03DE
16
03DF
16
03E0
16
Port P0 (P0)
03E1
16
Port P1 (P1)
03E2
16
Port P0 direction register (PD0)
03E3
16
Port P1 direction register (PD1)
03E4
16
Port P2 (P2)
03E5
16
Port P3 (P3)
03E6
16
Port P2 direction register (PD2)
03E7
16
Port P3 direction register (PD3)
03E8
16
Port P4 (P4)
03E9
16
Port P5 (P5)
03EA
16
Port P4 direction register (PD4)
03EB
16
Port P5 direction register (PD5)
03EC
16
Port P6 (P6)
03ED
16
Port P7 (P7)
03EE
16
Port P6 direction register (PD6)
03EF
16
Port P7 direction register (PD7)
03F0
16
Port P8 (P8)
03F1
16
Port P9 (P9)
03F2
16
Port P8 direction register (PD8)
03F3
16
Port P9 direction register (PD9)
03F4
16
Port P10 (P10)
03F5
16
03F6
16
Port P10 direction register (PD10)
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
Pull-up control register 0 (PUR0)
03FD
16
Pull-up control register 1 (PUR1)
03FE
16
Pull-up control register 2 (PUR2)
03FF
16
Port control register (PCR)
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 2-9. Location of peripheral unit control registers (8)
17
ent
Preliminary Specifications REV.B
Under
developm
CPU
Bus Control
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Central Processing Unit (CPU)
The CPU has a total of 13 registers shown in Figure 3-1. Seven of these registers (R0, R1, R2, R3, A0, A1,
and FB) come in two sets; therefore, these registers have two register banks.
R0
R1
R2
R3
A0
A1
FB
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
b15
b15
b15
b15
b15
b15
b15
b8 b7 b0
H
b8 b7 b0
H
L
b19
L
PC
b0
Program counter
Data
b0
registers
INTB
b19
H
b0
L
Interrupt table
register
b0
b0
b15
USP
b15
ISP
b0
User stack pointer
b0
Interrupt stack
pointer
Address
b0
b0
registers
Frame base
registers
SB
FLG
b15
b15
b0
Static base
register
b0
Flag register
IPL
CDZSBOIU
Note: These registers consist of two register banks.
Figure 3-1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can be
used as 32-bit data registers (R2R0/R3R1).
(2) Address rgisters (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
18
Preliminary Specifications REV.B
Under
development
Bus Control
CPU
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
(3) Frame base register (FB)
The frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
The program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
The interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt
vector table.
(6) Stack pointer (USP/ISP)
Stack pointers come in two types: the user stack pointer (USP) and the interrupt stack pointer (ISP), each
configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
The static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
The flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 3-2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation results in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation results in a negative value; otherwise, cleared to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is
selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation results in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to
“0” when the interrupt is acknowledged.
19
ent
Preliminary Specifications REV.B
Under
developm
CPU
Bus Control
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
• Bit 7: Stack pointer select flag (U flag)
The interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software
interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has a priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
IPL
b0b15
Flag register (FLG)
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Figure 3-2. Flag register (FLG)
Reserved area
20
Preliminary Specifications REV.B
Under
development
Bus Control
Processor Mode
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Processor Mode
(1) Processor Mode Types
One of three processor modes can be selected: single-chip mode, memory expansion mode and microprocessor mode. The functions of some pins, the memory map and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is
selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 3-3 shows the processor mode register 0 and 1.
Figure 3-4 shows the memory maps applicable for each of the modes when memory area dose not be
expanded (normal mode).
21
ent
Preliminary Specifications REV.B
Under
developm
Processor Mode
Bus Control
Specifications in this manual are tentative and subject to change.
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset
PM0 0004
16
00
16
(Note 2)
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
PM00
PM01
PM02
PM03
PM04
PM05
PM06
PM07
Note 1: Set bit 1 of the protect register (address 000A
values to this register.
Note 2: If the V
reset is 03
Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-
bit width.The processor operates using the separate bus after reset is revoked, so the entire
space multiplexed bus cannot be chosen in microprocessor mode.
The higher-order address becomes a port if the entire space multiplexed bus is chosen, so
only 256 bytes can be used in each chip select.
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol Address When reset
PM1 0005
0
Bit name FunctionBit symbol
Processor mode bit
R/W mode select bit
Software reset bit
Multiplexed bus space
select bit
Port P40 to P43 function
select bit (Note 3)
BCLK output disable bit
CC
voltage is applied to the CNV
16
. (PM00 and PM01 both are set to “1”.)
16
b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
1 1: Microprocessor mode
0 : RD,BHE,WR
1 : RD,WRH,WRL
The device is reset when this bit is set
to “1”. The value of this bit is “0” when
read.
b5 b4
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
0 : Address output
1 : Port function
(Address is not output)
0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)
16
) to “1” when writing new
SS
, the value of this register when
00000XX0
2
WR
Bit name FunctionBit symbol
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns
out to be
Note 1: Set bit 1 of the protect register (address 000A
Note 2: Be sure to set this bit to 0 except products whose RAM size and ROM size exceed 15K bytes
Note 3: With the processor running in memory expansion mode or in microprocessor mode, setting this
indeterminate.
PM13
PM14
PM15
Reserved bit
PM17 Wait bit
Internal reserved area
expansion bit (Note 2)
Memory area
expansion bit (Note 3)
and 192K bytes respectively.
Set this bit to "1" for M306N0FG.
Specify E0000
to “0” at the time reset is revoked, for the reset vector table of user program.
bit provides the means of expanding the external memory area. (Normal mode: up to 1M byte,
expansion mode 1: up to 1.2 M bytes, expansion mode 2: up to 4M bytes)
For details, see “Memory space expansion functions”.
16
or a subsequent address, which becomes an internal ROM area if PM13 is set
Must always be set to “0”
0: The same internal reserved
area as that of M16C/60 and
M16C/61 group
1: Expands the internal RAM area
and internal ROM area to 23 K
bytes and to 256K bytes
respectively. (Note 2)
b5 b4
0 0 : Normal mode
(Do not expand)
0 1 : Inhibited
1 0 : Memory area expansion
mode 1
1 1 : Memory area expansion
mode 2
Must always be set to “0”
0 : No wait state
1 : Wait state inserted
16
) to “1” when writing new values to this register.
WR
Figure 3-3. Processor mode register 0 and 1
22
Preliminary Specifications REV.B
Under
development
Bus Control
Processor Mode
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Type No. Address XXXXX16 Address YYYYY16
M306N0MC 017FF16 E000016
M306N0FG
Figure 3-4.
Memory maps in each processor mode
02BFF16 C000016
Single-chip mode
16
00000
0040016
XXXXX16
0400016
D000016
YYYYY16
FFFFF16
SFR area
Internal
RAM area
Inhibited
Internal
ROM area
Memory expansion mode
SFR area
Internal
RAM area
Internally
reserved area
External
area
Internally
reserved area
Internal
ROM area
External area : Accessing this area allows the user to
access a device connected externally
to the microcomputer.
Microprocessor mode
SFR area
Internal
RAM area
Internally
reserved area
External
area
23
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Preliminary Specifications REV.B
Under
developm
Bus Control
Bus Settings
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus
settings.
Table 3-1 shows the factors used to change the bus settings.
Table 3-1. Factors for switching bus settings
Bus setting Switching factor
Switching external address bus width Bit 6 of processor mode register 0
Switching external data bus width BYTE pin
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes
address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to
“1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to
P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the
external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be
set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus
width is permanently set to 16 bits.)
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the
BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as
the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits
and P0 and P1 are both used for the data bus.
When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin =
“H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7.
With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8.
D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are
mapped to the microcomputer’s even addresses (every 2nd address). To access these external devices, access the even addresses as bytes.
The ALE signal latches the address. It is output from P56.
Before accessing the multiplex bus, always set the CSi wait bit of the chip select control register to “0”.
In microprocessor mode, multiplexed bus for the entire space cannot be selected.
In memory expansion mode, when multiplexed bus for the entire space is selected, address bus range
is 256 bytes in each chip select.
24
Preliminary Specifications REV.B
Under
development
Bus Control
Bus Settings
Specifications in this manual are tentative and subject to change.
Table 3-2. Pin functions for each processor mode
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor mode
External bus type
Multiplexed bus
space select bit
Data bus width
BYTE pin level
P00 to P0
P1
P2
P2
P3
P31 to P3
P4
Port P40 to P4
function select bit = 1
P4
Port P40 to P4
function select bit = 0
P4
P5
0
to P1
0
1
to P2
0
0
to P4
0
to P4
4
to P4
0
to P5
7
7
7
7
3
3
3
3
7
3
Single-chip
mode
Memory expansion mode/microprocessor modes
Multiplexed bus and
separate bus
separate bus
Memory
expansion mode
Multiplexed
bus (Note 1)
01 , 10 00 11 (Note 2)
8 bits
= H
16 bits
= L
8 bits
= H
16 bits
= L
I/O port Data bus Data bus Data bus Data bus I/O port
I/O port I/O port Data bus I/O port Data bus I/O port
I/O port
I/O port
I/O port Address bus
Address bus
/data bus
Address bus Address bus
/data bus
(Note 3)
(Note 3)
Address bus Address bus Address bus Address bus
/data bus
Address bus
/data bus
(Note 3)
(Note 3)
/data bus
Address bus Address bus Address bus
/data bus
Address bus Address bus I/O port
I/O port Address bus Address bus Address bus Address bus I/O port
I/O port I/O port I/O port /O port I/O port I/O port
I/O port Address bus Address bus Address bus Address bus I/O port
I/O port
CS (chip select) or programmable I/O port
(For details, refer to Bus control )
I/O port
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to Bus control )
8 bita
= H
P5
P5
P5
P5
4
5
6
7
I/O port HLDA HLDA HLDA HLDA HLDA
I/O port HOLD HOLD HOLD HOLD HOLD
I/O port ALE ALE ALE ALE ALE
I/O port RDY RDY RDY RDY RDY
Note 1: In memory expansion mode, do not select a 16-bit multiplex bus.
Note 2: In microprocessor mode, multiplexed bus for the entire space cannot be selected.
In memory expansion mode, when multiplexed bus for the entire space is selected, address bus range is 256 bytes
in each chip select.
Note 3: Address bus when in separate bus mode.
25
ent
Under
developm
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Bus Control
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals
required for accessing the external devices are valid when the processor mode is set to memory expansion
mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space.
The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function
as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus.
Both the address and data bus retain their previous states when internal ROM or RAM is accessed.
Also, when a change is made from single-chip mode to memory expansion mode, the value of the
address bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control
register (address 000816) set each pin to function as a port or to output the chip select signal. The chip
select control register is valid in memory expansion mode and microprocessor mode. In single-chip
mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control
register.
In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been cancelled. CS1 to CS3 function as input ports. Figure 3-5 shows the chip select control register.
The chip select signal can be used to split the external area into as many as four blocks. Table 3-3
shows the external memory areas specified using the chip select signal.
Table 3-3. External areas specified by the chip select signals
Chip select
Special address range
Memory expansion mode
16
CS0
CS1
CS2
CS3
30000
28000
08000
04000
to CFFFF16 (640K)
16
to 2FFFF16 (32K)
16
to 27FFF16 (128K)
16
to 07FFF16 (16K)
Microprocessor mode
30000
16
to FFFFF16 (832K)
28000
16
to 2FFFF16 (32K)
16
08000
04000
to 27FFF16 (128K)
16
to 07FFF16 (16K)
26
Preliminary Specifications REV.B
Under
development
Specifications in this manual are tentative and subject to change.
Bus Control
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
Figure 3-5. Chip select control register
Symbol Address When reset
CSR 0008
Bit symbol
CS0
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
Bit name
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
Mitsubishi microcomputers
M16C / 6N Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
16
01
16
Function
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
W
R
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE pin
= “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0
(address 000416) to “0”.) Tables 3-4 and 3-5 show the operation of these signals.
After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
Table 3-4. Operation of RD, WRL, and WRH signals
Data bus width
16-bit
(BYTE = L )
WRHWRLRD
L
H
H
H
H
L
H
L
H
H
L
L
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
Status of external data bus
Table 3-5. Operation of RD, WR, and BHE signals
Data bus width A0
RD BHEWR
HLL
LHL
16-bit
(BYTE = L )
HLH
LHH
HLLL
LHLL
8-bit
(BYTE = H )
H L H / L
L H H / L
Not used
Not used
27
Status of external data bus
H
H
L
L
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
ent
Under
developm
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Bus Control
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the
ALE signal falls.
When BYTE pin = “H”
D
0/A0 to D7/A7
A8 to A19
ALE
Address Data (Note 1)
Address (Note 2)
Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
When BYTE pin = “L”
ALE
A
D
0/A1 to D7/A8
A9 to A19
0
Address Data (Note 1)
Address
Address
Figure 3-6. ALE sigal and address/data bus
(5) Ready signal
The ready signal facilitates access of external devices that require a long time for access. As shown in
Figure 3-7, inputting “L” to the RDY pin at the falling edge of BCLK causes the microcomputer to enter the
ready state. Inputting “H” to the RDY pin at the falling edge of BCLK cancels the ready state. Table 3-6
shows the microcomputer status in the ready state. Figure 3-7 shows the example of the RD signal being
extended using the RDY signal.
Ready is valid when accessing the external area during the bus cycle in which the software wait is applied.
Table 3-6. Microcomputer status in ready state (Note)
Item Status
Oscillation On
R/W signal, address bus, data bus, CS Maintain status when ready signal received
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits On
Note: The ready signal cannot be received immediately prior to a software wait.
BCLK
RD
CSi
(i = 0 to 3)
: Wait using ready function
: Wait using software
RDY
tsu
(RDY – BCLK)
Figure 3-7. Example of RD signal extended by RDY signal
28
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Bus Control
(6) Hold signal
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting “L” to
the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status
is maintained and “L” is output from the HLDA pin as long as “L” is input to the HOLD pin. Table 3-7 shows
the microcomputer status in the hold state.
Table 3-7. Microcomputer status in hold state
Item Status
Oscillation O N
R/W signal, address bus, data bus, CS, BHE Floating
Programmable I/O ports P0, P1, P2, P3, P4, P5 Floating
P6, P7, P8, P9, P10 Ma i ntains status when hold signal is received
HLDA Output “L”
Internal peripheral circuits ON (but watchdog timer stops)
ALE signal Undefined
(7) BCLK output
The output of the internal clock φ can be selected using bit 7 of the processor mode register 0 (address
000416) (Note). The output is floating when bit 7 is set to “1”.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
29
ent
Under
developm
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Mitsubishi microcomputers
M16C / 6N Group
Bus Control
(8) Software wait
A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address
000516) (Note) and bits 4 to 7 of the chip select control register (address 000816).
A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the
wait bit of the processor mode register 1. When set to “0”, each bus cycle is executed in one BCLK cycle.
When set to “1”, each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been
reset, this bit defaults to “0”. When set to “1”, bits 4 to 7 of the chip select control register are invalid and a
wait is applied to all external memory areas (two or three BCLK cycles). However, this is not necessary if the
oscillation frequency is less than 3MHz.
When the wait bit of the processor mode register 1 is “0”, software waits can be set independently for each
of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register correspond
to chip selects CS0 to CS3. When one of these bits is set to “1”, the bus cycle is executed in one BCLK
cycle. When set to “0”, the bus cycle is executed in two or three BCLK cycles. These bits default to “0”
after the microcomputer has been reset.
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,
the corresponding bits of the chip select control register must be set to “0” if using the multiplex bus to
access the external memory area.
Table 3-8 shows the software wait and bus cycles. Figure 3-8 shows example bus timing when using
software waits.
Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect
register (address 000A16) to “1”.
Table 3-8. Software waits and bus cycles
Area Bus status Wait bit
SFR
Internal
ROM/RAM
Separate bus
Separate bus
Bits 4 to 7 of chip select
control register
Invalid Invalid 2 BCLK cycles
0 Invalid 1 BCLK cycle
Invalid1 2 BCLK cycles
0 1 1 BCLK cycle
0 0 2 BCLK cycles
Bus cycle
External
memory
area
Separate bus
1 0 (Note) 2 BCLK cycles
Multiplex bus 0 0 (Note) 3 BCLK cycles
Multiplex bus
1 3 BCLK cycles0 (Note)
Note: Always set to "0".
30
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