How it Works
Mitsubishi
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M30620M8A-XXXFP
Datasheet
274 pgs3.58 Mb0
Table of contents
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Mitsubishi M30624MGA-XXXGP, M30624MGA-XXXFP, M30624FGAGP, M30624FGAFP, M30622M8A-XXXFP Datasheet

...
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Description

Features

• Memory capacity..................................ROM (See Figure 1.1.4. ROM Expansion)
RAM 3K to 20K bytes
• Shortest instruction execution time......62.5ns (f(XIN)=16MHZ, VCC=5V)
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait) : Mask ROM, flash memory 5V version
• Supply voltage .....................................
• Low power consumption ......................25.5mW ( f(XIN)=10MHZ, with software one-wait, VCC = 3V)
• Interrupts..............................................25 internal and 8 external interrupt sources, 4 software
• Multifunction 16-bit timer......................5 output timers + 6 input timers
• Serial I/O..............................................5 channels
• DMAC ..................................................2 channels (trigger: 24 sources)
• A-D converter.......................................10 bits X 8 channels (Expandable up to 10 channels)
• D-A converter.......................................8 bits X 2 channels
• CRC calculation circuit.........................1 circuit
• Watchdog timer....................................1 line
• Programmable I/O ...............................87 lines
• Input port..............................................
• Memory expansion ..............................Available (to a maximum of 1M bytes)
• Chip select output ................................4 lines
• Clock generating circuit .......................2 built-in clock generation circuits
4.2V to 5.5V (f(XIN)=16MHZ, without software wait) : Mask ROM, flash memory
2.7V to 5.5V (f(XIN)=10MHZ with software one-wait) :
interrupt sources; 7 levels (including key input interrupt)
(3 for UART or clock synchronous, 2 for clock synchro-
nous)
_______
1 line (P85 shared with NMI pin)
(built-in feedback resistor, and external ceramic or quartz oscillator)
Mask ROM, flash memory 5V version
5V
version

Applications

Audio, cameras, office equipment, communications equipment, portable equipment
Central Processing Unit (CPU) .....................11
Reset.............................................................14
Processor Mode............................................ 21
Clock Generating Circuit ............................... 34
Protection......................................................43
Interrupts.......................................................44
Watchdog Timer............................................64
DMAC ...........................................................66
------Table of Contents------
Timer.............................................................76
Serial I/O .....................................................106
A-D Converter ............................................. 147
D-A Converter ............................................. 157
CRC Calculation Circuit ..............................159
Programmable I/O Ports .............................161
Electrical characteristic ...............................176
Flash memory version.................................227
1
s
p
R
Description

Pin Configuration

Figures 1.1.1 and 1.1.2 show the pin configurations (top view).
PIN CONFIGURATION (top view)
)
)
)
3
/D
4
(/D
4
/A
4
P2
4
/D
5
(/D
5
/A
5
P2
5
/D
6
(/D
6
/A
6
P2
)
6
/D
7
(/D
7
/A
7
P2
Vss
)
)
)
0
1
2
/D
/D
/D
/-)
1
2
3
0
/INT5
/INT4
/INT3
10
8
11
12
9
/D
/D
0
1
P1
P1
13
/D
/D
/D
/D
2
3
4
5
P1
P1
P1
P1
(/D
(/D
(/D
(/D
15
14
1
2
3
0
/D
/D
/A
/A
/A
/A
7
6
1
2
3
0
P1
P1
P2
P2
P2
P2
)
7
(/-/D
8
/A
0
P3
Vcc
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
9
10
11
/A
/A
/A
1
2
3
P3
P3
P3
15
16
17
12
13
14
/A
/A
/A
4
5
6
P3
P3
P3
18
/A
7
P3
19
/A
/A
/A
/A
0
1
2
3
P4
P4
P4
P4
P107/AN7/KI P106/AN6/KI P105/AN5/KI
P104/AN4/KI
P103/AN P102/AN P101/AN
P100/AN
P97/AD
P07/D P06/D P05/D P04/D P03/D P02/D P01/D P00/D
AV
V
AVcc
TRG/SIN
REF
/W
OUT
/TA2
4
P7
/V
IN
/TA1
2
/RTS
2
/CTS
3
P7
515253545556575859606162636465666768697071727374757677787980
IN
/V
OUT
/TB5
IN
/TA1
2
/CLK
2
/SCL/TA0
2
P7
/RxD
1
P7
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
OUT
/SDA/TA0
2
D
X
/T
0
P7
7
81
6
82
5
83
4
84
3
85
2
86
1
87
0
88
3
89
2
90
1
91 92
0
93
3
94
2
95
1
SS
96 97
0
98 99 00
1
4
1 2 3 4 5 6 7 8 9 101112131415161718192021222324252627282930
4
OUT
/ANEX0/CLK4
/ANEX1/S
5
6
P9
P9
M16C/62A Group
3
IN
/TB4
1
/DA
4
P9
IN
/TB3
0
/DA
3
P9
3
OUT
/S
IN
/TB2
2
P9
IN
/S
IN
/TB1
1
P9
BYTE
/CLK3
IN
/TB0
0
P9
CIN
/X
7
CNVss
P8
COUT
/X
6
P8
OUT
X
RESET
IN
SS
CC
X
V
V
/NMI
5
P8
2
/INT
4
P8
1
/INT
3
P8
0
/INT
2
P8
/U
IN
/TA4
1
P8
/U
OUT
/TA4
0
P8
IN
/TA3
7
P7
OUT
/TA3
6
P7
/W
IN
/TA2
5
P7
P44/CS0 P45/CS1 P46/CS2 P47/CS3 P50/WRL/WR P51/WRH/BHE P5
2
/RD P53/BCLK P54/HLDA P55/HOLD P56/ALE P57/RDY/CLK P60/CTS0/RTS P61/CLK P62/RxD P6
3/TXD0
P64/CTS1/RTS1/CLKS P65/CLK P66/RxD P67/TXD
OUT
0 0 0
1 1 1
1
Figure 1.1.1. Pin configuration (top view)
2
Package: 100P6S-A
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
PIN CONFIGURATION (top view)
P12/D
P11/D P10/D
P07/D
P06/D P05/D
P04/D
P03/D
P02/D P01/D P00/D
P107/AN7/KI P106/AN6/KI P105/AN5/KI P104/AN4/KI
P103/AN P102/AN P101/AN
AV
P100/AN
V
P9
P97/AD
6
TRG/SIN
/ANEX1/S
AVcc
OUT
P95/ANEX0/CLK4
REF
)
3
/D
4
(/D
4
/A
4
P2
)
4
/D
5
(/D
5
/A
5
P2
)
5
/D
6
(/D
6
/A
6
P2
)
6
/D
7
(/D
7
/A
7
P2
Vss
)
7
(/-/D
8
/A
0
P3
Vcc
9
/A
1
P3
10
/A
2
P3
11
/A
3
P3
12
/A
4
P3
13
/A
5
P3
14
/A
6
P3
15
/A
7
P3
16
17
/A
/A
0
1
P4
P4
525354555657585960616263646566676869707172737475
51
P42/A
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
18
P43/A
19
P44/CS0
P45/CS1 P46/CS2 P47/CS3
P50/WRL/WR P51/WRH/BHE
2
/RD
P5 P53/BCLK P54/HLDA P55/HOLD
P56/ALE P57/RDY/CLK P60/CTS0/RTS
P61/CLK P62/RxD
3/TXD0
P6
OUT
0
0
0
P64/CTS1/RTS1/CLKS P65/CLK
1
P66/RxD
1
P67/TXD
1
P70/TXD2/SDA/TA0
1
/RxD2/SCL/TA0IN/TB5
P7 P72/CLK2/TA1
OUT
/V
OUT
1
IN
)
)
)
1
0
/-)
0
(/D
0
/A
0
P2
/D
1
(/D
1
/A
1
P2
/D
2
(/D
2
/A
2
P2
2
/D
3
(/D
3
/A
3
P2
3
4
5
/INT
/INT
11
/D
3
P1
10
SS
76
9
77
8
78
7
79
6
80
5
81
4
82
3
83
2
84
1
85
0
86
3
87
2
88
1
89
0
90
3
91
2
92
1
93 94 95
0
96 97
4
98
4
99 00
1
1 2 3 4 5 6 7 8 9 10111213141516171819202122 23 24 25
/INT
12
13
14
15
/D
/D
/D
/D
4
5
6
7
P1
P1
P1
P1
M16C/62A Group
Figure 1.1.2. Pin configuration (top view)
IN
/TB4
1
/DA
4
P9
IN
/TB3
0
/DA
3
P9
3
OUT
/S
IN
/TB2
2
P9
3
IN
/S
IN
/TB1
1
P9
BYTE
/CLK3
IN
/TB0
0
P9
CIN
/X
7
CNVss
P8
COUT
/X
6
P8
OUT
X
RESET
1
2
/NMI
5
P8
/INT
4
P8
/INT
3
P8
0
/INT
2
P8
/U
IN
/TA4
1
P8
/U
OUT
/TA4
0
P8
IN
/TA3
7
P7
OUT
/TA3
6
P7
/W
IN
/TA2
5
P7
/W
OUT
/TA2
4
P7
/V
IN
/TA1
2
/RTS
2
/CTS
3
Package: 100P6Q-A
P7
IN
SS
CC
X
V
V
3
s
p
R
Description
A
A
A
ote
depends o
type

Block Diagram

Figure 1.1.3 is a block diagram of the M16C/62A group.
Block diagram of the M16C/62A group
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
8
I/O ports
Internal peripheral functions
Timer TA0 (16 bits) Timer TA1 (16 bits) Timer TA2 (16 bits) Timer TA3 (16 bits) Timer TA4 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TB2 (16 bits) Timer TB3 (16 bits) Timer TB4 (16 bits) Timer TB5 (16 bits)
Port P08Port P18Port P28Port P38Port P48Port P58Port P6
Timer
Expandable up to 10 channels)
UART/clock synchronous SI/O
CRC arithmetic circuit (CCITT )
(Polynomial : X
M16C/60 series16-bit CPU core
Watchdog timer
(15 bits)
DMAC
(2 channels)
D-A converter
(8 bits X 2 channels)
Note 1: ROM size depends on MCU type. N
2: RAM size
n MCU
A-D converter
(10 bits X 8 channels
(8 bits X 3 channels)
16+X12+X5
Registers
R0LR0H
R1H R1L
R0LR0H
R1H R1L
R2
R2
R3
R3
A0
A0
A1
A1
FB
FB
SB FLG
.
+1)
Program counter
PC
Stack pointer
ISP
USP
Vector table
INTB
Flag register
System clock generator
X
IN-XOUT
X
CIN-XCOUT
Clock synchronous SI/O
(8 bits X 2 channels)
Memory
ROM
AAAA
(Note 1)
RAM
AAAA
(Note 2)
AAAA
Multiplier
Port P7
8
Port P8
7
Port P8
5
Port P9
8
Port P10
8
Figure 1.1.3. Block diagram of M16C/62A group
4
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description

Performance Outline

Table 1.1.1 is a performance outline of M16C/62A group.
Table 1.1.1. Performance outline of M16C/62A group
Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 62.5ns(f(XIN)=16MHZ,
100ns (f(XIN)=10MHZ, VCC=3V, with software one-wait)
: Mask ROM, flash memory 5V version Memory ROM (See the figure 1.1.4. ROM Expansion) capacity RAM 3K to 20K bytes I/O port P0 to P10 (except P85) 8 bits x 10, 7 bits x 1 Input port P85 1 bit x 1 Multifunction TA0, TA1, TA2, TA3, TA4 16 bits x 5 timer TB0, TB1, TB2, TB3, TB4, TB5 16 bits x 6 Serial I/O UART0, UART1, UART2 (UART or clock synchronous) x 3
SI/O3, SI/O4 (Clock synchronous) x 2 A-D converter 10 bits x (8 + 2) channels D-A converter 8 bits x 2 DMAC 2 channels (trigger: 24 sources) CRC calculation circuit CRC-CCITT Watchdog timer 15 bits x 1 (with prescaler) Interrupt Clock generating circuit 2 built-in clock generation circuits
Supply voltage 4.2V to 5.5V (f(XIN)=16MHZ, without software wait)
Power consumption I/O I/O withstand voltage 5V characteristics Memory expansion Available (to a maximum of 1M bytes) Device configuration CMOS high performance silicon gate Package 100-pin plastic mold QFP
Output current 5mA
25 internal and 8 external sources, 4 software sources, 7 levels
(built-in feedback resistor, and external ceramic or quartz oscillator)
: Mask ROM, flash memory 5V version
2.7V to 5.5V (f(XIN)=10MHZ with software one-wait) : Mask ROM, flash memory 5V version
25.5mW (f(XIN) = 10MHZ, VCC=3V with software one-wait)
VCC=5V
)
5
s
p
R
Description
p
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Mitsubishi plans to release the following products in the M16C/62A group: (1) Support for mask ROM version, external ROM version, and flash memory version (2) ROM capacity (3) Package
100P6S-A : Plastic molded QFP (mask ROM, one-time PROM, and flash memory versions) 100P6Q-A : Plastic molded QFP(mask ROM, one-time PROM, and flash memory versions)
ROM Size
(Byte)
External
ROM
256K
128K
96K
64K
32K
M30624MGA-XXXFP/GP M30620MCA-XXXFP/GP
M30622MCA-XXXFP/GP M30620MAA-XXXFP/GP
M30622MAA-XXXFP/GP M30620M8A-XXXFP/GP
M30622M8A-XXXFP/GP M30622M4A-XXXFP/GP
Mask ROM version
M30624FGAFP/GP
M30620FCAFP/GP
Flash memory version
M30620SAFP/GP M30622SAFP/GP
External ROM version
Mitsubishi microcomputer
M16C / 62A Grou
Figure 1.1.4. ROM expansion
The M16C/62A group products currently supported are listed in Table 1.1.2.
Table 1.1.2. M16C/62A group
ROM capacity M30622M4A-XXXFP M30622M4A-XXXGP 100P6Q-A
M30620M8A-XXXFP M30620M8A-XXXGP 100P6Q-A
M30622M8A-XXXFP M30622M8A-XXXGP
M30620MAA-XXXFP M30620MAA-XXXGP
M30622MAA-XXXFP M30622MAA-XXXGP 100P6Q-A
M30620MCA-XXXFP M30620MCA-XXXGP
M30622MCA-XXXFP M30622MCA-XXXGP
M30624MGA-XXXFP M30624MGA-XXXGP 100P6Q-A
M30620FCAFP
M30620FCAGP
M30624FGAFP
M30624FGAGP
** **
** ** ** ** ** ** ** ** ** ** ** ** ** **
** ** ** **
32K byte
64K byte
96K byte
128K byte
256K byte
128K byte
256K byte
**
M30620SAGP M30622SAFP M30622SAGP
**: Under develo
ment
** ** **
RAM capacity
3K byte
10K byte
4K byte
10K byte
5K byte
10K byte
5K byte
20K byte
10K byte
20K byte
10K byte
3K byte
Package type
100P6S-A
100P6S-A
100P6S-A 100P6Q-A
100P6S-A 100P6Q-A
100P6S-A
100P6S-A 100P6Q-A
100P6S-A 100P6Q-A
100P6S-A
100P6S-A 100P6Q-A 100P6S-A
100P6Q-A 100P6S-AM30620SAFP 100P6Q-A 100P6S-A 100P6QA-A
December. 1999
RemarksType No
Mask ROM version
Flash memory 5V version
External ROM version
6
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
Type No. M 3 0 6 2 2 M 8 A– X X X F P
Package type: FP : Package 100P6S-A GP : 100P6Q-A
ROM No. Omitted for flash memory version
ROM capacity: 4 : 32K bytes 8 : 64K bytes A : 96K bytes C : 128K bytes G: 256K bytes
Memory type: M : Mask ROM version S : External ROM version F : Flash memory version
Figure 1.1.5. Type No., memory size, and package
Shows RAM capacity, pin count, etc (The value itself has no specific meaning)
M16C/62 Group M16C Family
7
s
p
R
Pin Description
Pin Description
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Pin name
VCC, V
SS
CNV
SS
RESET X
IN
X
OUT
BYTE
CC
AV
AV
SS
V
REF
P00 to P0
D0 to D
7
7
Signal name
Power supply input
SS
CNV
Reset input Clock input
Clock output
External data bus width select input
Analog power supply input
Analog power supply input
Reference voltage input
I/O port P0
I/O type
Input
Input Input
Output
Input
Input
Input/output
Input/output
Function
Supply 2.7 to 5.5 V to the V
CC
pin. Supply 0 V to the VSS pin.
This pin switches between processor modes. Connect this pin to the
SS
pin when after a reset you want to start operation in single-chip
V mode (memory expansion mode) or the V
CC
pin when starting
operation in microprocessor mode. A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit.Connect a ceramic resonator or crystal between the X use an externally derived clock, input it to the X
OUT
pin open.
X
and the X
IN
pin and leave the
OUT
pins. To
IN
This pin selects the width of an external data bus. A 16-bit width is selected when this input is “L”; an 8-bit width is selected when this input is “H”. This input must be fixed to either “H” or “L”. Connect this
SS
pin to the V
pin when not using external data bus.
This pin is a power supply input for the A-D converter. Connect this
CC
pin to V
.
This pin is a power supply input for the A-D converter. Connect this
SS
pin to V
.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When used for input in single-chip mode, the port can be set to have or not have a pull-up resistor in units of four bits by software. In memory expansion and microprocessor modes, selection of the internal pull-resistor is not available.
When set as a separate bus, these pins input and output data (D
0–D7
).
P10 to P1
D8 to D
15
P20 to P2 A0 to A
7
A0/D0 to
7/D7
A
A0, A1/D to A7/D
P30 to P3 A8 to A
15
A8/D7,
9
to A
A
P40 to P4
0
to CS3,
CS
16
to A
A
0
15
7
7
6
7
7
19
I/O port P1
I/O port P2
I/O port P3
I/O port P4
Input/output
Input/output
Input/output
Output
Input/output
Output
Input/output
Input/output
Output
Input/output
Output
Input/output
Output Output
This is an 8-bit I/O port equivalent to P0. Pins in this port also function as external interrupt pins as selected by software.
When set as a separate bus, these pins input and output data
(D8–D15).
This is an 8-bit I/O port equivalent to P0.
0–A7
These pins output 8 low-order address bits (A
).
If the external bus is set as an 8-bit wide multiplexed bus, these pins
0–D7
input and output data (D
0–A7
) separated in time by multiplexing.
(A
) and output 8 low-order address bits
If the external bus is set as a 16-bit wide multiplexed bus, these pins
0–D6
input and output data (D in time by multiplexing. They also output address (A
) and output address (A1–A7) separated
0
).
This is an 8-bit I/O port equivalent to P0.
8–A15
These pins output 8 middle-order address bits (A
).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
7
input and output data (D by multiplexing. They also output address (A
) and output address (A8) separated in time
9–A15
).
This is an 8-bit I/O port equivalent to P0. These pins output CS0–CS3 signals and A16–A19. CS0–CS3 are chip
select signals used to specify an access space. A
16–A19
are 4 high-
order address bits.
8
Pin Description
s
p
R
Pin Description
0
to P5
P5
7
Signal name FunctionPin name I/O type
I/O port P5 Input/output
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
This is an 8-bit I/O port equivalent to P0. In single-chip mode, P57 in this port outputs a divide-by-8 or divide-by-32 clock of X the same frequency as X
CIN
as selected by software.
IN
or a clock of
WRL / WR, WRH / BHE, RD, BCLK, HLDA, HOLD,
ALE, RDY
P60 to P6
7
P70 to P77
P8
0
to P84,
P8
6
,
P8
7
,
P8
5
I/O port P6
I/O port P7
I/O port P8
I/O port P8
5
Output Output Output Output Output Input
Output Input
Input/output
Input/output
Input/output Input/output
Input/output
Input
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE signals. WRL and WRH, and BHE and WR can be switched using software control. WRL, WRH, and RD selected With a 16-bit external data bus, data is written to even addresses when the WRL signal is “L” and to the odd addresses when the WRH signal is “L”. Data is read when RD is “L”. WR, BHE, and RD selected Data is written when WR is “L”. Data is read when RD is “L”. Odd addresses are accessed when BHE is “L”. Use this mode when using an 8-bit external data bus. While the input level at the HOLD pin is “L”, the microcomputer is placed in the hold state. While in the hold state, HLDA outputs a “L” level. ALE is used to latch the address. While the input level of the RDY pin is “L”, the microcomputer is in the ready state.
This is an 8-bit I/O port equivalent to P0. When used for input in single­chip, memory expansion, and microprocessor modes, the port can be set to have or not have a pull-up resistor in units of four bits by software. Pins in this port also function as UART0 and UART1 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6 (P7 open-drain output). Pins in this port also function as timer A
0
and P71 are N channel
0–A3
,
timer B5 or UART2 I/O pins as selected by software.
P80 to P84, P86, and P87 are I/O ports with the same functions as P6. Using software, they can be made to function as the I/O pins for timer A4 and the input pins for external interrupts. P8
6
and P87 can be set using software to function as the I/O pins for a sub clock generation circuit. In this case, connect a quartz oscillator between P8 pin) and P8
7
(X
CIN
pin). P85 is an input-only port that also functions
6
(X
COUT
for NMI. The NMI interrupt is generated when the input at this pin changes from “H” to “L”. The NMI function cannot be cancelled using software. The pull-up cannot be set for this pin.
P90 to P9
7
P100 to P10
I/O port P9
I/O port P10
7
Input/output
Input/output
This is an 8-bit I/O port equivalent to P6. Pins in this port also function as SI/O3, 4 I/O pins, Timer B0–B4 input pins, D-A converter output pins, A-D converter extended input pins, or A-D trigger input pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function as A-D converter input pins. Furthermore, P10
4
–P107 also function as
input pins for the key input interrupt function.
9
Mitsubishi microcomputer
s
p
R
A
A
M16C / 62A Grou

Memory

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE

Operation of Functional Blocks

The M16C/62A group accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit, A-D converter, and I/O ports. The following explains each unit.
Memory
Figure 1.3.1 is a memory map of the M16C/62A group. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30622MCA-XXXFP, there is 128K bytes of internal ROM from E000016 to FFFFF16. The vector table for fixed interrupts such as the reset and NMI are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30622MCA-XXXFP, 5K bytes of internal RAM is mapped to the space from 0040016 to 017FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for periph­eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. For example, in the M30622MCA-XXXFP, the following spaces cannot be used.
• The space between 0180016 and 03FFF16 (Memory expansion and microprocessor modes)
• The space between D000016 and D7FFF16 (Memory expansion mode)
_______
Type No.
M30622M4A 00FFF M30620M8A 02BFF M30620MAA E8000
M30620MCA/FCA E0000 M30622M8A F0000
M30622MAA M30622MCA
M30624MGA/FGA
Address XXXXX
Figure 1.3.1. Memory map
10
02BFF 02BFF 013FF 017FF 017FF 053FF
16 16 16 16 16 16 16 16 16
Address YYYYY
F8000 F0000
E8000 E0000 C0000
00000
16
SFR area
For details, see Figures
1.6.1 to 1.6.3
00400
16
Internal RAM area
XXXXX
16
Internal reserved
04000
area (Note 1)
16
AAA
External area
AAA
D0000
16
YYYYY
16 16 16
FFFFF
16 16 16
Note 1: During memory expansion and microprocessor modes, can not be used.
16
Note 2: In memory expansion mode, can not be used.
16
Note 3: These memory maps show an instance in which PM13 is set to 0; but in the
Internal reserved
16
area (Note 2)
16
Internal ROM area
16
case of M30624MGA/FGA, they show an instance in which PM13 is set to 1.
FFE00
FFFDC
FFFFF
16
Special page
vector table
16
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
16
DBC NMI
Reset
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
A

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.
R0
R1
R2
R3
A0
A1
FB
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
b15
b15
b15
b15
b15
b15
b15
b8 b7 b0
H
b8 b7 b0
H
L
b19
L
PC
b0
Program counter
Data
b0
registers
INTB
b19
H
b0
L
Interrupt table register
b0
b0
b15
USP
b15
ISP
b0
User stack pointer
b0
Interrupt stack pointer
Address
b0
b0
registers
Frame base registers
SB
FLG
b15
b15
b0
Static base register
b0
Flag register
IPL
CDZSBOIU
Note: These registers consist of two register banks.
Figure 1.4.1. Central processing unit register
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H), and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
11
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
(3) Frame base register (FB)
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
(4) Program counter (PC)
Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.
(5) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.
(6) Stack pointer (USP/ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config­ured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).
(7) Static base register (SB)
Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.
(8) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.
“1”
when an arithmetic operation resulted in a negative value; otherwise, cleared to
“0”
.
12
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CPU
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.
• Bit 15: Reserved area
The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.
IPL
b0b15
Flag register (FLG)
CDZSBOIU
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Figure 1.4.2. Flag register (FLG)
13
Mitsubishi microcomputer
s
p
R
M16C / 62A Grou

Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence.
RESET
Example when V
V
CC
Figure 1.5.1. Example reset circuit
X
IN
More than 20 cycles are needed
Microprocessor
mode BYTE = “H”
RESET
BCLK
Address
RD
BCLK 24cycles
CC
= 5V
5V
V
CC
0V
5V
RESET
0V
4.0V
0.8V
.
Content of reset vector
FFFFC
16
FFFFD
16
FFFFE
16
WR
CS0
Microprocessor
mode BYTE = “L”
Address
RD
WR
CS0
Single chip
mode
Address
Figure 1.5.2. Reset sequence
14
Content of reset vector
FFFFC
FFFFC
16
16
FFFFE
FFFFE
16
Content of reset vector
16
s
p
R
Reset
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Table 1.5.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.5.3 and 1.5.4
____________
show the internal status of the microcomputer immediately after the reset is cancelled.
Table 1.5.1. Pin status when RESET pin level is “L”
____________
Status
Pin name
P0 P1 P2, P3, P4 P4
4
P45 to P4
P5
0
P5
1
P5
2
0
7
to P4
CNVSS = V
Input port (floating) Input port (floating) Input port (floating)
3
Input port (floating) Input port (floating)
Input port (floating) Input port (floating) Input port (floating)
SS
CNVSS = V
BYTE = V
SS
Data input (floating) Data input (floating) Address output (undefined) CS0 output (“H” level is output)
Input port (floating) (pull-up resistor is on)
WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output)
CC
BYTE = V
CC
Data input (floating) Input port (floating) Address output (undefined) CS0 output (“H” level is output)
Input port (floating) (pull-up resistor is on)
WR output (“H” level is output) BHE output (undefined) RD output (“H” level is output)
P5
3
P5
4
P5
5
P5
6
P5
7
P6, P7, P80 to P84,
6
, P87, P9, P10
P8
Input port (floating)
Input port (floating)
Input port (floating) Input port (floating) Input port (floating)
Input port (floating)
BCLK output HLDA output (The output value
depends on the input to the HOLD pin)
HOLD input (floating) ALE output (“L” level is output) RDY input (floating)
BCLK output HLDA output (The output value
depends on the input to the HOLD pin)
HOLD input (floating) ALE output (“L” level is output) RDY input (floating)
Input port (floating) Input port (floating)
15
s
p
R
Reset
16
(1) (0004
)···Processor mode register 0 (Note 1) 00
(2) (000516)···Processor mode register 1 000
16
(3) (0006 (4) (0007 (5) (0008 (6) (0009
Address match interrupt enable register (7) Protect register (000A (8) (9)
(10)
(11) (12) (13) (14) (15) (16) (17) (18)
Bus collision detection interrupt
(19)
control register
(20) (21) (22) (23)
A-D conversion interrupt control register (24)
UART2 transmit interrupt control register
(25)
UART2 receive interrupt control register
(26)
UART0 transmit interrupt control register UART0 receive interrupt control register
(27) (28)
UART1 transmit interrupt control register
)···System clock control register 0 10000100
16
)···System clock control register 1 00010000
16
)···Chip select control register 00000010
16
)···
16
)···
(000F16)···Watchdog timer control register 00?0????
16
)···Address match interrupt register 0
(0010
16
)···
(0011
16
)··· 0
(0012
16
)···Address match interrupt register 1
(0014
16
)···
(0015 (0016
16
)··· 0
16
)···DMA0 control register 00000?00
(002C
16
)···DMA1 control register 00000?00
(003C
(0044
16
)···INT3 interrupt control register 00?000
16
)···Timer B5 interrupt control register ?000
(0045
16
)···Timer B4 interrupt control register ?000
(0046
16
)···Timer B3 interrupt control register ?000
(0047 (0048
16
)···SI/O4 interrupt control register
16
)···SI/O3 interrupt control register
(0049
16
)···
(004A (004B
16
)···DMA0 interrupt control register ? 0 0 0
16
)···DMA1 interrupt control register ? 0 0 0
(004C
16
)···Key input interrupt control register ? 0 0 0
(004D
16
)··· ? 0 0 0
(004E (004F
16
)···
16
)···
(0050
(0051
16
)···
(0052
16
)···
16
)···
(0053
16
000
000
00
16
00
16
0 0 0
00
16
00
16
0 0 0
00?000
00?000
0 0 0?
? 0 0 0
? 0 0 0 ? 0 0 0 ? 0 0 0
? 0 0 0
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
(29)
UART1 receive interrupt control register
(30)
Timer A0 interrupt control register
(31)
Timer A1 interrupt control register
(32)
Timer A2 interrupt control register
(33)
Timer A3 interrupt control register
(34)
00
Timer A4 interrupt control register
(35)
Timer B0 interrupt control register
(36)
Timer B1 interrupt control register
(37)
Timer B2 interrupt control register
(38)
INT0 interrupt control register
(39)
INT1 interrupt control register
(40)
INT2 interrupt control register
(41)
Timer B3,4,5 count start flag
(42)
Three-phase PWM control register 0
(43)
Three-phase PWM control register 1
(44)
Three-phase output buffer register 0
(45)
Three-phase output buffer register 1
(46)
Timer B3 mode register
(47)
Timer B4 mode register
(48)
Timer B5 mode register
(49)
Interrupt cause select register (50) (51)
SI/O4 control register (52)
UART2 special mode register 3 (Note 2) (037516)···
UART2 special mode register 2 (0376
(53)
UART2 special mode register
(54)
(55)
UART2 transmit/receive mode register (56)
UART2 transmit/receive control register 0 (57)
UART2 transmit/receive control register 1
Mitsubishi microcomputer
M16C / 62A Grou
16
(0054 (0055 (0056 (0057 (0058 (0059 (005A (005B (005C (005D (005E (005F (0340 (0348 (0349 (034A (034B (035B
(035C (035D (035F (0362 (0366
(0377
(0378 (037C (037D
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···SI/O3 control register
16
)···
16
)···
16
)···
16
)···
16
)···
16
)···
? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 00000 ? 00000 ? 00000
000
00
16
00
16
00
16
00
16
00? 0000 00? 0000 00? 0000
00
16
40
16
40
16
?
00
16
00
16
00
16
00000001 01000000
x : Nothing is mapped to this bit ? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set. Note 1: When the V
Note 2: “00
CC
16
level is applied to the CNVSS pin, it is 0316 at a reset.
” is read out when set bit 7 (SDDS) of the UART2 special mode register ( address 037716) to “1”.
Figure 1.5.3. Device's internal status after a reset is cleared
16
s
p
R
Reset
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
(58)
Count start flag (0380
(59)
(61)
(65)
(67)
(69)
(79) (80) (81)
(82) (83)
16
16
)··· 00
16
)···Clock prescaler reset flag
(0381
16
)···One-shot start flag(60)
(0382 (038316)···Trigger select flag
16
)···Up-down flag(62)
(0384 (0396
16
)···Timer A0 mode register(63)
16
)···Timer A1 mode register(64)
(0397 (0398
16
)···Timer A2 mode register
16
)···Timer A3 mode register(66)
(0399
(039A
16
)···Timer A4 mode register
(039B
16
)···Timer B0 mode register(68)
16
)···Timer B1 mode register
(039C (039D
16
)···Timer B2 mode register(70)
16
)···UART0 transmit/receive mode register(71)
(03A0 (03A4
16
)···UART0 transmit/receive control register 0(72)
(03A5
16
)···UART0 transmit/receive control register 1(73)
(03A8
16
)···UART1 transmit/receive mode register(74) 00
(03AC
16
)···UART1 transmit/receive control register 0(75)
(03AD
16
)···UART1 transmit/receive control register 1(76)
(03B0
16
)···UART transmit/receive control register 2(77) 0
(03B6
16
)···Flash memory control register 1 (Note2)(78)
(03B7
16
)···Flash memory control register 0 (Note2)
16
)···DMA0 cause select register
(03B8
(03BA
16
)···DMA1 cause select register 00 (03D416)···A-D control register 2 (03D6
16
)···A-D control register 0
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note1: When the V Note2: This register is only exist in flash memory version.
16
0
0000 000
00
16
00
16
00
16
00
16
00
16
00
16
00
16
0
0? 0000 00? 0000 00? 0000
00
16
000 1000
0
000 0010
0
16
000 1000
0
000 0010
0
0 00000
0
???? ???
0 00010
00
16
16
0000
(84) (85) (86) (87) (88) (89) (90) (91) (92) (93) (94) (95) (96) (97) (98)
(99) (100)
Port control register
(101)
Data registers (R0/R1/R2/R3)
(102)
Address registers (A0/A1)
(103)
Frame base register (FB)
(104)
Interrupt table register (INTB)
(105)
User stack pointer (USP)
(106)
Interrupt stack pointer (ISP) Static base register (SB)
(107)
Flag register (FLG)
(108)
0
000 0???0
x : Nothing is mapped to this bit ? : Undefined
CC
level is applied to the CNVSS pin, it is 0216 at a reset.
(03D7
16
(03DC
16
(03E2
16
(03E3 (03E6
16
(03E7
16
(03EA
16
(03EB
16
(03EE
16
(03EF
16
16
(03F2 (03F3
16
(03F6
16
(03FC
16
16
(03FD (03FE
16
(03FF16)···
)···A-D control register 1 00 )···D-A control register )···Port P0 direction register )···Port P1 direction register )···Port P2 direction register )···Port P3 direction register )···Port P4 direction register )···Port P5 direction register )···Port P6 direction register )···Port P7 direction register )···Port P8 direction register )···Port P9 direction register )···Port P10 direction register )···Pull-up control register 0 )···Pull-up control register 1(Note1) )···Pull-up control register 2
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00 00000
00
16
00
16
00
16
00
16
00
16
00
16
0000 0000 0000
00000
0000 0000 0000 0000
16
16
16
16
16
16
16
16
Figure 1.5.4. Device's internal status after a reset is cleared
17
s
p
R
SFR
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
000016 000116 000216 000316
Processor mode register 0 (PM0)
000416 000516
Processor mode register 1(PM1)
000616
System clock control register 0 (CM0)
000716
System clock control register 1 (CM1)
000816
Chip select control register (CSR)
000916
Address match interrupt enable register (AIER)
000A16
Protect register (PRCR)
000B16 000C16 000D16 000E16
Watchdog timer start register (WDTS) Watchdog timer control register (WDC)
000F16 001016 001116
Address match interrupt register 0 (RMAD0)
001216 001316 001416
Address match interrupt register 1 (RMAD1)
001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 002016
DMA0 source pointer (SAR0)
002116 002216 002316 002416 002516
DMA0 destination pointer (DAR0)
002616 002716 002816
DMA0 transfer counter (TCR0)
002916 002A16 002B16 002C16
DMA0 control register (DM0CON)
002D16 002E16 002F16 003016
DMA1 source pointer (SAR1)
003116 003216 003316 003416
DMA1 destination pointer (DAR1)
003516 003616 003716 003816
DMA1 transfer counter (TCR1)
003916 003A16 003B16 003C16
DMA1 control register (DM1CON)
003D16 003E16 003F16
004016 004116 004216 004316
INT3 interrupt control register (INT3IC)
004416 004516
Timer B5 interrupt control register (TB5IC) Timer B4 interrupt control register (TB4IC)
004616
Timer B3 interrupt control register (TB3IC)
004716
SI/O4 interrupt control register (S4IC)
004816
INT5 interrupt control register (INT5IC) SI/O3 interrupt control register (S3IC)
004916
INT4 interrupt control register (INT4IC)
Bus collision detection interrupt control register (BCNIC)
004A16
DMA0 interrupt control register (DM0IC)
004B16 004C16
DMA1 interrupt control register (DM1IC) Key input interrupt control register (KUPIC)
004D16
A-D conversion interrupt control register (ADIC)
004E16
UART2 transmit interrupt control register (S2TIC)
004F16
UART2 receive interrupt control register (S2RIC)
005016
UART0 transmit interrupt control register (S0TIC)
005116
UART0 receive interrupt control register (S0RIC)
005216
UART1 transmit interrupt control register (S1TIC)
005316
UART1 receive interrupt control register (S1RIC)
005416
Timer A0 interrupt control register (TA0IC)
005516
Timer A1 interrupt control register (TA1IC)
005616
Timer A2 interrupt control register (TA2IC)
005716
Timer A3 interrupt control register (TA3IC)
005816
Timer A4 interrupt control register (TA4IC)
005916
Timer B0 interrupt control register (TB0IC)
005A16
Timer B1 interrupt control register (TB1IC)
005B16
Timer B2 interrupt control register (TB2IC)
005C16
INT0 interrupt control register (INT0IC)
005D16
INT1 interrupt control register (INT1IC)
005E16
INT2 interrupt control register (INT2IC)
005F16 006016 006116 006216 006316 006416 006516
032A16 032B16 032C16 032D16 032E16 032F16 033016 033116 033216 033316 033416 033516 033616 033716 033816 033916 033A16 033B16 033C16 033D16 033E16 033F16
Note 1: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.
Figure 1.6.1. Location of peripheral unit control registers (1)
18
s
p
R
SFR
0340
16
Timer B3, 4, 5 count start flag (TBSR)
0341
16
0342
16
Timer A1-1 register (TA11)
0343
16
0344
16
Timer A2-1 register (TA21)
0345
16
0346
16
Timer A4-1 register (TA41)
0347
16
0348
16
Three-phase PWM control register 0(INVC0)
0349
16
Three-phase PWM control register 1(INVC1)
034A
16
Three-phase output buffer register 0(IDB0)
034B
16
Three-phase output buffer register 1(IDB1)
034C
16
Dead time timer(DTT)
Timer B2 interrupt occurrence frequency set counter(ICTB2)
034D
16
034E
16
034F
16
0350
16
Timer B3 register (TB3)
0351
16
0352
16
Timer B4 register (TB4)
0353
16
0354
16
Timer B5 register (TB5)
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
Timer B3 mode register (TB3MR)
035C
16
Timer B4 mode register (TB4MR)
035D
16
Timer B5 mode register (TB5MR)
035E
16
035F
16
Interrupt cause select register (IFSR)
transmit/receive register
SI/O3
0360
16
0361
16
SI/O3 control register (S3C)
0362 0363 0364 0365 0366 0367 0368 0369 036A 036B 036C 036D 036E 036F 0370 0371 0372 0373 0374 0375 0376 0377 0378 0379 037A 037B 037C 037D 037E 037F
16 16 16 16 16 16 16 16
16 16 16 16
16 16 16 16 16 16 16 16 16 16 16 16
16
16
16
16
16 16
bit rate generator
SI/O3 SI/O4
transmit/receive register
(S3BRG)
SI/O4 control register (S4C) SI/O4
bit rate generator
(S4BRG)
UART2 special mode register 3(U2SMR3) UART2 special mode register 2(U2SMR2)
UART2 special mode register (U2SMR)
UART2 transmit/receive mode register (U2MR) UART2 bit rate generator (U2BRG)
UART2 transmit buffer register (U2TB) UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive control register 1 (U2C1) UART2 receive buffer register (U2RB)
(S3TRR)
(S4TRR)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
M16C / 62A Grou
0380
16
Count start flag (TABSR)
0381
16
Clock prescaler reset flag (CPSRF)
0382
16
One-shot start flag (ONSF)
0383
16
Trigger select register (TRGSR)
0384
16
Up-down flag (UDF)
0385
16
0386
16
Timer A0 (TA0)
0387
16
0388
16
Timer A1 (TA1)
0389
16
038A
16
Timer A2 (TA2)
038B
16
038C
16
Timer A3 (TA3)
038D
16
038E
16
Timer A4 (TA4)
038F
16
0390
16
Timer B0 (TB0)
0391
16
0392
16
Timer B1 (TB1)
0393
16
0394
16
Timer B2 (TB2)
0395
16
0396
16
Timer A0 mode register (TA0MR)
0397
16
Timer A1 mode register (TA1MR)
0398
16
Timer A2 mode register (TA2MR)
0399
16
Timer A3 mode register (TA3MR)
039A
16
Timer A4 mode register (TA4MR)
039B
16
Timer B0 mode register (TB0MR)
039C
16
Timer B1 mode register (TB1MR)
039D
16
Timer B2 mode register (TB2MR)
039E
16
039F
16
03A0
16
UART0 transmit/receive mode register (U0MR)
03A1
16
UART0 bit rate generator (U0BRG)
03A2
16
UART0 transmit buffer register (U0TB)
03A3
16
03A4
16
UART0 transmit/receive control register 0 (U0C0)
03A5
16
UART0 transmit/receive control register 1 (U0C1)
03A6
16
UART0 receive buffer register (U0RB)
03A7
16
03A8
16
UART1 transmit/receive mode register (U1MR)
03A9
16
UART1 bit rate generator (U1BRG)
03AA
16
UART1 transmit buffer register (U1TB)
03AB
16
03AC
16
UART1 transmit/receive control register 0 (U1C0) UART1 transmit/receive control register 1 (U1C1)
03AD
16
03AE
16
UART1 receive buffer register (U1RB)
03AF
16
03B0
16
UART transmit/receive control register 2 (UCON)
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
Flash memory control register 1 (FMR1) (Note1)
03B6
16
03B7
16
Flash memory control register 0 (FMR0) (Note1)
03B8
16
DMA0 request cause select register (DM0SL)
03B9
16
03BA
16
DMA1 request cause select register (DM1SL)
03BB
16
03BC
16
CRC data register (CRCD)
03BD
16
CRC input register (CRCIN)
03BE
16
03BF
16
Mitsubishi microcomputer
Note 1: This register is only exist in flash memory version. Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for
read or write.
Figure 1.6.2. Location of peripheral unit control registers (2)
19
s
p
R
SFR
03C016
A-D register 0 (AD0)
03C116 03C216
A-D register 1 (AD1)
03C316 03C416
A-D register 2 (AD2)
03C516 03C616
A-D register 3 (AD3)
03C716 03C816
A-D register 4 (AD4)
03C916 03CA16
A-D register 5 (AD5)
03CB16 03CC16
A-D register 6 (AD6)
03CD16 03CE16
A-D register 7 (AD7)
03CF16 03D016 03D116 03D216 03D316 03D416
A-D control register 2 (ADCON2)
03D516 03D616
A-D control register 0 (ADCON0)
03D716
A-D control register 1 (ADCON1)
03D816
D-A register 0 (DA0)
03D916 03DA16
D-A register 1 (DA1)
03DB16 03DC16
D-A control register (DACON)
03DD16 03DE16 03DF16 03E016
Port P0 (P0)
03E116
Port P1 (P1)
03E216
Port P0 direction register (PD0)
03E316
Port P1 direction register (PD1)
03E416
Port P2 (P2)
03E516
Port P3 (P3)
03E616
Port P2 direction register (PD2)
03E716
Port P3 direction register (PD3)
03E816
Port P4 (P4)
03E916
Port P5 (P5)
03EA16
Port P4 direction register (PD4)
03EB16
Port P5 direction register (PD5)
03EC16
Port P6 (P6)
03ED16
Port P7 (P7)
03EE16
Port P6 direction register (PD6)
03EF16
Port P7 direction register (PD7)
03F016
Port P8 (P8)
03F116
Port P9 (P9)
03F216
Port P8 direction register (PD8)
03F316
Port P9 direction register (PD9)
03F416
Port P10 (P10)
03F516 03F616
Port P10 direction register (PD10)
03F716 03F816 03F916 03FA16 03FB16 03FC16
Pull-up control register 0 (PUR0)
03FD16
Pull-up control register 1 (PUR1)
03FE16
Pull-up control register 2 (PUR2) Port control register (PCR)
03FF16
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Note : Locations in the SFR area where nothing is allocated are reserved
areas. Do not access these areas for read or write.
Figure 1.6.3. Location of peripheral unit control registers (3)
20
Mitsubishi microcomputer
s
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M16C / 62A Grou
Software Reset

Software Reset

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM are preserved.

Processor Mode

(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro­processor mode. The functions of some pins, the memory map, and the access space differ according to the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be accessed. However, after the reset has been released and the operation of shifting from the micropro­cessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the single-chip mode. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the operation of shifting from the microprocessor mode has started (“H” applied to the CNVSS pin), the internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The internal ROM area cannot be accessed. In this mode, some of the pins function as the address bus, the data bus, and as control signals. The number of pins assigned to these functions depends on the bus and register settings. (See “Bus Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”. Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore, never change the processor mode bits when changing the contents of other bits. Also do not attempt to shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.7.1 shows the processor mode register 0 and 1. Figure 1.7.2 shows the memory maps applicable for each of the modes.
21
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Processor mode register 0 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol Address When reset PM0 0004
16
00
16
(Note 2)
Bit name FunctionBit symbol
PM00
PM01
PM02
PM03
PM04
PM05
PM06
PM07
Note 1: Set bit 1 of the protect register (address 000A Note 2: If the V Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-
Processor mode bit
R/W mode select bit
Software reset bit
Multiplexed bus space select bit
Port P40 to P43 function select bit (Note 3)
BCLK output disable bit
values to this register.
CC
voltage is applied to the CNVSS, the value of this register when
reset is 03
16
. (PM00 and PM01 both are set to “1”.)
bit width.The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
b1 b0
0 0: Single-chip mode 0 1: Memory expansion mode 1 0: Inhibited 1 1: Microprocessor mode
0 : RD,BHE,WR 1 : RD,WRH,WRL
The device is reset when this bit is set to “1”. The value of this bit is “0” when read.
b5 b4
0 0 : Multiplexed bus is not used 0 1 : Allocated to CS2 space 1 0 : Allocated to CS1 space 1 1 : Allocated to entire space (Note4)
0 : Address output 1 : Port function (Address is not output)
0 : BCLK is output 1 : BCLK is not output (Pin is left floating)
16
) to “1” when writing new
WR
Processor mode register 1 (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol Address When reset PM1 0005
0
Reserved bit
Nothing is assigned.
In an attempt to write to these bits, write “0”. The value, if read, turns out to be
indeterminate.
PM13
Reserved bit Reserved bit
Reserved bit
PM17 Wait bit
Note 1: Set bit 1 of the protect register (address 000A Note 2: Be sure to set this bit to 0 except products whose RAM size and ROM size exceed 15K bytes
Internal reserved area expansion bit (Note 2)
and 192K bytes respectively. In using M30624MAG/FGA, a product having a RAM of more than 15K bytes and a ROM of more than 192K bytes, set this bit to “1” at the beginning of user program. Specify D0000 to “0” at the time reset is revoked, for the reset vector table of user program.
16
Bit name FunctionBit symbol
00000XX0
2
WR
Must always be set to “0”
0: The same internal reserved area as that of M16C/60 and M16C/61 group 1: Expands the internal RAM area and internal ROM area to 23 K bytes and to 256K bytes respectively. (Note 2)
Must always be set to “0” Must always be set to “0”
Must always be set to “0”
0 : No wait state 1 : Wait state inserted
16
) to “1” when writing new values to this register.
16
or a subsequent address, which becomes an internal ROM area if PM13 is set
Figure 1.7.1. Processor mode register 0 and 1
22
s
p
R
Processor Mode
Mitsubishi microcomputer
M16C / 62A Grou
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Single-chip mode
16
00000
00400
XXXXX
04000
D0000
YYYYY
FFFFF
M30622M4A 00FFF M30620M8A 02BFF M30620MAA E8000 M30620MCA/FCA E0000 M30622M8A F0000 M30622MAA M30622MCA M30624MGA/FGA
16
16
16
16
16
16
Type No.
SFR area
Internal
RAM area
Inhibited
Internal
ROM area
Address XXXXX
02BFF 02BFF
013FF 017FF 017FF 053FF
Memory expansion mode
SFR area
Internal
RAM area
Internally
reserved area
External
Internally
reserved area
Internal
ROM area
16
Address YYYYY
16 16 16 16 16 16 16 16
F8000 F0000
E8000 E0000 C0000
area
16 16 16
16
Microprocessor mode
SFR area
Internal
RAM area
Internally
reserved area
External
area
16
External area : Accessing this area allows the user to
access a device connected externally to the microcomputer.
16
16 16 16
Note : These memory maps show an instance in which PM13 is set to 0; but in the case of M30624MGA/FGA, they show an instance in which PM13 is set to 1.
Figure 1.7.2. Memory maps in each processor mode (without memory area expansion, normal mode)
23
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Processor Mode
Figure 1.7.3 shows the memory maps and the chip selection areas effected by PM13 (the internal reserved area expansion bit) in each processor mode for the product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes.
Internal reserved area expansion bit=“0”
00000
00400
04000 08000
28000
30000
CFFFF D0000
FFFFF
16
16
16
16
16
16
16
16
16
Memory expansion
mode
SFR area
(1K bytes)
Internal RAM area
(15K bytes)
External area
Internal ROM area
(192K bytes)
After reset
Microprocessor
mode
SFR area
(1K bytes)
Internal RAM area
(15K bytes)
External area
(16K bytes)
CS3
(128K bytes)
CS2
(32K bytes)
CS1
CS0
Memory expansion mode : 640K bytes
Microprocessor mode : 832K bytes
Figure 1.7.3. Memory location and chip select area
Internal reserved area expansion bit=“1”
Memory expansion
00000
16
SFR area
00400
05400 06000
08000
28000
30000
BFFFF
C0000
FFFFF
After reset, and set the
(1K bytes)
16
Internal RAM area
(20K bytes)
16
Internal reserved area
16 16
16
16
External area
16 16
Internal ROM area
(256K bytes)
16
mode
I
nternal reserved area expansion bit to “1”
Microprocessor
mode
SFR area
(1K bytes)
Internal RAM area
(20K bytes)
Internal reserved area
External area
(8K bytes)
CS3
(128K bytes)
CS2
(32K bytes)
CS1
CS0
Memory expansion mode : 576K bytes Microprocessor mode : 832K bytes
Note: The reset vector lies in an area between D000016 and FFFFB16.
in each processor mode
24
Mitsubishi microcomputer
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M16C / 62A Grou

Bus Settings

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Bus Settings
The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 000416) are used to change the bus settings. Table 1.8.1 shows the factors used to change the bus settings.
Table 1.8.1. Factors for switching bus settings
Bus setting Switching factor Switching external address bus width Bit 6 of processor mode register 0 Switching external data bus width BYTE pin Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0 is set to “1”, the external address bus width is set to 16 bits, and P2 and P3 become part of the address bus. P40 to P43 can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set to “0”, the external address bus width is set to 20 bits, and P2, P3, and P40 to P43 become part of the address bus.
(2) Selecting external data bus width
The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be set.) When the BYTE pin is “L”, the bus width is set to 16 bits; when “H”, it is set to 8 bits. (The internal bus width is permanently set to 16 bits.) While operating, fix the BYTE pin either to “H” or to “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this mode, the data and address are input and output separately. The data bus can be set using the BYTE pin to be 8 or 16 bits. When the BYTE pin is “H”, the data bus is set to 8 bits and P0 functions as the data bus and P1 as a programmable I/O port. When the BYTE pin is “L”, the data bus is set to 16 bits and P0 and P1 are both used for the data bus. When the separate bus is used for access, a software wait can be selected.
• Multiplex bus
In this mode, data and address I/O are time multiplexed. With an 8-bit data bus selected (BYTE pin = “H”), the 8 bits from D0 to D7 are multiplexed with A0 to A7. With a 16-bit data bus selected (BYTE pin = “L”), the 8 bits from D0 to D7 are multiplexed with A1 to A8. D8 to D15 are not multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the microcomputer’s even addresses (every 2nd address). To access these external de­vices, access the even addresses as bytes. The ALE signal latches the address. It is output from P56. Before using the multiplex bus for access, be sure to insert a software wait. If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width. The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
25
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Settings
Table 1.8.2. Pin functions for each processor mode
Processor mode
Multiplexed bus space select bit
Data bus width BYTE pin level
P00 to P0
P1
0
to P1
7
7
Single-chip
mode
I/O port Data bus Data bus Data bus Data bus I/O port
I/O port I/O port Data bus I/O port Data bus I/O port
Memory expansion mode/microprocessor modes
“01”, “10” “00”
Either CS1 or CS2 is for multiplexed bus and others are for separate bus
8 bits
“H”
16 bits
“L”
(separate bus)
8 bits
“H”
16 bits
“L”
Memory
expansion mode
“11” (Note 1)
multiplexed
bus for the
entire
space
8 bit
“H”
0
P2
P2
1
to P2
7
P3
0
P31 to P3
P4
Port P40 to P4
0
to P4
7
3
3
function select bit = 1
P4
0
to P4
Port P40 to P4
3
3
function select bit = 0
P4
4
to P4
7
P5
0
to P5
3
P5
4
P5
5
P5
6
I/O port
I/O port
I/O port
Address bus
/data bus
Address bus Address bus /data bus
Address bus
(Note 2)
(Note 2)
Address bus Address bus Address bus Address bus
/data bus
(Note 2)
Address bus Address bus Address bus A8/D
/data bus
(Note 2)
/data bus
Address bus Address bus Address bus
/data bus
7
I/O port Address bus Address bus Address bus Address bus I/O port
I/O port I/O port I/O port /O port I/O port I/O port
I/O port Address bus Address bus Address bus Address bus I/O port
I/O port
CS (chip select) or programmable I/O port
(For details, refer to “Bus control”)
I/O port
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”)
I/O port HLDA HLDA HLDA HLDA HLDA
I/O port HOLD HOLD HOLD HOLD HOLD
I/O port ALE ALE ALE ALE ALE
P5
7
I/O port RDY RDY RDY RDY RDY
Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.
The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be chosen in microprocessor mode. The higher-order address becomes a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used in each chip select.
Note 2: Address bus when in separate bus mode.
26
Mitsubishi microcomputer
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M16C / 62A Grou

Bus Control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
Bus Control
The following explains the signals required for accessing external devices and software waits. The signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. The software waits are valid in all processor modes.
(1) Address bus/data bus
The address bus consists of the 20 pins A0 to A19 for accessing the 1M bytes of address space. The data bus consists of the pins for data I/O. When the BYTE pin is “H”, the 8 ports D0 to D7 function as the data bus. When BYTE is “L”, the 16 ports D0 to D15 function as the data bus. When a change is made from single-chip mode to memory expansion mode, the value of the address bus is undefined until external memory is accessed.
(2) Chip select signal
The chip select signal is output using the same pins as P44 to P47. Bits 0 to 3 of the chip select control register (address 000816) set each pin to function as a port or to output the chip select signal. The chip select control register is valid in memory expansion mode and microprocessor mode. In single-chip mode, P44 to P47 function as programmable I/O ports regardless of the value in the chip select control register. In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-
_______ _______
celled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register. The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1 and 1.9.2 show the external memory areas specified using the chip select signal.
_______
Table 1.9.1. External areas specified by the chip select signals (A product having an internal RAM equal to or less than 15K bytes and a ROM equal to or less than 192K bytes)(Note)
Processor mode
Chip select signal
CS0 CS1 CS2 CS3
3000016 to
Memory expansion mode
Microprocessor mode
CFFFF
16
(640K bytes)
16 to
30000
FFFFF16
2800016 to
2FFFF
16
(32K bytes)
08000
16 to
27FFF
16
(128K bytes)
16 to
04000
07FFF
16
(16K bytes)
(832K bytes)
Note :Be sure to set bit 3 (PM13) of processor mode register 1 to “0”.
27
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
Table 1.9.2. External areas specified by the chip select signals (A product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes)
Processor mode
Memory expansion mode
Microprocessor mode
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
Chip select signal
CS0 CS1 CS2
When PM13=0
3000016 to CFFFF
(640K bytes)
When PM13=1 3000016 to BFFFF
(576K bytes)
03000
16
to FFFFF
(816K bytes)
Symbol Address When reset CSR 0008
Bit symbol
CS0 CS1 CS2 CS3
CS0W CS1W CS2W CS3W
CS0 output enable bit CS1 output enable bit CS2 output enable bit CS3 output enable bit
CS0 wait bit CS1 wait bit CS2 wait bit CS3 wait bit
16
16
16
Bit name
2800016 to
2FFFF
16
(32K bytes)
16
0 : Chip select output disabled 1 : Chip select output enabled
0 : Wait state inserted 1 : No wait state
01
16
(Normal port pin)
16
08000
27FFF
to
16
(128K bytes)
Function
CS3
When PM13=0
04000
16
to
07FFF
16
(16K bytes)
When PM13=1
16
06000
07FFF
to
16
(8K bytes)
W
R
Figure 1.9.1. Chip select control register
28
Mitsubishi microcomputer
s
p
R
M16C / 62A Grou
Bus Control
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTE
(3) Read/write signals
With a 16-bit data bus (BYTE pin =“L”), bit 2 of the processor mode register 0 (address 000416) select the combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE pin = “H”), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address 000416) to “0”.) Tables 1.9.3 and 1.9.4 show the operation of these signals. After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected. When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the processor mode register 0 (address 000416) has been set (Note).
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect
register (address 000A16) to “1”.
_____ ________ ______ _____ ________ _________
_____ ______ _______
_____ ______ ________
_____ _________ _________
Table 1.9.3. Operation of RD, WRL, and WRH signals
_____ ________ _________
Data bus width
16-bit
(BYTE = “L”)
L H H H
_____ ______ ________
H
L
H
L
WRHWRLRD
H H
L L
Read data Write 1 byte of data to even address Write 1 byte of data to odd address Write data to both even and odd addresses
Status of external data bus
Table 1.9.4. Operation of RD, WR, and BHE signals
Data bus width A0
16-bit
(BYTE = “L”)
RD
BHEWR
HLL
LHL
HLH
LHH
H H
HLLL
LHLL
8-bit
(BYTE = “H”)
HL H / L
LH H / L
Not used Not used
Write 1 byte of data to odd address
Read 1 byte of data from odd address L L
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data to both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data Read 1 byte of data
Status of external data bus
(4) ALE signal
The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the ALE signal falls.
When BYTE pin = “H”
ALE
D
0/A0
to D7/A
A8 to A
7
19
Address Data (Note 1)
Address (Note 2)
Note 1: Floating when reading. Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.
Figure 1.9.2. ALE signal and address/data bus
When BYTE pin = “L”
ALE
0/A1
to D7/A
D
A9 to A
0
A
8
19
Address Data (Note 1)
Address
Address
29
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Bus Control
________
(5) The RDY signal
________
RDY is a signal that facilitates access to an external device that requires long access time. As shown in Figure 1.9.3, if an “L” is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If
________
an “H” is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5 shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.3 shows an example in which the RD signal is prolonged by the RDY signal.
________
____ ________
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the chip select control register (address 000816) are set to “0”. The RDY signal is invalid when setting “1” to all bits 4 to 7 of the chip select control register (address 000816), but the RDY pin should be treated as properly as in non-using.
Table 1.9.5. Microcomputer status in ready state (Note)
Item Status
Oscillation On
___ _____
R/W signal, address bus, data bus, CS
__________
ALE signal, HLDA, programmable I/O ports Internal peripheral circuits On
________
Note: The RDY signal cannot be received immediately prior to a software wait.
________
________
________
________
Maintain status when RDY signal received
In an instance of separate bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
Accept timing of RDY signal
In an instance of multiplexed bus
BCLK
RD
CS
i
(i=0 to 3)
RDY
tsu(RDY - BCLK)
tsu(RDY - BCLK)
: Wait using RDY signal : Wait using software
Figure 1.9.3. Example of RD signal extended by RDY signal
30
Accept timing of RDY signal
_____ ________
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