MITSUBISHI M30201 User Manual

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Mitsubishi microcomputers

M30201 Group

Description

The M30201 group of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core. M30201 group is packaged in a 52-pin plastic molded SDIP, or 56-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. The M30201 group includes a wide range of products with different internal memory types and sizes and various package types.

Features

• Basic machine instructions ..................Compatible with the M16C/60 series

• Memory capacity..................................ROM/RAM (See figure 1.4. ROM expansion.)

• Shortest instruction execution time......

• Supply voltage .....................................4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version

• Interrupts..............................................9 internal and 3 external interrupt sources, 4 software

• Multifunction 16-bit timer......................Timer A x 1, timer B x 2, timer X x 3

• Clock output

• Serial I/O..............................................1 channel

• A-D converter.......................................10 bits X 8 channels (Expandable up to 13 channels)

• Watchdog timer....................................1 line

• Programmable I/O ...............................43 lines

• LED drive ports ....................................8 ports

• Clock generating circuit .......................2 built-in clock generation circuits

100ns (f(XIN)=10MHz)

2.7 to 5.5V (f(XIN)=7MHz with software one-wait):mask ROM version

4.0 to 5.5V (f(XIN)=10MHz) :flash memory version

(including key input interrupt)

for UART or clock synchronous, 1 for UART

(built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Home appliances, Audio, office equipment, Automobiles

------Table of Contents------

Central Processing Unit (CPU) .....................12

Reset.............................................................15

Clock Generating Circuit ............................... 19

Protection......................................................26

Interrupts.......................................................27

Watchdog Timer............................................35

Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free of error. Specifications in this manual may be changed for functional or performance improvements. Please make sure your manual is the latest edition.

Timer.............................................................37

Serial I/O ....................................................... 64

A-D Converter ............................................... 78

Programmable I/O Ports ...............................88

Electric Characteristics ................................. 95

Flash Memory version.................................126

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Description

Pin Configuration

Figures 1.1 to 1.2 show the pin configurations (top view).

PIN CONFIGURATION (top view)

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

P60/AN

P54/CK

OUT

P53/CLKS/AN

P52/CLK0/AN

P51/RXD0/AN

P50/TXD0/AN

P71/TB1IN/X

P70/TB0IN/X

RESET

P45/TX2

P44/INT1/TX1 P43/INT0/TX0

P42/RXD

P41/TA0

P40/TA0IN/TXD

/AN

CNV

COUT

INOUT INOUT

INOUT

REF

CIN

OUT

P3 P3

53 52

2 3

4 5

6 7

M30201F6TSP

M30201F6SP

M30201MXT-XXXSP

10 11

12 13

14 15

17 18

19 20

21 22

23 24

5 4

52 51

50 49

48 47

M30201MX-XXXSP

45 44

43 42

41 40

39 38

37 36

35 34

33 32

31 30

29 28

P61/AN P62/AN

P63/AN P64/AN

P65/AN P66/AN

P67/AN P00/KI

P01/KI P02/KI

P03/KI P04/KI P05/KI

P06/KI P07/KI

P3 P3

1 2

3 4

5 6

0 1

2 3

4 5

6 7

P10(LED0) P1

(LED1)

(LED2)

(LED3)

P1 P1

(LED4)

(LED5)

P1 P1

(LED6)

(LED7)

0 1

Package: 52P4B

Figure 1.1. Pin configuration for the M30201 group (shrink DIP product) (top view)

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Description

PIN CONFIGURATION (top view)

/AN

/CLK

/CLKS/AN

/AN

OUT

/CK

N.C.

REF

/AN

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

/AN

P51/RXD0/AN

P50/TXD0/AN

P71/TB1IN/X

P70/TB0IN/X

RESET

P45/TX2

P44/INT1/TX1 P43/INT0/TX0

CNV

COUT

N.C.

INOUT

INOUT INOUT

OUT

51 50

CIN

1 2

3 4

5 6

7 8

M30201MX-XXXFP M30201MXT-XXXFP M30201F6FP M30201F6TFP

11 12

13 14

OUT

/TA0

N.C.

)

(LED

)

(LED

)

(LED

42 41

40 39

38 37

36 35

34 33

32 31

30 29

)

(LED

P67/AN

N.C.

P00/KI

P01/KI

P02/KI

P03/KI

P04/KI

P05/KI

P06/KI

P07/KI

P10(LED0)

P11(LED1)

(LED2)

P1 P1

(LED3)

Package: 56P6S-A

Figure 1.2. Pin configuration for the M30201 group (QFP product) (top view)

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Description

Block Diagram

Figure 1.3 is a block diagram of the M30201 group.

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

I/O ports

Internal peripheral functions

Timer TA0 (16 bits) Timer TB0 (16 bits) Timer TB1 (16 bits) Timer TX0 (16 bits) Timer TX1 (16 bits) Timer TX2 (16 bits)

Watchdog timer

Port P08Port P1

Timer

(15 bits)

Port P36Port P46Port P55Port P6

A-D converter

(10 bits X 8 channels

Expandable up to 13 channels)

UART/clock synchronous SI/O

(8 bits X 1 channel)

UART

(8 bits X 1 channel)

M16C/60 series16-bit CPU core

Registers

R0LR0H

R1H R1L

R0LR0H

R1H R1L

SB FLG

Program counter

Vector table

INTB

Stack pointer

ISP

USP

System clock generator

IN-XOUT

XCIN-XCOUT

Memory

AAAAA AAAAA

ROM

(Note 1)

RAM

(Note 2)

AAAAA

Multiplier

Port P7

Note 1: ROM size depends on MCU type. Note 2: RAM size depends on MCU type.

Figure 1.3. Block diagram for the M30201 group

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Description

Performance Outline

Table 1.1 is performance outline of M30201 group.

Table 1.1. Performance outline of M30201 group

Item Performance Number of basic instructions 91 instructions Shortest instruction execution time 100ns (f(XIN)=10MHz Memory ROM (See figure 4. ROM expansion.) capacity RAM (See figure 4. ROM expansion.) I/O port P0 to P7 43 lines Multifunction TA0 16 bits x 1 timer TB0, TB1 16 bits x 2

TX0, TX1, TX2 16 bits x 3 Serial I/O UART0 (UART or clock synchronous) x 1

UART1 UART x 1 A-D converter 10 bits x 8 channels (Expandable up to 13 channels) Watchdog timer 15 bits x 1 (with prescaler) Interrupt 9 internal and 3 external sources, 4 software sources Clock generating circuit 2 built-in clock generation circuits

(built-in feedback resistor, and external ceramic or quartz oscillator)

Supply voltage 4.0 to 5.5V (f(XIN)=10MHz) :mask ROM version

2.7 to 5.5V (f(XIN)=7MHz with software one-wait) :mask ROM version

4.0 to 5.5V (f(XIN)=10MHz) :flash memory version

Power consumption 18mW (f(XIN)=7MHz with software one-wait, Vcc=3V)

:mask ROM version

95mW (f(XIN)=10MHz no wait, Vcc=5V) :flash memory version I/O I/O withstand voltage 5V characteristics Output current 5mA (15mA:LED drive port) Device configuration CMOS silicon gate Package 52-pin plastic mold SDIP

56-pin plastic mold QFP

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Mitsubishi plans to release the following products in the M30201 group: (1) Support for mask ROM version and flash memory version (2) ROM capacity (3) Package

52P4B : Plastic molded SDIP (mask ROM version and flash memory version) 56P6S-A : Plastic molded QFP (mask ROM version and flash memory version)

RAM Size

(Byte)

M30201M4-XXXSP/FP

M30201M4T-XXXSP/FP

Under development

Mitsubishi microcomputers

M30201 Group

July 1998

M30201F6SP/FP M30201F6TSP/FP

Under development

512

M30201M2-XXXSP/FP M30201M2T-XXXSP/FP

Figure 1.4. ROM expansion

Type No. M 3 0 2 0 1 M 4 T – X X X S P

Under planning

16K

32K

Package type: SP : Package 52P4B FP : Package 56P6S-A

ROM No. Omitted for flash memory version

Shows difference of characteristics and usage etc: Nothing : Common T : Automobiles

ROM capacity: 2 : 16K bytes 4 : 32K bytes 6 : 48K bytes

Memory type: M : Mask ROM version F : Flash memory version

Shows pin count, etc (The value itself has no specific meaning)

48K

ROM Size

(Byte)

Figure 1.5. Type No., memory size, and package

M16C/20 Group M16C Family

Under

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Pin Description

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin name

VCC, V

CNV

RESET X

OUT

REF

P00 to P0

Signal name

Power supply input

CNV

Reset input Clock input

Clock output

Analog power supply input

Reference voltage input

I/O port P0

I/O type

Input Input

Input Output

Input

Input/output

Function

Supply 2.7 to 5.5 V to the V

Connect it to the V

pin.

pin. Supply 0 V to the VSS pin.

A “L” on this input resets the microcomputer.

These pins are provided for the main clock generating circuit. Connect a ceramic resonator or crystal between the X X

OUT

pins. To use an externally derived clock, input it to the

pin and leave the X

OUT

pin open.

and the

This pin is a power supply input for the A-D converter. Connect it to V

This pin is a reference voltage input for the A-D converter.

This is an 8-bit CMOS I/O port. It has an input/output port direction register that allows the user to set each pin for input or output individually. When set for input, the user can specify in units of four bits via software whether or not they are tied to a

pull-up resistor. P10 to P1 P30 to P3

P40 to P4

P50 to P5

P60 to P6

P70 to P71

I/O port P1

I/O port P3

I/O port P4

I/O port P5 Input/output

I/O port P6

I/O port P7

Input/output Input/output

Input/output

This is an 8-bit I/O port equivalent to P0.

This is a 6-bit I/O port equivalent to P0.

This is a 6-bit I/O port equivalent to P0. The P4

with timer A0 input and serial I/O output TxD1. The P4

shared with timer A0 output. The P4

I/O input RxD1. The P4

pin is shared with external interrupt

INT0 and timer X0 input/output TX0

pin is shared with serial

INOUT

pin is shared

pin is

. The P44 pin is shared with external interrupt INT1 and timer X1 input/output TX1

INOUT

. The P45 pin is shared with timer X2 input/output

TX2

INOUT

This is a 5-bit I/O port equivalent to P0. The P5 P5

pins are shared with serial I/O pins TxD0, RxD0, CLK0,

and CLKS. The P5

pin is shared with clock output CLK Also, these pins are shared with analog input pins AN through AN

, P51, P52, and

OUT

This is an 8-bit I/O port equivalent to P0. These pins are shared with analog input pins AN

through AN7.

This is a 2-bit I/O port equivalent to P0 . These pins are used for input/output to and from the oscillator circuit for the clock. Connect a crystal oscillator between the X

CIN

and the X

COUT

pins.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Memory

Operation of Functional Blocks

The M30201 accommodates certain units in a single chip. These units include ROM and RAM to store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations. Also included are peripheral units such as timers, serial I/O, A-D converter, and I/O ports. The following explains each unit.

Memory

Figure 1.6 is a memory map of the M30201. The address space extends the 1M bytes from address 0000016 to FFFFF16. From FFFFF16 down is ROM. For example, in the M30201M4-XXXFP, there is 32K bytes of internal ROM from F800016 to FFFFF16. The vector table for fixed interrupts such as the reset are mapped to FFFDC16 to FFFFF16. The starting address of the interrupt routine is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the internal register (INTB). See the section on interrupts for details. From 0040016 up is RAM. For example, in the M30201M4-XXXFP, there is 1K byte of internal RAM from 0040016 to 007FF16. In addition to storing data, the RAM also stores the stack used when calling subroutines and when interrupts are generated. The SFR area is mapped to 0000016 to 003FF16. This area accommodates the control registers for peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Any part of the SFR area that is not occupied is reserved and cannot be used for other purposes. The special page vector table is mapped to FFE0016 to FFFDB16. If the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps.

Type No.

M30201M4

M30201M2

M30201F6

Address

XXXXX

F8000

FC000

F4000

Address

YYYYY

007FF

005FF

00BFF

Figure 1.6. Memory map

00000

SFR area

For details, see

00400

Figures 1.7 to 1.8

FFE00

Internal RAM area

Special page

YYYYY

FFFDC

XXXXX

FFFFF

Internal ROM area

FFFFF

vector table

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer

DBC

Reset

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Memory

0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 001C 001D 001E 001F 0020 0021 0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 002C 002D 002E 002F 0030 0031 0032 0033 0034 0035 0036 0037 0038 0039 003A 003B 003C 003D 003E 003F

16 16 16 16

Processor mode register 0 (PM0)

16 16

Processor mode register 1(PM1)

System clock control register 0 (CM0)

System clock control register 1 (CM1)

Address match interrupt enable register (AIER)

Protect register (PRCR)

16 16

Watchdog timer start register (WDTS)

Watchdog timer control register (WDC)

16 16 16

Address match interrupt register 0 (RMAD0)

16 16 16

Address match interrupt register 1 (RMAD1)

16 16 16 16 16 16 16

16 16 16 16 16 16 16 16 16 16 16 16 16 16 16

16 16 16

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

0040

0041

0042

0043

0044

0045

0046

0047

0048

0049

004A

004B

004C

Key input interrupt control register (KUPIC)

004D

A-D conversion interrupt control register (ADIC)

004E

004F

0050

UART0 transmit interrupt control register (S0TIC)

0051

UART0 receive interrupt control register (S0RIC)

0052

UART1 transmit interrupt control register (S1TIC)

0053

UART1 receive interrupt control register (S1RIC)

0054

Timer A0 interrupt control register (TA0IC)

0055

Timer X0 interrupt control register (TX0IC)

0056

Timer X1 interrupt control register (TX1IC)

0057

Timer X2 interrupt control register (TX2IC)

0058

0059

Timer B0 interrupt control register (TB0IC)

005A

Timer B1 interrupt control register (TB1IC)

005B

005C

INT0 interrupt control register (INT0IC)

005D

INT1 interrupt control register (INT1IC)

005E

005F

Mitsubishi microcomputers

M30201 Group

Figure 1.7. Location of peripheral unit control registers (1)

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Memory

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

038016

Count start flag (TABSR)

038116

Clock prescaler reset flag (CPSRF)

038216

One-shot start flag (ONSF)

038316

Trigger select register (TRGSR)

038416

Up-down flag (UDF)

038516 038616

Timer A0 (TA0)

038716 038816

Timer X0 (TX0)

038916 038A16

Timer X1 (TX1)

038B16 038C16

Timer X2 (TX2)

038D16 038E16

Clock divided counter (CDC)

038F16 039016

Timer B0 (TB0)

039116 039216

Timer B1 (TB1)

039316 039416 039516 039616

Timer A0 mode register (TA0MR)

039716

Timer X0 mode register (TX0MR)

039816

Timer X1 mode register (TX1MR)

039916

Timer X2 mode register (TX2MR)

039A16 039B16

Timer B0 mode register (TB0MR)

039C16

Timer B1 mode register (TB1MR)

039D16 039E16 039F16

03A016

UART0 transmit/receive mode register (U0MR)

03A116

UART0 bit rate generator (U0BRG)

03A216

UART0 transmit buffer register (U0TB)

03A316

03A416

UART0 transmit/receive control register 0 (U0C0)

03A516

UART0 transmit/receive control register 1 (U0C1)

03A616

UART0 receive buffer register (U0RB)

03A716

03A816

UART1 transmit/receive mode register (U1MR)

03A916

UART1 bit rate generator (U1BRG)

03AA16

UART1 transmit buffer register (U1TB)

03AB16

03AC16

UART1 transmit/receive control register 0 (U1C0)

03AD16

UART1 transmit/receive control register 1 (U1C1)

03AE16

UART1 receive buffer register (U1RB)

03AF16

03B016

UART transmit/receive control register 2 (UCON)

03B116

03B216

03B316

03B416

Flash memory control register 0 (FCON0) (Note)

03B516

Flash memory control register 1 (FCON1) (Note)

03B616

Flash command register (FCMD) (Note)

03B716

03B816

03B916

03BA16

03BB16

03BC16

03BD16

03BE16

03BF16

Note: This re

ister is only exist in flash memory version.

03C016

A-D register 0 (AD0)

03C116 03C216

A-D register 1 (AD1)

03C316 03C416

A-D register 2 (AD2)

03C516 03C616

A-D register 3 (AD3)

03C716 03C816

A-D register 4 (AD4)

03C916 03CA16

A-D register 5 (AD5)

03CB16 03CC16

A-D register 6 (AD6)

03CD16 03CE16

A-D register 7 (AD7)

03CF16 03D016 03D116 03D216 03D316 03D416

A-D control register 2 (ADCON2)

03D516 03D616

A-D control register 0 (ADCON0)

03D716

A-D control register 1 (ADCON1)

03D816 03D916 03DA16 03DB16 03DC16 03DD16 03DE16 03DF16 03E016

Port P0 (P0)

03E116

Port P1 (P1)

03E216

Port P0 direction register (PD0)

03E316

Port P1 direction register (PD1)

03E416

Port P2 (P2) (Reserved)

03E516

Port P3 (P3)

03E616

Port P2 direction register (PD2) (Reserved)

03E716

Port P3 direction register (PD3)

03E816

Port P4 (P4)

03E916

Port P5 (P5)

03EA16

Port P4 direction register (PD4)

03EB16

Port P5 direction register (PD5)

03EC16

Port P6 (P6)

03ED16

Port P7 (P7)

03EE16

Port P6 direction register (PD6)

03EF16

Port P7 direction register (PD7)

03F016 03F116 03F216 03F316 03F416 03F516 03F616 03F716 03F816 03F916 03FA16 03FB16 03FC16

Pull-up control register 0 (PUR0)

03FD16

Pull-up control register 1 (PUR1)

03FE16

Port P1 drive control register (DRR)

03FF16

Figure 1.8. Location of peripheral unit control registers (2)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

CPU

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Figure 1.9. Seven of these registers (R0, R1, R2, R3, A0, A1, and FB) come in two sets; therefore, these have two register banks.

(Note)

b15

b8 b7 b0

b19

Program counter

Data

registers

INTB

b19

USP

ISP

b15

Interrupt table register

User stack pointer

Interrupt stack pointer

Address

registers

Frame base registers

FLG

b15

Static base register

Flag register

IPL

CDZSBOIU

Note: These registers consist of two register banks.

Figure 1.9. Central processing unit register

(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H, R1H), and low-order bits as (R0L, R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can use as 32-bit data registers (R2R0, R3R1).

(2) Address registers (A0 and A1)

Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data registers. These registers can also be used for address register indirect addressing and address register relative addressing. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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CPU

(3) Frame base register (FB)

Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.

(4) Program counter (PC)

Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.

(5) Interrupt table register (INTB)

Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector table.

(6) Stack pointer (USP/ISP)

Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each configured with 16 bits. Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag). This flag is located at the position of bit 7 in the flag register (FLG).

(7) Static base register (SB)

Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.

(8) Flag register (FLG)

Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.10 shows the flag register (FLG). The following explains the function of each flag:

• Bit 0: Carry flag (C flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

• Bit 1: Debug flag (D flag)

This flag enables a single-step interrupt. When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is cleared to “0” when the interrupt is acknowledged.

• Bit 2: Zero flag (Z flag)

This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.

• Bit 3: Sign flag (S flag)

This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared to “0”.

• Bit 4: Register bank select flag (B flag)

This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.

• Bit 5: Overflow flag (O flag)

This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.

• Bit 6: Interrupt enable flag (I flag)

This flag enables a maskable interrupt. An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is cleared to “0” when the interrupt is acknowledged.

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CPU

• Bit 7: Stack pointer select flag (U flag)

Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected when this flag is “1”. This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of software interrupt Nos. 0 to 31 is executed.

• Bits 8 to 11: Reserved area

• Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt is enabled.

• Bit 15: Reserved area

The C, Z, S, and O flags are changed when instructions are executed. See the software manual for details.

(Note)

b15

b8 b7 b0

b19

Program cou

Data

registers

INTB

b19

USP

ISP

b15

Interrupt tabl register

User stack p

Interrupt stac pointer

Address

registers

b15

Static base register

Frame base registers

b15

FLG

Flag register

Figure 1.10. Flag register (FLG)

IPL

CDZSBOIU

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Reset

There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset. (See “Software Reset” for details of software resets.) This section explains on hardware resets. When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H” level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. Figure 1.11 shows the example reset circuit. Figure 1.12 shows the reset sequence.

RESET

Example when V

Figure 1.11. Example reset circuit

More than 20 cycles are needed

RESET

BCLK

(Internal clock)

BCLK 24cycles

= 5V

RESET

4.0V

0.8V

Content of reset vector

Address

(Internal address signal)

Figure 1.12. Reset sequence

FFFFC

FFFFE

Under

development

Reset

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

(25)

(26)

(27)

(28)

(29)

(30)

(31)

(32)

Processor mode register 0

Processor mode register 1 System clock control register 0

System clock control register 1 Address match interrupt

enable register Protect register

Watchdog timer control register Address match interrupt

Address match interrupt register 1

Key input interrupt control register A-D conversion interrupt

control register

UART0 transmit interrupt control register

UART0 receive interrupt control register

UART1 transmit interrupt control register

UART1 receive interrupt control register

Timer A0 interrupt control register

Timer X0 interrupt control register

Timer X1 interrupt control register

Timer X2 interrupt control register

Timer B0 interrupt control register

Timer B1 interrupt control register

INT0 interrupt control register

INT1 interrupt control register

Count start flag

One-shot start flag

Trigger select flag

Up-down flag

Timer A0 mode register

Timer X0 mode register

Timer X1 mode register

Timer X2 mode register

(0004

(0005

(0006

(0007

(0009

(000A

(000F

(0010

(0011

(0012

(0014

(0015

(0016

(004D

(004E

(0051

(0052

(0053

(0054

(0055

(0056

(0057

(0058

(005A

(005B

(005D

(005E

(0380

(0381

(0382

(0383

(0384

(0396

(0397

(0398

(0399

16)···

01001000

16)···

000?????

16)···

16)···Clock prescaler reset flag

16)···

0016

00 000?

0000000 0

0016

00 0016

0016

0000

000 00001

000

0000

000?

0000

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B0 mode register

(33)

Timer B1 mode register

(34)

UART0 transmit/receive mode

(35)

(36)

(37)

UART1 transmit/receive mode

(38)

UART1 transmit/receive control

(39)

(40)

UART transmit/receive control

(41)

Flash memory control register 0

(42)

(Note ) Flash memory control register 1

(43)

(Note)

Flash command register

(44)

A-D control register 2

(45)

A-D control register 0

(46)

A-D control register 1

(47)

Port P0 direction register

(48)

Port P1 direction register

(49)

Port P2 direction register

(50)

Port P3 direction register

(51)

Port P4 direction register

(52)

Port P5 direction register

(53)

Port P6 direction register

(54)

Port P7 direction register

(55)

Pull-up control register 0

(56)

Pull-up control register 1

(57)

Port P1 drive capacity control

(58)

(59)

Address registers (A0/A1)

(60)

Frame base register (FB)

(61)

Interrupt table register (INTB)

(62)

User stack pointer (USP)

(63)

Interrupt stack pointer (ISP)

(64)

Static base register (SB)

(65)

Flag register (FLG)

(66)

(039B

(039C

(03A0

(03A4

(03A5

(03A8

(03AC

(03AD

(03B0

(03B4

(03B5

(03B6

(03D4

(03D6

(03D7

(03E2

(03E3

(03E6

(03E7

(03EA

(03EB

(03EE

(03EF

(03FC

(03FD

(03FE

16)···

00 0000?

16)···

00 0000?

16)···

0016

00010000

00000100

0016

00010000

00000100

0000000

0100

0016

00000???

0016

0000000

000000

00000

0016

000016

0000016

000016 000016

000016

0000

000

x : Nothing is mapped to this bit ? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Note: This register is only exist in flash memory version.

Figure 1.13. Device's internal status after a reset is cleared

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Software Reset

Bus Control

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Software Reset

Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the microcomputer. A software reset has almost the same effect as a hardware reset. The contents of internal RAM are preserved. Figure 1.14 shows the processor mode register 0 and 1.

Processor mode register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset PM0 0004

0000

XXXX0000

Reserved bit

PM03

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Note: Set bit 1 of the protect register (address 000A

values to this register.

Processor mode register 1 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset PM1 0005

Reserved bit

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Bit name FunctionBit symbol

Software reset bit

Bit name FunctionBit symbol

Must always be set to “0”

The device is reset when this bit is set to “1”. The value of this bit is “0” when read.

) to “1” when writing new

00XXXXX0

Must always be set to “0”

PM17

Note: Set bit 1 of the protect register (address 000A

to this register.

Wait bit 0 : No wait state

Figure 1.14. Processor mode register 0 and 1.

1 : Wait state inserted

) to “1” when writing new values

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Software Wait

Software wait

The wait bit (bit 7) of the processor mode register 1 (address 000516)(note) allows you to insert software wait states for the internal ROM/RAM areas. If this bit is 0, the bus cycle is executed in one BCLK (internal clock) period; if the bit is 1, the bus cycle is executed in two BCLK periods. This bit is cleared to 0 after a reset. The SFR area is unaffected by this control bit; it is always accessed in two BCLK periods. Table 1.2 shows the relationship between software wait states and bus cycles.

Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect

Table 1.2. Software waits and bus cycles

Area Wait bit

SFR

Internal

ROM/RAM

Bus cycle

Invalid 2 BCLK cycles

0 1 BCLK cycle 1 2 BCLK cycles

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Clock Generating Circuit

The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the CPU and internal peripheral units.

Table 1.3. Main clock and sub-clock generating circuits

Main clock generating circuit Sub clock generating circuit

Use of clock • CPU’s operating clock source • CPU’s operating clock source

• Internal peripheral units’ • Timer A/B/X’s count clock

operating clock source source Usable oscillator Ceramic or crystal oscillator Crystal oscillator Pins to connect oscillator XIN, XOUT XCIN, XCOUT Oscillation stop/restart function Available Available Oscillator status immediately after reset

Oscillating Stopped Other Externally derived clock can be input

Example of oscillator circuit

Figure 1.15 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Figure 1.16 shows some examples of subclock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. Circuit constants in Figures 15 and 16 vary with each oscillator used. Use the values recommended by the manufacturer of your oscillator.

M30201

(Built-in feedback resistor)

OUT

(Note) R

OUT

Figure 1.15. Examples of main clock

M30201

(Built-in feedback resistor)

XCIN XCOUT

(Note) RCd

CCIN CCOUT

M30201

(Built-in feedback resistor)

Externally derived clock

Vcc Vss

M30201

(Built-in feedback resistor)

XCIN XCOUT

Externally derived clock

Vcc Vss

Open

OUT

Note: Insert a damping resistor if

required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X

OUT

and X instruction.

Note: Insert a damping resistor if

following the

CIN and XCOUT following the

Figure 1.16. Examples of sub-clock

Under

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Clock Generating Circuit

Clock Control

Figure 1.17 shows the block diagram of the clock generating circuit.

CIN

CM04

COUT

Sub clock

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

C32

1/32

RESET

Software reset

Interrupt request level judgment output

CM10 “1” Write signal

WAIT instruction

CM0i : Bit i at address 0006 CM1i : Bit i at address 0007 WDCi : Bit i at address 000F

CM06=1

CM07=1

CM07=0

BCLK

1/2

CM06=0 CM17,CM16=11

CM05

Main clock

OUT

CM02

Divider

16 16

1/2 1/2 1/2 1/2

CM06=0 CM17,CM16=10

CM06=0 CM17,CM16=01

CM06=0 CM17,CM16=00

Details of divider

Figure 1.17. Clock generating circuit

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Clock Generating Circuit

The following paragraphs describes the clocks generated by the clock generating circuit.

(1) Main clock

The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Stopping the clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation. After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716). Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

(2) Sub-clock

The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset. After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub-clock can be selected as BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure that the sub-clock oscillation has fully stabilized before switching. After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616). Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit changes to “1” when shifting to stop mode and at a reset.

(3) BCLK

The BCLK is the clock that drives the CPU, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The main clock division select bit 0(bit 6 at address 000616) changes to “1” when shifting from highspeed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

(4) Peripheral function clock (f1, f8, f32, fAD)

The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.

(5) fC32

This clock is derived by dividing the sub-clock by 32. It is used for the timer A, timer B and timer X counts.

(6) fC

This clock has the same frequency as the sub-clock. It is used for BCLK and for the watchdog timer.

Under

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Clock Generating Circuit

Figure 1.18 shows the system clock control registers 0 and 1.

System clock control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset CM0 0006

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bit name FunctionBit symbol

CM00

CM01

CM02

CM03

CM04 CM05

CM06

CM07

Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: Changes to “1” when shifting to stop mode and at a reset. Note 3: This bit is used to stop the main clock when placing the device in a low-power mode. If you want to operate with X

after exiting from the stop mode, set this bit to “0”. When operating with a self-excited oscillator, set the system clock

select bit (CM07) to “1” before setting this bit to “1”. Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. Note 5: If this bit is set to “1”, X

Note 6: Set port Xc select bit (CM04) to “1” and stabilize the sub-clock oscillating before setting to this bit from “0” to “1”.

Note 7: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting Note 8: f

OUT

(“H”) via the feedback resistor.

X Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to “0” and stabilize the main clock

oscillating before setting this bit from “1” to “0”. from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

C32

is not included.

OUT

Clock output function select bit

WAIT peripheral function clock stop bit

CIN-XCOUT

select bit (Note 2) Port XC select bit 0 : I/O port

Main clock (XIN-X stop bit (Note 3,4,5)

Main clock division select bit 0 (Note 7)

System clock select bit (Note 6)

turns “H”. The built-in feedback resistor remains being connected, so XIN turns pulled up to

drive capacity

OUT

b1 b0

0 0 : I/O port P5 0 1 : fC output

output

1 0 : f 1 1 : Clock divide counter output

0 : Do not stop peripheral function clock in wait mode 1 : Stop peripheral function clock in wait mode (Note 8)

0 : LOW 1 : HIGH

CIN-XCOUT

1 : X

)

0 : On 1 : Off

0 : CM16 and CM17 valid 1 : Division by 8 mode

0 : XIN, X 1 : X

CIN

OUT

, X

generation

COUT

System clock control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Note 1: Set bit 0 of the protect register (address 000A16) to “1” before writing to this register. Note 2: This bit changes to “1” when shifting from high-speed/medium-speed mode to stop mode and at a reset. When shifting

from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. Note 3: Can be selected when bit 6 of the system clock control register 0 (address 000616) is “0”. If “1”, division mode is fixed at 8. Note 4: If this bit is set to “1”, X

Symbol Address When reset CM1 0007

Bit name FunctionBit symbol

CM10

Reserved bit

CM15

CM16 CM17

OUT

turns “H”, and the built-in feedback resistor is cut off. X

All clock stop control bit (Note 4)

IN-XOUT

drive capacity

X select bit (Note 2)

Main clock division select bit 1 (Note 3)

0 : Clock on 1 : All clocks off (stop mode)

Always set to

Always set to 0 : LOW

1 : HIGH

b7 b6

0 0 : No division mode 0 1 : Division by 2 mode 1 0 : Division by 4 mode 1 1 : Division by 16 mode

“0”

CIN

and X

COUT

turn high-impedance state.

Figure 1.18. Clock control registers 0 and 1

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Clock Generating Circuit

Clock Output

The clock output function select bit allows you to choose the clock from f8, fc, or a divide-by-n clock that is output from the P54/CKOUT pin. The clock divide counter is an 8-bit counter whose count source is f32, and its divide ratio can be set in the range of 0016 to FF16. Figure 1.19 shows a block diagram of clock output.

Clock source selection

P54/CK

OUT

1/2

Clock divided couter (8)

Division n+1 n=0016 to FF

Reload register (8)

Low-order 8 bits

Data bus low-order bits

Figure 1.19. Block diagram of clock output

Address 038E

Example: When f(X n=07

16 :

n=26

16 :

n=4D

16 :

n=9B

16 :

)=10MHz approx. 16.5kHz approx. 4.0kHz approx. 2.0kHz approx. 1.0kHz

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Clock Generating Circuit

Wait Mode

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Stop Mode

Writing “1” to the all-clock stop control bit (bit 0 at address 000716) stops all oscillation and the microcomputer enters stop mode. In stop mode, the content of the internal RAM is retained provided that VCC remains above 2V. Because the oscillation of BCLK, f1 to f32, fc, fc32, and fAD stops in stop mode, peripheral functions such as the A-D converter and watchdog timer do not function. However, timer A, timer B and timer X operate provided that the event counter mode is set to an external pulse, and UART0 functions provided an external clock is selected. Table 1.4 shows the status of the ports in stop mode. Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. If returning by an interrupt, that interrupt routine is executed. When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 000616) is set to “1”. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Table 1.4. Port status during stop mode

Pin States

Port Retains status before stop mode CLKOUT When fC selected “H”

When f8, clock devided Retains status before stop mode counter output selected

Wait Mode

When a WAIT instruction is executed, BCLK stops and the microcomputer enters the wait mode. In this mode, oscillation continues but BCLK and watchdog timer stop. Writing “1” to the WAIT peripheral function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. Table 1.5 shows the status of the ports in wait mode. Wait mode is cancelled by a hardware reset or interrupt. If an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as BCLK, the clock that had been selected when the WAIT instruction was executed.

Table 1.5. Port status during wait mode

Pin States

Port CLKOUT When fC selected Does not stop

Retains status before wait mode

When f8, clock devided Does not stop when the WAIT counter output selected peripheral function clock stop bit is “0”.

When the WAIT peripheralfunction clock stop bit is “1”,the status immediately prior to entering wait mode is maintained.

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Clock Generating Circuit

Status Transition of BCLK

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Status Transition of BCLK

Power dissipation can be reduced and low-voltage operation achieved by changing the count source for BCLK. Table 1.6 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address

000616) changes to “1” when shifting from high-speed/medium-speed to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. The following shows the operational modes of BCLK.

(1) Division by 2 mode

The main clock is divided by 2 to obtain the BCLK.

(2) Division by 4 mode

The main clock is divided by 4 to obtain the BCLK.

(3) Division by 8 mode

The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably.

(4) Division by 16 mode

The main clock is divided by 16 to obtain the BCLK.

(5) No-division mode

The main clock is divided by 1 to obtain the BCLK.

(6) Low-speed mode

fC is used as BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the subclock starts. Therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled.

(7) Low power dissipation mode

fC is the BCLK and the main clock is stopped.

Note : Before the count source for BCLK can be changed from XIN to XCIN or vice versa, the clock to which

the count source is going to be switched must be oscillating stably. Allow a wait time in software for the oscillation to stabilize before switching over the clock.

Table 1.6. Operating modes dictated by settings of system clock control registers 0 and 1

CM17 CM16 CM07 CM06 CM05 CM04 Operating mode of BCLK

0 1 0 0 0 Invalid Division by 2 mode 1 0 0 0 0 Invalid Division by 4 mode

Invalid Invalid 0 1 0 Invalid Division by 8 mode

1 1 0 0 0 Invalid Division by 16 mode

0 0 0 0 0 Invalid No-division mode Invalid Invalid 1 Invalid 0 1 Low-speed mode Invalid Invalid 1 Invalid 1 1 Low power dissipation mode

Under

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Power Saving

Clock Generating Circuit

Power Saving

There are three power save modes.

(1) Normal operating mode

• High-speed mode

In this mode, one main clock cycle forms BCLK. The CPU operates on the BCLK. The peripheral functions operate on the clocks specified for each respective function.

• Medium-speed mode

In this mode, the main clock is divided into 2, 4, 8, or 16 to form BCLK. The CPU operates on the BCLK. The peripheral functions operated on the clocks specified for each respective function.

• Low-speed mode

In this mode, fc forms BCLK. The CPU operates on the fc clock. fc is the clock supplied by the subclock. The peripheral functions operate on the clocks specified for each respective function.

• Low power-dissipation mode

This mode is selected when the main clock is stopped from low-speed mode. The CPU operates on the fc clock. fc is the clock supplied by the subclock. Only the peripheral functions for which the subclock was selected as the count source continue to run.

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M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

(2) Wait mode

CPU operation is halted in this mode. The oscillator continues to run.

(3) Stop mode

All oscillators stop in this mode. The CPU and internal peripheral functions all stop. Of all 3 power saving modes, power savings are greatest in this mode.

Figure 1.20 shows the transition between each of the three modes, (1), (2), and (3).

Under

development

Clock Generating Circuit

Power Saving

Transition of stop mode, wait mode

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Reset

All oscillators stopped

Stop mode

All oscillators stopped

Interrupt

Stop mode

All oscillators stopped

Stop mode

Transition of normal mode

Main clock is oscillating

Medium-speed mode

CM06 = “1”

Main clock is oscillating

Sub clock is oscillating

High-speed mode

BCLK : f(XIN) CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0”

Medium-speed mode

(divided-by-4 mode)

BCLK : f(XIN)/4 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0”

CM04 = “0”

Medium-speed mode

Medium-speed mode (divided-by-16 mode)

CM10 = “1” Interrupt

CM10 = “1”

CM10 = “1” Interrupt

Medium-speed mode

(divided-by-8 mode)

High-speed/medium-

Low-speed/low power

Sub clock is stopped

(divided-by-8 mode)

BCLK : f(XIN)/8

CM07 = “0” CM06 = “1”

CM04 = “1” (Notes 1, 3)

(divided-by-2 mode)

BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1”

BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1”

CPU operation stopped

Wait mode

CPU operation stopped

Wait mode

CPU operation stopped

Wait mode

speed mode

dissipation mode

WAIT instruction

Interrupt

WAIT instruction

Interrupt

WAIT instruction

Interrupt

Normal mode

(Refer to the following for the transition of normal mode.)

CM07 = “0” (Note 1) CM06 = “1” CM04 = “0”

Main clock is oscillating

Medium-speed mode

(divided-by-8 mode)

BCLK : f(XIN)/8

CM07 = “0” CM06 = “1”

CM07 = “0” (Note 1, 3)

CM07 = “1” (Note 2)

Sub clock is oscillating

Low-speed mode

BCLK : f(X

CM07 = “1”

CM05 = “0” CM05 = “1”

CIN)

CM04 = “0” CM04 = “1”

High-speed mode

CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “0”

CM06 = “0” (Notes 1,3)

Medium-speed mode

(divided-by-4 mode)

CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “0”

Note 1: Switch clock after oscillation of main clock is sufficiently stable. Note 2: Switch clock after oscillation of sub clock is sufficiently stable. Note 3: Change CM06 after changing CM17 and CM16. Note 4: Transit in accordance with arrow.

Figure 1.20. Clock transition

Main clock is oscillating

Sub clock is stopped

BCLK : f(XIN)

BCLK : f(XIN)/4

Medium-speed mode

(divided-by-2 mode)

BCLK : f(XIN)/2 CM07 = “0” CM06 = “0” CM17 = “0” CM16 = “1”

Medium-speed mode

(divided-by-16 mode)

BCLK : f(XIN)/16 CM07 = “0” CM06 = “0” CM17 = “1” CM16 = “1”

CM07 = “1” (Note 2) CM05 = “1”

CM07 = “0” (Note 1) CM06 = “0” (Note 3) CM04 = “1”

Main clock is stopped

Sub clock is oscillating

Low power dissipation mode

BCLK : f(XCIN)

CM07 = “1”

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Clock Generating Circuit

Protection

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Protection

The protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. Figure 1.21 shows the protect register. The values in the processor mode register 0 (address 000416), processor mode register 1 (address 000516), system clock control register 0 (address 000616), system clock control register 1 (address 000716) and port P4 direction register (address 03EA16) can only be changed when the respective bit in the protect register is set to “1”. Therefore, important outputs can be allocated to port P4. If, after “1” (write-enabled) has been written to the port P4 direction register write-enable bit (bit 2 at address 000A16), a value is written to any address, the bit automatically reverts to “0” (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at 000A16) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A16) do not automatically return to “0” after a value has been written to an address. The program must therefore be written to return these bits to “0”.

Protect register

b7 b6 b5 b4 b3 b2 b1 b0

Figure 1.21. Protect register

Symbol Address When reset

PRCR 000A

XXXXX000

Bit nameBit symbol

) (Note

PRC0

PRC1

PRC2

Nothing is assigned. These bits can neither be set nor reset. When read, their contents are indeterminate.

Enables writing to system clock control registers 0 and 1 (addresses 0006

and 0007

Enables writing to processor mode registers 0 and 1 (addresses 0004 and 0005

Enables writing to port P4 direction register (address 03EA

)

0 : Write-inhibited 1 : Write-enabled

0 : Write-inhibited

1 : Write-enabled

0 : Write-inhibited 1 : Write-enabled

)

Function

Note: Writing a value to an address after “1” is written to this bit returns the bit

to “0” . Other bits do not automatically return to “0” and they must therefore be reset by the program.

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Overview of Interrupt

Type of Interrupts

Figure 1.22 lists the types of interrupts.

Software

   

Interrupt

    

Hardware



Special

   

Peripheral I/O

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

Undefined instruction (UND instruction)



Overflow (INTO instruction)



BRK instruction



INT instruction





Reset

________



DBC



Watchdog timer



Single step



Address matched

M30201 Group

Peripheral I/O interrupts are generated by the peripheral functions built into the microcomputer system.

Figure 1.22. Classification of interrupts

• Maskable interrupt : An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority can be changed by priority level.

• Non-maskable interrupt : An interrupt which cannot be enabled (disabled) by the interrupt enable flag (I flag) or whose interrupt priority cannot be changed by priority level.

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Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.

• Undefined instruction interrupt

An undefined instruction interrupt occurs when executing the UND instruction.

• Overflow interrupt

An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to “1”. The following are instructions whose O flag changes by arithmetic: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

• BRK interrupt

A BRK interrupt occurs when executing the BRK instruction.

• INT interrupt

An INT interrupt occurs when assigning one of software interrupt numbers 0 through 63 and executing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/O interrupt does. The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is involved. So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to “0” and select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt request. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.

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Interrupts

Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral I/O interrupts.

(1) Special interrupts

Special interrupts are non-maskable interrupts.

• Reset

Reset occurs if an “L” is input to the RESET pin.

• DBC interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances.

• Watchdog timer interrupt

Generated by the watchdog timer.

• Single-step interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to “1”, a single-step interrupt occurs after one instruction is executed.

• Address match interrupt

An address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to “1”. If an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs.

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(2) Peripheral I/O interrupts

A peripheral I/O interrupt is generated by one of built-in peripheral functions. The interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.

• Key-input interrupt

A key-input interrupt occurs if an “L” is input to the KI pin.

• A-D conversion interrupt

This is an interrupt that the A-D converter generates.

• UART0 and UART1 transmission interrupt

These are interrupts that the serial I/O transmission generates.

• UART0 and UART1 reception interrupt

These are interrupts that the serial I/O reception generates.

• Timer A0 interrupt

This is an interrupts that timer A0 generates.

• Timer B0 and timer B2 interrupt

These are interrupts that timer B generates.

• Timer X0 to timer X2 interrupt

These are interrupts that timer X generates.

________ ________

• INT0 and INT1 interrupt

______ ______

An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin.

___

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Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. Set the first address of the interrupt routine in each vector table. Figure 1.23 shows format for specifying interrupt vector addresses. Two types of interrupt vector tables are available — fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.

MSB

Vector address + 0 Vector address + 1 Vector address + 2 Vector address + 3

Figure 1.23. Format for specifying interrupt vector addresses

Low address Mid address

0 0 0 0 High address 0 0 0 0 0 0 0 0

LSB

• Fixed vector tables

The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from FFFDC16 to FFFFF16. One vector table comprises four bytes. Set the first address of interrupt routine in each vector table. Table 1.7 shows the interrupts assigned to the fixed vector tables and addresses of vector tables.

Table 1.7. Interrupt and fixed vector address

Interrupt source Vector table addresses Remarks

Address (L) to address (H) Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction Overflow FFFE016 to FFFE316 Interrupt on INTO instruction BRK instruction FFFE416 to FFFE716

Address match FFFE816 to FFFEB16 There is an address-matching interrupt enable bit Single step (Note) FFFEC16 to FFFEF16 Do not use Watchdog timer FFFF016 to FFFF316

________

DBC (Note) FFFF416 to FFFF716 Do not use

- FFFF816 to FFFFB16 Reset FFFFC16 to FFFFF16

Note: Interrupts used for debugging purposes only.

If the vector is filled with FF16, program execution starts from the address shown by the vector in the variable vector table

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• Variable vector tables

The addresses in the variable vector table can be modified, according to the user’s settings. Indicate the first address using the interrupt table register (INTB). The 256-byte area subsequent to the address the INTB indicates becomes the area for the variable vector tables. One vector table comprises four bytes. Set the first address of the interrupt routine in each vector table. Table 1.8 shows the interrupts assigned to the variable vector tables and addresses of vector tables.

Table 1.8. Interrupt causes (variable interrupt vector addresses)

Software interrupt number Interrupt source

Vector table address

Address (L) to address (H)

+44 to +47 (Note) Software interrupt number 11 +48 to +51 (Note)Software interrupt number 12 +52 to +55 (Note)Software interrupt number 13 +56 to +59 (Note)Software interrupt number 14

+68 to +71 (Note)Software interrupt number 17 +72 to +75 (Note)Software interrupt number 18 +76 to +79 (Note)Software interrupt number 19 +80 to +83 (Note)Software interrupt number 20 +84 to +87 (Note)Software interrupt number 21 +88 to +91 (Note)Software interrupt number 22 +92 to +95 (Note)Software interrupt number 23 +96 to +99 (Note)Software interrupt number 24

+100 to +103 (Note)Software interrupt number 25

Key input interrupt A-D

UART0 transmit UART0 receive UART1 transmit UART1 receive Timer A0 Timer X0 Timer X1 Timer X2

Remarks

Cannot be masked by I flag+0 to +3 (Note) BRK instructionSoftware interrupt number 0

+104 to +107 (Note)Software interrupt number 26 +108 to +111 (Note)Software interrupt number 27 +112 to +115 (Note)Software interrupt number 28 +116 to +119 (Note)Software interrupt number 29 +120 to +123 (Note)Software interrupt number 30 +124 to +127 (Note)Software interrupt number 31 +128 to +131 (Note)Software interrupt number 32

+252 to +255 (Note)Software interrupt number 63

Note : Address relative to address in interrupt table register (INTB).

Timer B0 Timer B1

INT0 INT1

Software interrupt

Cannot be masked by I flag

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Interrupt Control

Descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. What is described here does not apply to non-maskable interrupts. Enable or disable a maskable interrupt using the interrupt enable flag (I flag), interrupt priority level select bit, and processor interrupt priority level (IPL). Whether an interrupt request is present or absent is indicated by the interrupt request bit. The interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. Also, the interrupt enable flag (I flag) and the IPL are located in the flag register (FLG). Figure 1.24 shows the interrupt control registers.

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Interrupt control register

b7 b6 b5 b4 b3 b2 b1 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Symbol Address When reset KUPIC 004D ADIC 004E SiTIC(i=0, 1) 005116, 0053 SiRIC(i=0, 1) 005216, 0054 TAiIC(i=0) 0055 TXiIC(i=0 to 2) 005616 to 0058 TBiIC(i=0, 1) 005A16, 005B

16 16 16 16 16 16 16

XXXXX000 XXXXX000 XXXXX000 XXXXX000 XXXXX000 XXXXX000 XXXXX000

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2 2 2 2 2 2 2

b7 b6 b5 b4 b3 b2 b1 b0

Bit name FunctionBit symbol

ILVL0

ILVL1

ILVL2

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Interrupt priority level select bit

Interrupt request bit

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7

0 : Interrupt not requested 1 : Interrupt requested

Note: This bit can only be accessed for reset (= 0), but cannot be accessed

for set (= 1).

Symbol Address When reset

INTiIC(i=0, 1) 005D

, 005E16XX00X000

Bit name FunctionBit symbol

ILVL0

ILVL1

ILVL2

Interrupt priority level select bit

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled) 0 0 1 : Level 1 0 1 0 : Level 2 0 1 1 : Level 3 1 0 0 : Level 4 1 0 1 : Level 5 1 1 0 : Level 6 1 1 1 : Level 7

(Note)

POL

Reserved bit

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Note: This bit can only be accessed for reset (= 0), but cannot be accessed

for set (= 1).

Figure 1.24. Interrupt control register

Interrupt request bit

Polarity select bit

0: Interrupt not requested 1: Interrupt requested

0 : Selects falling edge 1 : Selects rising edge

Always set to “0”

(Note)

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Interrupt Enable Flag

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This flag is set to “0” after reset.

Interrupt Request Bit

The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").

Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt. Table 1.9 shows the settings of interrupt priority levels and Table 1.10 shows the interrupt levels enabled, according to the consist of the IPL.

The following are conditions under which an interrupt is accepted:

· interrupt enable flag (I flag) = 1

· interrupt request bit = 1

· interrupt priority level > IPL

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are independent, and they are not affected by one another.

Table 1.9. Settings of interrupt priority levels

Table 1.10. Interrupt levels enabled according

to the contents of the IPL

Interrupt priority

level select bit

b2 b1 b0

0 0 0 0 0 1 0 1 0

0 1 1

1 0 0

Interrupt priority

level

Level 0 (interrupt disabled)

Level 1 Level 2 Level 3 Level 4

Priority

order

Low

IPL

IPL2 IPL1 IPL

0 0 0 0 0 1 0 1 0

0 1 1

1 0 0

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled Interrupt levels 2 and above are enabled Interrupt levels 3 and above are enabled Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled 1 0 1 1 1 0 1 1 1

Level 5 Level 6 Level 7

High

1 0 1 1 1 0 1 1 1

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

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Changing the Interrupt Control Register

< Program examples >

The program examples are described as follow:

Example 1:

INT_SWITCH1:

FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. NOP ; Four NOP instructions are required when using HOLD function. NOP FSET I ; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. MOV.W MEM, R0 ; Dummy read. FSET I ; Enable interrupts.

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Example 3:

INT_SWITCH3:

PUSHC FLG ; Push Flag register onto stack FCLR I ; Disable interrupts. AND.B #00h, 0055h ; Clear TA0IC int. priority level and int. request bit. POPC FLG ; Enable interrupts.

The reason why two NOP instructions or dummy read are inserted before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the interrupt control register is rewritten due to effects of the instruction queue.

If changing the interrupt control register using an instruction other than the instructions listed hear, and if an interrupt occurs associated with this register during execution of the instruction, there can be instances in which the interrupt request bit is not set. To avoid this problem, use one of the instructions given below to change the register. Following instructions: AND, OR, BCLR or BSET

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Interrupt Sequence

An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here. If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. In the interrupt sequence, the processor carries out the following in sequence given:

(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading

address 0000016. After this, the corresponding interrupt request bit becomes "0".

(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt

sequence in the temporary register (Note) within the CPU.

(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U

flag) to “0” (the U flag, however, does not change if the INT instruction, in software interrupt

numbers 32 through 63, is executed). (4) Saves the content of the temporary register (Note) within the CPU in the stack area. (5) Saves the content of the program counter (PC) in the stack area. (6) Sets the interrupt priority level of the accepted instruction in the IPL.

After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine.

Note: This register cannot be utilized by the user.

Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). Figure 1.25 shows the interrupt response time.

Interrupt request acknowledgedInterrupt request generated

Time

Instruction Interrupt sequence

(a) (b)

Interrupt response time

Instruction in

interrupt routine

(a) Time from interrupt request is generated to when the instruction then under execution is completed. (b) Time in which the instruction sequence is executed.

Figure 1.25. Interrupt response time

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Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction (without wait). Time (b) is as shown in Table 1.11.

Table 1.11. Time required for executing the interrupt sequence

Stack pointer (SP) valueInterrupt vector address 16-bit bus, without wait 8-bit bus, without wait

Even Even

Odd (Note 2)

Even

Odd

Even

Odd

________

18 cycles (Note 1) 19 cycles (Note 1) 19 cycles (Note 1) 20 cycles (Note 1)

20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1) 20 cycles (Note 1)

Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match

interrupt or of a single-step interrupt.

Note 2: Locate an interrupt vector address in an even address, if possible.

123456789101112 13 14 15 16 17 18

BCLK

Address bus

Data bus

Address

0000

Interrupt

information

Indeterminate SP-2 SP-4 vec vec+2 PC

Indeterminate

SP-2

contents

SP-4

contents

vec

contents

vec+2

contents

The indeterminate segment is dependent on the queue buffer. If the queue buffer is ready to take an instruction, a read cycle occurs.

Figure 1.26. Time required for executing the interrupt sequence

Variation of IPL when Interrupt Request is Accepted

If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL. If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in Table 1.12 is set in the IPL.

Table 1.12. Relationship between interrupts without interrupt priority levels and IPL

Interrupt sources without priority levels Watchdog timer Reset Other

Value set in the IPL

7 0

Not changed

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Saving Registers

In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter (PC) are saved in the stack area. First, the processor saves the 4 high-order bits of the program counter, and 4 high-order bits and 8 loworder bits of the FLG register, 16 bits in total, in the stack area, then saves 16 low-order bits of the program counter. Figure 1.27 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. Save other necessary registers at the beginning of the interrupt routine using software. Using the PUSHM instruction alone can save all the registers except the stack pointer (SP).

Address

MSB LSB

m – 4

m – 3

m – 2

m – 1

m + 1

Stack area

Content of previous stack

Stack status before interrupt request is acknowledged

[SP] Stack pointer value before interrupt occurs

Address

MSB LSB

m – 4

m – 3

m – 2

m – 1

m + 1

Stack status after interrupt request is acknowledged

Stack area

Program counter (PC

Flag register (FLG

Flag register

(FLG

Content of previous stack

)

Program

counter (PC

Figure 1.27. State of stack before and after acceptance of interrupt request

[SP]

)

New stack pointer value

)

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The operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer (Note), at the time of acceptance of an interrupt request, is even or odd. If the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at a time. Figure 1.28 shows the operation of the saving registers. Note: Stack pointer indicated by U flag.

(1) Stack pointer (SP) contains even number

Address

[SP] – 5 (Odd)

[SP] – 4 (Even)

[SP] – 3(Odd)

[SP] – 2 (Even)

[SP] – 1(Odd)

[SP] (Even)

Stack area

Program counter (PC

Flag register (FLG

Flag register

(FLG

)

counter (PC

)

Program

)

Sequence in which order registers are saved

(2) Saved simultaneously,

(1) Saved simultaneously,

)

Finished saving registers in two operations.

(2) Stack pointer (SP) contains odd number

Address

[SP] – 5 (Even)

Stack area

Sequence in which order registers are saved

all 16 bits

[SP] – 4(Odd)

[SP] – 3 (Even)

[SP] – 2(Odd)

[SP] – 1 (Even)

[SP] (Odd)

Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

Program counter (PC

Program counter (PCM)

Flag register (FLG

)

Program

counter (PC

Flag register

(FLG

Figure 1.28. Operation of saving registers

)

(3) (4)

Saved simultaneously, all 8 bits

(1) (2)

Finished saving registers in four operations.

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Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter (PC), both of which have been saved in the stack area. Then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. Return the other registers saved by software within the interrupt routine using the POPM or similar instruction before executing the REIT instruction.

Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. Figure 1.29 shows the priorities of hardware interrupts. Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches invariably to the interrupt routine.

Interrupt Priority Level Judge Circuit

This circuit selects the interrupt with the highest priority level when two or more interrupts are generated simultaneously. Figure 1.30 shows the interrupt resolution circuit.

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________

Reset > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

Figure 1.29. Hardware interrupts priorities

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Priority level of each interrupt

INT1

Timer B0

Timer X2

Timer X0

INT0

Timer B1

Timer X1

UART1 reception

UART0 reception

A-D conversion

Timer A0

UART1 transmission

Level 0 (initial value)

High

Priority of peripheral I/O interrupts (if priority levels are same)

UART0 transmission

Key input interrupt

Processor interrupt priority level

(IPL)

Interrupt enable flag (I flag)

Address match

Watchdog timer

DBC

Reset

Figure 1.30. Interrupt resolution circuit

Low

Interrupt request level judgment output

Interrupt

request

accepted

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Interrupts

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Key Input Interrupt

If the direction register of any of P00 to P07 is set for input and a falling edge is input to that port, a key input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancelling the wait mode or stop mode. Figure 1.31 shows the block diagram of the key input interrupt. Note that if an “L” level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt.

Port P04-P07 pull-up select

Pull-up transistor

Port P07 direction register

bit Port P07 direction

Key input interrupt control register

(address 004D

)

P07/KI

Port P06 direction register

Port P0

Port P0 register

direction

P06/KI

P01/KI

P00/KI

Pull-up transistor

Figure 1.31. Block diagram of key input interrupt

Interrupt control

circuit

Key input interrupt request

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Address Match Interrupt

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Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents match the program counter value. Two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. Address match interrupts are not affected by the interrupt enable flag (I flag) and processor interrupt priority level (IPL). Figure 1.32 shows the address match interrupt-related registers.

Address match interrupt enable register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset AIER 0009

AIER0

AAAAAAAAAAAA

AIER1

AAAAAAAAAAAA

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Address match interrupt register i (i = 0, 1)

(b23)

(b19) (b16)

(b15) (b8)

b0 b7 b0b3

Address setting register for address match interrupt

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

b7 b0

Bit nameBit symbol

Address match interrupt 0

enable bit

Address match interrupt 1

enable bit

Function Values that can be set

XXXXXX00

Symbol Address When reset RMAD0 0012 RMAD1 0016

Function

0 : Interrupt disabled 1 : Interrupt enabled

to 0010

to 0014

0000016 to FFFFF

16 16

X00000 X00000

16 16

Figure 1.32. Address match interrupt-related registers

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Precautions for Interrupts

(1) Reading address 0000016

• When maskable interrupt is occurred, CPU read the interrupt information (the interrupt number and

interrupt request level) in the interrupt sequence. The interrupt request bit of the certain interrupt written in address 0000016 will then be set to “0”. Reading address 0000016 by software sets enabled highest priority interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed. Do not read address 0000016 by software.

(2) Setting the stack pointer

• The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt

before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in the

stack pointer before accepting an interrupt. Concerning the first instruction immediately after reset,

generating any interrupts is prohibited.

(3) External interrupt

• Either an “L” level or an “H” level of at least 250 ns width is necessary for the signal input to pins INT0

________

and INT1 regardless of the CPU operation clock.

• When changing a polarity of pins INT0 and INT1, the interrupt request bit may become "1". Clear the

interrupt request bit after changing the polarity. Figure 1.33 shows the switching condition of INT inter-

rupt request.

(Enable the accepting of INTi interrupt request)

________ ________

Clear the interrupt enable flag to “0”

Set the interrupt priority level to level 0

Clear the interrupt request bit to “0”

Set the interrupt priority level to level 1 to 7

(Disable interrupt)

(Disable

Set the polarity select bit

INTi

interrupt)

______

________

Set the interrupt enable flag to “1”

(Enable interrupt)

______

Figure 1.33. Switching condition of INT interrupt request

(4) Changing interrupt control register

See "Changing Interrupt Control Register".

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M30201 Group

Watchdog Timer

The watchdog timer has the function of detecting when the program is out of control. The watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. When XIN is selected for the BCLK, bit 7 of the watchdog timer control register (address 000F16) selects the prescaler division ratio (by 16 or by 128). When XCIN is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000F16).

When XIN is selected in BCLK

Watchdog timer cycle =

Prescaler division ratio (16 or 128) x watchdog timer count (32768)

BCLK

When XCIN is selected in BCLK

Watchdog timer cycle =

Prescaler division ratio (2) x watchdog timer count (32768)

BCLK

For example, when BCLK is 10MHz and the prescaler division ratio is set to 16, the watchdog timer cycle is approximately 52.4 ms.

The watchdog timer is initialized by writing to the watchdog timer start register (address 000E16) and when a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by writing to the watchdog timer start register (address 000E16). Figure 1.34 shows the block diagram of the watchdog timer. Figure 1.35 shows the watchdog timer-related registers.

Prescaler

1/16

BCLK

Write to the watchdog timer start register (address 000E

RESET

)

1/128

1/2

Figure 1.34. Block diagram of watchdog timer

“CM07 = 0” “WDC7 = 0”

“CM07 = 0” “WDC7 = 1”

“CM07 = 1”

Watchdog timer

Set to “7FFF

Watchdog timer interrupt request

”

Under

development

Watchdog Timer

Watchdog timer control register

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

b7 b6 b5 b4 b3 b2 b1 b0

High-order bit of watchdog timer

Reserved bit

Reserved bit Must always be set to “0”

WDC7

Watchdog timer start register

b7 b0

The watchdog timer is initialized and starts counting after a write instruction to this register. The watchdog timer value is always initialized to “7FFF regardless of whatever value is written.

Symbol Address When reset WDC 000F

Bit name

Prescaler select bit 0 : Divided by 16

Symbol Address When reset WDTS 000E

Function

000XXXXX

Must always be set to “0”

1 : Divided by 128

Indeterminate

FunctionBit symbol WR

”

Figure 1.35. Watchdog timer control and start registers

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer A

Timer

There are six 16-bit timers. These timers can be classified by function into timer A (one), timers B (two) and timers X (three). All these timers function independently. Figure 1.36 show the block diagram of timers.

TA0

TX0

TX1

INOUT

f1 f8 f32 f

1/8

c32

Noise

filter

Noise

filter

Noise

filter

1/4

CIN

Clock prescaler reset flag (bit 7 at address 0381

) set to “1”

• Timer mode

• One-shot mode

• PWM mode

Clock prescaler

1/32

Reset

C32

Timer A0

• Event counter mode

• Timer mode

• One-shot mode

• PWM mode

• Pulse width measuring mode

Timer X0

• Event counter mode

• Timer mode

• One-shot mode

• PWM mode

• Pulse width measuring mode

Timer X1

• Event counter mode

TX2

INOUT

TB0

TB1

Figure 1.36. Timer block diagram

Noise

filter

Noise

filter

Noise

filter

• Timer mode

• One-shot mode

• PWM mode

• Pulse width measuring mode

Timer X2

• Event counter mode

• Timer mode

• Pulse width measuring mode

Timer B0

• Event counter mode

• Timer mode

• Pulse width measuring mode

Timer B1

• Event counter mode

Timer X2

Timer B0

Timer B1

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer A

Figure 1.37 shows the block diagram of timer A. Figures 1.38 to 1.40 show the timer A-related registers. Use the timer A0 mode register bits 0 and 1 to choose the desired mode. Timer A has the four operation modes listed as follows:

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external source or a timer over flow.

• One-shot timer mode: The timer stops counting when the count reaches “000016”.

• Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.

Clock source selection

C32

Polarity

selection

TA0

TB1 overflow TX0 overflow

TX2 overflow

OUT

TA0

Pulse output

• Timer

• One shot

• PWM

• Timer (gate function)

• Event counter

Clock selection

External trigger

Figure 1.37. Block diagram of timer A

Count start flag

Down count

Up/down flag

Toggle flip-flop

Data bus high-order bits

Data bus low-order bits

Low-order 8 bits

Reload register (16)

Counter (16)

Up count/down count

Always down count except in event counter mode

High-order 8 bits

Timer A0 mode register

b7 b6 b5 b4 b3 b2 b1 b0

Figure 1.38. Timer A-related registers (1)

Symbol Address When reset TA0MR 0396

TMOD0

TMOD1

MR0 MR1 MR2 MR3 TCK0 TCK1

Bit name FunctionBit symbol

Operation mode select bit

Function varies with each operation mode

Count source select bit (Function varies with each operation mode)

b1 b0

0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode 1 1 : Pulse width modulation

(PWM) mode

Under

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Timer A

Timer A0 register (Note)

(b15) (b8)

b7 b0b7 b0

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Symbol Address When reset

TA0 0387

,0386

Indeterminate

Mitsubishi microcomputers

M30201 Group

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0

Values that can be set

to FFFE

0000

to FF

(Low-

(High-order addresses)

0016 to FE

order addresses)

Function

• Timer mode 000016 to FFFF Counts an internal count source

• Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow

• One-shot timer mode 000016 to FFFF Counts a one shot width

• Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator

• Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator

Note: Read and write data in 16-bit units.

Symbol Address When reset TABSR 0380

TA0S TX0S TX1S TX2S

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag

Bit name FunctionBit symbol

000X0000

0 : Stops counting 1 : Starts counting

Up/down flag

b7 b6 b5 b4 b3 b2 b1 b0

TB0S TB1S

CDCS

TA0UD

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

TA0P

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Timer B0 count start flag Timer B1 count start flag

Clock devided count start flag

Symbol Address When reset UDF 0384

Timer A0 up/down flag

Timer A0 two-phase pulse signal processing select bit

Bit name FunctionBit symbol

0 : Stops counting 1 : Starts counting

XXX0XXX0

0 : Down count 1 : Up count This specification becomes valid when the up/down flag content is selected for up/down switching cause

0 : two-phase pulse signal

processing disabled

1 : two-phase pulse signal

processing enabled

When not using the two-phase pulse signal processing function, set the select bit to “0”

Figure 1.39. Timer A-related registers (2)

Under

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Timer A

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

One-shot start flag

b7 b6 b5 b4 b3 b2 b1 b0

Trigger select register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ONSF 0382

TA0OS TX0OS TX1OS TX2OS

Nothing is assigned. When write, set "0". When read, its content is indeterminate.

Symbol Address When reset TRGSR 0383

TA0TGL

TA0TGH

TX0TGL

TX0TGH

TX1TGL

TX1TGH

TX2TGL

TX2TGH

Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag

Timer A0 event/trigger select bit

Timer X0 event/trigger select bit

Timer X1 event/trigger select bit

Timer X2 event/trigger select bit

16 XXXX00002

Bit name FunctionBit symbol

1 : Timer start When read, the value is “0”

16 0016

Bit name FunctionBit symbol

b1 b0

0 0 :

Input on TA0IN is selected (Note)

0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected

b3 b2

0 0 : Input on TX0INOUT is selected (Note) 0 1 : TB1 overflow is selected 1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected

b5 b4

Input on TX1INOUT is selected (Note)

0 0 : 0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected

b7 b6

0 0 :

Input on TX2INOUT is selected (Note)

0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected

Note: Set the corresponding port direction register to “0”(input mode).

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset CPSRF 0381

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

CPSR

Clock prescaler reset flag

AAAAAAAAAAAAA

Figure 1.40. Timer A-related registers (3)

16 0XXXXXXX2

Bit name FunctionBit symbol

0 : No effect 1 : Prescaler is reset (When read, the value is “0”)

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer A

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.13.) Figure 1.41 shows the timer A0 mode register in timer mode.

Table 1.13. Specifications of timer mode

Item Specification Count source f1, f8, f32, fc32 Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting

Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing TA0IN pin function Programmable I/O port or gate input TA0OUT pin function Programmable I/O port or pulse output Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped

Select function • Gate function

When the timer underflows

When a value is written to timer A0 register, it is written to both reload register and counter

• When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time)

Counting can be started and stopped by the TA0IN pin’s input signal

• Pulse output function Each time the timer underflows, the TA0OUT pin’s polarity is reversed

Timer A0 mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset TA0MR 0396

Bit name FunctionBit symbol WR

TMOD0 TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Operation mode select bit

Pulse output function select bit

Gate function select bit

0 (Must always be fixed to “0” in timer mode) Count source select bit

Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: The bit can be “0” or “1”. Note 3: Set the corresponding port direction register to “0” (input mode).

Figure 1.41. Timer A0 mode register in timer mode

b1 b0

0 0 : Timer mode 0 : Pulse is not output

(TA0

OUT

1 : Pulse is output (Note 1) (TA0

b4 b3

0 X 1 0 : Timer counts only when TA0IN pin 1 1 : Timer counts only when TA0

b7 b6

0 0 : f 0 1 : f8 1 0 : f 1 1 : f

pin is a normal port pin)

OUT

pin is a pulse output pin)

(Note 2)

: Gate function not available

(TA0IN pin is a normal port pin)

is held “L” (Note 3) is held “H” (Note 3)

32 C32

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer A

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer’s overflow. Timer A0 can count a single-phase and a two-phase external signal. Table 1.14 lists timer specifications when counting a single-phase external signal. Figure 1.42 shows the timer A0 mode register in event counter mode. Table 1.15 lists timer specifications when counting a two-phase external signal. Figure 1.43 shows the timer A0 mode register in event counter mode.

Table 1.14.

Count source

Count operation • Up count or down count can be selected by external signal or software

Divide ratio 1/ (FFFF16 - n + 1) for up count

Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing TA0IN pin function Programmable I/O port or count source input TA0OUT pin function Programmable I/O port, pulse output, or up/down count select input Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped

Select function • Free-run count function

Note: This does not apply when the free-run function is selected.

Timer specifications in event counter mode (when not processing two-phase pulse signal)

Item Specification

•

External signals input to TA0IN pin (effective edge can be selected by software)

• TB1 overflow, TX0 overflow, TX2 overflow

• When the timer overflows or underflows, it reloads the reload register con tents before continuing counting (Note)

1/ (n + 1) for down count n : Set value

The timer overflows or underflows

When a value is written to timer A0 register, it is written to both reload register and counter

• When counting in progress When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time)

Even when the timer overflows or underflows, the reload register content is not reloaded to it

• Pulse output function Each time the timer overflows or underflows, the TA0OUT pin’s polarity isreversed

Timer A0 mode register

b7 b6 b5 b4 b3 b2 b1 b0

010

(When not using two-phase pulse signal processing)

Symbol Address When reset TA0MR 0396

Bit symbol Bit name Function

TMOD0 TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Note 1: Set the corresponding port direction register to “1” (output mode). Note 2: This bit is valid when only counting an external signal. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: When performing two-phase pulse signal processing, make sure the two-phase

Operation mode select bit

Pulse output function select bit

Count polarity select bit (Note 2)

Up/down switching cause select bit

0 (Must always be fixed to “0” in event counter mode) Count operation type

select bit

Two-phase pulse operation select bit (Note 4)

pulse signal processing operation select bit (address 0384 event/trigger select bits (addresses 0383

16 0016

b1 b0

0 1 : Event counter mode

0 : Pulse is not output

(TA0

1 : Pulse is output (Note 1)

(TA0

0 : Counts external signal's falling edge 1 : Counts external signal's rising edge

0 : Up/down flag's content 1 : TA

0 : Reload type 1 : Free-run type

0 : Normal processing operation 1 : Multiply-by-4 processing operation

Figure 1.42. Timer A0 mode register in event counter mode

OUT pin is a normal port pin) OUT pin is a pulse output pin)

iOUT pin's input signal (Note 3)

16) to “00”.

16) is set to “1” and

Mitsubishi microcomputers

TA0

OUT

Up count

Down count

TA0

OUT

TA0

Count up all edges

Count down all edges

Under

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer A

Table 1.15. Timer specifications in event counter mode (when processing two-phase pulse signal)

Item Specification Count source • Two-phase pulse signals input to TA0IN or TA0OUT pin Count operation • Up count or down count can be selected by two-phase pulse signal

• When the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (Note)

Divide ratio • 1/ (FFFF16 - n + 1) for up count

• 1/ (n + 1) for down count n : Set value

Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0)

Interrupt request generation timing

TA0IN pin function Two-phase pulse input TA0OUT pin function Two-phase pulse input Read from timer Count value can be read out by reading timer A0 register Write to timer • When counting stopped

Select function • Normal processing operation

Timer overflows or underflows

When a value is written to timer A0 register, it is written to both reload register and counter

• When counting in progress When a value is written to timer A0 register, it is written to only reload register. (Transferred to counter at next reload time.)

The timer counts up rising edges or counts down falling edges on the TA0IN pin when input signal on the TA0OUT pin is “H”

• Multiply-by-4 processing operation If the phase relationship is such that the TA0IN pin goes “H” when the input signal on the TA0OUT pin is “H”, the timer counts up rising and falling edges on the TA0OUT and TA0IN pins. If the phase relationship is such that the TA0IN pin goes “L” when the input signal on the TA0OUT pin is “H”, the timer counts down rising and falling edges on the TA0OUT and TA0IN pins.

Note: This does not apply when the free-run function is selected.

Under

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Timer A

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A0 mode register

(When using two-phase pulse signal processing)

b7 b6 b5 b4 b3 b2 b1 b0

010

001

Symbol Address When reset TA0MR 0396

Bit name Function

TMOD0 TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Note: When performing two-phase pulse signal processing, make sure the two-phase

pulse signal processing operation select bit (address 0384 always be sure to set the event/trigger select bit (addresses 0383

Operation mode select bit

0 (Must always be “0” when using two-phase pulse signal processing)

1 (Must always be “1” when using two-phase pulse signal processing)

0 (Must always be “0” when using two-phase pulse signal processing)

Count operation type select bit

Two-phase pulse processing operation select bit (Note)

b1 b0

0 1 : Event counter mode

0 : Reload type 1 : Free-run type

0 : Normal processing operation 1 : Multiply-by-4 processing operation

) is set to “1”. Also,

) to “00”.

Figure 1.43. Timer A0 mode register in event counter mode

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer A

(3) One-shot timer mode

In this mode, the timer operates only once. (See Table 1.16.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.44 shows the timer A0 mode register in one-shot

timer mode.

Table 1.16. Timer specifications in one-shot timer mode

Item Specification Count source f1, f8, f32, fC32 Count operation • The timer counts down

• When the count reaches 000016, the timer stops counting after reloading a new count

• If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input

• The timer overflows

• The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016

• The count start flag is reset (= 0)

Interrupt request generation timing

TA0IN pin function Programmable I/O port or trigger input TA0OUT pin function Programmable I/O port or pulse output Read from timer When timer A0 register is read, it indicates an indeterminate value Write to timer • When counting stopped

The count reaches 000016

When a value is written to timer A0 register, it is written to both reload register and counter

• When counting in progress

When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time)

Timer A0 mode register

b7 b6 b5 b4 b3 b2 b1 b0

100

Symbol Address When reset TA0MR 0396

Bit symbol

TMOD0 TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Bit name

Operation mode select bit

Pulse output function select bit

External trigger select bit (Note 2)

Trigger select bit

0 (Must always be “0” in one-shot timer mode)

Count source select bit

b1 b0

1 0 : One-shot timer mode 0 : Pulse is not output

(TA0 1 : Pulse is output (Note 1) (TA0

0 : Falling edge of TA0IN pin's input signal (Note 3) 1 : Rising edge of TA0

0 : One-shot start flag is valid 1 : Selected by event/trigger select

b7 b6

0 0 : f 0 1 : f 1 0 : f 1 1 : f

Note 1: Set the corresponding port direction register to “1” (output mode).

Valid only when the TA0IN pin is selected by the event/trigger select bit

Note 2:

(addresses 0383

). If timer overflow is selected, this bit can be “1” or “0”.

Note 3: Set the corresponding port direction register to “0” (input mode).

Figure 1.44. Timer A0 mode register in one-shot timer mode

Function

OUT

pin is a normal port pin)

OUT

pin is a pulse output pin)

1 8 32 C32

pin's input signal (Note 3)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer A

(4) Pulse width modulation (PWM) mode

In this mode, the timer outputs pulses of a given width in succession. (See Table 1.17.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.45 shows the timer A0 mode register in pulse width modulation mode. Figure 1.46 shows the example of how a 16-bit pulse width modulator operates. Figure 1.47 shows the example of how an 8-bit pulse width modulator operates.

Table 1.17. Timer specifications in pulse width modulation mode

Item Specification Count source f1, f8, f32, fc32 Count operation •

16-bit PWM • High level width n / fi n : Set value

8-bit PWM

Count start condition • External trigger is input

Count stop condition • The count start flag is reset (= 0) 8 bits PWM •Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”

Interrupt request 16 bits PWM • Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”

generation timing

TA0IN pin function Programmable I/O port or trigger input TA0OUT pin function Pulse output Read from timer When timer A0 register is read, it indicates an indeterminate value Write to timer • When counting stopped :When a value is written to timer A0 register, it is

Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.

The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)

•

The timer reloads a new count at a rising edge of PWM pulse and continues counting

• The timer is not affected by a trigger that occurs when counting

• Cycle time (216-1) / fi fixed

•

High level width n (m+1) / fi n : values set to timer A0 register’s high-order address

• Cycle time (28-1) (m+1) / fi m : values set to timer A0 register’s low-order address

• The timer overflows

• The count start flag is set (= 1)

• Set value of "H" level width is FF16, 0016 : Timing that count value goes to 01

• Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 0001

written to both reload register and counter

• When counting in progress : When a value is written to timer A0 register, it is written to only reload register (Transferred to counter at next reload time)

Timer A0 mode register

b7 b6 b5 b4 b3 b2 b1 b0

111

Note 1: Valid only when the TA0 Note 2: Set the corresponding port direction register to “0” (input mode).

Note 3: Set the corresponding port direction register to “1” (output mode) when the pulse is output.

Symbol Address When reset TA0MR 0396

Bit name FunctionBit symbol

TMOD0 TMOD1

MR0 MR1

MR2

MR3

TCK0

TCK1

(addresses 0383

Operation mode select bit

1 (Must always be “1” in PWM mode) External trigger select

bit (Note 1)

Trigger select bit

16/8-bit PWM mode select bit

Count source select bit

). If timer overflow is selected, this bit can be “1” or “0”.

b1 b0

1 1 : PWM mode

0: Falling edge of TA0IN pin's input signal (Note 2) 1: Rising edge of TA0

0: Count start flag is valid 1: Selected by event/trigger select register

0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator

b7 b6

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

pin is selected by the event/trigger select bit

pin's input signal (Note 2)

Figure 1.45. Timer A0 mode register in pulse width modulation mode

Under

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Timer A

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Condition : Reload register = 000316, when external trigger

IN pin input signal) is selected

1 / fi X (2 – 1)

Trigger is not generated by this signal

i X

1 / f

Cleared to “0” when interrupt request is accepted, or cleared by software

Count source

TA0

input signal

PWM pulse output from TA0

OUT

Timer A0 interrupt request bit

fi : Frequency of count source

Note: n = 0000

(rising edge of TA0

“H”

“L”

“H”

“L”

“1” “0”

, f8, f32, f

C32

)

to FFFF16.

Figure 1.46. Example of how a 16-bit pulse width modulator operates

Condition : Reload register high-order 8 bits = 02

Reload register low-order 8 bits = 02 External trigger (falling edge of TA0

Count source (Note1)

pin input signal

TA0

Underflow signal of 8-bit prescaler (Note2)

PWM pulse output

OUT

from TA0

Timer A0 interrupt request bit

Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. Note 3: m = 00

“H” “L”

“1” “0”

fi : Frequency of count source

, f8, f32, f

C32

)

to FF16; n = 0016 to FF16.

pin input signal) is selected

1 / fi X (m + 1) X (2 – 1)

1 / fi X (m + 1)

1 / fi X (m + 1) X n

Cleared to “0” when interrupt request is accepted, or cleaerd by software

Figure 1.47. Example of how an 8-bit pulse width modulator operates

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer B

Figure 1.48 shows the block diagram of timer B. Figures 1.49 and 1.50 show the timer B-related registers. Use the timer Bi mode register (i = 0, 1) bits 0 and 1 to choose the desired mode. Timer B has three operation modes listed as follows:

• Timer mode : The timer counts an internal count source.

• Event counter mode : The timer counts pulses from an external source or a timer overflow.

• Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or pulse width.

Data bus high-order bits

Clock source selection

f1 f8

• Timer

• Pulse period/pulse width measurement

f32

TBi

(i = 0, 1)

fC32

Polarity switching and edge pulse

Can be selected in only event counter mode

TBj overflow (j = 1 when i = 0, j = 0 when i = 1)

• Event counter

Figure 1.48. Block diagram of timer B

Timer Bi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset TBiMR(i = 0, 1) 039B

TMOD0

TMOD1

MR0 MR1 MR2

Data bus low-order bits

Low-order 8 bits

Reload register (16)

Count start flag

Counter reset circuit

, 039C

00XX00002

Bit name

Operation mode select bit

Function varies with each operation mode

b1 b0

0 0 : Timer mode 0 1 : Event counter mode 1 0 : Pulse period/pulse width

measurement mode

1 1 : Inhibited

Counter (16)

FunctionBit symbol

High-order 8 bits

(Note 1)

MR3 TCK0 TCK1

Note 1: Timer B0. Note 2: Timer B1. Note 3: Must set “00” to operation mode select bit of M30200.

Count source select bit (Function varies with each operation mode)

Figure 1.49. Timer B-related registers (1)

(Note 2)

Under

development

Timer B

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer Bi register (Note)

(b15) (b8)

b7 b0b7 b0

• Timer mode 000016 to FFFF16 Counts the timer's period

• Event counter mode 000016 to FFFF16 Counts external pulses input or a timer overflow

• Pulse period / pulse width measurement mode Measures a pulse period or width

Note1: Read and write data in 16-bit units.

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset TABSR 0380

TA0S TX0S TX1S TX2S

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

Symbol Address When reset

TB0 0391 TB1 0393

Function

16 000X00002

Bit name FunctionBit symbol

Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag

16, 039016 Indeterminate 16, 039216 Indeterminate

Values that can be set

0 : Stops counting 1 : Starts counting

TB0S TB1S

CDCS

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset CPSRF 0381

Bit symbol

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

CPSR

AAAAAAAAAAAAA

Figure 1.50. Timer B-related registers (2)

Timer B0 count start flag Timer B1 count start flag

Clock devided count start flag

16 0XXXXXXX2

Bit name Function

Clock prescaler reset flag

0 : Stops counting 1 : Starts counting

0 : No effect 1 : Prescaler is reset (When read, the value is “0”)

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer B

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.18.) Figure 1.51 shows the timer Bi mode register in timer mode.

Table 1.18. Timer specifications in timer mode

Item Specification Count source f1, f8, f32, fC32 Count operation • Counts down

• When the timer underflows, it reloads the reload register contents before continuing counting

Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing TBiIN pin function Programmable I/O port Read from timer Count value is read out by reading timer Bi register Write to timer • When counting stopped

The timer underflows

When a value is written to timer Bi register, it is written to both reload register and counter

• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)

Timer Bi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Figure 1.51. Timer Bi mode register in timer mode

Symbol Address When reset TBiMR(i=0, 1) 039B

Bit symbol WR

TMOD0 TMOD1

MR0 MR1

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

MR3

TCK0

TCK1

Operation mode select bit

Invalid in timer mode Can be “0” or “1”

Invalid in timer mode. This bit can neither be set nor reset. When read in timer mode, its content is indeterminate.

Count source select bit

Bit name Function

to 039C

00XX0000

b1 b0

0 0 : Timer mode

b7 b6

0 0 : f 0 1 : f

1 0 : f

1 1 : f

C32

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer B

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.19.) Figure

1.52 shows the timer Bi mode register in event counter mode.

Table 1.19. Timer specifications in event counter mode

Item Specification

Count source • External signals input to TBiIN pin

• Effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software

Count operation • Counts down

• When the timer underflows, it reloads the reload register contents before continuing counting

Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing TBiIN pin function Count source input Read from timer Count value can be read out by reading timer Bi register Write to timer • When counting stopped

The timer underflows

When a value is written to timer Bi register, it is written to both reload register and counter

• When counting in progress When a value is written to timer Bi register, it is written to only reload register (Transferred to counter at next reload time)

Timer Bi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset TBiMR(i=0, 1) 039B

TMOD0 TMOD1

MR0

MR1

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

MR3

TCK0

TCK1

Note 1: Valid only when input from the TBiIN pin is selected as the event clock. Note 2: Set the corresponding port direction register to “0” (input mode).

Operation mode select bit

Count polarity select bit (Note 1)

Invalid in event counter mode. This bit can neither be set nor reset. When read in event counter mode, its content is indeterminate.

Invalid in event counter mode. Can be “0” or “1”.

Event clock select

If timer's overflow is selected, this bit can be “0” or “1”.

to 039C1600XX0000

Bit name FunctionBit symbol

b1 b0

0 1 : Event counter mode

b3 b2

0 0 : Counts external signal's

falling edges

0 1 : Counts external signal's

rising edges

1 0 : Counts external signal's

falling and rising edges

1 1 : Inhibited

0 : Input from TBi 1 : TBj overflow

( j = 1 when i = 0,

j = 0 when i = 1)

pin (Note 2)

Figure 1.52. Timer Bi mode register in event counter mode

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer B

(3) Pulse period/pulse width measurement mode

In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.20.) Figure 1.53 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure

1.54 shows the operation timing when measuring a pulse period. Figure 1.55 shows the operation timing when measuring a pulse width.

Table 1.20. Timer specifications in pulse period/pulse width measurement mode

Item Specification Count source f1, f8, f32, fc32 Count operation • Up count

• Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting

Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing

TBiIN pin function Measurement pulse input Read from timer When timer Bi register is read, it indicates the reload register’s content

Write to timer Cannot be written to Note 1: Note 2:

An interrupt request is not generated when the first effective edge is input after the timer has started counting. The value read out from the timer Bi register is indeterminate until the second effective edge is input after the timer.

• When measurement pulse's effective edge is input (Note 1)

• When an overflow occurs. (Simultaneously, the timer Bi overflow flag changes to “1”. The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Bi mode register.)

(measurement result) (Note 2)

Timer Bi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Note : The timer Bi overflow flag changes to “0” when the count start flag is “1” and a value is written to the

Symbol Address When reset TBiMR(i=0 , 1) 039B

Bit nameBit symbol

TMOD0 TMOD1

MR0

MR1

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

MR3

TCK0

TCK1

Operation mode select bit

Measurement mode select bit

Timer Bi overflow flag ( Note)

Count source select bit

timer Bi mode register. This flag cannot be set to “1” by software.

, 039C

00XX0000

b1 b0

1 0 : Pulse period / pulse width

measurement mode

b3 b2

0 0 : Pulse period measurement (Interval between

measurement pulse's falling edge to falling edge)

0 1 : Pulse period measurement (Interval between

measurement pulse's rising edge to rising edge)

1 0 : Pulse width measurement (Interval between

measurement pulse's falling edge to rising edge, and between rising edge to falling edge)

1 1 : Inhibited

0 : Timer did not overflow 1 : Timer has overflowed

b7 b6

0 0 : f 0 1 : f

1 0 : f

1 1 : f

C32

Function

Figure 1.53. Timer Bi mode register in pulse period/pulse width measurement mode

Under

development

Timer B

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

When measuring measurement pulse time interval from falling edge to falling edge

Count source

Measurement pulse

“H”

“L”

Transfer (indeterminate value)

Reload register counter transfer timing

Timing at which counter

reaches “0000

Count start flag

Timer Bi interrupt request bit

”

“1” “0”

Cleared to “0” when interrupt request is accepted, or cleared by software.

Timer Bi overflow flag

“1” “0”

Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.

Figure 1.54. Operation timing when measuring a pulse period

Transfer (measured value)

(Note 1)(Note 1)

(Note 2)

Count source

Measurement pulse

Reload register counter

“H”

“L”

Transfer (indeterminate value)

Transfer (measured value)

transfer timing

Timing at which counter reaches “0000

Count start flag

Timer Bi interrupt request bit

Timer Bi overflow flag

16”

“1” “0”

Cleared to “0” when interrupt request is accepted, or cleared by software.

Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.

Figure 1.55. Operation timing when measuring a pulse width

Transfer (measured value)

(Note 1)

Transfer (measured value)

(Note 1)(Note 1)(Note 1)

(Note 2)

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer X

Figure 1.56 shows the block diagram of timer X. Figures 1.57 to 1.59 show the timer X-related registers. Use the timer Xi mode register bits 0 and 1 to choose the desired mode. Timer X has the five operation modes listed as follows:

• Timer mode : The timer counts an internal count source.

• Event counter mode : The timer counts pulses from an external source or a timer overflow.

• One-shot timer mode : The timer stops counting when the count reaches “000016”.

• Pulse period/pulse width measuring mode : The timer measures an external signal's pulse period or pulse width.

• Pulse width modulation (PWM) mode : The timer outputs pulses of a given width.

TXi

INOUT

(i=0 to 2)

Clock source selection

C32

Polarity

switching and

edge pulse

TB1 overflow

Pulse output

• Timer

• One shot

• PWM

• Pulse period/pulse width measurement

• Timer (gate function)

• Event counter

Clock selection

Figure 1.56. Block diagram of timer X

Count start flag

Counter reset circuit

External trigger

*1 = TA0, *2 = TX1 when TX0 *1 = TX0, *2 = TX2 when TX1 *1 = TX1, *2 = TA0 when TX2

Toggle flip-flop

Data bus high-order bits

Data bus low-order bits

Low-order 8 bits

Reload register (16)

Counter (16)

High-order 8 bits

Timer Xi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset TXiMR(i = 0 to 2) 0397

TMOD0

TMOD1

MR0 MR1 MR2 MR3

TCK0 TCK1

Operation mode select bit

Function varies with each operation mode

Count source select bit (Function varies with each operation mode)

Figure 1.57. Timer X-related registers (1)

Bit name

16 to 039916 0016

FunctionBit symbol

b1 b0

0 0 : Timer mode 0 1 : Event counter mode 1 0 : One-shot timer mode or pulse period/

pulse width measurement mode

1 1 : Pulse width modulation (PWM) mode

Under

development

Timer X

Timer Xi register (Note)

(b15) (b8)

b7 b0b7 b0

Mitsubishi microcomputers

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Symbol Address When reset

TX0 0389 TX1 038B TX2 038D

16,038816 Indeterminate 16,038A16 Indeterminate 16,038C16 Indeterminate

M30201 Group

Count start flag

b7 b6 b5 b4 b3 b2 b1 b0

Function

• Timer mode 000016 to FFFF16 Counts an internal count source

• Event counter mode 000016 to FFFF16 Counts pulses from an external source or timer overflow

• One-shot timer mode 000016 to FFFF16 Counts a one shot width

• Pulse period / pulse width measurement mode Measures a pulse period or width

• Pulse width modulation mode (16-bit PWM) Functions as a 16-bit pulse width modulator

• Pulse width modulation mode (8-bit PWM) Timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator

Note: Read and write data in 16-bit units.

Symbol Address When reset TABSR 0380

TA0S TX0S TX1S TX2S

Nothing is assigned. When write, set "0" When read, their contents are indeterminate.

Timer A0 count start flag Timer X0 count start flag Timer X1 count start flag Timer X2 count start flag

16 000X00002

Bit name FunctionBit symbol

0 : Stops counting 1 : Starts counting

Values that can be set

16 to FFFE16

0000

16 to FF16

(High-order addresses)

16 to FF16 (Low-

order addresses)

TB0S TB1S

CDCS

Figure 1.58. Timer X-related registers (2)

Timer B0 count start flag Timer B1 count start flag

Clock devided count start flag

0 : Stops counting 1 : Starts counting

Under

development

Timer X

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

One-shot start flag

b7 b6 b5 b4 b3 b2 b1 b0

Trigger select register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ONSF 0382

XXXX0000

Bit name FunctionBit symbol

TA0OS TX0OS TX1OS TX2OS

Timer A0 one-shot start flag Timer X0 one-shot start flag Timer X1 one-shot start flag Timer X2 one-shot start flag

1 : Timer start When read, the value is “0”

Nothing is assigned. When write, set "0". When read, its content is indeterminate.

Symbol Address When reset TRGSR 0383

Bit name FunctionBit symbol

TA0TGL

TA0TGH

TX0TGL

Timer A0 event/trigger select bit

Timer X0 event/trigger select bit

b1 b0

Input on TA0IN is selected (Note)

0 0 : 0 1 : TB1 overflow is selected 1 0 : TX2 overflow is selected 1 1 : TX0 overflow is selected

b3 b2

0 0 :

Input on TX0

INOUT

0 1 : TB1 overflow is selected

TX0TGH

TX1TGL

TX1TGH

Timer X1 event/trigger select bit

1 0 : TA0 overflow is selected 1 1 : TX1 overflow is selected

b5 b4

Input on TX1

0 0 :

INOUT

0 1 : TB1 overflow is selected 1 0 : TX0 overflow is selected 1 1 : TX2 overflow is selected

TX2TGL

TX2TGH

Timer X2 event/trigger select bit

b7 b6

0 0 :

Input on TX2

INOUT

0 1 : TB1 overflow is selected 1 0 : TX1 overflow is selected 1 1 : TA0 overflow is selected

is selected (Note)

Note: Set the corresponding port direction register to “0”(input mode).

Clock prescaler reset flag

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset CPSRF 0381

Nothing is assigned. When write, set "0". When read, their contents are indeterminate.

CPSR

Clock prescaler reset flag

AAAAAAAAAAAAAA

Figure 1.59. Timer X-related registers (3)

Bit name FunctionBit symbol

0XXXXXXX

0 : No effect 1 : Prescaler is reset (When read, the value is “0”)

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer X

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.21.) Figure 1.60 shows the timer Xi mode register in timer mode.

Table 1.21. Specifications of timer mode

Item Specification Count source f1, f8, f32, fC32 Count operation • Down count

•

When the timer underflows, it reloads the reload register contents before continuing counting Divide ratio 1/(n+1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing TXiINOUT pin function Programmable I/O port, gate input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer • When counting stopped

Select function • Gate function

When the timer underflows

When a value is written to timer Xi register, it is written to both reload register and counter

• When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time)

Counting can be started and stopped by the TXiINOUT pin’s input signal

• Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed

Timer Xi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Note 1: Set the corresponding port direction register to “1” (output mode). Gate function Note 2: The bit can be “0” or “1”.

Note 3: Set the corresponding port direction register to “0” (input mode). Pulse output

Symbol Address When reset TXiMR(i = 0 to 2) 0397

TMOD0 TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Operation mode select bit

Pulse output function select bit

Gate function select bit

0 (Must always be fixed to “0” in timer mode) Count source select bit

cannot be selected when pulse output function is selected.

function cannot be selected when gate function is selected.

to 0399

Bit name FunctionBit symbol WR

b1 b0

0 0 : Timer mode 0 : Pulse is not output

(TXi

INOUT

1 : Pulse is output (Note 1) (TXi

INOUT

b4 b3

(Note 2)

0 X 1 0 : Timer counts only when TXi 1 1 : Timer counts only when TXi

b7 b6

0 0 : f 0 1 : f8 1 0 : f 1 1 : f

: Gate function not available

(TXi

pin is held “L” (Note 3) pin is held “H” (Note 3)

32 C32

pin is a normal port pin)

pin is a pulse output pin)

INOUT

pin is a normal port pin)

INOUT

Figure 1.60. Timer Xi mode register in timer mode

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer X

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer’s overflow. (See Table 1.22.) Figure

1.61 shows the timer Xi mode register in event counter mode.

Table 1.22.

Timer specifications in event counter mode (when not processing two-phase pulse signal)

Item Specification

Count source

•

External signals input to TXi

INOUT

pin (effective edge can be selected by software)

• TB1 overflow, TA0 overflow, TXi overflow

Count operation • Down count

• When the timer underflows, it reloads the reload register contents before continuing counting (Note)

Divide ratio 1/ (n + 1) n : Set value Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing

The timer underflows TXiINOUT pin function Programmable I/O port, count source input or pulse output Read from timer Count value can be read out by reading timer Xi register Write to timer • When counting stopped

When a value is written to timer Xi register, it is written to both reload register and counter

• When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time)

Select function • Free-run count function

Even when the timer underflows, the reload register content is not reloaded to it

• Pulse output function Each time the timer underflows, the TXiINOUT pin’s polarity is reversed

Note: This does not apply when the free-run function is selected.

Timer Xi mode register

b7 b6 b5 b4 b3 b2 b1 b0

010

Note 1: Count source is selected by event/trigger select bit(address 038316) in event counter mode. Note 2: Set the corresponding port direction register to “1” (output mode). TXi

selected as count source when pulse output function is selected.

Note 3: This bit is valid when only counting an external signal.

Symbol Address When reset TXiMR(i = 0 to 2) 0397

Bit symbol Bit name Function

TMOD0 TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Operation mode select bit

Pulse output function select bit

Count polarity select bit (Note 3)

Invalid in event counter mode. Can be “0” or “1”.

0 (Must always be fixed to “0” in event counter mode)

Count operation type select bit

Invalid in event counter mode. Can be “0” or “1”.

to 0399

b1 b0

0 1 : Event counter mode

0 : Pulse is not output

INOUT

(TXi

1 : Pulse is output (Note 2)

(TXi

0 : Counts external signal's falling edge 1 : Counts external signal's rising edge

0 : Reload type 1 : Free-run type

pin is a normal port pin)

INOUT

pin is a pulse output pin)

(Note 1)

INOUT

pin input is not

Figure 1.61. Timer Xi mode register in event counter mode

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer X

(3) One-shot timer mode

In this mode, the timer operates only once. (See Table 1.23.) When a trigger occurs, the timer starts up and continues operating for a given period. Figure 1.62 shows the timer Xi mode register in one-shot timer mode.

Table 1.23. Timer specifications in one-shot timer mode

Item Specification Count source f1, f8, f32, fC32 Count operation • The timer counts down

• When the count reaches 000016, the timer stops counting after reloading a new count

• If a trigger occurs when counting, the timer reloads a new count and restarts counting Divide ratio 1/n n : Set value Count start condition • An external trigger is input

• The timer overflows

• The one-shot start flag is set (= 1) Count stop condition • A new count is reloaded after the count has reached 000016

• The count start flag is reset (= 0)

Interrupt request generation timing

TXiINOUT pin function Programmable I/O port, trigger input or pulse output Read from timer When timer Xi register is read, it indicates an indeterminate value Write to timer • When counting stopped

The count reaches 000016

When a value is written to timer Xi register, it is written to both reload register and counter

• When counting in progress

When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time)

Timer Xi mode register

b7 b6 b5 b4 b3 b2 b1 b0

100

Note 1: Set the corresponding port direction register to “1” (output mode). External trigger cannot be selected

as count start condition when pulse output function is selected.

Note 2: Valid only when the TXi

timer overflow is selected, this bit can be “1” or “0”. Note 3: Set the corresponding port direction register to “0” (input mode). Note 4: Pulse output function cannot be selected when TXi

(addresses 0383

Symbol Address When reset TXiMR(i = 0 to 2) 0397

Bit symbol

TMOD0 TMOD1

MR0

MR1

MR2

MR3

TCK0

TCK1

Operation mode select bit

Pulse output function select bit

External trigger select bit (Note 2)

Trigger select bit

0 (Must always be “0” in one-shot timer mode) Count source select bit

to 0399

Bit name

b1 b0

1 0 : One-shot timer mode or pulse period /

0 : Pulse is not output (TXi 1 : Pulse is output (Note 1) (TXi

0 : Falling edge of TXi 1 : Rising edge of TXi

0 : One-shot start flag is valid 1 : Selected by event/trigger select register (Note 4)

b7 b6

0 0 : f 0 1 : f 1 0 : f 1 1 : f

INOUT

pin is selected by the event/trigger select bit (addresses 038316). If

0016

Function

pulse width measurement mode

INOOUT

pin is a normal port pin)

INOOUT

pin is a pulse output pin)

INOOUT

pin's input signal (Note 3)

INOOUT

pin's input signal (Note 3)

1 8 32 C32

INOUT

pin is selected by the event/trigger select bit

Figure 1.62. Timer Xi mode register in one-shot timer mode

Mitsubishi microcomputers

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

Timer X

(4) Pulse period/pulse width measurement mode

In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.24.) Figure 1.63 shows the timer Xi mode register in pulse period/pulse width measurement mode. Figure

1.64 shows the operation timing when measuring a pulse period. Figure 1.65 shows the operation timing when measuring a pulse width.

Table 1.24. Timer specifications in pulse period/pulse width measurement mode

Item Specification Count source f1, f8, f32, fc32 Count operation • Up count

• Counter value “000016” is transferred to reload register at measurement pulse's effective edge and the timer continues counting

Count start condition Count start flag is set (= 1) Count stop condition Count start flag is reset (= 0) Interrupt request generation timing

TXiINOUT pin function Measurement pulse input Read from timer When timer Xi register is read, it indicates the reload register’s content

Write to timer Cannot be written to Note 1: Note 2:

An interrupt request is not generated when the first effective edge is input after the timer has started counting. The value read out from the timer Xi register is indeterminate until the second effective edge is input after the timer.

• When measurement pulse's effective edge is input (Note 1)

• When an overflow occurs. (Simultaneously, the timer Xi overflow flag changes to “1”. The timer Xi overflow flag changes to “0” when the count start flag is “1” and a value is written to the timer Xi mode register.)

(measurement result) (Note 2)

Timer Xi mode register

b7 b6 b5 b4 b3 b2 b1 b0

Note: The timer Xi overflow flag changes to “0” when the count start flag is “1” and a value is written to

Symbol Address When reset TXiMR(i = 0 to 2) 0397

TMOD0 TMOD1

MR0

MR1

MR3

TCK0

TCK1

the timer Xi mode register. This flag cannot be set to “1” by software.

Operation mode select bit

Measurement mode select bit

Timer Xi overflow flag (Note)

1 (Must always be “1” in pulse period / pulse width measurement mode)

Count source select bit

to 0399

002

Bit nameBit symbol

b1 b0

1 0 : One-shot timer mode or pulse period /

pulse width measurement mode

b3 b2

0 0 : Pulse period measurement (Interval between

measurement pulse's falling edge to falling edge)

0 1 : Pulse period measurement (Interval between

measurement pulse's rising edge to rising edge)

1 0 : Pulse width measurement (Interval between

measurement pulse's falling edge to rising edge, and between rising edge to falling edge)

1 1 : Inhibited 0 : Timer did not overflow

1 : Timer has overflowed

b7 b6

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

Function

Figure 1.63. Timer Xi mode register in pulse period/pulse width measurement mode

Under

development

Timer X

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

When measuring measurement pulse time interval from falling edge to falling edge

Count source

Measurement pulse

“H” “L”

Transfer (indeterminate value)

Reload register counter transfer timing

Timing at which counter reaches “0000

Count start flag

Timer Xi interrupt request bit

”

“1” “0”

Cleared to “0” when interrupt request is accepted, or cleared by software.

Timer Xi overflow flag

“1” “0”

Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.

Figure 1.64. Operation timing when measuring a pulse period

Transfer (measured value)

(Note 1)(Note 1)

(Note 2)

Count source

Measurement pulse

Reload register counter

“H”

“L”

Transfer (indeterminate value)

transfer timing

Timing at which counter

reaches “0000

Count start flag

Timer Xi interrupt request bit

Timer Xi overflow flag

”

“1” “0”

Cleared to “0” when interrupt request is accepted, or cleared by software.

Note 1: Counter is initialized at completion of measurement. Note 2: Timer has overflowed.

Transfer (measured value)

(Note 1)

Transfer (measured value)

(Note 1)(Note 1)(Note 1)

(Note 2)

Figure 1.65. Operation timing when measuring a pulse width

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Timer X

(5) Pulse width modulation (PWM) mode

In this mode, the timer outputs pulses of a given width in succession. (See Table 1.25.) In this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure 1.66 shows the timer Xi mode register in pulse width modulation mode. Figure 1.67 shows the example of how a 16-bit pulse width modulator operates. Figure 1.68 shows the example of how an 8-bit pulse width modulator operates.

Table 1.25. Timer specifications in pulse width modulation mode

Item Specification

Count source Count operation

16-bit PWM

8-bit PWM

Count start condition

Count stop condition

Interrupt

8 bits PWM request generation

16 bits PWM timing

TXiINOUT pin function Read from timer Write to timer

Note: When set value of "H" level width is 0016 or 000016, pulse outputs "L" level and inversion value, FF16 or FFFF16 is set to timer.

f1, f8, f32, fC32

• Down counts (operating as an 8-bit or a 16-bit pulse width modulator)

•

The timer reloads a new count at a rising edge of PWM pulse and continues counting

• The timer is not affected by a trigger that occurs when counting

• "H" level width n / fi n : Set value

• Cycle time (216-1) / fi fixed

•

"H" level width n (m+1)/ fi n:values set to timer Xi register’s high-order address

•

Cycle time (28-1) (m+1) / fi m : values set to timer Xi register’s low-order address

• The timer overflows

• The count start flag is set (= 1)

• The count start flag is reset (= 0)

• Set value of "H" level width is except FF16, 0016 : PWM pulse goes “L”

• Set value of "H" level width is FF16, 0016 : Timing that count value goes to 01

• Set value of "H" level width is except FFFF16, 000016 : PWM pulse goes “L”

• Set value of "H" level width is FFFF16, 000016 : Timing that count value goes to 0001 Pulse output When timer Xi register is read, it indicates an indeterminate value

• When counting stopped When a value is written to timer Xi register, it is written to both reload register and counter

• When counting in progress When a value is written to timer Xi register, it is written to only reload register (Transferred to counter at next reload time)

Timer Xi mode register

b7 b6 b5 b4 b3 b2 b1 b0

111

Note 1: TXi Note 2: Set the corresponding port direction register to “1” (output mode).

Symbol Address When reset TXiMR(i = 0 to 2) 0397

TMOD0 TMOD1

MR0 MR1 MR2

MR3

TCK0

TCK1

Operation mode select bit

1 (Must always be “1” in PWM mode) Invalid in PWM mode. Can be “0” or “1”. Trigger select bit

16/8-bit PWM mode select bit

Count source select bit

INOUT

pin inout cannot be selected by the event/trigger select bit(addresses 038316).

to 0399

Bit name FunctionBit symbol

b1 b0

1 1 : PWM mode

0: Count start flag is valid 1: Selected by event/trigger select register

0: Functions as a 16-bit pulse width modulator 1: Functions as an 8-bit pulse width modulator

b7 b6

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

Figure 1.66. Timer Xi mode register in pulse width modulation mode

(Note 1)

Under

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Timer X

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Condition : Reload register = 000316, when trigger (timer overflow) is selected

1 / fi X (2 – 1)

Count source

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Trigger signal

PWM pulse output from TXi

INOUT pin

Timer Xi interrupt request bit

“H”

“L”

“H”

“L”

“1” “0”

Trigger is not generated by this signal

i X n

1 / f

fi : Frequency of count source

1, f8, f32, fC32)

Note1: n = 0000

16 to FFFF16.

Cleared to “0” when interrupt request is accepted, or cleared by software

Figure 1.67. Example of how a 16-bit pulse width modulator operates

Condition : Reload register high-order 8 bits = 02

Reload register low-order 8 bits = 02 Trigger (timer overflow) is selected

Count source (Note1)

1 / fi X (m + 1) X (2 – 1)

Trigger signal

“H” “L”

1 / fi X (m + 1)

Underflow signal of 8-bit prescaler (Note2)

“H” “L”

1 / fi X (m + 1) X n

PWM pulse output

INOUT

from TXi

Timer Xi interrupt request bit

“H” “L”

“1” “0”

fi : Frequency of count source

, f8, f32, f

C32

)

Cleared to “0” when interrupt request is accepted, or cleaerd by software

Note 1: The 8-bit prescaler counts the count source. Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.

Note 3: m = 00

to FF16; n = 0016 to FF16.

Figure 1.68. Example of how an 8-bit pulse width modulator operates

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Serial I/O

Serial I/O is configured as two channels: UART0 and UART1. UART0 and UART1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. Figure 1.69 shows the block diagram of UART0 and UART1. Figure 1.70 shows the block diagram of the transmit/receive unit. UART0 has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous serial I/ O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses 03A016 and 03A816) determine whether UART0 is used as a clock synchronous serial I/O or as a UART. UART1 is used as a UART only. Figures 1.71 through 1.73 show the registers related to UARTi.

(UART0)

RxD

Clock source selection

CLK

polarity

reversing

CLKS

circuit

(UART1)

RxD

Clock source selection

Bit rate generator

Internal

1 / (m+1)

External

Clock synchronous type (when internal clock is selected)

Clock output pin select switch

Bit rate generator

1 / (n+1)

UART reception

1/16

Clock synchronous type

UART transmission

1/16

Clock synchronous type

(when internal clock is selected)

1/2

Clock synchronous type (when external clock is selected)

1/16

Reception

control circuit

Transmission control circuit

Reception

control circuit

Transmission

control circuit

Receive clock

Transmit clock

Receive clock

Transmit clock

Transmit/

receive

unit

Transmit/

receive

unit

TxD

m : Values set to UART0 bit rate generator (BRG0) n : Values set to UART1 bit rate generator (BRG1)

Figure 1.69. Block diagram of UARTi (i = 0, 1)

Under

development

Serial I/O

RxDi

1SP

SP SP

2SP

PAR

PAR disabled

PAR enabled

Clock synchronous type

UART

Clock synchronous type

UART (7 bits) UART (8 bits)

UART (9 bits)

UART (7 bits)

Clock synchronous type

UART (8 bits) UART (9 bits)

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UARTi receive register

0000000

D7D6D5D4D3D2D1D

Data bus high-order bits

Data bus low-order bits

D7D6D5D4D3D2D1D

UART (8 bits) UART (9 bits)

Clock synchronous type

UART (7 bits)

SP SP

2SP

1SP

PAR

PAR enabled

PAR disabled

“0”

UART

Clock synchronous type

UART (9 bits)

UART (7 bits) UART (8 bits)

Clock synchronous type

Note: UART1 cannot be used in clock synchronous serial I/O.

MSB/LSB conversion circuit

UARTi transmit register

SP: Stop bit PAR: Parity bit

UARTi receive

buffer register

UARTi transmit

buffer register

TxDi

Figure 1.70. Block diagram of transmit/receive unit

Under

development

Serial I/O

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UARTi transmit buffer register

(b15) (b8)

b7 b0

UARTi receive buffer register

(b15) b7 b0

(b8)

b7 b0

Symbol Address When reset

U0TB 03A3 U1TB 03AB

Transmit data Nothing is assigned.

When write, set "0". When read, their contents are indeterminate.

Symbol Address When reset

U0RB 03A7 U1RB 03AF

Bit

symbol

Nothing is assigned. When write, set "0". When read, the value of these bits is “0”.

OER

FER

PER

SUM

Note: Bits 15 through 12 are set to “0” when the receive enable bit is set to “0”. (Bit 15 is set

to “0” when bits 14 to 12 all are set to “0”.) Bits 14 and 13 are also set to “0” when the lower byte of the UARTi receive buffer register (addresses 03A6 read out.

Bit name

Overrun error flag (Note)

Framing error flag (Note)

Parity error flag (Note)

Error sum flag (Note)

16, 03A216 Indeterminate 16, 03AA16 Indeterminate

Function

16, 03A616 Indeterminate 16, 03AE16 Indeterminate

Function (During clock synchronous serial I/O

mode)

Receive data

0 : No overrun error 1 : Overrun error found

Invalid

Function

(During UART mode)

Receive data

0 : No overrun error 1 : Overrun error found

0 : No framing error 1 : Framing error found

0 : No parity error 1 : Parity error found

0 : No error 1 : Error found

16, and 03AE16) is

UARTi bit rate generator

Assuming that set value = n, BRGi divides the count source by n + 1

Figure 1.71. Serial I/O-related registers (1)

Symbol Address When reset U0BRG 03A1 U1BRG 03A9

Function

16 Indeterminate 16 Indeterminate

Values that can be set

0016 to FF16

Under

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Serial I/O

UARTi transmit/receive mode register

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

UiMR(i=0,1) 03A0

, 03A8

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Bit

symbol

SMD0

Bit name

Serial I/O mode select bit (Note 1)

SMD1

SMD2

CKDIR

Internal/external clock select bit (Note 2)

STPS

Stop bit length select bit

PRY

Odd/even parity select bit

PRYE

Parity enable bit

Sleep select bit

SLEP

Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: UART1 can use only internal clock. Must set this bit to “1”.

UARTi transmit/receive control register 0

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

UiC0(i=0,1) 03A4

Bit

symbol

CLK0

Bit name

BRG count source select bit

CLK1

Set this bit to “0”.

Function

(During clock synchronous

serial I/O mode)

Must be fixed to 001

b2 b1 b0

0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited

0 : Internal clock 1 : External clock

Invalid

Must always be “0”

, 03AC

Function (Note)

(During clock synchronous

serial I/O mode)

b1 b0

is selected

0 0 : f 0 1 : f

is selected

1 0 : f 1 1 : fc is selected

Function

(During UART mode)

b2 b1 b0

1 0 0 : Transfer data 7 bits long

1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long 0 0 0 : Serial I/O invalid 0 1 0 : Inhibited 0 1 1 : Inhibited 1 1 1 : Inhibited

0 : Internal clock 1 : External clock

0 : One stop bit 1 : Two stop bits

Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity

0 : Parity disabled 1 : Parity enabled

0 : Sleep mode deselected 1 : Sleep mode selected

Function

(During UART mode)

b1 b0

is selected

0 0 : f 0 1 : f

is selected

1 0 : f

1 1 : fc is selected

TXEPT

Transmit register empty flag

Set this bit to “1”.

NCH

Data output select bit

CKPOL

CLK polarity select bit

UFORM Transfer format select bit

Note: UART1 cannot be used in clock synchronous serial I/O.

Figure 1.72. Serial I/O-related registers (2)

0 : Data present in transmit

1 : No data present in transmit

0 : TXDi pin is CMOS output 1 : TXDi pin is N-channel

open-drain output

0 : Transmit data is output at

falling edge of transfer clock and receive data is input at rising edge

1 : Transmit data is output at

rising edge of transfer clock and receive data is input at falling edge

0 : LSB first 1 : MSB first

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

0: TXDi pin is CMOS output 1: TXDi pin is N-channel

open-drain output

Must always be “0”

Under

development

Serial I/O

UARTi transmit/receive control register 1

b7 b6 b5 b4 b3 b2 b1 b0

UiC1(i=0,1) 03A5

Symbol Address When reset

03AD

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Bit

symbol

Bit name

Transmit enable bit

Transmit buffer empty flag

Receive enable bit (Note 2)

Receive complete flag

Nothing is assigned. When write, set "0". When read, the value of these bits is “0”.

Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: If you are using clock asynchronous serial I/O mode, you can enable 'receive enable bit' when RxD port input is “H”. If RxD port input is “L” and you have enabled 'receive enable bit' , then receive operation starts immediately.

UART transmit/receive control register 2

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

UCON 03B0

Bit

symbol

U0IRS

UART0 transmit

name

interrupt cause select bit

U1IRS

UART1 transmit interrupt cause select bit

U0RRM

UART0 continuous receive mode enable bit

Set this bit to “0”.

Bit

Function (Note 1)

(During clock synchronous

serial I/O mode)

0 : Transmission disabled 1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled 1 : Reception enabled

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

XX000000

Function

(During clock synchronous

serial I/O mode)

0 :

Transmit buffer empty

(Tl = 1)

1 : Transmission completed

(TXEPT = 1)

Set this bit to “0”.

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enable

Function

(During UART mode)

0 : Transmission disabled 1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled 1 : Reception enabled

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

Function

(During UART mode)

0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed

(TXEPT = 1)

0 : Transmit buffer empty (Tl = 1) 1 : Transmission completed

(TXEPT = 1)

Invalid

CLKMD0

CLKMD1

CLK/CLKS select bit 0

CLK/CLKS select bit 1 (Note 2)

Nothing is assigned. When write, set "0". When read, its content is indeterminate.

Note 1: UART1 cannot be used in clock synchronous serial I/O. Note 2: When using multiple pins to output the transfer clock, the following requirements must be met:

• UART0 internal/external clock select bit (bit 3 at address 03A0

Figure 1.73. Serial I/O-related registers (3)

Valid when bit 5 = “1” 0 : Clock output to CLK1 1 : Clock output to CLKS1

0 : Normal mode

(CLK output is CLK0 only)

1 : Transfer clock output

from multiple pins function selected

Invalid

Must always be “0”

) = “0”.

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Clock synchronous serial I/O mode

(1) Clock synchronous serial I/O mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. (See Table

1.26.) Figure 1.65 shows the UART0 transmit/receive mode register.

Table 1.26. Specifications of clock synchronous serial I/O mode

Item Transfer data format Transfer clock

Transmission start condition

Reception start conditio

Interrupt request generation timing

Error detection

Select function

• Transfer data length: 8 bits

• When internal clock is selected (bit 3 at address 03A016 = “0”) : fi/ 2(n+1) (Note 1) fi = f1, f8, f32, fc

• When external clock is selected (bit 3 at address 03A016 = “1”) : Input from CLK0 pin

• To start transmission, the following requirements must be met:

Transmit enable bit (bit 0 at address 03A516) = “1”

Transmit buffer empty flag (bit 1 at addresses 03A516) = “0”

• Furthermore, if external clock is selected, the following requirements must also be met:

CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”

CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”

• To start reception, the following requirements must be met:

Receive enable bit (bit 2 at address 03A516) = “1”

Transmit enable bit (bit 0 at address 03A516) = “1”

Transmit buffer empty flag (bit 1 at address 03A516) = “0”

• Furthermore, if external clock is selected, the following requirements must also be met:

CLK0 polarity select bit (bit 6 at address 03A416) = “0”: CLK0 input level = “H”

CLK0 polarity select bit (bit 6 at address 03A416) = “1”: CLK0 input level = “L”

• When transmitting

Transmit interrupt cause select bit (bit 0 at address 03B016) = “0”: Interrupts re-

quested when data transfer from UART0 transfer buffer register to UART0 transmit register is completed

Transmit interrupt cause select bit (bit 0 at address 03B016) = “1”: Interrupts re-

quested when data transmission from UART0 transfer register is completed

• When receiving

Interrupts requested when data transfer from UART0 receive register to UART0

receive buffer register is completed

• Overrun error (Note 2) This error occurs when the next data is ready before contents of UART0receive buffer register are read out

• CLK polarity selection Whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected

• LSB first/MSB first selection Whether transmission/reception begins with bit 0 or bit 7 can be selected

• Continuous receive mode selection Reception is enabled simultaneously by a read from the receive buffer register

• Transfer clock output from multiple pins selection UART0 transfer clock can be chosen by software to be output from one of the two pins set

Specification

Note 1: “n” denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: If an overrun error occurs, the UART0 receive buffer will have the next data written in. Note also that the

UART0 receive interrupt request bit is not set to “1”.

Under

development

Clock synchronous serial I/O mode

UART0 transmit/receive mode registers

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b7 b6 b5 b4 b3 b2 b1 b0

010

Symbol Address When reset

U0MR 03A0

Bit name FunctionBit symbol WR

SMD0 SMD1 SMD2

CKDIR

STPS

PRY

PRYE

SLEP

Serial I/O mode select bit

Internal/external clock select bit

Invalid in clock synchronous serial I/O mode

0 (Must always be “0” in clock synchronous serial I/O mode)

b2 b1 b0

0 0 1 : Clock synchronous serial

I/O mode

0 : Internal clock 1 : External clock

Figure 1.74. UART0 transmit/receive mode register in clock synchronous serial I/O mode

Table 1.27 lists the functions of the input/output pins during clock synchronous serial I/O mode. Note that for a period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs a “H”. (If the N-channel open-drain is selected, this pin is in floating state.)

Table 1.27. Input/output pin functions in clock synchronous serial I/O mode

Pin name Function Method of selection

TxD0 (P5

RxD0 (P5

CLK0 (P5

)

Serial data output

Serial data input

Transfer clock output Transfer clock input

Port P5

direction register (bit 0 at address 03EB16)= “1”

(Outputs dummy data when performing reception only) Port P51 direction register (bit 1 at address 03EB16)= “0”

(Can be used as an input port when performing transmission only) Internal/external clock select bit (bit 3 at address 03A0

Internal/external clock select bit (bit 3 at address 03A0

Port P5

direction register (bit 2 at address 03EB16) = “0”

) = “0”

) = “1”

Under

development

Clock synchronous serial I/O mode

• Example of transmit timing (when internal clock is selected)

Transfer clock

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Transmit enable bit (TE)

Transmit buffer empty flag (Tl)

“1” “0”

Data is set in UART0 transmit buffer register

Transferred from UART0 transmit buffer register to UART0

CLK

transmit register

CLK0

TxD0

Transmit register empty flag (TXEPT)

Transmit interrupt request bit (IR)

D0D1D2D3D4D5D

“1” “0”

D0D1D2D3D4D5D

Cleared to “0” when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings:

• Internal clock is selected.

Tc = TCLK = 2(n + 1) / fi

• CLK polarity select bit = “0”.

• Transmit interrupt cause select bit = “0”.

• Example of receive timing (when external clock is selected)

Receive enable bit (RE)

Transmit enable bit (TE)

Transmit buffer empty flag (Tl)

CLK0

RxD0

Receive complete flag (Rl)

Receive interrupt request bit (IR)

Shown in ( ) are bit symbols.

“1” “0”

Transferred from UART0 receive register

“1” “0”

Dummy data is set in UART0 transmit buffer register

Transferred from UART0 transmit buffer register to UART0 transmit register

to UART0 receive buffer register

Cleared to “0” when interrupt request is accepted, or cleared by software

1 / fEXT

Receive data is taken in

Read out from UART0 receive buffer register

Stopped pulsing because transfer enable bit = “0”

D0D1D2D3D4D5D

fi: frequency of BRG0 count source (f n: value set to BRG0

, f8, f32, fc)

The above timing applies to the following settings:

• External clock is selected.

• CLK polarity select bit = “0”.

Meet the following conditions are met when the CLK input before data reception = “H”

• Transmit enable bit “1”

• Receive enable bit “1”

• Dummy data write to UART0 transmit buffer register

EXT

: frequency of external clock

Figure 1.75. Typical transmit/receive timings in clock synchronous serial I/O mode

Under

development

Clock synchronous serial I/O mode

(a) Polarity select function

As shown in Figure 1.76, the CLK polarity select bit (bit 6 at addresses 03A416) allows selection of the polarity of the transfer clock.

• When CLK polarity select bit = “0”

CLK

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TXD

RXD

D1D2D3D4D

D2D3D

D5D

D6D

Note 1: The CLK0 pin level when not

transferring data is “H”.

• When CLK polarity select bit = “1”

CLK

Note 2: The CLK0 pin level when not

TXD

RXD

D1D2D3D4D

D2D3D

D5D

D6D

Figure 1.76. Polarity of transfer clock

(b) LSB first/MSB first select function

As shown in Figure 1.77, when the transfer format select bit (bit 7 at addresses 03A416) = “0”, the transfer format is “LSB first”; when the bit = “1”, the transfer format is “MSB first”.

transferring data is “L”.

• When transfer format select bit = “0”

CLK

TXD

RXD

• When transfer format select bit = “1”

CLK

TXD

RXD

Figure 1.77. Transfer format

LSB first

MSB first

Note: This applies when the CLK polarity select bit = “0”.

Under

development

Clock synchronous serial I/O mode

This function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B016). (See Figure 1.78.) The multiple pins function is valid only when the internal clock is selected for UART0.

Microcomputer

TXD0 (P50)

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CLKS (P5

CLK

(P52)

)

IN CLK

Note: This applies when the internal clock is selected and transmission

is performed only in clock synchronous serial I/O mode.

Figure 1.78. The transfer clock output from the multiple pins function usage

(d) Continuous receive mode

If the continuous receive mode enable bit (bits 2 and 3 at address 03B016) is set to “1”, the unit is placed in continuous receive mode. In this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again.

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Clock asynchronous serial I/O (UART) mode

(2) Clock asynchronous serial I/O (UART) mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. (See Table 1.28.) Figure 1.79 shows the UARTi transmit/receive mode register.

Table 1.28. Specifications of UART Mode

Item Specification

Transfer data format

Transfer clock

Transmission start condition

Reception start condition

Interrupt request generation timing

Error detection

Select function

• Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

• Start bit: 1 bit

• Parity bit: Odd, even, or nothing as selected

• Stop bit: 1 bit or 2 bits as selected

• When internal clock is selected (bit 3 at addresses 03A016, 03A816 = “0”) : fi/16(n+1) (Note 1) fi = f1, f8, f32, fC

• When external clock is selected (bit 3 at addresses 03A016=“1”) : fEXT/16(n+1) (Note 1) (Note 2)

• To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 03A516, 03AD16) = “1”

- Transmit buffer empty flag (bit 1 at addresses 03A516, 03AD16) = “0”

• To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 03A516, 03AD16) = “1”

- Start bit detection

• When transmitting

- Transmit interrupt cause select bits (bits 0,1 at address 03B016) = “0”: Interrupts requested when data transfer from UARTi transfer buffer register to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0, 1 at address 03B016) = “1”: Interrupts requested when data transmission from UARTi transfer register is completed

• When receiving

- Interrupts requested when data transfer from UARTi receive register to UARTi receive buffer register is completed

• Overrun error (Note 3) This error occurs when the next data is ready before contents of UARTi receive buffer register are read out

• Framing error This error occurs when the number of stop bits set is not detected

• Parity error This error occurs when if parity is enabled, the number of 1’s in parity and character bits does not match the number of 1’s set

• Error sum flag This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered

• Sleep mode selection This mode is used to transfer data to and from one of multiple slave microcomputers

Note 1: ‘n’ denotes the value 0016 to FF16 that is set to the UART bit rate generator. Note 2: fEXT is input from the CLK0 pin. Since UART1 does not have this pin, cannot select external clock. Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit is not set to “1”.

Under

development

Clock asynchronous serial I/O (UART) mode

UARTi transmit / receive mode registers

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset

UiMR(i=0,1) 03A0

, 03A8

Bit name FunctionBit symbol

SMD0 SMD1 SMD2

CKDIR

STPS

PRY

PRYE

SLEP

Note: UART1 can use only internal clock. Must set this bit to “1”.

Serial I/O mode select bit

Internal / external clock select bit (Note)

Stop bit length select bit

Odd / even parity select bit

Parity enable bit

Sleep select bit

b2 b1 b0

1 0 0 : Transfer data 7 bits long 1 0 1 : Transfer data 8 bits long 1 1 0 : Transfer data 9 bits long

0 : Internal clock 1 : External clock

0 : One stop bit 1 : Two stop bits

Valid when bit 6 = “1” 0 : Odd parity 1 : Even parity

0 : Parity disabled 1 : Parity enabled

0 : Sleep mode deselected 1 : Sleep mode selected

Figure 1.79. UARTi transmit/receive mode register in UART mode

Table 1.29 lists the functions of the input/output pins during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs a “H”. (If the Nchannel open-drain is selected, this pin is in floating state.)

Table 1.29. Input/output pin functions in UART mode

Pin name Function Method of selection

TxDi (P5

RxDi

1, P42)

(P5

CLK0 (P52)

0, P40)

Serial data output

Serial data input

Programmable I/O port Transfer clock input

Port P5

1 and P42 direction register (bit 0 at address 03EB16, bit 0 at

address 03EA16)= “1”

(Can be used as an input port when performing reception only)

Port P51 and P42 direction register (bit 1 at address 03EB16, bit 2 at address 03EA16)= “0” (Can be used as an input port when performing transmission only)

Internal/external clock select bit (bit 3 at address 03A0

16) = “0”

16) = “1”

Under

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock asynchronous serial I/O (UART) mode

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

Transfer clock

Transmit enable bit(TE)

Transmit buffer empty flag(TI)

“1” “0”

Data is set in UARTi transmit buffer register.

Transferred from UARTi transmit buffer register to UARTi transmit register

Mitsubishi microcomputers

M30201 Group

TxDi Transmit register

empty flag (TXEPT)

Transmit interrupt request bit (IR)

Start

bit

“1” “0”

Parity

Stop

bit

Stopped pulsing because transmit enable bit = “0”

D7SP

Cleared to “0” when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings :

• Parity is enabled.

• One stop bit.

• Transmit interrupt cause select bit = “1”.

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

fi : frequency of BRGi count source (f1, f8, f32, fc) f

EXT : frequency of BRGi count source (external clock)

n : value set to BRGi

EXT

• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Transfer clock

Transmit enable bit(TE)

Transmit buffer empty flag(TI)

TxDi

“1” “0” “1”

“0”

Data is set in UARTi transmit buffer register

Transferred from UARTi transmit buffer register to UARTi transmit register

Start

bit

Stop

bit

SPSP

Transmit register empty flag (TXEPT)

Transmit interrupt request bit (IR)

“1” “0” “1”

“0”

Cleared to “0” when interrupt request is accepted, or cleared by software

Shown in ( ) are bit symbols.

The above timing applies to the following settings :

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

• Parity is disabled.

• Two stop bits.

• Transmit interrupt cause select bit = “0”.

Figure 1.80. Typical transmit timings in UART mode

fi : frequency of BRGi count source (f1, f8, f32)

EXT

EXT : frequency of BRGi count source (external clock)

f n : value set to BRGi

Under

development

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Clock asynchronous serial I/O (UART) mode

• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

BRGi count source

Receive enable bit

RxDi

Transfer clock

Receive complete flag

“1” “0”

Start bit

Sampled “L”

Reception triggered when transfer clock is generated by falling edge of start bit

“1” “0”

Receive data taken in

Transferred from UARTi receive register to UARTi receive buffer register

Mitsubishi microcomputers

M30201 Group

Stop bit

Receive interrupt request bit

“1” “0”

Cleared to “0” when interrupt request is accepted, or cleared by software

The above timing applies to the following settings :

•Parity is disabled.

•One stop bit.

Figure 1.81. Typical receive timing in UART mode

(a) Sleep mode

This mode is used to transfer data between specific microcomputers among multiple microcomputers connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses 03A016, 03A816) is set to “1” during reception. In this mode, the unit performs receive operation when the MSB of the received data = “1” and does not perform receive operation when the MSB = “0”.

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

A-D Converter

The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling amplifier. Pins P60 to P67, and P50 to P54 also function as the analog signal input pins. The direction registers of these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D716) can be used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (VREF) when the A-D converter is not used. Doing so stops any current flowing into the resistance ladder from VREF, reducing the power dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D716 to connect VREF. The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low 8 bits are stored in the even addresses. Table 1.30 shows the performance of the A-D converter. Figure 1.82 shows the block diagram of the A-D converter, and Figures 1.83 and 1.84 show the A-D converter-related registers.

Table 1.30. Performance of A-D converter

Item Performance Method of A-D conversion Successive approximation (capacitive coupling amplifier) Analog input voltage (Note 1) Operating clock φAD (Note 2)

Resolution 8-bit or 10-bit (selectable) Absolute precision VCC = 5V • Without sample and hold function

Operating modes One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

Analog input pins 8 pins (AN0 to AN7) + 5 pins (AN50 to AN54) A-D conversion start condition

Conversion speed per pin • Without sample and hold function

Note 1: Does not depend on use of sample and hold function. Note 2: Without sample and hold function, set the

With the sample and hold function, set the

0V to AVCC (VCC) VCC = 5V fAD, divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN) VCC = 3V divide-by-2 of fAD, divide-by-4 of fAD, fAD=f(XIN)

±3LSB

• With sample and hold function (8-bit resolution) ±2LSB

• With sample and hold function (10-bit resolution) ±3LSB

VCC = 3V • Without sample and hold function (8-bit resolution)

±2LSB

and repeat sweep mode 1

• Software trigger A-D conversion starts when the A-D conversion start flag changes to “1”

8-bit resolution: 49

AD cycles

10-bit resolution: 59

AD cycles

• With sample and hold function 8-bit resolution: 28

AD cycles

AD frequency to 250kHz min.

AD frequency to 1MHz min.

10-bit resolution: 33

AD cycles

Under

development

A-D Converter

fAD

1/2

CKS0=1

CKS0=0

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CKS1=1

φAD

CKS1=0

A-D conversion rate selection

VREF

AVSS

Addresses

(03C116, 03C016)

(03C3 (03C5 (03C7

(03C9

(03CB (03CD (03CF

VCUT=0

VCUT=1

16, 03C216) 16, 03C416) 16, 03C616)

16, 03C816)

16, 03CA16)

16, 03CC16)

16, 03CE16)

Resistor ladder

Successive conversion register

A-D control register 1 (address 03D7

A-D control register 0 (address 03D616)

A-D register 0(16) A-D register 1(16)

A-D register 2(16) A-D register 3(16)

A-D register 4(16)

A-D register 5(16)

A-D register 6(16)

A-D register 7(16)

Data bus high-order

16)

Decoder

VIN

ref

Comparator

Data bus low-order

Port P6 group

P60/AN0 P61/AN1 P62/AN2

P63/AN3 P64/AN4 P65/AN5

P66/AN6 P67/AN7

CH2,CH1,CH0=000 CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011 CH2,CH1,CH0=100 CH2,CH1,CH0=101 CH2,CH1,CH0=110 CH2,CH1,CH0=111

Port P5 group

P50/AN50 P51/AN51 P52/AN52 P53/AN53 P54/AN54

CH2,CH1,CH0=000

CH2,CH1,CH0=001 CH2,CH1,CH0=010 CH2,CH1,CH0=011

CH2,CH1,CH0=100

Figure 1.82. Block diagram of A-D converter

ADGSEL0=0

ADGSEL0=1

Under

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A-D Converter

A-D control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Symbol Address When reset

ADCON0 03D6

16 00000XXX2

Bit symbol Bit name Function

CH0

CH1

CH2

MD0

MD1

Set this bit to “0”.

ADST

CKS0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is

indeterminate.

Note 2: AN

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ADCON1 03D7

Analog input pin select bit

A-D operation mode select bit 0

b2 b1 b0

0 0 0 : AN 0 0 1 : AN 0 1 0 : AN 0 1 1 : AN 1 0 0 : AN 1 0 1 : AN 1 1 0 : AN 1 1 1 : AN

b4 b3

0 0 : One-shot mode 0 1 : Repeat mode

0 is selected 1 is selected 2 is selected 3 is selected 4 is selected 5 is selected 6 is selected 7 is selected (Note 2)

1 0 : Single sweep mode 1 1 : Repeat sweep mode 0

Repeat sweep mode 1

A-D conversion start flag 0 : A-D conversion disabled

1 : A-D conversion started

Frequency select bit 0 0 : fAD/4 is selected

1 : f

AD/2 is selected

50 to AN54 can be used in the same way as for AN0 to AN4.

16 0016

Bit name FunctionBit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

CKS1

VCUT

A-D operation mode select bit 1

8/10-bit mode select bit 0 : 8-bit mode

Frequency select bit 1 0 : f

Vref connect bit

Set this bit to “0”.

ADGSEL0

A-D input group select bit

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is

indeterminate.

Note 2: AN

50 to AN54 can be used in the same way as for AN0 to AN4.

Note 3: If the repeat sweep mode is selected for the port P5 group, the contents of A-D

registers 5 to 7 are indeterminate.

When single sweep and repeat sweep mode 0 are selected

b1 b0

0 0 : AN

0, AN1 (2 pins)

0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins)

When repeat sweep mode 1 is selected

b1 b0

0 0 : AN

0 (1 pin)

0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins)

0 : Any mode other than repeat sweep

mode 1

1 : Repeat sweep mode 1

(Note 2, 3)

1 : 10-bit mode

AD/2 or fAD/4 is selected

1 : f

AD is selected

0 : Vref not connected 1 : Vref connected

0 : Port P6 group is selected 1 : Port P5 group is selected

Figure 1.83. A-D converter-related registers (1)

Under

development

A-D Converter

A-D control register 2 (Note)

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

b7 b6 b5 b4 b3 b2 b1 b0

000

A-D register i

(b15)

Symbol Address When reset

ADCON2 03D416 XXXX00002

Bit symbol Bit name Function R W

SMP

Reserved bit Always set to “0”

Nothing is assigned. When write, set "0". When read, their content is indeterminate.

Note: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

A-D conversion method select bit

0 : Without sample and hold 1 : With sample and hold

Symbol Address When reset

(b8)

ADi(i=0 to 7) 03C016 to 03CF16 Indeterminate

b7b7 b0 b0

Function R W

Eight low-order bits of A-D conversion result

• During 10-bit mode Two high-order bits of A-D conversion result

• During 8-bit mode When read, the content is indeterminate

Nothing is assigned. When write, set "0". When read, their content is indeterminate.

Figure 1.84. A-D converter-related registers (2)

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

A-D Converter

(1) One-shot mode

In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conversion. (See Table 1.31.) Figure 1.85 shows the A-D control register in one-shot mode.

Table 1.31. One-shot mode specifications

Item Specification Function Start condition Writing “1” to A-D conversion start flag Stop condition

Interrupt request generation timing Input pin One of AN0 to AN7, as selected (Note) Reading of result of A-D converter

Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

A-D control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

The pin selected by the analog input pin select bit is used for one A-D conversion

•

End of A-D conversion (A-D conversion start flag changes to “0”)

• Writing “0” to A-D conversion start flag End of A-D conversion

Read A-D register corresponding to selected pin

Symbol Address When reset ADCON0 03D6

16 00000XXX2

Bit symbol Bit name Function

CH0

CH1

CH2

MD0 MD1

Set this bit to “0”.

ADST

CKS0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN

to AN54 can be used in the same way as for AN0 to AN4.

A-D control register 1 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ADCON1 03D7

SCAN0 SCAN1

MD2

BITS

CKS1

VCUT

b2 b1 b0

Analog input pin select bit

A-D operation mode select bit 0

A-D conversion start flag 0 : A-D conversion disabled

Frequency select bit 0 0 : fAD/4 is selected

0 0 0 : AN 0 0 1 : AN 0 1 0 : AN 0 1 1 : AN 1 0 0 : AN 1 0 1 : AN 1 1 0 : AN 1 1 1 : AN

b4 b3

0 0 : One-shot mode

1 : A-D conversion started

1 : f

16 0016

is selected

is selected (Note 2)

/2 is selected

Bit name FunctionBit symbol

A-D sweep pin select bit

A-D operation mode select bit 1

8/10-bit mode select bit 0 : 8-bit mode

Frequency select bit 1 0 : f

Vref connect bit

Invalid in one-shot mode

Set this bit to “0” in this mode.

1 : 10-bit mode

/2 or fAD/4 is selected

1 : f

is selected

1 : Vref connected

Set this bit to “0”.

ADGSEL0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D input group select bit

Figure 1.85. A-D conversion register in one-shot mode

0 : Port P6 group is selected 1 : Port P5 group is selected

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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A-D Converter

(2) Repeat mode

In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion. (See Table 1.32.) Figure 1.86 shows the A-D control register in repeat mode.

Table 1.32. Repeat mode specifications

Item Specification Function Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timing Input pin One of AN0 to AN7, as selected (Note) Reading of result of A-D converter

Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

A-D control register 0 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

The pin selected by the analog input pin select bit is used for repeated A-D conversion

None generated

Read A-D register corresponding to selected pin

Symbol Address When reset ADCON0 03D6

00000XXX

Bit symbol Bit name Function

CH0

CH1

CH2

MD0 MD1

Set this bit to “0”.

ADST

CKS0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN

to AN54 can be used in the same way as for AN0 to AN4.

A-D control register 1 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ADCON1 03D7

SCAN0 SCAN1

MD2

BITS

CKS1

VCUT

b2 b1 b0

Analog input pin select bit

A-D operation mode select bit 0

A-D conversion start flag 0 : A-D conversion disabled

Frequency select bit 0 0 : fAD/4 is selected

0 0 0 : AN 0 0 1 : AN 0 1 0 : AN 0 1 1 : AN 1 0 0 : AN 1 0 1 : AN 1 1 0 : AN 1 1 1 : AN

b4 b3

0 1 : Repeat mode

1 : A-D conversion started

1 : f

is selected

is selected (Note 2)

/2 is selected

Bit name FunctionBit symbol

A-D sweep pin select bit

A-D operation mode select bit 1

8/10-bit mode select bit 0 : 8-bit mode

Frequency select bit 1 0 : f

Vref connect bit

Invalid in repeat mode

Set this bit to “0” in this mode.

1 : 10-bit mode

/2 or fAD/4 is selected

1 : f

is selected

1 : Vref connected

Set this bit to “0”.

ADGSEL0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D input group select bit

Figure 1.86. A-D conversion register in repeat mode

0 : Port P6 group is selected 1 : Port P5 group is selected

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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A-D Converter

(3) Single sweep mode

In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D conversion. (See Table 1.33.) Figure 1.87 shows the A-D control register in single sweep mode.

Table 1.33. Single sweep mode specifications

Item Specification Function Start condition Writing “1” to A-D converter start flag Stop condition • End of A-D conversion (A-D conversion start flag changes to “0”.)

Interrupt request generation timing Input pin Reading of result of A-D converter

Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion

• Writing “0” to A-D conversion start flag End of A-D conversion AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Read A-D register corresponding to selected pin

Symbol Address When reset ADCON0 03D6

00000XXX

Bit symbol Bit name Function

CH1

CH2

MD0 MD1

Set this bit to “0”.

ADST

CKS0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ADCON1 03D7

SCAN0

SCAN1

MD2

BITS

CKS1

VCUT

Analog input pin select bit

A-D operation mode select bit 0

A-D conversion start flag 0 : A-D conversion disabled

Frequency select bit 0 0 : fAD/4 is selected

Invalid in single sweep modeCH0

b4 b3

1 0 : Single sweep mode

1 : A-D conversion started

1 : f

/2 is selected

Bit name FunctionBit symbol

A-D sweep pin select bit

A-D operation mode select bit 1

8/10-bit mode select bit 0 : 8-bit mode

Frequency select bit 1 0 : f

Vref connect bit

When single sweep and repeat sweep mode 0 are selected

b1 b0

0 0 : AN

, AN1 (2 pins)

0 1 : AN

to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN0 to AN7 (8 pins)

Set this bit to “0” in this mode.

1 : 10-bit mode

/2 or fAD/4 is selected

1 : f

is selected

1 : Vref connected

(Note 2, 3)

Set this bit to “0”.

ADGSEL0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN Note 3: If port P5 group is selected, do not select 6 pins and 8 pins sweep mode.

to AN54 can be used in the same way as for AN0 to AN4.

A-D input group select bit

0 : Port P6 group is selected 1 : Port P5 group is selected

Figure 1.87. A-D conversion register in single sweep mode

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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A-D Converter

(4) Repeat sweep mode 0

In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep A-D conversion. (See Table 1.34.) Figure 1.88 shows the A-D control register in repeat sweep mode 0.

Table 1.34. Repeat sweep mode 0 specifications

Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

The pins selected by the A-D sweep pin select bit are used for repeat sweep A-D conversion

None generated AN0 and AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or AN0 to AN7 (8 pins)(Note) Read A-D register corresponding to selected pin (at any time)

Symbol Address When reset ADCON0 03D6

00000XXX

Bit symbol Bit name Function

CH1

CH2

MD0 MD1

Set this bit to “0”.

ADST

CKS0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ADCON1 03D7

SCAN0

SCAN1

MD2

BITS

CKS1

VCUT

Analog input pin select bit

A-D operation mode select bit 0

A-D conversion start flag 0 : A-D conversion disabled

Frequency select bit 0 0 : fAD/4 is selected

Invalid in repeat sweep mode 0CH0

b4 b3

1 1 : Repeat sweep mode 0

1 : A-D conversion started

1 : f

/2 is selected

Bit name FunctionBit symbol

A-D sweep pin select bit

A-D operation mode select bit 1

8/10-bit mode select bit 0 : 8-bit mode

Frequency select bit 1 0 : f

Vref connect bit

When single sweep and repeat sweep mode 0 are selected

b1 b0

0 0 : AN

, AN1 (2 pins) 0 1 : AN0 to AN3 (4 pins) 1 0 : AN0 to AN5 (6 pins) 1 1 : AN

to AN7 (8 pins)

Set this bit to “0” in this mode.

1 : 10-bit mode

/2 or fAD/4 is selected

1 : f

is selected

1 : Vref connected

(Note 2, 3)

Set this bit to “0”.

ADGSEL0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate. Note 2: AN Note 3: If port P5 group is selected, the contents of A-D registers 5 to 7 are indeterminate.

to AN54 can be used in the same way as for AN0 to AN4.

A-D input group select bit

Figure 1.88. A-D conversion register in repeat sweep mode 0

0 : Port P6 group is selected 1 : Port P5 group is selected

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A-D Converter

(5) Repeat sweep mode 1

In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected using the A-D sweep pin select bit. (See Table 1.35.) Figure 1.89 shows the A-D control register in repeat sweep mode

Table 1.35. Repeat sweep mode 1 specifications

Item Specification

Function All pins perform repeat sweep A-D conversion, with emphasis on the pin or

pins selected by the A-D sweep pin select bit

Example : AN0 selected AN0 AN1 AN0 AN2 AN0 AN3, etc Start condition Writing “1” to A-D conversion start flag Stop condition Writing “0” to A-D conversion start flag Interrupt request generation timing Input pin Reading of result of A-D converter

Note : AN50 to AN54 can be used in the same way as for AN0 to AN4.

A-D control register 0 (Note)

b7 b6 b5 b4 b3 b2 b1 b0

None generated

AN0 (1 pin), AN0 and AN1 (2 pins), AN0 to AN2 (3 pins), AN0 to AN3 (4 pins) (Note)

Read A-D register corresponding to selected pin (at any time)

Symbol Address When reset ADCON0 03D6

00000XXX

Bit symbol Bit name Function

CH1

CH2 MD0

MD1

Set this bit to “0”.

ADST

CKS0

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is indeterminate.

A-D control register 1 (Note 1)

b7 b6 b5 b4 b3 b2 b1 b0

Symbol Address When reset ADCON1 03D7

SCAN0

SCAN1

MD2

BITS

CKS1

VCUT

Analog input pin select bit

A-D operation mode select bit 0

A-D conversion start flag 0 : A-D conversion disabled

Frequency select bit 0 0 : fAD/4 is selected

Bit name FunctionBit symbol

A-D sweep pin select bit

A-D operation mode select bit 1

8/10-bit mode select bit 0 : 8-bit mode

Frequency select bit 1 0 : f

Vref connect bit

Invalid in repeat sweep mode 1CH0

b4 b3

1 1 : Repeat sweep mode 1

1 : A-D conversion started

/2 is selected

1 : f

When single sweep and repeat sweep mode 1 are selected

b1 b0

0 0 : AN

(1 pins) 0 1 : AN0, AN1 (2 pins) 1 0 : AN0 to AN2 (3 pins) 1 1 : AN0 to AN3 (4 pins)

Set “1” in this mode.

1 : 10-bit mode

/2 or fAD/4 is selected

is selected

1 : f 1 : Vref connected

(Note 2, 3)

Set this bit to “0”.

ADGSEL0

to AN54 can be used in the same way as for AN0 to AN4.

A-D input group select bit

0 : Port P6 group is selected 1 : Port P5 group is selected

Figure 1.89. A-D conversion register in repeat sweep mode 1

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

M30201 Group

A-D Converter

• Sample and hold

Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D416) to “1”. When sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28 φAD cycle is achieved with 8-bit resolution and 33 φAD with 10-bit resolution. Sample and hold can be selected in all modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and hold is to be used.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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Programmable I/O Port

Programmable I/O Ports

There are 43 programmable I/O ports: P0 to P7. Each port can be set independently for input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. The port P1 allows the drive capacity of its N-channel output transistor to be set as necessary. Figures 1.90 to 1.92 show the programmable I/O ports. Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices. To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. When the pins are used as the outputs for the built-in peripheral devices, they function as outputs regardless of the contents of the direction registers. See the descriptions of the respective functions for how to set up the built-in peripheral devices.

(1) Direction registers

Figure 1.93 shows the direction registers. These registers are used to choose the direction of the programmable I/O ports. Each bit in these registers corresponds one for one to each I/O pin.

(2) Port registers

Figure 1.94 shows the port registers. These registers are used to write and read data for input and output to and from an external device. A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit in port registers corresponds one for one to each I/O pin.

(3) Pull-up control registers

Figure 1.95 shows the pull-up control registers. The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input.

(4) Port P1 drive capacity control register

Figure 1.95 shows a structure of the port P1 drive capacity control register. This register is used to control the drive capacity of the port P1's N-channel output transistor. Each bit in this register corresponds one for one to the port pins.

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Programmable I/O Port

Mitsubishi microcomputers

M30201 Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pull-up selection

P30 to P3

P00 to P07, P42, P7

Direction register

Data bus

Input to respective peripheral functions

Port latch

Pull-up selection

Direction register

Port latch

P41, P7

P40, P43, P4

Pull-up selection

Direction register

Data bus

Port latch

Direction register

Port latch

Input to respective peripheral functions

output

Pull-up selection

output

Figure 1.90. Programmable I/O ports (1)

100

MITSUBISHI M30201 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual