MITEL VP5311GP1N, VP5311CG, VP5311B Datasheet

The VP5311/VP5511 converts digital Y, Cr, Cb, data
into analog NTSC/PAL composite video and S-video signals.
The outputs are capable of driving doubly terminated 75
ohm loads with standard video levels.

The device accepts data inputs complying with CCIR
Recommendation 601 and 656. The data is time multiplexed
on an 8 bit bus at 27MHz and is formatted as Y, Cr, Y, Cb
(i.e. 4:2:2). The video blanking and sync information from
REC 656 is included in the data stream when the VP5311/
VP5511 is working in slave mode.

The output pixel rate is 27MHz and the input pixel rate
is half this frequency, i.e. 13.5MHz.

All necessary synchronisation signals are generated
internally when the device is operating in master mode. In
slave mode the device will lock to the TRS codes or the HS
and VS inputs.

The rise and fall times of sync, burst envelope and
video blanking are internally controlled to be within
composite video specifications.

Three digital to analog converters (DACs) are used to
convert the digital luminance, chrominance and composite
data into true analog signals. An internally generated
reference voltage provides the biasing for the DACs.

PIN FUNCTION PIN FUNCTION
1 VDD 33 VDD
2 GND 34 RESET
3 D0 (VS I/O) 35 REFSQ
4 D1 (HS I/O) 36 GND
5 D2 (FC0 O/P) 37 VDD
6 D3 (FC1 O/P) 38 GND
7 D4 (FC2 O/P) 39 PD7
8 D5 40 PD6
9 D6 (SCSYNC I/P) 41 PD5
10 D7 (PALID I/P) 42 PD4
11 GND 43 PD3
12 VDD 44 PD2
13 GND 45 PD1
14 GND 46 PD0
15 PXCK 47 GND
16 VDD 48 VDD
17 CLAMP 49 AGND
18 COMPSYNC 50 VREF
19 GND 51 DACGAIN
20 VDD 52 COMP
21 TDO 53 AVDD
22 TDI 54 LUMAOUT
23 TMS 55 AGND
24 TCK 56 COMPOUT
25 GND 57 AGND
26 SA1 58 CHROMAOUT
27 SA2 59 AVDD
28 SCL 60 N/C
29 VDD 61 N/C
30 SDA 62 AVDD
31 GND 63 AVDD
32 VDD 64 N/C

Figure 1 Pin connections (top view)

GP64

PIN 64

PIN 1

FEATURES

■ Converts Y, Cr, Cb data to analog composite video and

S-video

■ Supports CCIR recommendations 601 and 656

■ All digital video encoding

■ Selectable master/slave mode for sync signals

■ Switchable chrominance bandwidth

■ Switchable pedestal with gain compensation

■ SMPTE 170M NTSC or CCIR 624 PAL compatible

outputs

■ GENLOCK mode

■ Line 21 Closed Caption encoding

■ I2C bus serial microprocessor interface

■ VP5311B supports Macrovision anti-taping format Rev.

6.1, in PAL and Rev. 7.01 in NTSC.

APPLICATIONS

■ Digital Cable TV

■ Digital Satellite TV

■ Multi-media

■ Video games

■ Karaoke

■ Digital VCRs

ORDERING INFORMATION

VP5311B/CG/GP1N
VP5511B/CG/GP1N

VP5311B/VP5511B

NTSC/PAL Digital Video Encoder

Advance Information

Supersedes DS4575 1.5 May 1997 version DS4575 - 2.2 October 1998

VP5311B/VP5511B

2

66.83

1.050
27k

1.3699

24.93

50

33.75

17.64

1.40

7.62

7.62

0.40

34.15

18.71

26.73

8.02

8.02

0.00

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions

DC CHARACTERISTICS

VIN

VIL

VIH

VIL

IIH

IIL

VOH

VOL

VOL

2.0

0.7 VDD

3.7

0.8

0.3 VDD
10

-10

0.4

0.6

V
V

V
V

µA
µA

V
V

V

Parameter Conditions

VIN = VDD
VIN = VSS

IOH = -1mA
IOL = +4mA

IOL = +6mA

Symbol Min.

Typ.

Max.

Units

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions

DC CHARACTERISTICS DACs

INL

DNL

VREF

ZR

IREF

KDAC

±1.5

±1
±5

LSB
LSB

%

µA

V

Ω

mA

pV-s

mA
mA
mA
mA
mA
mA

mA
mA
mA
mA
mA
mA

Parameter

Symbol Min.

Typ.

Max.

Units

Accuracy (each DAC)

Integral linearity error
Diffential linearity error
DAC matching error
Monotonicity

LSB size
Internal reference voltage
Internal reference voltage output impedance
Reference Current (V

REF/RREF) RREF = 769Ω

DAC Gain Factor (VOUT = KDAC x IREF x RL), VOUT = DAC code 511
Peak Glitch Energy (see fig.3)

CVBS, Y and C - NTSC (pedestal enabled)
Maximum output, relative to sync bottom
White level relative to black level
Black level relative to blank level
Blank level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)

CVBS, Y and C - PAL
Maximum output
White level relative to black level
White level relative to sync level
Black level relative to sync level
Colour burst peak - peak
DC offset (bottom sync)

Digital Inputs TTL compatible (except SDA, SCL)

Input high voltage
Input low voltage

Digital Inputs SDA, SCL

Input high voltage
Input low voltage
Input high current
Input low current

Digital Outputs CMOS compatible

Output high voltage
Output low voltage

Digital Output SDA

Output low voltage

guaranteed

Note: All figures are for: RREF = 769Ω RL = 37.5Ω. When the device is set up in NTSC mode there is a +0.25% error in the PAL
levels. If RL = 75Ω then RREF = 1538Ω.

ABSOLUTE MAXIMUM RATINGS

Supply voltage VDD, AVDD -0·3 to 7·0V
Voltage on any non power pin -0·3 to VDD+0·3V
Ambient operating temperature 0 to 70°C
Storage temperature -55°C to 150°C

Note: Stresses exceeding these listed under Absolute
Maximum Ratings may induce failure. Exposure to Absolute
Maximum Ratings for extended periods may reduce
reliability. Functionality at or above these conditions is not
implied.

VP5311B/VP5511B

3

RECOMMENDED OPERATING CONDITIONS

Parameter

Min.

Typ.

Max.

Units

Power supply voltage
Power supply current (including analog outputs)
Input clock frequency
SCL clock frequency
Analog video output load
DAC gain resistor
Ambient operating temperature

Symbol

VDD, AVDD

IDD

PXCK

f

SCL

4.75

-50ppm

0

5.25

+50ppm

500

70

V

mA

MHz

kHz

Ω
Ω

°C

5.00
150

27.00

37.5
769

VIDEO CHARACTERISTICS

Parameter

-61

-56

-58

2.5

2.5

Max.

Symbol Min.

Typ.

5.5

1.3

650

3.57954545

4.43361875

3.58205625
9

10
300
300
145
245

1.5

0.5

-61

-56

-58

-60
10

MHz
MHz

kHz
MHz
MHz
MHz

Fsc cycles
Fsc cycles

ns
ns
ns
ns

% pk-pk

° pk-pk

dB
dB
dB

%
%

dB

ns

Units

ESD COMPLIANCE

Pins

All pins
All pins

Notes

Meets Mil-Std-883 Class 2

Test Levels

2kV on 100pF through 1k5Ω

200V on 200pF through 0Ω & 500nH

Test

Human body model

Machine model

Luminance bandwidth
Chrominance bandwidth (Extended B/w mode)
Chrominance bandwidth (Reduced B/w mode)
Burst frequency (NTSC)
Burst frequency (PAL-B, D,G,H,I)
Burst frequency (PAL-N Argentina)
Burst cycles (NTSC )
Burst cycles (NTSC and PAL-B, D, G, H,I)
Burst envelope rise / fall time (NTSC and PAL-N)
Burst envelope rise / fall time (NTSC and PAL-B, D, G, H,I)
Analog video sync rise / fall time (NTSC and PAL-N)
Analog video blank rise / fall time (NTSC and PAL-B, D, G, H,I)
Differential gain
Differential phase
Signal to noise ratio (unmodulated ramp)
Chroma AM signal to noise ratio (100% red field)
Chroma PM signal to noise ratio (100% red field)
Hue accuracy
Colour saturation accuracy
Residual sub carrier
Luminance / chrominance delay

VP5311B/VP5511B

4

Figure 3 Glitch Energy

Figure 2 Functional block diagram of the VP5311B, the VP5511B is identical except there is no Anti-Taping Control

The glitch energy is calculated by measuring the area under the voltage

time curve for any LSB step, typically specified in picoVolt-seconds (pV-s)

Peak Glitch Area = H x W/2

V

t(ps)

W

H

I2C INTERFAC E

SET-UP

REGISTERS

ANTI-TAPING

CONTROL

VIDEO TIMI NG GENERATOR

COLOUR SU BCARRI ER

GENERATOR

MODU LATOR

CHROMA

LOW-PASS

FILTER

INPUT
DEMUX

8

8

PD7-0

D7-0

PXCK

SDA
SCL

SA1
SA2

Y

Cr

Cb

SYNC
BLANK
INSERT

LUMA OU T

COMP

CHROMA OUT

INTERPOLATOR

INTERPOLATOR

JTAG .

GENERAL

PURPOSE PORT

&
CHROMA

INTERP

RESET

CLAMP

CHROMA

DAC

COMP

DAC

OUT

TDI

TMS TCK

TDO

+

DAC
REF

VREF

+

REFSQ

DIGITAL
PHASE COMP

CLOSED

CAPTION

+

DACGAIN

COMP

COMPSYNC

LUMA

DAC

VP5311B/VP5511B

5

Pin Name Pin No. Description

PD0-7 39 - 46 8 Bit Pixel Data inputs clocked by PXCK. PD0 is the least significant bit, corresponding to Pin

46. These pins are internally pulled low.

D0-7 3 - 10 8 Bit General Purpose Port input/output. D0 is the least significant bit, corresponding to Pin 3.

These pins are internally pulled low.

PXCK 15 27MHz Pixel Clock input. The VP5311 internally divides PXCK by two to provide the pixel

clock.

CLAMP 17 The CLAMP output signal is synchronised to COMPSYNC output and indicates the position of

the BURST pulse, (lines 10-263 and 273-525 for NTSC; lines 6-310 and 319-623 for PAL­B,D, G,I,N(Argentina)).

COMPSYNC 18 Composite sync pulse output. This is an active low output signal.

TDO 21 JTAG Data scan output port.

TDI 22 JTAG Data scan input port.

TMS 23 JTAG Scan select input.

TCK 24 JTAG Scan clock input.

SA1 26 Slave address select.

SA2 27 Slave address select.

SCL 28 Standard I

2

C bus serial clock input.

SDA 30 Standard I

2

C bus serial data input/output.

RESET 34 Master reset. This is an asynchronous, active low, input signal and must be asserted for a

minimum 200ns in order to reset the VP5311.

REFSQ 35 Reference square wave input used only during Genlock mode.

VREF 50 Voltage reference output. This output is nominally 1·055V and should be decoupled with a

100nF capacitor to GND.

DAC GAIN 51 DAC full scale current control. A resistor connected between this pin and GND sets the

magnitude of the video output current. An internal loop amplifier controls a reference current
flowing through this resistor so that the voltage across it is equal to the Vref voltage.

COMP 52 DAC compensation. A 100nF ceramic capacitor must be connected between pin 52 and pin

53.

LUMAOUT 54 True luminance, composite and chrominance video signal outputs. These are high

COMPOUT 56 impedance current source outputs. A DC path to GND must exist from each of these pins.

CHROMAOUT 58

NOT USED 60, 61, 64

VDD 1, 12, 16, Positive supply input. All VDD pins must be connected.

20, 29,

32, 33,

37, 48

AVDD 53, 59 Analog positive supply input. All AVDD pins must be connected.

62, 63

GND 2, 11, 13, Negative supply input. All GND pins must be connected.

14, 19,

25, 31,

36, 38, 47

AGND 49, 55, 57 Negative supply input. All AGND pins must be connected.

PIN DESCRIPTIONS

All other pins are N/C and should not be connected.

VP5311B/VP5511B

6

5

RA5

ID15
ID0D
ID05

REV5

YCDELAY

CHRBW

DFI2

AN5

SC5
FR15
FR0D
FR05

-

SCH5

CTL5

RD5
WR5

F1W1D5
F1W2D5
F2W1D5
F2W2D5

-

HSOFF5

-

VSMODE

HCNT5

REGISTER
REGISTER

GENLKEN

7

RA7

ID17
ID0F
ID07

REV7

-

-

­AN7
SC7

FR17
FR0F
FR07

-

SCH7

CTL7

RD7

WR7

-

-

-

-

-

HSOFF7

-

NCORSTD

HCNT7

FSC4SEL

6

RA6
ID16

ID0E

ID06

REV6

-

CLAMPDIS

­AN6
SC6

FR16
FR0E
FR06

-

SCH6

CTL6

RD6

WR6

F1W1D6
F1W2D6
F2W1D6
F2W2D6

-

HSOFF6

-

VBITDIS

HCNT6

GENDITH

4

RA4

ID14
ID0C
ID04

REV4

RAMPEN

SYNCDIS

DFI1

AN4

SC4
FR14
FR0C
FR04

-

SCH4

CTL4

RD4

WR4

F1W1D4
F1W2D4
F2W1D4
F2W2D4

-

HSOFF4

-

F_SWAP

HCNT4

RESERVED
RESERVED

NOLOCK

2

RA2

ID12
ID0A
ID02

REV2

CVBSCLP

LUMDIS

Reserved

AN2

SC2
FR12
FR0A
FR02

-

SCH2

CTL2

RD2
WR2

F1W1D2
F1W2D2
F2W1D2
F2W2D2

F1ST

HSOFF2

-

SL_HS0

HCNT2

TEST
TEST

TSURST

1

RA1

ID11
ID09
ID01

REV1
VFS1

CHRDIS

Reserved

AN1

SC1
FR11
FR09
FR01

-

SCH1

CTL1

RD1
WR1

F1W1D1
F1W2D1
F2W1D1
F2W2D1

F2EN

HSOFF1
HSOFF9

HCNT9
HCNT1

CHRMCLIP

3

RA3

ID13
ID0B
ID03

REV3

SLH&V

BURDIS

DFI0

AN3

SC3

FR13

FR0B

FR03

-

SCH3

CTL3

RD3
WR3

F1W1D3
F1W2D3
F2W1D3
F2W2D3

F2ST

HSOFF3

-

SL_HS1

HCNT3

FOR
FOR

PALIDEN

DEFAULT

hex

13
66
58
05

00
00
00

00
9C
87
C1
F1
00
00

FF

-

00
00

00
00
00
00

7E
00
00
00

00

0

RA0
ID10

ID08
ID00

REV0
VFS0

PEDEN

ACTREN

PARITY

SC0
FR10
FR08
FR00
SCH8
SCH0

CTL0

RD0

WR0

F1W1D0
F1W2D0
F2W1D0
F2W2D0

F1EN

HS0FF0

HSOFF8

HCNT8
HCNT0

TRSEL

R/W

W

R
R
R
R

R/W
R/W

*
R/W
R/W
R/W
R/W
R/W
R/W
R/W

W

R

W

R/W
R/W
R/W
R/W
R/W

R/W
R/W
R/W
R/W
R/W
R/W
R/W

REGISTERS MAP

See Register Details for further explanations.

ADDRESS

hex

00
01
02
03

04
05
06
07
08
09
0A

0B
0C
0D

0E to 1F

20

21

22

23 to EF

F0

F1

F2

F3

F4

F0 to F7

F8

F9
FB
FC
FD
FE

FF

REGISTER

NAME

BAR

PART ID2
PART ID1
PART ID0

REV ID

GCR
VOCR
HANC

ANCID

SC_ADJ

FREQ2
FREQ1
FREQ0

SCHPHM

SCHPHL

Reserved

GPPCTL

GPPRD

GPPWR

Not used
CCREG1
CCREG2
CCREG3
CCREG4

CC_CTL
Reserved

HSOFFL
HSOFFM

SLAVE1
SLAVE2

TEST1
TEST2

GPSCTL

Table.1 Register map

xx = don’t care.

The calculation of the FREQ register value is according to the following formula:-

FREQ = 2

26

x fSC/PXCK hex, where PXCK = 27.00MHz

NTSC value is rounded UP from the decimal number. PAL-B, D, G, H, I and N (Argentina) are rounded DOWN. The SC_ADJ
value is derived from the adjustment needed to be added after 8 fields to ensure accuracy of the Subcarrier frequency. Note the
SC_ADJ value of 9C required for PAL-B, D, G, H, I, is different to the default state of the register.
In NTSC the NCO is reset at the end of every line, this can be disabled by setting the NCORSTD bit in SLAVE1, this allows the
VP5311 to cope with line lengths that are not exactly as specified in REC656.

NOTE * For register HANC, bits 3, 4 and 5 are read only. Bits 1 and 2 are reserved. N/A = not applicable.

For register PART ID0 the VP551 value is AB

Standard

NTSC (default)
PAL-B, G, H, I
PAL-N (Argentina)

FREQ2-0

registers hex

87 C1 F1

A8 26 2B

87 DA 51

Lines/

field

525
625
625

Field

freq. Hz

59.94
50
50

1716
1728
1728

Number of

pixels/line

at 27MHz

15.734266

15.625000

15.625000

Horizontal

freq. kHz.

f

H

3.57954545

4.43361875

3.58205625

Subcarrier

freq. kHz.

fSC

(455/2)

(1135/4+1/625)

(917/4+1/625)

fSC/fH

SC_ADJ

register

hex

xx
9C
57

Table.2 Line, field and subcarrier standards and register settings