MITEL GP1020 Datasheet

GP2010

GPS Receiver RF Front End

Supersedes edition in August 1996 Global Positioning Products Handbook, HB4305-1.0 DS4056 - 3.4 October 1996

The GP2010 is Mitel Semiconductor second generation
RF Front-end for Global Positioning System (GPS) receivers.
The GP2010 uses many innovative design techniques and a
leading-edge bipolar process to offer a low power, low cost
and high reliability RF Front End solution . The GP2010 is
designed to operate from either 3 or 5 Volt power supplies.

The input to the device is the L1 (1575.42MHz) Coarse­Acquisition (C/A) code Global Positioning signal from an
antenna (via a low-noise pre-amplifier). The output is 2-bit
quantised for subsequent signal processing in the digital
domain. The GP2010 contains an on-chip synthesiser, mixers,
AGC and a quantiser which provides Sign and Magnitude
digital outputs. A minimum of external components is required
to make a complete GPS front-end.

The device has been designed to operate with the GP2021
12-channel Global Positioning Correlator, and DW9255 SAW
filter, both also available from Mitel Semiconductor.

FEATURES

■ Low Voltage Operation (3V - 5V)

■ Low Power - 200mW typ. (3V supply)

■ C/A Code Compatible

■ On-chip PLL Including Complete VCO

■ Triple Conversion Receiver

■

44-Lead Surface Mount Quad Flat-Pack Package

■ Sign and Magnitude Digital Outputs

■ Compatible with GP2021 CMOS Correlator

APPLICATIONS

■ C/A Code Global Positioning by Satellite Receivers

■ Time Standards

■ Navigation

■ Surveying

Pin

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22

24

25

26

27

28

29

30

31

32

33

34
35
36
37
38
39
40
41
42
43
44

IF Output
PLL Filter 1
PLL Filter 2

(OSC)

V

EE

(OSC)

V

CC

(OSC)

V

EE

VEE (REG)
PRef
PReset

(IO)

V

EE

CLK
MAG
SIGN

IK-

OPC
OPCIK+
VDD (IO)

N

PD
TEST
LD

(DIG)

V

EE

AGC ­AGC +

1

Name

GP

43 2

2010

Pin

23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

10

98765

Fig. 1 Pin connections - top view

23

11

(DIG)

V

CC

REF 2
REF 1

(RF)

V

CC

(RF)

V

EE

(RF)

V

EE

RF Input

(RF)

V

EE

(RF)

V

EE

(RF)

V

CC

O/P 1­O/P 1+

(2)

V

CC

I/P 2­I/P 2+

(IF)

V

EE

(IF)

V

EE

O/P 2­O/P 2+

(3)

V

CC

I/P 3­I/P 3+

22
21
20
19
18
17
16
15
14
13
12

Name

GP

44

ORDERING INFORMATION

The GP2010 is available in 44 pin Quad Flat pack (gullwing

formed leads) to Industrial (-40°C to +85°C) grade.

ORDERING CODE

GP2010 IG GPBR Industrial - Plastic 44-pin PQFP

RELATED PRODUCTS AND PUBLICATIONS

Part

DW9255

GP2021

GPSBuilder-2

GP2010
GP2015
GP2015

35.42MHz SAW Filter
Twelve-Channel Correlator
Twelve-Channel GPS receiver
development system
Design with the GP2010
Small RF Format Front End
Design with the GP2015

Description

Reference

Data

DS3861
DS4057
DS4004

AN4364
DS4374
AN4533

GP2010

ABSOLUTE MAXIMUM RATINGS
(Non-simultaneous)

Max. Supply Voltage 7V
Max. RF Input +15dBm
Max. voltage on any pin V
except LD (pin 19) and PReset (pin 9), which are 5.5V

CC/VDD

+ 0.5V

Min. voltage on any pin VEE - 0.5V

Storage Temperature -65°C to +150°C
Operation Junction Temperature -40°C to +150°C

10MHz Reference Input 1.5V pk -pk

ESD PROTECTION

The GP2010 device is static sensitive. The most
sensitive pins withstand a 750V test by the human body
model. Therefore, ESD handling precautions are essential to
avoid degradation of performance or permanent damage to
this device.

PRODUCT DESCRIPTION

The GP2010 receives the 1575.42MHz signal
transmitted by GPS satellites and converts it to a 4.309MHz
IF, using a triple down-conversion. The 4.309MHz IF is
sampled to produce a 2-bit digital output. If the GP2010 is
used in conjunction with the GP2021 correlator, then the
GP2021 provides a sampling clock of 5.714MHz. This converts
the IF to a 1.405MHz 2-bit digital output at TTL levels.

The GP2010 can operate from a single supply from
+3V (nominal) to +5V (nominal).

A block diagram of the circuit is shown in figure 2.

IF STRIP

The input signal to the GP2010 is the GPS L1 signal
received via an antenna and a suitable LNA. The L1 input is
a spread spectrum signal at 1575.42MHz with 1.023Mbps
BPSK modulation. The signal level at the antenna is about

-130dBm, spread over a 2.046MHz bandwidth, so the wanted
signal is actually buried in noise. The high RF input compression
point of the GP2010 means that with subsequent IF filtering
it is possible to reject large out of band jamming signals, in
particular 900MHz as used by mobile telephones.The on-chip
PLL generates the first local-oscillator frequency at 1400MHz.
The output of the front-end mixer (Stage 1) at 175.42 MHz can
then be filtered before being applied to the second stage. The
double-balanced stage 1 mixer outputs are open-collectors,
and require external dc bias to V

CC

.

The second stage contains further gain and a mixer
with a local oscillator signal at 140 MHz giving a second IF at

35.42 MHz. The second stage mixer is also double-balanced
with open-collector outputs requiring external dc bias to V

CC

The signal from stage 2 is passed through an external
filter with a 1dB bandwidth of 1.9MHz. The performance of this
filter is critical to system performance and it is recommended
that a SAW filter is used (part number DW9255, also available
from Mitel Semiconductor). The output of the filter then feeds
the main IF amplifier. This includes 2 AGC amplifiers and a
third mixer with a local oscillator signal at 31.111 MHz giving
a final IF at 4.309 MHz. There is an on-chip filter after the third
mixer which provides filtering centred on 4.309 MHz. The IF
output, which has 1kΩ output impedance, is provided for test
purposes. All of the signals within the IF amplifier are differential
including the filter inputs and outputs, except the IF output (pin

1), to reduce any common mode interference.

.

RF Input

EXTERNAL

LOOP

FILTER

PLL LOCK
LOGIC O/P

(LD)

PLL REF I/P

10MHz (REF 2)

REF 1 I/P

(FOR USE WITH

CRYSTAL REF

ONLY)

(29)

(2)

(3)

(19)

(24)

(25)

L1

(1575.42MHz)

VOLTAGE

REGULATOR

175.42MHz FILTER

(33,34) (36,37) (40,41) (43,44) (21) (22)

FRONT

END

MIXER

1.400GHz

VCO

PLL

LOOP

FILTER

PHASE

DETECTOR

PLL
REFERENCE
OSCILLATOR

40MHz CLOCK O/P

(FOR CORRELATOR

(14, 15)

CHIP)

(OPCIK +/-)

÷5 ÷5÷5

÷7÷4÷9

1.400GHz
PHASE-

LOCKED

LOOP

35.42MHz FILTER

2nd
STAGE
MIXER

÷2

BITE

(TEST)

POWER-ON

REFERENCE

I/P

(PREF)

AGC AGC

+1.21V

POWER-ON

_

+

RESET

POWER

CONTROL

POWER

DOWN I/P

(PDn)

AGC CAPACITOR

AGC

CONTROL

POWER-ON
RESET O/P

(PRESET)

3rd

STAGE

MIXER

(9)(17)(8)(18)

31.11MHz140MHz

4.3MHz
FILTER

SIGN

O/P

LATCH

MAG

O/P

LATCH

A -> D

CONVERTER

(1)

IF Output
(4.309MHz)

+Vr

-Vr

(13)

SIGN
TTL O/P

(12)

MAG
TTL O/P

(11)

SAMPLE
CLOCK I/P (CLK)
(5.71MHz TTL)

Fig. 2 Block diagram of GP2010

2

The IF output is fed to a 2-bit quantiser which provides
sign and magnitude (MSB and LSB) outputs. The magnitude
data controls the AGC loop, such that on average the magnitude
bit is set (high) 30% of the time. The AGC time constant is set
by an external capacitor.

The sign and magnitude data, SIGN (pin 13) and MAG (pin

12), are latched by the rising edge of the sample clock, CLK
(pin 11), which is normally derived from the correlator; the
GP2021 provides a 5.714MHz (=40/7) clock, giving a sampled
IF centred on 1.405MHz.

The Digital Interface circuits use a separate power-supply,

V

(IO), which would normally be shared with the correlator to

DD

minimise crosstalk between the analog and digital sections of
the device.

ON-CHIP PHASE-LOCKED LOOP SYNTHESISER

All of the local oscillator signals are derived from an on
chip phase locked loop synthesiser. This includes a 1400MHz
VCO complete with on-chip tank circuit, dividers and phase
detector, with external loop filter components. A 10.000MHz
reference frequency is required for the PLL. This can be
achieved by attaching an external 10.000MHz crystal to the
on-chip PLL reference oscillator (see figure 5). However in
most applications the user will need an external source, such
as a TCXO, to provide greater frequency stability (see figure

6). An external reference should be ac coupled to REF2 (pin

24); REF 1 (pin 25) should be left open circuit.

The three local oscillator signals 1400MHz, 140.0MHz
and 31.11MHz are derived from the 1400MHz synthesiser
output. The synthesiser also provides a 40 MHz balanced
differential output clock (pins 14 & 15) which can be used to
clock the GP2021 correlator. The clock is a low level differential
signal which helps minimise interference with the analog
areas of the circuit. A PLL lock-detect output, LD (pin 19), is
also provided, which is logic high when the PLL is phase­locked to the 10.000MHz reference signal.

The VCO power-supply incorporates an on-chip
regulator to improve the noise-immunity of the PLL. This
feature is only available when operating with a 5 volt (nominal)
supply which is regulated to 3.3 volts internally. This internal
regulated supply is referenced to V

(OSC) (pin 5). Figure 7

CC

shows the required connections for both 3 volt and 5 volt
operation.

A further feature of the circuit is the TEST input (pin 18).
When this input is held high the PLL is unlocked with the VCO
at its maximum frequency.

GP2010

POWER-DOWN CAPABILITY

A power down function is provided on the GP2010, to
limit power consumption. This powers down the majority of
the circuit except the “power-on reset” function (see below).

If the power down feature is not required, the Power­down input, PD
(=Vee/Ground).

POWER-ON RESET FUNCTION

The GP2010 includes a voltage detector which
operates from the digital interface supply. This circuit is used
to produce a TTL logic low output while the GPS receiver
power supply is switching on, and produces a logic high
output when the power supply voltage has achieved a nominal
value. This output can be used to disable the GP2021
correlator while the power supply is switching on. An internal
bandgap reference of approximately +1.21V is compared
with the voltage on a sense pin, PRef (pin 8); when the
voltage on this pin exceeds the reference, a TTL logic high
level appears at the Power-on Reset output, PReset (pin 9).
Thus, if the sense input voltage is derived from an external
resistive divider from the Digital Interface supply, V

16), such that the sense voltage at nominal VCC is VS, then the
supply threshold, Vcc(thresh), at which the PReset output
goes to logic high is:-

For a VCC (nom) of 5.0V, VCC (thresh) may be set to approx.

4.0V, giving VS of 1.5V.
For a V

CC

2.4V, giving VS of 1.5V.

ADDITIONAL INFORMATION

All the digital inputs and outputs can use a separate
power supply to help prevent digital switching transitions
interacting with the analog sections of the device, and as an
additional precaution, the digital inputs and outputs are on
the opposite side of the device to the critical analog pins.

(pin 17), should be connected to 0V dc

n

(IO) (pin

DD

VS = VCC (nom) x 1.21

V

(thresh)

CC

(nom) of 3.0V, VCC (thresh) may be set to approx.

3

GP2010

ELECTRICAL CHARACTERISTICS

The Electrical Characteristics are guaranteed over the following range of operating conditions (see Fig. 3 for test circuit):

Industrial (I) grade: T
Supply voltage: V

Test conditions (unless otherwise stated):

Supply voltages: VCC = +2.7V and +5.5V, VDD = +2.7V and +5.5V
Test temperature: Industrial (I) grade product: +25°C

= -40°C to +85°C

AMB

and VDD = +2.7V to +5.5V

CC

Characteristic

SUPPLY CURRENT

Normal mode - Analog interface

- Digital interface

Power down mode - Analog interface

- Digital interface
Power Supply Differential
Power down Response time

IF STRIP

Front End/Mixer 1

Conversion Gain (G1)
Noise Figure

Input Compression (1dB)
Input Impedance

Differential Output Impedance
RF Input Image Rejection

Stage 2/Mixer 2

Conversion Gain (G2)
Input Compression (1dB)
Differential Input Impedance
Differential Output Impedance

Min.

11

-22

22

5

Value

Typ. Max.

55

77

14.5

9
3
3

100

3

18

25

9

-16
15

3.6

700

8

27

33

14

700
500

6
5

Units

mA
mA
mA
mA
mV

µs

dB
dB

dBm

Ω

nH

Ω

dB

dB

mV rms

Ω
Ω

Conditions

Pins 5, 23, 26, 32, 35, 42
Pin 16
Pins 5, 23, 26, 32, 35, 42
Pin 16
Between any V

CC/VDD

pins (Note 7)

(Note 7)

R

= 600Ω (Note 2)

O

FIN = 1575.42MHz
Z

= 50Ω (Note 7)

S

Pin 29 (Notes 1 and 7)
(Notes 1 and 7)
Pins 33 & 34 (Note 8)

F

= 1224.58MHz (Note 7)

IN

F

= 175.42MHz

IN

Pins 36 & 37 (Note 8)
Pins 40 & 41 (Note 8)

Stage 3

High Gain (In terms of total strip)
High Gain (G3)
Gain Control Range
Differential Input Impedance
IF Output amplitude
IF Output impedance

4.3MHz Filter Response
Flatness 4.3 ± 1MHz
Rejection @ 0.5MHz

@ 50MHz

2 BIT QUANTISER

Sign Duty Cycle
Mag Duty Cycle
AGC Time Constant

ON-CHIP PLL SYNTHESISER

Phase Noise

± 1kHz
± 10kHz
± 100kHz
± 1MHz
± 5MHZ
± 50MHz

PLL Spurs

106-G1-G2

60

-1.5
45

40
20

75
60

1

85

1

14
70

50
30

2

-68

-75

-88

-110

-120

-120

-50

120

+1.0

60
40

dB
dB
dB
kΩ

mV rms

kΩ
dB

dB
dB

%
%

ms

dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz

dBc

(Note 6)
F

= 35.42MHz

IN

(Note 3)
Pins 43 & 44 (Note 8)
CW input (Note 3)
Pin 1(Note 8)

(Note 7 and 9)

(Note 10)

C

= 100nF

AGC

15kHz Loop Bandwidth

(Note 7)

(Note 7)

4

Characteristic

Min.

Value

Typ. Max.

Units

GP2010

Conditions

VCO Maximum Lock Frequency
VCO Minimum Lock Frequency
VCO regulator output voltage
VCO Gain
Phase Detector Gain

10MHz Reference Input
10MHz Reference Input Impedance

PLL Lockup Time
PLL Loop Gain

DIGITAL INTERFACES
Sample Clock, Power Down,
Test Inputs.

V

IH

V

IL

Input Current High I
Input Current Low I

IH

IL

Sign/Mag Outputs

V

OH

V

OL

Sample Clock to Sign/Mag Delay

40MHz Clock Output

High Level (V

OH

)
Low Level (VOL)
Output (differential)

Duty Cycle

1414

3

50

0.1

2
0

-300

V

-1

DD

VDD-1.25

3.3

150

5.3

0.6
5

6

150

20

V

-1

DD

VOH-0.1

220

43

1386

3.5

240

1.2

V

DD

0.5
10

0.5

VDD-0.8

MHz
MHz

V

MHz/V

V/rad

V pk-pk

kΩ

ms
dB

V
V

µA
µA

V
V

ns

V
V

mV p-p

%

(Note 4)
(Note 7)
Pin 24

(Note 11)
From Power up (Note 7)

(Note 7)

Pins 11, 17, 18

V

= V

IH

DD

VIL = V

EE

Pins 13, 12
IO = -0.5mA
IO = 0.5mA

CL = 15pF, RL = 15kΩ (Note 7)

Pins 14 & 15
(Note 5)
CL = 15pF (GND) (Note 7)
CL = 5pF (Diff) (Note 7)
(Note 7)

LD (PLL Lock)/PReset Outputs

Low Level (V
High Level (V

OL

OH

)

)

Power-on Reset comparator input

Power Reset Reference Level
Power Reset Reference Input Current

VDD-1

1.1

-10

0.2

V

DD

0.5

1.35
10

µA

V
V

V

Pins 19 and 9
I

= 0.5mA

O

I

= -10µA

O

Pin 8

Notes On Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output
impedances, such as balun transformers, and levels refer to matched 50ohm ports (see figure 3 for test circuit)

1. RF input impedance (series) without input matching components connected - expressed as Real impedance with reactive
inductor value. Measured at 1575.42MHz.

2. Input matched to 50ohm, output loaded wlth 600ohms differential

3. Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms.

4. VCO regulator voltage measured with respect to Vcc (OSC) - pin 5.

5. OPCLK outputs are differential and are referenced to V

DD

.

6. Minimum gain requirement expressions:

-7dBm < -174dBm/Hz + 19dB + G1 + G2 + G3 - 21dB + 63dB
where -7dBm = typical IF Output level with AGC active (equivalent to 100mV rms)

-174dBm/Hz = background noise level at RF input

19dB = sum of LNA gain and noise figure

-21dB = total loss in 175MHz and 35MHz filters
63dB = summation of noise over a 2MHz bandwidth

Rearranging the above expression gives G1 + G2 + G3 > 106dB.

7. This parameter is not production tested.

8. This impedance is toleranced at +/-30% and is not production tested.

9. Roll off occurs in on-chip capacitive coupling IF Output to input of ADC circuit. Not measurable at IF Output.

10. CW input on pins 43 & 44 of 35.42MHz at 7mV rms.

11. This input impedance applies to the typical input level. The impedance is level dependent and is not tested or guaranteed.

5

GP2010

PIN DESCRIPTIONS

All VEE and VCC/VDD pins should be connected to ensure reliable operation

Pin No. Signal Name Input/Output Description

1 IFOutput Output IF Test output.

Connected to output of Stage 3 prior to the A to D converter.
A series 1kΩ resistor is incorporated for buffering purposes.

2 PLL Filt1 Output PLL Filter 1.

Connected to the bias network within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 2 (see below).

3 PLL Filt2 Output PLL Filter 2.

Connected to the varactor diodes within the on-chip VCO. An
external PLL loop filter network should be connected between
this pin and PLL Filt 1 (see above).

4,6 VEE (OSC) Input Negative supply to the on-chip VCO. (See Note 1)

5V
7V

8 PRef Input Power-on Reset Reference input.

9 PReset Output Power-on Reset Output.

10 VEE (IO) Input Negative supply to the Digital Interface. (See Note 2)
11 CLK Input Sample Clock input from the correlator chip.

12 MAG Output Magnitude bit data output.

13 SIGN Output Sign bit data output.

(OSC) Input Positive supply to the on-chip VCO.

CC

(REG) Input Negative supply to the VCO regulator.

EE

This must be connected to GND.

An on-chip comparator produces a logic HI when the PRef
input voltage exceeds +1.21V. (Nom) (See Page 3).

A TTL compatible output controlled by the Power-on reset
comparator (See above). This output remains active even
when the chip is powered down. (See pin 17 - PDn).

A TTL compatible input (which operates at 5.714MHz if used
with GP2021 correlator device) used to clock the MAG & SIGN
output latches, on the rising edge of the CLK signal.

A TTL compatible signal, representing the
mixed down IF signal. Derived from the on-chip 2-bit A to D
converter, synchronised to the CLK input clock signal.

A TTL compatible signal, representing the
down IF signal. Derived from the on-chip 2-bit A to D converter,
synchronised to the CLK input clock signal.

magnitude

polarity

of the mixed

of the

14 OPClk- Output 40MHz Clock output - inverse phase.

One side of a balanced differential output clock, with opposite
polarity to Pin 15 - OPClk+. Used to drive a master-clock signal
within the correlator chip.

15 OPClk+ Output 40MHz Clock output - true phase.

Other side of a balanced differential output clock set, with
opposite polarity to Pin 14 - OPClk-. Used to drive a master­clock signal within the correlator chip.

16 VDD (IO) Input Positive supply to the Digital Interface. (See Note 2)

6

Pin No. Signal Name Input/Output Description

17 PDn Input Power-Down control input.

A TTL compatible input, which when set to logic high, will
disable ALL of the GP2010 functions, except the power-on
reset block. Useful to reduce the total power consumption of
the GP2010. If this feature is not required, the pin should be
connected to 0V (VEE/GND).

18 TEST Input Test control input - Disable PLL.

A TTL compatible input, which when set to logic high, will
disable the on-chip PLL, by disconnecting the divided-down
VCO signal to the phase-detector. The VCO will free run at its
upper range of frequency operation. If this feature is not
required, the pin should be connected to 0V (VEE/GND).

19 LD Output PLL Lock Detect output.

A TTL compatible output, which indicates if the PLL is phase­locked to the PLL reference oscillator. Will become logic high

only when phase-lock is achieved.
20 VEE (DIG) Input Negative supply to the PLL and A to D converter.
21 AGC- Output AGC Capacitor output - inverse phase.

One side of a balanced output from the AGC block within IF

Stage 3, to which an external capacitor is connected to set the

AGC time-constant.

GP2010

22 AGC+ Output AGC Capacitor output - true phase.

One side of a balanced output from the AGC block within IF

Stage 3, to which an external capacitor is connected to set the

AGC time-constant.
23 VCC (DIG) Input Positive supply to the PLL and A to D converter.
24 REF 2 Input 10.000MHz PLL Reference signal input .

Input to which an externally generated 10.000MHz PLL

reference signal should be ac coupled, if an external PLL

reference frequency source (e.g TCXO) is used (see fig. 6).

If no external reference is used, this pin forms part of the on-

chip PLL reference oscillator, in conjunction with an external

10.000MHz crystal (see fig. 5).

25 REF 1 Input PLL reference oscillator auxillary connection.

Used in conjunction with Pin 24 (REF 2) to allow a 10.000MHz

external crystal to provide the PLL reference signal if no

external PLL reference frequency source (e.g TCXO) is used.

This pin should NOT be connected if an external TCXO is

being used (see fig. 5).

26, 32 VCC (RF) Input Positive supply to the RF input and Stage 1 IF mixer.

Both pins 26 & 32 (VCC (RF)) are connected internally, but

must both be connected to VCC externally, to keep series

inductance to a minimum.

27, 28, VEE (RF) Input Negative supply to the RF input and Stage 1 IF mixer.

30, 31 Pins 27, 28, 30 & 31 are all connected internally, but must ALL

be connected to 0V (VEE/GND) externally, to keep series

inductance to a minimum.

7

GP2010

Pin No. Signal Name Input/Output Description

29 RF Input Input RF input.

The GPS RF input signal @ 1575.42MHz from an external

antenna with LNA and filter is connected to this pin via an

input-matching network (see fig.4).
33 O/P 1- Output Stage 1 mixer output @ 175.42MHz - inverse phase.

One of a balanced output from first stage IF mixer, to which

one input of an external balanced 175MHz bandpass filter is

connected. External dc biasing is required via an inductor

connected to VCC(RF) - the value of which is dependent on the

filter used.
34 O/P 1+ Output Stage 1 mixer output @ 175.42MHz - true phase.

Second of a balanced output from first stage IF mixer, to which

the second input of an external balanced 175MHz bandpass

filter is connected. External dc biasing is required via an

inductor connected to VCC(RF) - the value of which is dependent

on the filter used.
35 VCC (2) Input Positive supply to the Stage 2 IF mixer.
36 I/P 2- Input Stage 2 mixer input @ 175.42MHz - inverse phase.

One of a balanced input to the second stage IF mixer, to which

one of the balanced signal outputs from the external 175MHz

bandpass filter is connected.
37 I/P 2+ Input Stage 2 mixer input @ 175.42MHz - true phase.

Second of a balanced input to the second stage IF mixer, to

which the second of the balanced signal outputs from the

external 175MHz bandpass filter is connected.

38,39 VEE (IF) Input Negative supply to the Stage 2 IF mixer, and Stage 3 IF block.

40 O/P 2- Output Stage 2 mixer output @ 35.42MHz - inverse phase.

One of a balanced output from second stage IF mixer, to which

one input of an external balanced 35.42MHz bandpass filter is

connected. External dc biasing is required via an Inductor

connected to VCC. (See Note 3)
41 O/P 2+ Output Stage 2 mixer output @ 35.42MHz - true phase.

Second of a balanced output from second stage IF mixer, to

which the second input of an external balanced 35.42MHz

bandpass filter is connected. External dc biasing is required

via an Inductor connected to VCC. (See Note 3)
42 VCC (3) Input Positive supply to the Stage 3 IF mixer.
43 I/P 3- Input Stage 3 mixer input @ 35.42MHz - inverse phase.

One of a balanced input to the third stage IF mixer, to which

one of the balanced signal outputs from the external 35.42MHz

bandpass filter is connected. (See Note 3)
44 I/P 3+ Input Stage 3 mixer input @ 35.42MHz - true phase.

Second of a balanced input to the third stage IF mixer, to which

the second of the balanced signal outputs from the external

35.42MHz bandpass filter is connected. (See Note 3)

8