Microsoft Xbox 360 Schematics Xenon
PAGE
CONTENTS
[1] COVER PAGE
[2] CLOCK DIAGRAM
[3] RESET/ENABLE DIAGRAM
[4] CPU, CLOCKS + EEPRO M + STRAPPING
[5] CPU, FSB
[6] CPU, FSB POWER + PLL POWER
[7] CPU, CORE POWER
[8] CPU, POWER
[9] CPU, DECOUPLING
[10] CPU, DECOUPLING
[11] CPU, DECOUPLING
[12] GPU, FSB
[13] GPU, VIDEO + PCIEX + EEPROM
[14] GPU, MEMORY CONTROLLER A + B
[15] GPU, MEMORY CONTROLLER C + D
[16] GPU, PLL POWER + FSB POWER
[17] GPU, CORE POWER + MEM POWER
[18] GPU, DECOUPLING
[19] DUAL ETHERNET PHY
[20] MEMORY, A (TOP)
[21] MEMORY, A MIRRORED (BOTTOM)
[22] MEMORY, B (TOP)
[23] MEMORY, B MIRRORED (BOTTOM)
[24] MEMORY, C (TOP)
[25] MEMORY, C MIRRORED (BOTTOM)
[26] MEMORY, D (TOP)
[27] MEMORY, D MIRRORED (BOTTOM)
[28] ANA, CLOCKS + STRAPPING
[29] ANA, VIDEO + FAN + JTAG
[30] ANA, POWER + DECOUPLING
[31] DEBUG MAPPING, WN DBG VS WN XDK
[32] POWER TRACE EMI CAPS
SCHEMA TI C REV PB N U M BER VER BOM RELEASE DATE
PAGE
CONTENTS
K7 X803600-011 RETAIL XX/XX/XX
[33] SB, PCIEX + SMM GPIO + JTAG
[34] SB, SMC
[35] SB, FLASH + USB + SPI
[36] SB, ETHERNET + AUDIO + SATA
[37] SB, STANDBY POWER + DECOUPLE
[38] SB, MAIN POWER + DECOUPLE
[39] SB OUT, ETHERNET
[40] SB OUT, AUDIO
[41] SB O U T, FLASH
[42] SB OUT, FAN + INFRARED + BUTTONS
[43] CONN, AVIP
[44] CONN, RJ45 + USB COMBO
[45] CONN, GAME PORTS + MEMORY PORTS
[46] BACKUP CLOCK + V_5P0 DUAL
[47] CONN, ODD AND HDD
[48] CONN, ARGON + POWER
[49] VREGS, INPUT + OUTPUT FILTERS
[50] VREGS, CPU CONTROLLER
[51] VREGS, GPU OUTPUT PHASE 1,2,3
[52] VREGS, GPU CONTROLLER
[53] VREGS, GPU OUTPUT PHASE 1,2
[54] VREGS, SWITCHED 1.8, 5.0V
[55] VREGS, LINEAR REGULATORS
[56] XDK, DEBUG CONN
[57] DEBUG BOARD, CPU + GPU BREAKO U T
[58] DEBUG BOARD, CPU CONN
[59] DEBUG BOARD, CPU CONN + TERM
[60] DEBUG BOARD, CPU TERM
[61] DEBUG BOARD, TITAN + YETI CONN
[62] DEBUG BOARD, GPU CONN + TERM
[63] XDK, LEDS
[64] LABELS AND MOUNTING
XENON
RETAIL
REV K7
FAB K
RULES: (APPLIED WHEN POSSIBLE)
1.) MSB TO LSB IS TOP TO BOTTOM
2.) WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
3.) ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING
4.) AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
5.) LANED SIGNAL S ARE GROU PED ON SYMBOLS
6.) TRANSIMITTER NAME USED AS PREFIX WITH RX A ND TX CONNECTIONS
7.) SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
8.) SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
9.) UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
10.) SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
12.) SUFFIX _P FOR P JUNCTION
13.) SUFFIX _EN FOR ENABLE
14.) 'CLK' FOR CLOCKS, 'RST' FOR RESETS
15.) PWRGD FOR POWER GOOD
[PAGE_TITLE=COVER PAGE]
DRAWING
XENON_FABK
Wed Aug 24 09:41:55 2005
BOM RELEASE DATE
SIGNATURE
DRN BY
CHK BY
ENGR
APVD
APVD
APVD
XENON
PLEASE REFER TO THE XENON DESI GN SPEC
PB NUMBER
XX/XX/XX
DATE
MICROSOFT XBOX
TITLE
MICROSOFT
CONFIDENTIAL
X803600-011
SCH, PBA, XENON
PROJECT NAME
XENON_RETAIL
PAGE
1/73
REV
K7
RJ45/USB
CONN
AVIP
CONN POWER
FAN
CONN
CONN
ENET
PHY
DVD
SATA
CONN
DVD
PWR
CONN
HDD
CONN
ENET_CLK(25MHZ)
1P8 VR
3P3 VR
MPORT VR
I2S_MCLK(12.288MHZ)
I2S_BCLK(3.072MHZ)
SB
FLSH
AUDIO
DAC
DEBUG
CONN
STBY_CLK(48MH Z)
SATA_CLK_REF(25MHZ)
SATA_CLK_DP/DN(100MHZ)
PCIEX_CLK_DP/DN(100MHZ)
AUD_CLK(24.576MHZ)
ANA
BCKUP
CLAM C+D
MEM
ANA_XTAL_IN(27MHZ)
ANA
BCKUP
GPU_CLK_DP/DN (100MHZ)
MC_CLK1_DP/DN(800MHZ)
MC_CLK0_DP/DN(800MHZ)
MD_CLK1_DP/DN(800MHZ)
MD_CLK0_DP/DN(800MHZ)
VMEM VR
5P0 VR
CLOCK DIAGRAM
GPU VR
ANA
CPU_CLK_DP/DN(100MHZ)
PIX_CLK_OUT_DP/DN(100MHZ)
GPU
MA_CLK0_DP/DN(800MHZ)
MA_CLK1_DP/DN(800MHZ)
MEM
CLAM A+B
MB_CLK0_DP/DN(800MHZ)
MB_CLK1_DP/DN(800MHZ)
EFUSE V R
CPU
TITAN JTAG
CONN
RISCWATCH
CONN
GPU VR
CNTL
CPU V R
CNTL
CPU
VR
EJECT
IR
SW
<PAGE_TITLE=CLOCK DIAGR AM>
MEM MEM
CONN
CONN SW
BIND
ARGON
CONN
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
GAME
CONN
PROJECT NAME
XENON_RETAILWed Jul 27 21:53:30 2005
PAGE
2/73
REV
K7
RJ45/USB
CONN
ENET
PHY
ENET_RST_N
AVIP
CONN
AUD_CLAMP
AUD_RST_N
AUDIO
DAC
FAN
CONN
RESET/ENABLE DIAGRAM
PSU_V12P0_EN
POWER
CONN
DVD
SATA
CONN
DVD
PWR
CONN
HDD
CONN
IR
DEBUG
CONN
EJECT
SW
CPU_PWRGD
EFUSE V R
GPU VR
VREG_GPU_EN_N
CPU_CHECKSTOP_N
CPU
TITAN JTAG
CONN
VREG_CPU_EN
GPU VR
CNTL
RISCWATCH
CONN
CPU V R
CNTL
CPU
VR
GAME
CONN
EXT_PWR_ON_N
SMC_RST_N
SB
VREG_GPU_PWRGD
EXT_PWR_ON_ N
SB_RST_N
GPU_RST_DONE
MEM
SMC_DBG_EN
VREG_3P3_EN
VREG_CPU_PWRGD
3P3
VR
CLAM C+D
VREG_1P8_EN_N
VREG_5P0_EN_N
MEM
ANA_CLK_OE
ANA_RST_N
GPU_RST_N
MEM_RST
MEM_SCAN_EN
MEM_SCAN_TOP_EN
MEM_SCAN_BOT_EN
VMEM VR
5P0 VR
MEM
CONN
ANA
GPU
MEM_RST
MEM_SCAN_EN
MEM
CLAM A+B
MEM_SCAN_BOT_EN
MEM_SCAN_TOP_EN
CPU_RST_N
CPU_PWRGD
VREG_EFUSE_EN
BIND
SWCONN
ARGON
CONN
[PAGE_TITLE=RESET/ENABLE DIAGRAM]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Jul 27 21:53:44 2005
PAGE
3/73
REV
K7
R6R4
R6R5
R7R13
10K
5%
CH
402
R7R3
10K
5%
EMPTY
402
CPU_RST_V1P1_N
1
3.92K
402
1
3.92K
402
1
5%
CH
1
5%
CH
1
R7D1
10K
5%
CH
402
2
1
R7R22
10K
5%
CH
402
2
3
1
R7R19
10K
5%
EMPTY
402
2
R7R4
R7R10
V_GPUCORE
1
R7R15
10K
5%
EMPTY
402
2
1
R7R6
10K
5%
CH
402
2
2
1%
CH
2
1%
CH
1
2
1
2
R7R16
1
6.19K
402
CPU_PWRGD_ V1P 1_N
R7R11
1
6.19K
402
TP6D1
PROBE
1
2
SMT
1
2
1
2
R7R23
10K
5%
CH
402
4
R7R18
10K
5%
EMPTY
402
FT7R4
FT7R6
FT7R2
FT7R1
FT7R5
R7R8
10K
5%
EMPTY
402
R7R7
10K
5%
CH
402
1%
CH
1%
CH
FTP
FTP
FTP
FTP
FTP
1
C7R112
2
360PF
10%
50V
2
NPO
603
1
2
2
FSB_CLK_DP
FSB_CLK_DN
1
4
1
3
1
2
1
1
1
0
C7R113
360PF
10%
50V
NPO
603
CPU_PULSE_LIMIT_BYPASS
R7R24
1
402
CPU_POS T_IN< 0.. 4>
TP6R1
PROBE
1
SMT
1
2
TP6R2
PROBE
1
SMT
1
R7R1
0
5%
EMPTY
402
2
CPU, CLOCKS + EEPROM + STRAPPING
CPU_CLK_DP
46
IN
CPU_CLK_DN
46
IN
CPU_FSB_CLK_SEL
CPU_EXT_CLK_EN
CPU_PLL_BYPASS
2
CPU_TRI GGER_I N
5%10K
CH
CPU_SYS_CONF I G0
CPU_SYS_CONF I G1
OUT
CPU_ANL_1
2
CPU_SPI_SI
4
IN
R6R10
2
1
5.11K
R7R2
0
5%
EMPTY
402
IN
CPU_A NL_1_R
1%
EMPTY402
CPU_ANL_2
CPU_SPARE0
CPU_SPARE1
CPU_TE ST_EN
1
R7R14
10K
5%
CH
402
2
4
IN
4
IN
CPU_SPI_EN
CPU_SPI_CLK
CPU_SPI_SO
C6R46
10UF
10%
6.3V
EMPTY
1206
2
1
2
4
IN
IN
FT2P11
FT2P12
CPU_RST_N
FTP
FTP
CPU_PWRGD
34
34
V_GPUCORE
V_GPUCORE
R6R9
10K
5%
CH
402
R6R8
10K
5%
EMPTY
402
1
R6R6
10K
5%
EMPTY
402
2
1
2
R6R7
10K
5%
CH
402
1
2
1
2
1
2
LAYOUT: MUST BE ACCESSIBLE
V_GPUCORE
1
1
2
1
2
R7R21
10K
5%
CH
402
0
R7R20
10K
5%
EMPTY
402
R7R12
10K
5%
CH
402
2
1
1
R7R5
10K
5%
EMPTY
402
2
56
R7R17
10K
5%
CH
402
OUT
1
1
2
1K
402
2
1K
402
1
2
2
1
2
[PAGE_TITLE=CPU, CLOCKS + EEPROM + STRAPPING]
0
1
2
3
4
V_MEM
AH25
AF16
AK23
AK22
AG18
AF18
AH16
AJ16
AG16
AH10
AJ10
AK10
AK11
AG24
AF24
1
2
AJ2
AK3
AH1
AK9
AK1
AJ1
AH4
B3
R7U3
10K
5%
CH
402
N: STUFF C?,C? WITH ZERO OHM R'S FOR WN
N: STUFF C?,C? WITH .01UF CAPS FOR SHIVA
U7D1
CORE_CLK_DP
CORE_CLK_DN
HARD_RESET_B
POWER_GOOD
FSB_CLK_DP
FSB_CLK_DN
FSB_CLK_SEL
EXT_CLK_EN
PLL_BYPASS
PULSE_LIMIT_BYPASS
TRIGGER_IN
SYS_CONFIG0
SYS_CONFIG1
POST_IN0
POST_IN1
POST_IN2
POST_IN3
POST_IN4
SPI_SI
ANL_1
ANL_2
SPARE0
SPARE1
TE
X02046-002
1OF10
CPU VERSION 20
FSB_HF_CLKOUT_DP
FSB_HF_CLKOUT_DN
FSB_IMPED_CAL_DP
FSB_IMPED_CAL_DN
CORE_IF_BGR_PLL
EFU_POWERON
RESISTOR0_DP
RESISTOR0_DN
VDDS0_DP
VDDS0_DN
VDDS1_DP
VDDS1_DN
PSRO0_OUT
SPI_CLK
SPI_EN
SPI_SO
TEMP_ P
TEMP_ N
J7F1
2X3HDR
1
3
VID0
VID1
VID2
VID3
VID4
VID5
EMPTY
R6E2
1K
402
R7E7
1K
402
R7F2
1K 5%
402
5%
CH
5%
CH
CH
V_MEM
CPU_S P I_CLK_R
CPU_SP I_SO _R
CPU_SP I_EN_ R
2
10K
402
2
10K
402
R7E8
R7F1
5%
CH
5%
EMPTY
IC
CPU_CORE_IF_BGR_PLL
AK17AJ25
VREG_EFUSE_EN
C6
CPU_FSB_HF_CLKOUT_DP
AH22
CPU_FSB_HF_CLKOUT_DN
AJ22
CPU_FSB_IMPED_CAL_DP
AK25
CPU_FSB_IMPED_CAL_DN
AK24
CPU_RES0_DP
AK14
CPU_RES0_DN
AK15
CPU_VDDS0_DP
AH13
CPU_VDDS0_DN
AK12
CPU_VDDS1_DP
AJ4
CPU_VDDS1_DN
AK5
CPU_PSRO0_OUT
AK16
CPU_SPI_CLK
A2
CPU_SPI_EN
B2
CPU_SPI_SO
A3
CPU_TEMP_P
AK20
CPU_TEMP_N
AK21
CPU_VREG_APS0
C4
CPU_VREG_APS1
B5
CPU_VREG_APS2
A4
CPU_VREG_APS3
B4
CPU_VREG_APS4
A5
CPU_VREG_APS5
C5
CPU_SPI_SI
2
CPU_SPI_WP_N
4
65
V_MEM
U7E1
AT25020A
6
SCK
5
SDI
7
HOLD_N*
1
CS_N*
3
WP_N*
X800552-001
1
1
CPU_SPI_WP_N
DRAWING
XENON_FABK
Wed Aug 24 09:27:00 2005
V_GPUCORE
TP7R1
PROBE
1
2
1
2
TP7R2
PROBE
SMT
49
49
49
49
49
49
FT7T5
FT7T4
FT7T3
2
1
V_MEM
1
2
R6E1
10K
5%
CH
402
R7F3
10K
5%
EMPTY
402
1
2
SMT
R7F4
100
5%
CH
402
OUT
R7F7
2
1K
402
PROJECT NAME
XENON_RETAIL
55
OUT
OUT
OUT
TP7R3
PROBE
1
2
TP7R4
SMT
PROBE
1
2
SMT
4
OUT
4
OUT
29
IN
29
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V_MEM
8
CPU_SPI_SI_R
2
4
4
1
FTP
1
FTP
1
FTP
1
C6F1
.1UF
10%
6.3V
2
X5R
402
1
FTP
FT7T2
1
FTP
FT7T1
1
FT7T7
FTP
4
OUT
4
OUT
IC
VCC
SDO
GND
IN
MICROSOFT
CONFIDENTIAL
4
5%
CH
1
2
R6D1
931
1%
CH
402
1
1
R7R9
10K
5%
CH
402
2
CPU_SPI_SI
1
R6D2
1.07K
1%
CH
402
2
DB7R1
TP
1
4
OUT
PAGE
REV
K7
4/73
CPU, FSB
U7D1
FSB_GP_CP0_CLK_DP
12
IN
FSB_GP_CP0_CLK_DN
12
IN
FSB_GP_CP0_FLAG_DP
12
IN
FSB_GP_CP0_FLAG_DN
12
IN
FSB_GP_CP0_DATA0_DP
12
IN
FSB_GP_CP0_DATA0_DN
12
IN
FSB_GP_CP0_DATA1_DP
12
IN
FSB_GP_CP0_DATA1_DN FSB_CP_GP0_DATA1_DN
12 12
IN
FSB_GP_CP0_DATA2_DP
12
IN
FSB_GP_CP0_DATA2_DN FSB_CP_GP0_DATA2_DN
12 12
IN
FSB_GP_CP0_DATA3_DP
12
IN
FSB_GP_CP0_DATA3_DN
12
IN
FSB_GP_CP0_DATA4_DP
12
IN
FSB_GP_CP0_DATA4_DN
12
IN
FSB_GP_CP0_DATA5_DP
12
IN
FSB_GP_CP0_DATA5_DN
12
IN
FSB_GP_CP0_DATA6_DP
12
IN
FSB_GP_CP0_DATA6_DN
12
IN
FSB_GP_CP0_DATA7_DP
12
IN
FSB_GP_CP0_DATA7_DN
12
IN
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
FSB_GP_CP1_CLK_DP
IN
FSB_GP_CP1_CLK_DN
IN
FSB_GP_CP1_FLAG_DP
12
IN
FSB_GP_CP1_FLAG_DN
12
IN
FSB_GP_CP1_DATA0_DP
IN
FSB_GP_CP1_DATA0_DN
IN
FSB_GP_CP1_DATA1_DP
IN
FSB_GP_CP1_DATA1_DN
IN
FSB_GP_CP1_DATA2_DP FSB_CP_GP1_DATA2_DP
IN
FSB_GP_CP1_DATA2_DN
IN
FSB_GP_CP1_DATA3_DP
IN
FSB_GP_CP1_DATA3_DN
IN
FSB_GP_CP1_DATA4_DP
IN
FSB_GP_CP1_DATA4_DN
IN
FSB_GP_CP1_DATA5_DP
IN
FSB_GP_CP1_DATA5_DN
IN
FSB_GP_CP1_DATA6_DP
IN
FSB_GP_CP1_DATA6_DN
IN
FSB_GP_CP1_DATA7_DP
IN
FSB_GP_CP1_DATA7_DN
IN
AD29
AD30
AA29
AA30
AB28
AB27
AB30
AB29
AC29
AC30
Y30
Y29
V28
V27
V30
V29
W29
W30
Y28
Y27
G30
G29
L28
L27
E28
E27
E30
E29
F29
F30
G28
G27
H29
H30
J28
J27
J30
J29
K29
K30
GP_CP0_CLK_DP
GP_CP0_CLK_DN
GP_CP0_FLAG_DP
GP_CP0_FLAG_DN
GP_CP0_DATA0_DP
GP_CP0_DATA0_DN
GP_CP0_DATA1_DP
GP_CP0_DATA1_DN
GP_CP0_DATA2_DP
GP_CP0_DATA2_DN
GP_CP0_DATA3_DP
GP_CP0_DATA3_DN
GP_CP0_DATA4_DP
GP_CP0_DATA4_DN
GP_CP0_DATA5_DP
GP_CP0_DATA5_DN
GP_CP0_DATA6_DP
GP_CP0_DATA6_DN
GP_CP0_DATA7_DP
GP_CP0_DATA7_DN
GP_CP1_CLK_DP
GP_CP1_CLK_DN
GP_CP1_FLAG_DP
GP_CP1_FLAG_DN
GP_CP1_DATA0_DP
GP_CP1_DATA0_DN
GP_CP1_DATA1_DP
GP_CP1_DATA1_DN
GP_CP1_DATA2_DP
GP_CP1_DATA2_DN
GP_CP1_DATA3_DP
GP_CP1_DATA3_DN
GP_CP1_DATA4_DP
GP_CP1_DATA4_DN
GP_CP1_DATA5_DP
GP_CP1_DATA5_DN
GP_CP1_DATA6_DP
GP_CP1_DATA6_DN
GP_CP1_DATA7_DP
GP_CP1_DATA7_DN
X02046-002
2OF10
CPU VERSION 20
CP_GP0_DATA0_DP
CP_GP0_DATA0_DN
CP_GP0_DATA1_DP
CP_GP0_DATA1_DN
CP_GP0_DATA2_DP
CP_GP0_DATA2_DN
CP_GP0_DATA3_DP
CP_GP0_DATA3_DN
CP_GP0_DATA4_DP
CP_GP0_DATA4_DN
CP_GP0_DATA5_DP
CP_GP0_DATA5_DN
CP_GP0_DATA6_DP
CP_GP0_DATA6_DN
CP_GP0_DATA7_DP
CP_GP0_DATA7_DN
CP_GP1_DATA0_DP
CP_GP1_DATA0_DN
CP_GP1_DATA1_DP
CP_GP1_DATA1_DN
CP_GP1_DATA2_DP
CP_GP1_DATA2_DN
CP_GP1_DATA3_DP
CP_GP1_DATA3_DN
CP_GP1_DATA4_DP
CP_GP1_DATA4_DN
CP_GP1_DATA5_DP
CP_GP1_DATA5_DN
CP_GP1_DATA6_DP
CP_GP1_DATA6_DN
CP_GP1_DATA7_DP
CP_GP1_DATA7_DN
CP_GP0_CLK_DP
CP_GP0_CLK_DN
CP_GP0_FLAG_DP
CP_GP0_FLAG_DN
CP_GP1_CLK_DP
CP_GP1_CLK_DN
CP_GP1_FLAG_DP
CP_GP1_FLAG_DN
IC
FSB_CP_GP0_CLK_DP
AG29
FSB_CP_GP0_CLK_DN
AG30
FSB_CP_GP0_FLAG_DP
AK27
FSB_CP_GP0_FLAG_DN
AK28
FSB_CP_GP0_DATA0_DP
AD28
FSB_CP_GP0_DATA0_DN
AD27
FSB_CP_GP0_DATA1_DP
AE29
AE30
FSB_CP_GP0_DATA2_DP
AF30
AF29
FSB_CP_GP0_DATA3_DP
AF27
FSB_CP_GP0_DATA3_DN
AF28
FSB_CP_GP0_DATA4_DP
AH30
FSB_CP_GP0_DATA4_DN
AH29
FSB_CP_GP0_DATA5_DP
AH27
FSB_CP_GP0_DATA5_DN
AH28
FSB_CP_GP0_DATA6_DP
AJ29
FSB_CP_GP0_DATA6_DN
AJ30
FSB_CP_GP0_DATA7_DP
AK30
FSB_CP_GP0_DATA7_DN
AK29
FSB_CP_GP1_CLK_DP
P30
FSB_CP_GP1_CLK_DN
P29
FSB_CP_GP1_FLAG_DP
U30
FSB_CP_GP1_FLAG_DN
U29
FSB_CP_GP1_DATA0_DP
L30
FSB_CP_GP1_DATA0_DN
L29
FSB_CP_GP1_DATA1_DP
M30
FSB_CP_GP1_DATA1_DN
M29
N27
FSB_CP_GP1_DATA2_DN
N28
FSB_CP_GP1_DATA3_DP
N30
FSB_CP_GP1_DATA3_DN
N29
FSB_CP_GP1_DATA4_DP
R27
FSB_CP_GP1_DATA4_DN
R28
FSB_CP_GP1_DATA5_DP
R30
FSB_CP_GP1_DATA5_DN
R29
FSB_CP_GP1_DATA6_DP
T30
FSB_CP_GP1_DATA6_DN
T29
FSB_CP_GP1_DATA7_DP
U27
FSB_CP_GP1_DATA7_DN
U28
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
V_GPUCORE
1
C6T33
.1UF
10%
6.3V
X5R
402
1
C6T32
.1UF
10%
6.3V
2
X5R
402
C6R6
.1UF
10%
6.3V
2
X5R
402
1
1
2
C6R14
.1UF
10%
6.3V
X5R
402
1
1
C6R25
.1UF
10%
6.3V
2
X5R
402
1
C6R37
C6T19
.1UF
.1UF
10%
10%
6.3V
6.3V
2
2
X5R
X5R
402
402
1
1
2
C6T7
.1UF
10%
6.3V
X5R
402
C6T27
.1UF
10%
6.3V
2
2
X5R
402
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
[PAGE_TITLE=CPU, FSB]
DRAWING
XENON_FABK
Wed Aug 24 09:27:01 2005
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAIL
PAGE
5/73
REV
K7
V_CPUPLL
CPU, FSB POWER + PLL POWER
V_1P8
IC
V_GPUCORE
AA27
AB26
AC27
AD26
AE27
AF26
AG27
AH26
AJ27
AK26
B9
B12
B15
B18
B21
B24
B27
C8
C11
C14
C17
C20
C23
C26
D10
D13
D17
D21
D25
D27
D29
E26
F27
G26
H27
J26
K27
L26
M27
N26
P27
R26
T27
U26
V26
W27
Y26
AJ19
AH19
AK19
AK18
AF22
AG22
AF20
AG20
AK13
AJ13
AK6
A6
B6
U7D1
VDD_IO
VDDE
VDDE_SEC
CORE_HF_VDDA_PLL
CORE_HF_GNDA_PLL
CORE_IF_VDDA_PLL
CORE_IF_GNDA_PLL
FSB_HF_VDDA_PLL
FSB_HF_GNDA_PLL
FSB_IF_VDDA_PLL
FSB_IF_GNDA_PLL
VDDA_RNG
GNDA_RNG
X02046-002
FB7R1
2
1
1K
0.2AFB603
C7R1
.1UF
10%
6.3V
X5R
402
C6D1
.1UF
10%
6.3V
X5R
402
C6R2
.1UF
10%
6.3V
X5R
402
C6R3
.1UF
10%
6.3V
X5R
402
C7D1
1UF
10%
50V
EMPTY
603
0.7DCR
0.7DCR
0.7DCR
0.7DCR
0.7DCR
1
C7R7
2.2UF
10%
6.3V
2
X5R
ST7R1
1
SHORT
FB6D1
1
1K
0.2A
ST6D1
1
SHORT
FB6R1
1
1K
0.2A
ST6R1
1
SHORT
FB6R2
1
1K
0.2A
ST6R2
1
SHORT
FB7D1
1
1K
0.2A
ST7D1
1
SHORT
603
2
2
FB
603
1
C6D4
2.2UF
10%
6.3V
2
X5R
603
2
2
FB
603
1
C6R4
2.2UF
10%
6.3V
2
X5R
603
2
2
FB
603
1
C6R5
2.2UF
10%
6.3V
2
X5R
603
2
2
FB
603
1
C7D2
2.2UF
10%
6.3V
2
X5R
603
2
1
2
1
2
1
2
1
2
1
2
1
2
C7R115
.1UF
10%
6.3V
X5R
402
V_EFUSE
1
2
C7R116
.1UF
10%
6.3V
X5R
402
1
C7R114
.1UF
10%
6.3V
2
X5R
402
R7T2
2
1
5%
10K
CH
402
V_CPU_ CORE_HF _VDDA_ PLL
V_CPU_ CORE_HF _GNDA_ PLL
V_CPU_ CORE_I F_VDDA _PL L
V_CPU_ CORE_I F_GNDA _PL L
V_CPU_ FSB_ HF_VDDA _PL L
V_CPU_ FSB_ HF_GNDA _PL L
V_CPU_ FSB_ IF_ VDDA_P LL
V_CPU_ FSB_ IF_ GNDA_PL L
V_CPU_ VDDA_ RNG
V_CPU_ GNDA_RNG
CPU_VDDE
4of 10
CPU VERSION 20
VDD_FSB0
VDD_FSB1
VDD_FSB2
VDD_FSB3
VDD_FSB4
VDD_FSB5
VDD_FSB6
VDD_FSB7
VDD_FSB8
VDD_FSB9
VDD_FSB10
VDD_FSB11
VDD_FSB12
VDD_FSB13
VDD_FSB14
VDD_FSB15
VDD_FSB16
VDD_FSB17
VDD_FSB18
VDD_FSB19
VDD_FSB20
VDD_FSB21
VDD_FSB22
VDD_FSB23
VDD_FSB24
VDD_FSB25
VDD_FSB26
VDD_FSB27
VDD_FSB28
VDD_FSB29
VDD_FSB30
VDD_FSB31
VDD_FSB32
VDD_FSB33
VDD_FSB34
VDD_FSB35
VDD_FSB36
VDD_FSB37
VDD_FSB38
VDD_FSB39
VDD_FSB40
VDD_FSB41
VDD_FSB42
VDD_FSB43
VDD_FSB44
VDD_FSB45
VDD_FSB46
[PAGE_TITLE=CPU, FSB POWER + PLL POWER]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:01 2005
PAGE
6/73
REV
K7
CPU, CORE POWER
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA24
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC24
AD11
AD13
AD15
AD17
AD19
AD21
AA2
AA4
AA6
AA8
AB1
AB3
AB5
AB7
AB9
AC2
AC4
AC6
AC8
AD1
AD3
AD5
AD7
AD9
U7D1
5of 10
CPU VERSION 20
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
X02046-002
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
VDD93
VDD94
VDD95
IC
AD23
AD25
AE2
AE4
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE22
AE24
AF1
AF3
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF23
AF25
AG2
AG4
AG6
AG8
AG10
AG12
AG14
AH3
AH6
AH9
AH12
AH15
AJ5
AJ8
AJ11
AJ14
B1
C2
D1
D3
D5
D7
D9
E2
E4
E6
E8
E10
F1
F3
F5
F7
F9
F11
G2
G4
G6
G8
G10
G12
G14
G16
G18
G20
G22
G24
H1
H3
H5
H7
H9
H11
H13
H15
H17
H19
H21
H23
H25
J2
J4
J6
J8
J10
J12
J14
J16
J18
U7D1
6of 10
CPU VERSION 20
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD134
VDD135
VDD136
VDD137
VDD138
VDD139
VDD140
VDD141
VDD142
X02046-002
VDD143
VDD144
VDD145
VDD146
VDD147
VDD148
VDD149
VDD150
VDD151
VDD152
VDD153
VDD154
VDD155
VDD156
VDD157
VDD158
VDD159
VDD160
VDD161
VDD162
VDD163
VDD164
VDD165
VDD166
VDD167
VDD168
VDD169
VDD170
VDD171
VDD172
VDD173
VDD174
VDD175
VDD176
VDD177
VDD178
VDD179
VDD180
VDD181
VDD182
VDD183
VDD184
VDD185
VDD186
VDD187
VDD188
VDD189
V_CPUCOREV_CPUCOREV_CPUCORE V_CPUCORE V_CPUCOREV_CPUCORE
IC
J20
J22
J24
K1
K3
K5
K7
K9
K11
K13
K15
K17
K19
K21
K23
K25
L2
L4
L6
L8
L10
L12
L14
L16
L18
L20
L22
L24
M1
M3
M5
M7
M9
M11
M13
M15
M17
M19
M21
M23
M25
N2
N4
N6
N8
N10
N12
N14
N16
N18
N20
N22
N24
P1
P3
P5
P7
P9
P11
P13
P15
P17
P19
P21
P23
P25
R2
R4
R6
R8
R10
R12
R14
R16
R18
R20
R22
R24
T1
T3
T5
T7
T9
T11
T13
T15
T17
T19
T21
T23
T25
U2
U4
U6
U7D1
7of 10
CPU VERSION 20
VDD190
VDD191
VDD192
VDD193
VDD194
VDD195
VDD196
VDD197
VDD198
VDD199
VDD200
VDD201
VDD202
VDD203
VDD204
VDD205
VDD206
VDD207
VDD208
VDD209
VDD210
VDD211
VDD212
VDD213
VDD214
VDD215
VDD216
VDD217
VDD218
VDD219
VDD220
VDD221
VDD222
VDD223
VDD224
VDD225
VDD226
VDD227
VDD228
VDD229
VDD230
VDD231
VDD232
VDD233
VDD234
VDD235
VDD236
X02046-002
VDD237
VDD238
VDD239
VDD240
VDD241
VDD242
VDD243
VDD244
VDD245
VDD246
VDD247
VDD248
VDD249
VDD250
VDD251
VDD252
VDD253
VDD254
VDD255
VDD256
VDD257
VDD258
VDD259
VDD260
VDD261
VDD262
VDD263
VDD264
VDD265
VDD266
VDD267
VDD268
VDD269
VDD270
VDD271
VDD272
VDD273
VDD274
VDD275
VDD276
VDD277
VDD278
VDD279
VDD280
VDD281
VDD282
VDD283
IC
U8
U10
U12
U14
U16
U18
U20
U22
U24
V1
V3
V5
V7
V9
V11
V13
V15
V17
V19
V21
V23
V25
W2
W4
W6
W8
W10
W12
W14
W16
W18
W20
W22
W24
Y1
Y3
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
[PAGE_TITLE=CPU, CORE POWER]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:01 2005
PAGE
7/73
REV
K7
CPU, POWER
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA26
AA28
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AC25
AC26
AC28
AD10
AD12
AD14
AD16
AD18
AD20
AD22
AD24
AA1
AA3
AA5
AA7
AA9
AB2
AB4
AB6
AB8
AC1
AC3
AC5
AC7
AC9
AD2
AD4
AD6
AD8
AE1
AE3
AE5
AE7
U7D1
8of 10
CPU VERSION 20
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
X02046-002
VSS58VSS0
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
B14
B17
B20
B23
B26
B29
C1
C3
C9
C12
C15
C18
C21
C24
C27
D2
D4
D6
D8
D11
D15
D19
D23
D26
D28
D30
E1
E3
E5
E7
E9
F2
F4
F6
F8
F10
F12
F14
F16
F18
F20
F22
F24
F26
F28
G1
G3
G5
G7
G9
G11
G13
G15
G17
G19
G21
G23
G25
U7D1
9of 10
CPU VERSION 20
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
X02046-002
IC
AE9
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE26
AE28
AF2
AF4
AF6
AF8
AF10
AF12
AF14
AG1
AG3
AG5
AG7
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AG25
AG26
AG28
AH2
AH5
AH8
AH11
AH14
AH17
AH18
AH20
AH21
AH23
AH24
AJ3
AJ6
AJ9
AJ12
AJ15
AJ17
AJ18
AJ20
AJ21
AJ23
AJ24
AJ26
AJ28
B8
B11
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
IC
H2
H4
H6
H8
H10
H12
H14
H16
H18
H20
H22
H24
H26
H28
J1
J3
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
J25
K2
K4
K6
K8
K10
K12
K14
K16
K18
K20
K22
K24
K26
K28
L1
L3
L5
L7
L9
L11
L13
L15
L17
L19
L21
L23
L25
M2
M4
M6
M8
M10
M12
M14
M16
M18
M20
M22
M24
M26
M28
N1
N3
N5
N7
N9
N11
N13
N15
N17
N19
N21
N23
N25
P2
P4
P6
P8
P10
P12
P14
P16
P18
P20
P22
P24
P26
P28
R1
R3
R5
R7
R9
R11
R13
R15
R17
R19
R21
R23
R25
T2
T4
T6
T8
T10
T12
T14
T16
U7D1
10 of 10
CPU VERSION 20
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS290
X02046-002
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
IC
T18
T20
T22
T24
T26
T28
U1
U3
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
U25
V2
V4
V6
V8
V10
V12
V14
V16
V18
V20
V22
V24
W1
W3
W5
W7
W9
W11
W13
W15
W17
W19
W21
W23
W25
W26
W28
Y2
Y4
Y6
Y8
Y10
Y12
Y14
Y16
Y18
Y20
Y22
Y24
[PAGE_TITLE=CPU, POWER]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:02 2005
PAGE
8/73
REV
K7
V_CPUCORE
V_CPUCORE
CPU, DECOUPLING
C7D21
1
6.3V
X5R
805
C7T94
1
6.3V
X5R
805
C7T101
1
6.3V
X5R
805
C7T87
1
6.3V
X5R
805
C7R2
1
6.3V
X5R
805
C7E3
1
6.3V
X5R
805
C7T32
1
6.3V
X5R
805
C7R28
1
6.3V
X5R
805
C7D20
1
6.3V
X5R
805
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
C7R122
1
6.3V
X5R
805
C7E8
1
6.3V
X5R
805
C7E14
1
6.3V
X5R
805
C7T93
1
6.3V
X5R
805
C7D16
1
6.3V
X5R
805
C7E12
1
6.3V
X5R
805
C7E10
1
6.3V
X5R
805
C7E11
1
6.3V
X5R
805
C7T33
1
6.3V
X5R
805
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
C7T85
1
6.3V
X5R
805
C7E6
1
6.3V
X5R
805
C7D12
1
6.3V
X5R
805
C7D19
1
6.3V
X5R
805
C7T36
1
6.3V
X5R
805
C7R118
1
6.3V
X5R
805
C7E5
1
6.3V
X5R
805
C7D14
1
6.3V
X5R
805
C7R121
1
6.3V
X5R
805
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
C7R6
1
6.3V
X5R
805
C7R94
1
6.3V
X5R
805
C7E1
1
6.3V
X5R
805
C7R119
1
6.3V
X5R
805
C7E7
1
6.3V
X5R
805
C7D13
1
6.3V
X5R
805
C7T83
1
6.3V
X5R
805
C7D11
1
6.3V
X5R
805
C7T84
1
6.3V
X5R
805
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
C7D9
1
6.3V
C7R5
1
6.3V
C7T34
1
6.3V
C7R26
1
6.3V
C7R117
1
6.3V
C7T96
1
6.3V
C7R92
1
6.3V
C7D6
1
6.3V
C7D17
1
6.3V
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
2
10%4.7UF
X5R
805
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
C7R27
1
1
1
C7D18
1
1
C7E16
1
C7R91
1
C7R29
1
1
6.3V
X5R
805
C7D8
6.3V
X5R
805
C7D4
6.3V
X5R
805
6.3V
X5R
805
C7D7
6.3V
X5R
805
6.3V
X5R
805
6.3V
X5R
805
6.3V
X5R
805
C7E4
6.3V
X5R
805
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
C7D10
1
6.3V
X5R
805
C7R4
1
6.3V
X5R
805
C7T35
1
6.3V
X5R
805
C7D5
1
6.3V
X5R
805
C7R93
1
6.3V
X5R
805
C7T95
1
6.3V
X5R
805
C7D3
1
6.3V
X5R
805
C7R120
1
6.3V
X5R
805
C7D15
1
6.3V
X5R
805
10%
10%
10%
10%
10%
10%
10%
10%
10%
2
2
2
2
2
2
2
2
2
1
C7R30
1
C7R90
1
1
C7E15
1
1
C7T86
1
C7T97
1
C7D22
1
C7R3
6.3V
X5R
805
6.3V
X5R
805
6.3V
X5R
805
C7E2
6.3V
X5R
805
6.3V
X5R
805
C7E9
6.3V
X5R
805
6.3V
X5R
805
6.3V
X5R
805
6.3V
X5R
805
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
2
10%4.7UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
C7T79
1
C7T78
1
C7T77
1
C7T76
1
C7T88
1
C7R12
1
C7R10
1
C7R11
1
C7R13
1
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
.1UF
.1UF
.1UF
1
C7T45
1
C7R16
1
C7T1
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
2
10%
2
10%
2
10%
[PAGE_TITLE=CPU, DECOUPLING]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:03 2005
PAGE
9/73
REV
K7
V_CPUCORE
CPU, DECOUPLING
C7R36
1
.1UF 10%
6.3V
X5R
402
C7R22
1
.1UF 10%
6.3V
X5R
402
C7R23
1
.1UF 10%
6.3V
X5R
402
C7R24
1
6.3V
X5R
402
C7R25
1
.1UF 10%
6.3V
X5R
402
C7R38
1
.1UF
6.3V
X5R
402
C7R37
1
.1UF
6.3V
X5R
402
C7R44
1
.1UF 10%
6.3V
X5R
402
C6R11
1
.1UF 10%
6.3V
X5R
402
C7R46
1
.1UF
6.3V
X5R
402
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
1
1
1
1
1
1
1
1
1
1
C7T20
6.3V
X5R
402
C7T22
6.3V
X5R
402
C7T27
6.3V
X5R
402
C7R48
6.3V
X5R
402
C6T4
6.3V
X5R
402
C7T37
6.3V
X5R
402
C7R89
6.3V
X5R
402
C6T25
6.3V
X5R
402
C7R99
6.3V
X5R
402
C6T23
6.3V
X5R
402
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
2
2
2
2
2
2
2
2
2
2
C6R44
1
.1UF
6.3V
C6T2
1
.1UF
6.3V
C6T1
1
.1UF
6.3V
C6R43
1
.1UF
6.3V
C7R102
1
.1UF
6.3V
C7R81
1
.1UF
6.3V
C6R36
1
.1UF
6.3V
C7T81
1
.1UF
6.3V
C7R100
1
.1UF
6.3V
C7R74
1
.1UF
6.3V
2
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
C6T10
1
.1UF 10%
6.3V
X5R
402
C7T19
1
10%
.1UF
6.3V
X5R
402
C7R66
1
10%
.1UF
6.3V
X5R
402
C7R111
1
.1UF 10%
6.3V
X5R
402
C7R110
1
10%
.1UF
6.3V
X5R
402
C7T2
1
.1UF 10%
6.3V
X5R
402
C6R35
1
10%
.1UF
6.3V
X5R
402
C7T10
1
.1UF
10%
6.3V
X5R
402
C6R39
1
.1UF 10%
6.3V
X5R
402
C6R18
1
.1UF 10%
6.3V
X5R
402
2
2
2
2
2
2
2
2
2
2
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
C7T21
1
C7T71
1
C6R42
1
C7R67
1
1
1
C7T82
1
C6R40
1
C6R38
1
C6R34
1
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
C7T3
6.3V
X5R
402
C7T5
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
2
2
2
10%.1UF
2
2
10%
2
10%
2
2
2
10%
C7R62
2
1
10% 10%
.1UF
6.3V
X5R
402
C7R78
2
1
10%
.1UF
6.3V
X5R
402
C7R70
2
1
.1UF
10%
6.3V
X5R
402
C7R53
2
1
10%
.1UF
6.3V
X5R
402
C7R47
2
1
10%
.1UF
6.3V
X5R
402
C7R63
2
1
.1UF
10%
6.3V
X5R
402
C7R79
2
1
10%
.1UF
6.3V
X5R
402
C7R77
2
1
.1UF
10%
6.3V
X5R
402
C6R17
2
1
10%
.1UF
6.3V
X5R
402
C7R45
2
1
10%
.1UF
6.3V
X5R
402
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
C7R49
1
C7R72
1
C6R29
1
C6R28
1
C6R27
1
C7R76
1
C7T15
1
C7R64
1
C7R71
1
C7R84
1
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
C7T9
1
.1UF 10%
6.3V
X5R
402
C7R55
1
.1UF 10%
6.3V
X5R
402
C7R35
1
.1UF
6.3V
X5R
402
C7R34
1
.1UF 10%
6.3V
X5R
402
C7R19
1
.1UF 10%
6.3V
X5R
402
C7R43
1
.1UF 10%
6.3V
X5R
402
C6R16
1
.1UF
6.3V
X5R
402
C6R19
1
.1UF 10%
6.3V
X5R
402
C7R61
1
.1UF 10%
6.3V
X5R
402
C7R54
1
.1UF
6.3V
X5R
402
2
2
2
10%
2
2
2
2
10%
2
2
2
10%
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
1
1
1
1
1
1
1
1
1
1
C7R80
6.3V
X5R
402
C6R32
6.3V
X5R
402
C6R31
6.3V
X5R
402
C6T5
6.3V
X5R
402
C7R68
6.3V
X5R
402
C7R69
6.3V
X5R
402
C7R57
6.3V
X5R
402
C6R20
6.3V
X5R
402
C6R21
6.3V
X5R
402
C6T26
6.3V
X5R
402
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
2
2
2
2
2
2
2
2
2
2
C7R52
1
.1UF
10%
6.3V
X5R
402
C7R51
1
.1UF 10%
6.3V
X5R
402
C7R50
1
.1UF 10%
6.3V
X5R
402
C6T6
1
10%.1UF
6.3V
X5R
402
C6R22
1
.1UF
10%
6.3V
X5R
402
C6R23
1
.1UF 10%
6.3V
X5R
402
C7R58
1
.1UF
10%
6.3V
X5R
402
C7R59
1
.1UF 10%
6.3V
X5R
402
C7R60
1
.1UF 10%
6.3V
X5R
402
C6R30
1
.1UF 10%
6.3V
X5R
402
2
2
2
2
2
2
2
2
2
2
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
C7T69
1
C7T70
1
C7T75
1
C7T74
1
C7T73
1
C7T72
1
C6R33
1
C7R88
1
C6R45
1
1
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
C7T8
6.3V
X5R
402
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
[PAGE_TITLE=CPU, DECOUPLING]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
N: EMPTY FOR
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:03 2005
CPU SOCKET
PAGE
10/73
REV
K7
V_CPUCORE
CPU, DECOUPLING
C7R31
1
.1UF
6.3V
X5R
402
C7T12
1
.1UF 10%
6.3V
X5R
402
C7R82
1
.1UF 10%
6.3V
X5R
402
C7R56
1
.1UF 10%
6.3V
X5R
402
C6R26
1
.1UF 10%
6.3V
X5R
402
C6T9
1
.1UF 10%
6.3V
X5R
402
C6T3
1
.1UF
6.3V
X5R
402
C7R21
1
.1UF 10%
6.3V
X5R
402
C7R107
1
.1UF 10%
6.3V
X5R
402
C6R13
1
.1UF 10%
6.3V
X5R
402
2
10%
2
2
2
2
2
2
10%
2
2
2
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
C6T11
1
6.3V
C7R17
1
6.3V
C7R18
1
6.3V
C7R20
1
6.3V
C7R42
1
6.3V
C7R41
1
6.3V
C7R40
1
6.3V
C7R39
1
6.3V
C6T21
1
6.3V
C6R12
1
6.3V
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
C7T38
1
C7R65
1
C6T14
1
C7T28
1
C7T31
1
C6R10
1
1
C7R15
1
C7R33
1
C7R32
1
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
C7R8
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
6.3V
X5R
402
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
2
2
2
2
2
2
2
2
2
2
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
C7T58
6.3V
X5R
402
C6R24
6.3V
X5R
402
C7T56
6.3V
X5R
402
C7R98
6.3V
X5R
402
C6T8
6.3V
X5R
402
C7T17
6.3V
X5R
402
C7T41
6.3V
X5R
402
C6T12
6.3V
X5R
402
C6R15
6.3V
X5R
402
C6R41
6.3V
X5R
402
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
C7T30
2
1
10%.1UF
6.3V
X5R
402
C7T29
2
1
10%
.1UF .1UF
6.3V
X5R
402
C7T50
2
1
.1UF 10%
6.3V
X5R
402
C7R106
2
1
10%
.1UF
6.3V
X5R
402
C6T20
2
1
.1UF 10%
6.3V
X5R
402
C7T49
2
1
.1UF 10%
6.3V
X5R
402
C6T22
2
1
.1UF 10%
6.3V
X5R
402
C7T13
2
1
10%.1UF
6.3V
X5R
402
C7R14
2
1
10%.1UF
6.3V
X5R
402
C7R9
2
1
10%.1UF
6.3V
X5R
402
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
1
1
1
1
1
1
1
1
1
1
C7T54
6.3V
X5R
402
C6T24
6.3V
X5R
402
C7T53
6.3V
X5R
402
C7T52
6.3V
X5R
402
C6R9
6.3V
X5R
402
C6R7
6.3V
X5R
402
C7T61
6.3V
X5R
402
C7T60
6.3V
X5R
402
C7T59
6.3V
X5R
402
C7R86
6.3V
X5R
402
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
2
2
2
2
2
2
2
2
2
2
C6T13
1
.1UF
6.3V
C7T14
1
.1UF
6.3V
C7T80
1
.1UF
6.3V
C7T11
1
.1UF
6.3V
C7T40
1
.1UF
6.3V
C7R75
1
.1UF
6.3V
C7R85
1
.1UF
6.3V
C7R101
1
.1UF
6.3V
C6R8
1
.1UF
6.3V
C7R73
1
.1UF
6.3V
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
C7R95
1
.1UF 10%
6.3V
X5R
402
C7R103
1
10%.1UF
6.3V
X5R
402
C7R104
1
.1UF 10%
6.3V
X5R
402
C7R96
1
.1UF 10%
6.3V
X5R
402
C7R108
1
.1UF 10%
6.3V
X5R
402
C7R109
1
.1UF 10%
6.3V
X5R
402
C7R105
1
.1UF 10%
6.3V
X5R
402
C7T4
1
.1UF 10%
6.3V
X5R
402
C6T18
1
.1UF 10%
6.3V
X5R
402
C7T16
1
.1UF 10%
6.3V
X5R
402
2
.1UF
2
2
.1UF
2
.1UF
2
.1UF
2
.1UF
2
.1UF
2
.1UF
2
.1UF
2
.1UF
C7T51
1
C7T47
1
C7T46
1
C7R97
1
C7T57
1
C7T55
1
C7T18
1
C7T39
1
C7T26
1
C7T48
1
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
2
10%
6.3V
X5R
402
C6T15
1
.1UF 10%
6.3V
X5R
402
C6T16
1
.1UF 10%
6.3V
X5R
402
C7T43
1
.1UF 10%
6.3V
X5R
402
C7T44
1
.1UF 10%
6.3V
X5R
402
C7T42
1
.1UF 10%
6.3V
X5R
402
C7R83
1
.1UF 10%
6.3V
X5R
402
C7T24
1
.1UF 10%
6.3V
X5R
402
C7T25
1
6.3V
X5R
402
C6T17
1
.1UF 10%
6.3V
X5R
402
C7T23
1
.1UF 10%
6.3V
X5R
402
2
2
2
2
2
2
2
2
2
2
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF.1UF 10%
.1UF
.1UF
1
1
1
1
1
1
1
1
1
1
C6T28
6.3V
X5R
402
C6T29
6.3V
X5R
402
C6T30
6.3V
X5R
402
C7T62
6.3V
X5R
402
C7T63
6.3V
X5R
402
C7T64
6.3V
X5R
402
C7T65
6.3V
X5R
402
C7T66
6.3V
X5R
402
C7T67
6.3V
X5R
402
C7T68
6.3V
X5R
402
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
[PAGE_TITLE=CPU, DECOUPLING]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:05 2005
PAGE
11/73
REV
K7
V_GPUCORE
1
R5R1
1K
5%
EMPTY
402
2
1
R5R2
1K
5%
CH
402
2
GPU, FSB
R5C12
2
1
5%1K
CH
402
R5C11
2
1
1K
5%
CH
402
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
FSB_CP_GP0_CLK_DP
IN
FSB_CP_GP0_CLK_DN
IN
FSB_CP_GP0_FLAG_DP
IN
FSB_CP_GP0_FLAG_DN
IN
FSB_CP_GP0_DATA0_DP
IN
FSB_CP_GP0_DATA0_DN
IN
FSB_CP_GP0_DATA1_DP
IN
FSB_CP_GP0_DATA1_DN
IN
FSB_CP_GP0_DATA2_DP
IN
FSB_CP_GP0_DATA2_DN
IN
FSB_CP_GP0_DATA3_DP
IN
FSB_CP_GP0_DATA3_DN
IN
FSB_CP_GP0_DATA4_DP
IN
FSB_CP_GP0_DATA4_DN
IN
FSB_CP_GP0_DATA5_DP
IN
FSB_CP_GP0_DATA5_DN
IN
FSB_CP_GP0_DATA6_DP
IN
FSB_CP_GP0_DATA6_DN
IN
FSB_CP_GP0_DATA7_DP
IN
FSB_CP_GP0_DATA7_DN
IN
FSB_CP_GP1_CLK_DP
IN
FSB_CP_GP1_CLK_DN
IN
FSB_CP_GP1_FLAG_DP
IN
FSB_CP_GP1_FLAG_DN
IN
FSB_CP_GP1_DATA0_DP
IN
FSB_CP_GP1_DATA0_DN
IN
FSB_CP_GP1_DATA1_DP
IN
FSB_CP_GP1_DATA1_DN
IN
FSB_CP_GP1_DATA2_DP
IN
FSB_CP_GP1_DATA2_DN
IN
FSB_CP_GP1_DATA3_DP
IN
FSB_CP_GP1_DATA3_DN
IN
FSB_CP_GP1_DATA4_DP
IN
FSB_CP_GP1_DATA4_DN
IN
FSB_CP_GP1_DATA5_DP
IN
FSB_CP_GP1_DATA5_DN
IN
FSB_CP_GP1_DATA6_DP
IN
FSB_CP_GP1_DATA6_DN
IN
FSB_CP_GP1_DATA7_DP
IN
FSB_CP_GP1_DATA7_DN
IN
FSB_BYPCLK_DP
FSB_BYPCLK_DN
FSB_BYPCLK_SEL
1
R5R3
4.87K
1%
CH
402
2
FSB_IMPED_CAL
FSB_IMPED_NCAL
AA31
AA32
AA28
B29
A29
D25
J34
J33
J30
J29
M29
M30
L32
L31
K33
K34
L30
L29
J31
J32
K30
K29
H34
H33
H31
H32
V33
V34
T33
T34
Y33
Y34
W30
W29
W33
W34
V29
V28
V31
V32
U33
U34
U30
U29
T28
U4D1
FSB_BYPCLK_DP
FSB_BYPCLK_DN
FSB_BYPCLK_SEL
CP_GP0_CLK_DP
CP_GP0_CLK_DN
CP_GP0_FLAG_DP
CP_GP0_FLAG_DN
CP_GP0_DATA0_DP
CP_GP0_DATA0_DN
CP_GP0_DATA1_DP
CP_GP0_DATA1_DN
CP_GP0_DATA2_DP
CP_GP0_DATA2_DN
CP_GP0_DATA3_DP
CP_GP0_DATA3_DN
CP_GP0_DATA4_DP
CP_GP0_DATA4_DN
CP_GP0_DATA5_DP
CP_GP0_DATA5_DN
CP_GP0_DATA6_DP
CP_GP0_DATA6_DN
CP_GP0_DATA7_DP
CP_GP0_DATA7_DN
CP_GP1_CLK_DP
CP_GP1_CLK_DN
CP_GP1_FLAG_DP
CP_GP1_FLAG_DN
CP_GP1_DATA0_DP
CP_GP1_DATA0_DN
CP_GP1_DATA1_DP
CP_GP1_DATA1_DN
CP_GP1_DATA2_DP
CP_GP1_DATA2_DN
CP_GP1_DATA3_DP
CP_GP1_DATA3_DN
CP_GP1_DATA4_DP
CP_GP1_DATA4_DN
CP_GP1_DATA5_DP
CP_GP1_DATA5_DN
CP_GP1_DATA6_DP
CP_GP1_DATA6_DN
CP_GP1_DATA7_DP
CP_GP1_DATA7_DN
FSB_IMPED_PCAL
FSB_IMPED_NCAL
X02056-010
V_GPUCORE
C4R27 C4R33 C4R45 C4T22 C5R18 C4R65 C4R60 C4T13
.1UF
.1UF
10%
10%
6.3V
6.3V
X5R
X5R
402
402
1OF8
GPU VERSION 57
FSB DECOUPLING
.1UF
.1UF
10%
10%
6.3V
6.3V
X5R
X5R
402
402
GP_CP0_CLK_DP
GP_CP0_CLK_DN
GP_CP0_FLAG_DP
GP_CP0_FLAG_DN
GP_CP0_DATA0_DP
GP_CP0_DATA0_DN
GP_CP0_DATA1_DP
GP_CP0_DATA1_DN
GP_CP0_DATA2_DP
GP_CP0_DATA2_DN
GP_CP0_DATA3_DP
GP_CP0_DATA3_DN
GP_CP0_DATA4_DP
GP_CP0_DATA4_DN
GP_CP0_DATA5_DP
GP_CP0_DATA5_DN
GP_CP0_DATA6_DP
GP_CP0_DATA6_DN
GP_CP0_DATA7_DP
GP_CP0_DATA7_DN
GP_CP1_CLK_DP
GP_CP1_CLK_DN
GP_CP1_FLAG_DP
GP_CP1_FLAG_DN
GP_CP1_DATA0_DP
GP_CP1_DATA0_DN
GP_CP1_DATA1_DP
GP_CP1_DATA1_DN
GP_CP1_DATA2_DP
GP_CP1_DATA2_DN
GP_CP1_DATA3_DP
GP_CP1_DATA3_DN
GP_CP1_DATA4_DP
GP_CP1_DATA4_DN
GP_CP1_DATA5_DP
GP_CP1_DATA5_DN
GP_CP1_DATA6_DP
GP_CP1_DATA6_DN
GP_CP1_DATA7_DP
GP_CP1_DATA7_DN
.1UF
10%
6.3V
X5R
402
.1UF
10%
6.3V
X5R
402
IC
P33
P34
L34
L33
T29
T30
T31
T32
R34
R33
R29
R30
N34
N33
P29
P30
N31
N32
M34
M33
AC33
AC34
Y29
Y30
AC28
AC29
AD29
AD30
AD34
AD33
AB29
AB30
AC32
AC31
AA29
AA30
AB33
AB34
AA34
AA33
.1UF
10%
6.3V
X5R
402
FSB_GP_CP0_CLK_DP
FSB_GP_CP0_CLK_DN
FSB_GP_CP0_FLAG_DP
FSB_GP_CP0_FLAG_DN
FSB_GP_CP0_DATA0_DP
FSB_GP_CP0_DATA0_DN
FSB_GP_CP0_DATA1_DP
FSB_GP_CP0_DATA1_DN
FSB_GP_CP0_DATA2_DP
FSB_GP_CP0_DATA2_DN
FSB_GP_CP0_DATA3_DP
FSB_GP_CP0_DATA3_DN
FSB_GP_CP0_DATA4_DP
FSB_GP_CP0_DATA4_DN
FSB_GP_CP0_DATA5_DP
FSB_GP_CP0_DATA5_DN
FSB_GP_CP0_DATA6_DP
FSB_GP_CP0_DATA6_DN
FSB_GP_CP0_DATA7_DP
FSB_GP_CP0_DATA7_DN
FSB_GP_CP1_CLK_DP
FSB_GP_CP1_CLK_DN
FSB_GP_CP1_FLAG_DP
FSB_GP_CP1_FLAG_DN
FSB_GP_CP1_DATA0_DP
FSB_GP_CP1_DATA0_DN
FSB_GP_CP1_DATA1_DP
FSB_GP_CP1_DATA1_DN
FSB_GP_CP1_DATA2_DP
FSB_GP_CP1_DATA2_DN
FSB_GP_CP1_DATA3_DP
FSB_GP_CP1_DATA3_DN
FSB_GP_CP1_DATA4_DP
FSB_GP_CP1_DATA4_DN
FSB_GP_CP1_DATA5_DP
FSB_GP_CP1_DATA5_DN
FSB_GP_CP1_DATA6_DP
FSB_GP_CP1_DATA6_DN
FSB_GP_CP1_DATA7_DP
FSB_GP_CP1_DATA7_DN
.1UF
10%
6.3V
X5R
402
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
MEM_SCAN_EN _BUFF
13
IN
MEM_SCAN_TOP_EN_BUFF
13
IN
MEM_SCAN_BOT_EN_BUFF
13 21
IN
1
.1UF
1
.1UF
1
.1UF
C2E4
6.3V
X5R
402
C2R12
6.3V
X5R
402
C2D5
6.3V
X5R
402
10%
10%
10%
V_MEM
2
V_MEM
2
V_MEM
2
R2E5
1
0
5%
402
CH
U2E2
EMPTY
SN74LVC1G125
5
VCC
2
IN
3
GND OE_N
X801565-001
R2D12
1
5%
0
402
CH
U2D1
EMPTY
SN74LVC1G125
5
VCC
2
IN
3
GND OE_N
X801565-001
R2R6
1
5%
0
CH
402
U2R1
EMPTY
SN74LVC1G125
5
VCC
2
IN
3
GND OE_N
X801565-001
13
GPU_SCAN_BUF F_EN_N
IN
V_MEM
2
OUT
1
R2R5
0
5%
CH
402
2
4
1
MEM_SCAN_EN
1
1
R4F8
1K
5%
CH
402
2
2
R2D11
1K
5%
CH
402
OUT
27
26
202122
23 24 25
2
MEM_SCAN_TOP_EN
4
OUT
1
1
1
R4F7
R2T2
1K
1K
5%
5%
CH
CH
402
2
402
2
OUT
20 22 24
26
V_MEM
2
1
1
R4U6
R2T1
1K
1K
5%
5%
CH
CH
402
402
2
4
OUT
1
MEM_SCAN_BOT_EN
2
23 25
OUT
27
[PAGE_TITLE=GPU, FSB]
DRAWING
XENON_FABK
Wed Aug 24 09:27:06 2005
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAIL
PAGE
12/73
REV
K7
R4D3
2
1
49.9
1%
EMPTY
402
R4D4
2
1
1%
49.9
FT2P14
34 34
IN
33
33
33
33
R5D1
2
1
562
1%
402
CH
1
1.47K
402
1
GPU_RST_N GPU_RST_DONE
IN
IN
IN
IN
PEX_SB_GPU_L1_DP
PEX_SB_GPU_L1_DN
PEX_SB_GPU_L0_DP
PEX_SB_GPU_L0_DN
PEX_PCAL
V_GPUPCIE
R4R3
2
PEX_ICAL
1%
CH
28
28
29
29
29
29
R3C28
1
1.27K
402
R4T1
1
40.2
402
V_MEM
1
R2E2
1.5K
1%
CH
J2D2
402
2X4HDR
2
1
3
R2D10
1.5K
1%
CH
402
7
EMPTY
1
2
GPU_SCAN_BUFF_EN_N
46
46
ANA_PIX_CLK_2X_DP
IN
ANA_PIX_CLK_2X_DN
IN
GPU_TEMP_P
IN
GPU_TEMP_N
OUT
EDRAM_TEMP_P
IN
EDRAM_TEMP_N
OUT
2
DBG_LED3
1%
CH
2
1%
CH
1
40.2
402
V_MEM
1
R2E4
1.5K
1%
CH
402
2
2
4
65
8
1
R2D9
1.5K
1%
CH
402
2
12
OUT
R4R8
IN
IN
R5D2
1
2K
402
13
IN
2
1%
CH
1
2
GPU_CLK_DP
GPU_CLK_DN
2
1%
CH
GPU_SPI_SI
GPU_TCLK
GPU_TDO
GPU_TDI
GPU_TMS
GPU_TRST
GPU_TRST_ED
R2E3
1.5K
1%
CH
402
PEX_NCAL
IN
MEM_CALA
MEM_CALB
13
13
13
EMPTY402
34
56
IN
IN
IN
GPU, VIDEO + PCIEX + EEPROM + JTAG
U4D1
A25
NB_CLK_DP
A24
NB_CLK_DN
E11
RST_IN_N*
B22
PEX_RX1_DP
A22
PEX_RX1_DN
B26
PEX_RX0_DP
A26
PEX_RX0_DN
A28
PEX_PCAL
B28
PEX_NCAL
B21
PEX_ICAL
D10
PIX_CLK_IN_DP
C10
PIX_CLK_IN_DN
C22
NB_THERMD _P
C23
NB_THERMD _N
G14
ED_THERMD_P
G15
ED_THERMD_N
G16
SROM_SO
AG16
MEM_CALA
V8
MEM_CALB
E13
TCLK
D12
TDO
E12
TDI
G12
TMS
G11
TRST
G13
TRST_ED
X02056-010
V_1P8
GPU_SPI_CLK
GPU_SPI_SO
GPU_SPI_CS_N
1
1
R5P3
R5C10
10K
10K
5%
5%
CH
CH
402
402
2
2
1
2
R4C7
10K
5%
CH
402
1K
402
1KCH5%
402
1K
402
2OF12
GPU VERSION 57
R5C5
5%
CH
R5C8
R4C3
5%
CH
PEX_TX1_DP
PEX_TX1_DN
PEX_TX0_DP
PEX_TX0_DN
PIX_CLK_OUT
PIX_DATA14
PIX_DATA13
PIX_DATA12
PIX_DATA11
PIX_DATA10
SROM_EN_PSRO_OUT
MEM_SCAN_EN
MEM_SCAN_OEN_A
MEM_SCAN_OEN_B
V_1P8
RST_DONE
PIX_DATA9
PIX_DATA8
PIX_DATA7
PIX_DATA6
PIX_DATA5
PIX_DATA4
PIX_DATA3
PIX_DATA2
PIX_DATA1
PIX_DATA0
VSYNC_OUT
HSYNC_OUT
SROM_SI
SROM_SCLK
SROM_CS
MEM_RST
1
3
GPU_S PI _CLK_R
GPU_SPI_SO_R
GPU_SPI_CS_N_R
2
10K
402
2
10K
402
J5C2
2X3HDR
EMPTY
R4C4
R4C5
IC
EMPTY
D14
B23
A23
B27
A27
B14
B17
A17
D16
B16
A16
D15
B15
A15
A14
D13
B13
A13
B12
A12
D11
A11
B11
G17
E16
E15
E14
AG11
AN13
G9
G10
PEX_GPU_SB_L1_DP_C
PEX_GPU_SB_L1_DN_C
PEX_GPU_SB_L0_DP_C
PEX_GPU_SB_L0_DN_C
GPU_PIX_CLK_1X
PIX_DATA<14..0>
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
GPU_VSYNC_OUT
GPU_HSYNC_OUT
GPU_SROM_EN_PSRO_OUT
GPU_SPI_SO
GPU_SPI_CLK
GPU_SPI_CS_N
MEM_RST
MEM_SCAN_EN _BUFF
MEM_SCAN_TOP_EN_BUFF
MEM_SCAN_BOT_EN_BUFF
GPU_SPI_SI
2
GPU_SPI_WP_N
4
65
V_1P8
U4C1
6
SCK
5
SDI
7
HOLD_N*
1
CS_N*
3
WP_N*
1
5%
CH
1
5%
X800552-001
GPU_SPI_WP_N
AT25020A
OUT
OUT
OUT
OUT
VCC
SDO
GND
29
29
EMPTY
IN
1
13
13
8
2
4
[PAGE_TITLE=GPU, VIDEO + PCIEX + EEPROM + JTAG]
FTPFTP
OUT
OUT
OUT
V_MEM
1
2
1
2
OUT
OUT
OUT
13
FT2P13
29
29
R4D1
1K
5%
EMPTY
402
DB4D1
1
TP
R4D2
1K
5%
CH
402
13
13
13
OUT
OUT
OUT
OUT
2
2
1
R2E1
5%
CH
402
R4F6
1K1K
5%
CH
402
1
V_1P8
1
C5C3
.1UF
10%
6.3V
2
X5R
402
GPU_SPI_SI
DRAWING
XENON_FABK
Wed Aug 24 09:27:07 2005
1
.1UF
1
.1UF
1
.1UF
1
.1UF
21
20
12
12
12
2
R4C6
10K
5%
CH
402
1
C4D1
2
10%
6.3V
X5R
402
C4D2
2
10%
6.3V
X5R
402
C4D3
2
10%
6.3V
X5R
402
C5D1
2
10%
6.3V
X5R
402
22 23 24 25 26
OUT
PEX_GPU_SB_L1_DP
PEX_GPU_SB_L1_DN
PEX_GPU_SB_L0_DP
PEX_GPU_SB_L0_DN
27
V_MEM
C3C2 C4R2 C4R26 C4R1
13
10UF
20%
6.3V
X5R
805
MICROSOFT
CONFIDENTIAL
33
OUT
33
OUT
33
OUT
33
OUT
VIDEO DECOUPLING
.1UF
.1UF
10%
10%
6.3V
6.3V
X5R
X5R
402 402
PROJECT NAME
XENON_RETAIL
.1UF
10%
6.3V
X5R
402
PAGE
REV
K7
13/73
GPU, MEMORY CONTROLLER 0 PARTITION A & B
AN27
AP28
AP27
AP29
AL25
AP31
AM25
AP32
AP30
AN26
AP26
AM23
AP23
AL23
AN23
AN25
AP22
AP25
AN21
AN22
AP24
AN24
AH26
AN32
AK26
AN31
AN29
AN30
AK28
AK29
AK30
AN28
AK27
AK25
AH21
AH25
AK21
AH23
AK22
AJ23
AH22
AM22
AJ24
AK24
AG33
AP21
MB_VREF0
U4D1
MB_DQ31
MB_DQ30
MB_DQ29
MB_DQ28
MB_DQ27
MB_DQ26
MB_DQ25
MB_DQ24
MB_WDQS3
MB_RDQS3
MB_DM3
MB_DQ22
MB_DQ21
MB_DQ20
MB_DQ19
MB_DQ18
MB_DQ17
MB_DQ16
MB_WDQS2
MB_RDQS2
MB_DM2
MB_DQ15
MB_DQ14
MB_DQ13
MB_DQ12
MB_DQ11
MB_DQ10
MB_DQ9
MB_DQ8
MB_WDQS1
MB_RDQS1
MB_DM1
MB_DQ7
MB_DQ6
MB_DQ5
MB_DQ4
MB_DQ3
MB_DQ2
MB_DQ1
MB_DQ0
MB_WDQS0
MB_RDQS0
MB_DM0
MB_VREF1
MB_VREF0
X02056-010
V_MEM
1
2
1
2
R4T8
549
1%
CH
402
R4T5
1.27K
1%
CH
402
4OF8
GPU VERSION 57
1
2
C4T46
.1UF
10%
6.3V
X5R
402
MB_CLK1_DPMB_DQ23
MB_CLK1_DN
MB_CLK0_DP
MB_CLK0_DN
MB_A12
MB_A11
MB_A10
MB_A9
MB_A8
MB_A7
MB_A6
MB_A5
MB_A4
MB_A3
MB_A2
MB_A1
MB_A0
MB_BA2
MB_BA1
MB_BA0
MB_CKE
MB_WE_N*
MB_CAS_N*
MB_RAS_N*
MB_CS1_N*
MB_CS0_N*
V_MEM
IC
MB_CLK1_DP
AM33
MB_CLK1_DN
AM34
MB_CLK0_DP
AL33
MB_CLK0_DN
AL34
AK32
AE29
AE34
AJ30
AK33
AJ33
AK34
AM32
AJ34
AE30
AF28
AE33
AF29
AH30
AH33
AG30
AG34
AF33
AF32
AF31
AH34
AF34
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
MB_CKE
MB_WE_N
MB_CAS_N
MB_RAS_N
MB_CS1_N
MB_CS0_N
MB_A<12..0>
MB_BA<2..0>MA_BA<2..0>
OUT
OUT
OUT
OUT
OUT
OUT
22 23
22 23
22 23
22 23
23
22
OUT
MEMORY CONTROLLER B, DECOUPLING
C4T47
6.3V
X5R
10UF
10%
1206
C4T33 C5T3
.22UF
10%
6.3V
X5R
402
C4T31
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
C5T4
.22UF
10%
6.3V
X5R
402
C4T34 C5T2 C4T39
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
C5T1
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
OUT
OUT
OUT
OUT
OUT
232223
23
22
22
22 23
22 2320
U4D1
20
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
21
21
20
21
20
21
20
21
20
21
20
21
20
21
21
20
20
21
20
21
21
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
21
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
20
21
21
21
MA_DQ31
BI
MA_DQ30
BI
MA_DQ29
BI
MA_DQ28
BI
MA_DQ27
BI
MA_DQ26
BI
MA_DQ25
BI
MA_DQ24
BI
MA_WDQS3
OUT
MA_RDQS3
20
IN
MA_DM3
20
OUT
MA_DQ23
BI
MA_DQ22
BI
MA_DQ21
BI
MA_DQ20
BI
MA_DQ19
BI
MA_DQ18
BI
MA_DQ17
BI
MA_DQ16
BI
MA_WDQS2
OUT
MA_RDQS2
20
IN
MA_DM2
20
OUT
MA_DQ15
BI
MA_DQ14
BI
MA_DQ13
BI
MA_DQ12
BI
MA_DQ11
BI
MA_DQ10
BI
MA_DQ9
BI
MA_DQ8
BI
MA_WDQS1
OUT
MA_RDQS1
20
IN
MA_DM1
20
OUT
MA_DQ7
BI
MA_DQ6
BI
MA_DQ5
BI
MA_DQ4
BI
MA_DQ3
BI
MA_DQ2
BI
MA_DQ1
BI
MA_DQ0
BI
MA_WDQS0
OUT
MA_RDQS0
20
IN
MA_DM0
20
OUT
V_MEM
1
R4T4
549
1%
CH
402
2
MA_VREF1
1
1
2
C4T40
.1UF
10%
6.3V
X5R
402
R4T3
1.27K
1%
CH
402
2
AP19
AN19
AL18
AN20
AN18
AM20
AN17
AL20
AP20
AM18
AP18
AP15
AN15
AM15
AN14
AN16
AL13
AP17
AM13
AP14
AL15
AP16
AH16
AK20
AK16
AH20
AH17
AJ19
AJ18
AH18
AK19
AK17
AM17
AK15
AH11
AH15
AK11
AH13
AK12
AJ13
AH12
AM12
AJ14
AK14
AP13
AK6
MA_VREF0
MA_DQ31
MA_DQ30
MA_DQ29
MA_DQ28
MA_DQ27
MA_DQ26
MA_DQ25
MA_DQ24
MA_WDQS3
MA_RDQS3
MA_DM3
MA_DQ23
MA_DQ22
MA_DQ21
MA_DQ20
MA_DQ19
MA_DQ18
MA_DQ17
MA_DQ16
MA_WDQS2
MA_RDQS2
MA_DM2
MA_DQ15
MA_DQ14
MA_DQ13
MA_DQ12
MA_DQ11
MA_DQ10
MA_DQ9
MA_DQ8
MA_WDQS1
MA_RDQS1
MA_DM1
MA_DQ7
MA_DQ6
MA_DQ5
MA_DQ4
MA_DQ3
MA_DQ2
MA_DQ1
MA_DQ0
MA_WDQS0
MA_RDQS0
MA_DM0
MA_VREF1
MA_VREF0
X02056-010
V_MEM
1
2
1
2
GPU VERSION 57
R4T7
549
1%
CH
402
R4T6
1.27K
1%
CH
402
3OF8
1
C4T45
.1UF
10%
6.3V
2
X5R
402
MA_CLK1_DP
MA_CLK1_DN
MA_CLK0_DP
MA_CLK0_DN
MA_A12
MA_A11
MA_A10
MA_A9
MA_A8
MA_A7
MA_A6
MA_A5
MA_A4
MA_A3
MA_A2
MA_A1
MA_A0
MA_BA2
MA_BA1
MA_BA0
MA_CKE
MA_WE_N*
MA_CAS_N*
MA_RAS_N*
MA_CS1_N*
MA_CS0_N*
V_MEM
IC
MA_CLK1_DP
AH10
AK10
AN12
AP12
AN4
AP7
AP4
AP8
AN11
AP9
AN10
AP11
AN9
AN8
AN7
AN5
AP6
AP10
AM10
AP5
AN6
AJ9
AK8
AK7
AK9
AL10
MA_CLK1_DN
MA_CLK0_DP
MA_CLK0_DN
MA_A<12..0>
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
MA_CKE
MA_WE_N
MA_CAS_N
MA_RAS_N
MA_CS1_N
MA_CS0_N
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
20
21
20
21
20
21
20
21
21
20
MEMORY CONTROLLER A, DECOUPLING
C4R3
10UF
10%
6.3V
X5R
1206
C4T29 C4T32
.22UF
.22UF
10%
10%
6.3V
6.3V
X5R
X5R
402
402
C4T42 C4T44
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
2223
2223
2223
2223
2223
2223
2223
2223
2223
21
21
20
20
20
21
21
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
2223
MB_DQ31
BI
MB_DQ30
BI
MB_DQ29
BI
MB_DQ28
BI
MB_DQ27
BI
MB_DQ26
BI
MB_DQ25
BI
MB_DQ24
BI
MB_WDQS3
OUT
MB_RDQS3
2223
IN
MB_DM3
2223
OUT
MB_DQ23
BI
MB_DQ22
BI
MB_DQ21
BI
MB_DQ20
BI
MB_DQ19
BI
MB_DQ18
BI
MB_DQ17
BI
MB_DQ16
BI
MB_WDQS2
OUT
MB_RDQS2
2223
IN
MB_DM2
2223
OUT
MB_DQ15
BI
MB_DQ14
BI
MB_DQ13
BI
MB_DQ12
BI
MB_DQ11
BI
MB_DQ10
BI
MB_DQ9
BI
MB_DQ8
BI
MB_WDQS1
OUT
MB_RDQS1
2223
IN
MB_DM1
2223
OUT
MB_DQ7
BI
MB_DQ6
BI
MB_DQ5
BI
MB_DQ4
BI
MB_DQ3
BI
MB_DQ2
BI
MB_DQ1
BI
MB_DQ0
BI
MB_WDQS0
OUT
MB_RDQS0
2223
IN
MB_DM0
2223
OUT
V_MEM
1
R5E2
549
1%
CH
402
2
MB_VREF1
1
1
2
C5E1
.1UF
10%
6.3V
X5R
402
R5E1
1.27K
1%
CH
402
2
C4T35
C4T27 C4T41
.22UF
.22UF
.22UF
10%
6.3V
X5R
402
10%
6.3V
X5R
402
10%
6.3V
X5R
402
[PAGE_TITLE=GPU, MEMORY CONTROLLER A + B]
C4T43
.22UF
10%
6.3V
X5R
402
DRAWING
XENON_FABK
Wed Aug 24 09:27:08 2005
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAIL
PAGE
14/73
REV
K7
GPU, MEMORY CONTROLLER 1 PARTITION C & D
U4D1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
MC_DQ31
MC_DQ30
MC_DQ29
MC_DQ28
MC_DQ27
MC_DQ26
MC_DQ25
MC_DQ24
MC_WDQS3
MC_RDQS3
MC_DM3
MC_DQ23
MC_DQ22
MC_DQ21
MC_DQ20
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DM2
MC_DQ15
MC_DQ14
MC_DQ13
MC_DQ12
MC_DQ11
MC_DQ10
MC_DQ9
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1
MC_DQ7
MC_DQ6
MC_DQ5
MC_DQ4
MC_DQ3
MC_DQ2
MC_DQ1
MC_DQ0
MC_WDQS0
MC_RDQS0
MC_DM0
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
2425
V_MEM
2
R4R4
549
1%
CH
402
1
MC_VREF1
1
1
2
C4R25
.1UF
10%
6.3V
X5R
402
R4R5
1.27K
1%
CH
402
2
E10
R1
R3
R2
R4
N4
T2
N3
U1
T1
P2
P1
L1
K4
L2
K3
N2
K2
N1
J2
K1
M1
M2
J6
N6
J5
N7
L5
M5
L7
M3
M7
K5
K7
H2
B2
H5
C2
F2
E5
F5
E2
D2
G5
G2
G1
MC_VREF0
MC_DQ31
MC_DQ30
MC_DQ29
MC_DQ28
MC_DQ27
MC_DQ26
MC_DQ25
MC_DQ24
MC_WDQS3
MC_RDQS3
MC_DM3
MC_DQ23
MC_DQ22
MC_DQ21
MC_DQ20
MC_DQ19
MC_DQ18
MC_DQ17
MC_DQ16
MC_WDQS2
MC_RDQS2
MC_DM2
MC_DQ15
MC_DQ14
MC_DQ13
MC_DQ12
MC_DQ11
MC_DQ10
MC_DQ9
MC_DQ8
MC_WDQS1
MC_RDQS1
MC_DM1
MC_DQ7
MC_DQ6
MC_DQ5
MC_DQ4
MC_DQ3
MC_DQ2
MC_DQ1
MC_DQ0
MC_WDQS0
MC_RDQS0
MC_DM0
MC_VREF1
MC_VREF0
X02056-010
V_MEM
2
R4R1
549
1%
CH
402
1
1
R4R2
1.27K
1%
CH
402
2
5OF8
GPU VERSION 57
1
C4R10
.1UF
10%
6.3V
2
X5R
402
MC_CLK1_DP
MC_CLK1_DN
MC_CLK0_DP
MC_CLK0_DN
MC_A12
MC_A11
MC_A10
MC_A9
MC_A8
MC_A7
MC_A6
MC_A5
MC_A4
MC_A3
MC_A2
MC_A1
MC_A0
MC_BA2
MC_BA1
MC_BA0
MC_CKE
MC_WE_N*
MC_CAS_N*
MC_RAS_N*
MC_CS1_N*
MC_CS0_N*
IC
MC_CLK1_DP
J1
MC_CLK1_DN
H1
MC_CLK0_DP
F1
MC_CLK0_DN
E1
A10
12
A7
11
B10
10
B6
9
D1
8
7
A5
6
A4
C1
5
B5
4
A6
3
B7
2
A9
1
0
B8
B4
A3
B9
A8
E7
E8
E9
E6
B3
2
1
0
MC_CKE
MC_WE_N
MC_CAS_N
MC_RAS_N
MC_CS1_N
MC_CS0_N
MC_BA<2..0>
OUT
OUT
OUT
OUT
OUT
OUT
V_MEM
MEMORY CONTROLLER C, DECOUPLING
1
1
C3R5
10UF
10%
6.3V
2
X5R
1206
1
C4R23
.22UF
10%
6.3V
2
X5R
402
1
C4R38
C4R51
.22UF
.22UF
10%
10%
6.3V
6.3V
2
2
X5R
X5R
402
402
1
1
C4R66
C4T12
.22UF
.22UF
10%
10%
6.3V
6.3V
2
2
X5R
X5R
402
402
2
2
1
1
24 25
24 25
24 25
24 25
25
24
OUT
C4T14
.22UF
10%
6.3V
X5R
402
C4R32
.22UF
10%
6.3V
X5R
402
OUT
OUT
OUT
OUT
OUT
MD_DQ31
2627
BI
MD_DQ30
2627
BI
MD_DQ29
2627
BI
MD_DQ28
2627
BI
MD_DQ27
2627
BI
MD_DQ26
2627
BI
MD_DQ25
2627
BI
MD_DQ24
2627
BI
MD_WDQS3
26
27
OUT
MD_RDQS3
26
27
IN
MD_DM3
2627
OUT
MD_DQ23
2627
BI
MD_DQ22
2627
BI
MD_DQ21
2627
BI
MD_DQ20
2627
BI
MD_DQ19
2627
BI
MD_DQ18
2627
BI
MD_DQ17
2627
BI
MD_DQ16
2627
BI
27
27
27
27
27
27
MD_WDQS2
26
OUT
MD_RDQS2
26
IN
MD_DM2
2627
OUT
MD_DQ15
2627
BI
MD_DQ14
2627
BI
MD_DQ13
2627
BI
MD_DQ12
2627
BI
MD_DQ11
2627
BI
MD_DQ10
2627
BI
MD_DQ9
2627
BI
MD_DQ8
2627
BI
MD_WDQS1
26
OUT
MD_RDQS1
26
IN
MD_DM1
2627
OUT
MD_DQ7
2627
BI
MD_DQ6
2627
BI
MD_DQ5
2627
BI
MD_DQ4
2627
BI
MD_DQ3
2627
BI
MD_DQ2
2627
BI
MD_DQ1
2627
BI
MD_DQ0
2627
BI
MD_WDQS0
26
OUT
MD_RDQS0
26
IN
MD_DM0
2627
OUT
24 25
25
25
24
24
V_MEM
1
R3T2
549
1%
CH
402
2
MD_VREF1
1
1
2
1
C4R48
.22UF
10%
6.3V
2
X5R
402
C4T36
.1UF
10%
6.3V
X5R
402
R4T2
1.27K
1%
CH
402
2
AC3
AC4
AC1
AD1
AB1
AE2
AA2
AE1
AD2
AC2
AB2
W2
W1
Y2
V4
Y4
V1
AA1
V2
V3
Y1
Y3
W6
AC7
W5
AC6
AA5
AB5
AA7
AB3
AB7
Y5
Y7
V7
P6
V6
P5
U3
R5
T5
T7
R7
U5
U7
AF1
U2
MD_VREF0
U4D1
MD_DQ31
MD_DQ30
MD_DQ29
MD_DQ28
MD_DQ27
MD_DQ26
MD_DQ25
MD_DQ24
MD_WDQS3
MD_RDQS3
MD_DM3
MD_DQ23
MD_DQ22
MD_DQ21
MD_DQ20
MD_DQ19
MD_DQ18
MD_DQ17
MD_DQ16
MD_WDQS2
MD_RDQS2
MD_DM2
MD_DQ15
MD_DQ14
MD_DQ13
MD_DQ12
MD_DQ11
MD_DQ10
MD_DQ9
MD_DQ8
MD_WDQS1
MD_RDQS1
MD_DM1
MD_DQ7
MD_DQ6
MD_DQ5
MD_DQ4
MD_DQ3
MD_DQ2
MD_DQ1
MD_DQ0
MD_WDQS0
MD_RDQS0
MD_DM0
MD_VREF1
MD_VREF0
X02056-010
V_MEM
1
R4R6
549
1%
CH
402
2
1
R4R7
1.27K
1%
CH
402
2
6OF8
GPU VERSION 57
1
C4R64
.1UF
10%
6.3V
2
X5R
402
IC
MD_CLK1_DP
MD_A12
MD_A11
MD_A10
MD_A9
MD_A8
MD_A7
MD_A6
MD_A5
MD_A4
MD_A3
MD_A2
MD_A1
MD_A0
MD_BA2
MD_BA1
MD_BA0
MD_CKE
AD6
AD5
AE4
AE3
AK5
AL2
AM2
AF5
AE5
AF2
AF7
AE7
AG2
AM1
AJ2
AM3
AK2
AG5
AH2
AJ5
AK1
AH1
AJ1
AL1
AH5
AG1
MD_CLK1_DN
MD_CLK0_DP
MD_CLK0_DN
12
11
10
9
8
7
6
5
4
3
2
1
0
2
1
0
MD_CKE
MD_WE_N
MD_CAS_N
MD_RAS_N
MD_CS1_N
MD_CS0_N
MD_CLK1_DP
MD_CLK1_DN
MD_CLK0_DP
MD_CLK0_DN
MD_WE_N*
MD_CAS_N*
MD_RAS_N*
MD_CS1_N*
MD_CS0_N*
V_MEM
MEMORY CONTROLLER D, DECOUPLING
1
1
C4T28
10UF
10%
6.3V
2
X5R
1206
1
C4T7
.22UF
10%
6.3V
2
X5R
402
1
C4R15
C4R61
.22UF
.22UF
10%
10%
6.3V
6.3V
2
2
X5R
X5R
402
402
1
1
C4R31
C4R12
.22UF
.22UF
10%
10%
6.3V
6.3V
2
2
X5R
X5R
402
402
MD_A<12..0>MC_A<12..0>
MD_BA<2..0>
1
C4T38
.22UF
10%
6.3V
2
X5R
402
1
C4R19
.22UF
10%
6.3V
2
X5R
402
OUT
OUT
OUT
OUT
OUT
OUT
27
OUT
27
OUT
26
OUT
26
OUT
26 2724 25
OUT
26 27
OUT
26
27
26
27
26
27
27
26
27
26
1
C4R50
.22UF
10%
6.3V
2
X5R
402
PAGE_TITLE=[GPU, MEMORYCONTROLLER C + D]
DRAWING
XENON_FABK
Wed Aug 24 09:27:10 2005
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAIL
PAGE
15/73
REV
K7
V_GPUCORE
0.5 DCR
0.5 DCR
0.5 DCR
FB4D1
1
120
FB
0.2A
603
FB4T1
1
120
FB
0.2A
603
FB4R1
1
120
FB
0.2A
603
V_GPUPCIE
GPU, PLL POWER + FSB POWER
2
1
2
2
1
2
2
1
2
C4D6
2.2UF
10%
6.3V
X5R
603
C4T48
2.2UF
10%
6.3V
X5R
603
C4R68
2.2UF
10%
6.3V
X5R
603
1
2
C4D5
.1UF
10%
6.3V
X5R
402
1
C4D4
0.01UF
10%
16V
2
X7R
402
V_GPUCORE
V_GPUPCIE
1
C4T30
.1UF
10%
6.3V
2
X5R
402
1
C4R4
.1UF
10%
6.3V
2
X5R
402
C4T37
0.01UF
10%
16V
X7R
402
C4R6
0.01UF
10%
16V
X7R
402
1
2
V_PVDDA_MEM
V_PVDDA_ED
V_PVDDA_FSB
C5R7
.1UF
10%
6.3V
X5R
402
1
C4R8
.1UF
10%
6.3V
2
X5R
402
V_PVDDA
AG10
U4D1
A20
PVDDA
A21
PVSSA
C27
VDD_BSB1
C26
VSS_BSB1
C25
VDD_BSB0
C24
VSS_BSB0
PVDDA_MEM
AG9
PVSSA_MEM
A18
PVDDA_ED
A19
PVSSA_ED
B25
PVDDA_PEX
B24
PVSSA_PEX
G34
PVDDA_FSB
F34
PVSSA_FSB
X02056-010
8OF12
GPU VERSION 57
VDD_FSB24
VDD_FSB23
VDD_FSB22
VDD_FSB21
VDD_FSB20
VDD_FSB19
VDD_FSB18
VDD_FSB17
VDD_FSB16
VDD_FSB15
VDD_FSB14
VDD_FSB13
VDD_FSB12
VDD_FSB11
VDD_FSB10
VDD_FSB9
VDD_FSB8
VDD_FSB7
VDD_FSB6
VDD_FSB5
VDD_FSB4
VDD_FSB3
VDD_FSB2
VDD_FSB1
VDD_FSB0
IC
AA27
AB28
AB32
AC27
AD28
AD31
K28
K31
L27
M28
M32
N27
P28
P31
R28
R32
T27
U28
U31
V27
V30
W28
W32
Y28
Y31
120
0.2A
0.5 DCR
FB5R1
1
1
C4R5
.1UF
10%
6.3V
2
X5R
402
2
FB
603
1
2
C5R19
2.2UF
10%
6.3V
X5R
603
1
C5R13
.1UF
10%
6.3V
2
X5R
402
C4R7
0.01UF
10%
16V
X7R
402
C5R15
0.01UF
10%
16V
X7R
402
[PAGE_TITLE=GPU, PLL POWER + FSB POWER]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:10 2005
PAGE
16/73
REV
K7
GPU, CORE POWER + MEM POWER
V_GPUCOREV_GPUCORE
AA14
AA15
AA16
AA19
AA20
AA21
AB11
AB12
AB13
AB17
AB18
AB22
AB23
AB24
AC11
AC12
AC13
AC17
AC18
AC22
AC23
AC24
AD11
AD12
AD13
AD17
AD18
AD22
AD23
AD24
U4D1
B18
B20
C19
C21
C29
C31
C33
C34
D17
D18
D20
D22
D30
D32
D34
E17
E19
E21
E31
F17
F18
F20
F23
F25
F27
F29
F30
G19
G28
G32
H12
H14
H16
H18
H20
H22
H24
H26
H27
J27
X02056-010
9OF12
GPU VERSION 57
VDD_CORE139
VDD_CORE138 VDD_CORE68
VDD_CORE137
VDD_CORE136
VDD_CORE135 GPU VERSION 57
VDD_CORE134
VDD_CORE133
VDD_CORE132
VDD_CORE131
VDD_CORE130
VDD_CORE129
VDD_CORE128
VDD_CORE127
VDD_CORE126
VDD_CORE125
VDD_CORE124
VDD_CORE123
VDD_CORE122
VDD_CORE121
VDD_CORE120
VDD_CORE119
VDD_CORE118
VDD_CORE117
VDD_CORE116
VDD_CORE115
VDD_CORE114
VDD_CORE113
VDD_CORE112
VDD_CORE111
VDD_CORE110
VDD_CORE109
VDD_CORE108
VDD_CORE107
VDD_CORE106
VDD_CORE105
VDD_CORE104
VDD_CORE103
VDD_CORE102
VDD_CORE101
VDD_CORE100
VDD_CORE99
VDD_CORE98
VDD_CORE97
VDD_CORE96
VDD_CORE95
VDD_CORE94
VDD_CORE93
VDD_CORE92
VDD_CORE91
VDD_CORE90
VDD_CORE89
VDD_CORE88
VDD_CORE87
VDD_CORE86
VDD_CORE85
VDD_CORE84
VDD_CORE83
VDD_CORE82
VDD_CORE81
VDD_CORE80
VDD_CORE79
VDD_CORE78
VDD_CORE77
VDD_CORE76
VDD_CORE75
VDD_CORE74
VDD_CORE73
VDD_CORE72
VDD_CORE71
VDD_CORE70
VDD_CORE69
VDD_CORE67
VDD_CORE66
VDD_CORE65
VDD_CORE64
VDD_CORE63
VDD_CORE62
VDD_CORE61
VDD_CORE60
VDD_CORE59
VDD_CORE58
VDD_CORE57
VDD_CORE56
VDD_CORE55
VDD_CORE54
VDD_CORE53
VDD_CORE52
VDD_CORE51
VDD_CORE50
VDD_CORE49
VDD_CORE48
VDD_CORE47
VDD_CORE46
VDD_CORE45
VDD_CORE44
VDD_CORE43
VDD_CORE42
VDD_CORE41
VDD_CORE40
VDD_CORE39
VDD_CORE38
VDD_CORE37
VDD_CORE36
VDD_CORE35
VDD_CORE34
VDD_CORE33
VDD_CORE32
VDD_CORE31
VDD_CORE30
VDD_CORE29
VDD_CORE28
VDD_CORE27
VDD_CORE26
VDD_CORE25
VDD_CORE24
VDD_CORE23
VDD_CORE22
VDD_CORE21
VDD_CORE20
VDD_CORE19
VDD_CORE18
VDD_CORE17
VDD_CORE16
VDD_CORE15
VDD_CORE14
VDD_CORE13
VDD_CORE12
VDD_CORE11
VDD_CORE10
VDD_CORE9
VDD_CORE8
VDD_CORE7
VDD_CORE6
VDD_CORE5
VDD_CORE4
VDD_CORE3
VDD_CORE2
VDD_CORE1
VDD_CORE0
BGA
IC
L11
L12
L13
L17
L18
L22
L23
L24
M11
M12
M13
M17
M18
M22
M23
M24
N11
N12
N13
N17
N18
N22
N23
N24
P14
P15
P16
P19
P20
P21
R14
R15
R16
R19
R20
R21
T14
T15
T16
T19
T20
T21
U11
U12
U13
U17
U18
U22
U23
U24
V11
V12
V13
V17
V18
V22
V23
V24
W14
W15
W16
W19
W20
W21
Y14
Y15
Y16
Y19
Y20
Y21
AE28
AE31
AF27
AF30
AG13
AG15
AG17
AG20
AG23
AG25
AG28
AG32
AH14
AH19
AH24
AH27
AH29
AH31
AJ11
AJ12
AJ16
AJ21
AJ22
AJ26
AJ28
AJ32
AK13
AK23
AK31
AL11
AL14
AL17
AL21
AL24
AA4
AA6
AB6
AC5
AC8
AD4
AD7
AE8
AF3
AF6
AG4
AG7
AH3
AH6
AH8
AH9
AJ4
AJ7
AK3
AL4
AL6
AL8
U4D1
VDD_MEM111
VDD_MEM110
VDD_MEM109
VDD_MEM108
VDD_MEM107
VDD_MEM106
VDD_MEM105
VDD_MEM104
VDD_MEM103
VDD_MEM102
VDD_MEM101
VDD_MEM100
VDD_MEM99
VDD_MEM98
VDD_MEM97
VDD_MEM96
VDD_MEM95
VDD_MEM94
VDD_MEM93
VDD_MEM92
VDD_MEM91
VDD_MEM90
VDD_MEM89
VDD_MEM88
VDD_MEM87
VDD_MEM86
VDD_MEM85
VDD_MEM84
VDD_MEM83
VDD_MEM82
VDD_MEM81
VDD_MEM80
VDD_MEM79
VDD_MEM78
VDD_MEM77
VDD_MEM76
VDD_MEM75
VDD_MEM74
VDD_MEM73
VDD_MEM72
VDD_MEM71
VDD_MEM70
VDD_MEM69
VDD_MEM68
VDD_MEM67
VDD_MEM66
VDD_MEM65
VDD_MEM64
VDD_MEM63
VDD_MEM62
VDD_MEM61
VDD_MEM60
VDD_MEM59
VDD_MEM58
VDD_MEM57
VDD_MEM56
X02056-010
10 OF 12
VDD_MEM55
VDD_MEM54
VDD_MEM53
VDD_MEM52
VDD_MEM51
VDD_MEM50
VDD_MEM49
VDD_MEM48
VDD_MEM47
VDD_MEM46
VDD_MEM45
VDD_MEM44
VDD_MEM43
VDD_MEM42
VDD_MEM41
VDD_MEM40
VDD_MEM39
VDD_MEM38
VDD_MEM37
VDD_MEM36
VDD_MEM35
VDD_MEM34
VDD_MEM33
VDD_MEM32
VDD_MEM31
VDD_MEM30
VDD_MEM29
VDD_MEM28
VDD_MEM27
VDD_MEM26
VDD_MEM25
VDD_MEM24
VDD_MEM23
VDD_MEM22
VDD_MEM21
VDD_MEM20
VDD_MEM19
VDD_MEM18
VDD_MEM17
VDD_MEM16
VDD_MEM15
VDD_MEM14
VDD_MEM13
VDD_MEM12
VDD_MEM11
VDD_MEM10
VDD_MEM9
VDD_MEM8
VDD_MEM7
VDD_MEM6
VDD_MEM5
VDD_MEM4
VDD_MEM3
VDD_MEM2
VDD_MEM1
VDD_MEM0
BGA
F21
F24
F26
F28
F31
G4
G7
G18
G20
G27
G29
G33
H3
H6
H8
H9
H11
H13
H15
H17
H19
H21
H23
H25
H28
J4
J8
J28
K6
K27
K32
L3
L8
L14
L15
L16
L19
L20
L21
L28
M4
M8
M14
M15
M16
M19
M20
M21
M27
M31
N14
N15
N16
N19
N20
N21
N28
N29
N30
P3
P8
P11
P12
P13
P17
U4D1
12 OF 12
GPU VERSION 51
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85
VSS84
VSS83
VSS82
VSS81
VSS80
VSS79
VSS78
VSS77
VSS76
VSS75
VSS74
VSS73
VSS72
VSS71
VSS70
VSS69
VSS68
VSS67
VSS66
X02056-010
U4D1
11 OF 12
AA11
AA12
AA13
AA17
AA18
AA22
AA23
AA24
AB14
AB15
AB16
AB19
AB20
AB21
AB27
AB31
AC14
AC15
AC16
AC19
AC20
AC21
AC30
AD14
AD15
AD16
AD19
AD20
AD21
AD27
AD32
AE27
AE32
AG12
AG14
AG18
AG19
AG21
AG22
AG24
AG26
AG27
AG29
AG31
AH28
AH32
AJ10
A1
AA3
AA8
AB4
AB8
AD3
AD8
AE6
AF4
AF8
AG3
AG6
AG8
AH4
AH7
AJ3
AJ6
AJ8
GPU VERSION 51
VSS260
VSS259
VSS258
VSS257
VSS256
VSS255
VSS254
VSS253
VSS252
VSS251
VSS250
VSS249
VSS248
VSS247
VSS246
VSS245
VSS244
VSS243
VSS242
VSS241
VSS240
VSS239
VSS238
VSS237
VSS236
VSS235
VSS234
VSS233
VSS232
VSS231
VSS230
VSS229
VSS228
VSS227
VSS226
VSS225
VSS224
VSS223
VSS222
VSS221
VSS220
VSS219
VSS218
VSS217
VSS216
VSS215
VSS214
VSS213
VSS212
VSS211
VSS210
VSS209
VSS208
VSS207
VSS206
VSS205
VSS204
VSS203
VSS202
VSS201
VSS200
VSS199
VSS198
VSS197
VSS196
V_MEMV_MEM
IC
AL28
AL30
AL32
AM5
AM7
AM9
AM16
AM19
AM26
AM27
AM29
AM31
AN2
AP3
C3
C5
C7
C9
C12
C14
C16
C18
D4
D6
D8
E3
F4
F7
F9
F11
F13
F15
G3
G6
G8
H4
H7
H10
J3
J7
K8
L4
L6
M6
N5
N8
P4
P7
R8
T3
T6
U4
U8
W3
W7
Y8
VSS195
VSS194
VSS193
VSS192
VSS191
VSS190
VSS189
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS182
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS150
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
BGA
IC
AJ15
AJ17
AJ20
AJ25
AJ27
AJ29
AJ31
AK4
AK18
AL3
AL5
AL7
AL9
AL12
AL16
AL19
AL22
AL26
AL27
AL29
AL31
AM4
AM6
AM8
AM11
AM14
AM21
AM24
AM28
AM30
AN3
AN33
B19
B33
C4
C6
C8
C11
C13
C15
C17
C20
C28
C32
D3
D5
D7
D9
D19
D21
D31
E4
E18
E20
E22
E30
E32
F3
F6
F8
F10
F12
F14
F16
F19
VSS65
VSS64
VSS63
VSS62
VSS61
VSS60
VSS59
VSS58
VSS57
VSS56
VSS55
VSS54
VSS53
VSS52
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
VSS26
VSS25
VSS24
VSS23
VSS22
VSS20
VSS21
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
IC
P18
P22
P23
P24
P27
P32
R6
R11
R12
R13
R17
R18
R22
R23
R24
R27
R31
T4
T8
T11
T12
T13
T17
T18
T22
T23
T24
U6
U14
U15
U16
U19
U20
U21
U27
U32
V5
V14
V15
V16
V19
V20
V21
W4
W11
W8
W12
W13
W17
W18
W22
W23
W24
W27
W31
Y6
Y11
Y12
Y13
Y17
Y18
Y22
Y23
Y24
Y27
Y32
BGAX02056-010
[PAGE_TITLE=GPU, CO R E POWER + MEM POWER]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:11 2005
PAGE
17/73
REV
K7
V_GPUCORE
GPU, DECOUPLING
V_GPUCORE
C4R20
1
.1UF 10%
6.3V
X5R
402
C4R37
1
.1UF
6.3V
X5R
402
C4R59
1
.1UF
6.3V
X5R
402
C4T6
1
.1UF 10%
6.3V
X5R
402
C4T9
1
.1UF 10%
6.3V
X5R
402
C4R57
1
.1UF
6.3V
X5R
402
C4T11
1
.1UF
6.3V
X5R
402
C4T3
1
.1UF
6.3V
X5R
402
C4R52
1
.1UF
6.3V
X5R
402
C4R18
1
.1UF
6.3V
X5R
402
2
2
10%
2
10%
2
2
2
10%
2
10%
2
10%
2
10%
2
10%
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
1
1
1
1
1
1
1
1
1
1
C4R11
6.3V
X5R
402
C4R17
6.3V
X5R
402
C4R55
6.3V
X5R
402
C4R47
6.3V
X5R
402
C4T20
6.3V
X5R
402
C4R36
6.3V
X5R
402
C4R34
6.3V
X5R
402
C4R42
6.3V
X5R
402
C4T16
6.3V
X5R
402
C4T1
6.3V
X5R
402
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
C4R16
1
C4R21
1
1
C4T21
1
C4R46
1
1
C4R35
1
C4R54
1
C4R63
1
1
6.3V
6.3V
C4T5
6.3V
6.3V
6.3V
C4T8
6.3V
6.3V
6.3V
6.3V
C4T2
6.3V
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
2
10%
X5R
402
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
1
1
1
1
1
1
1
1
1
1
C4R28
6.3V
X5R
402
C4R22
6.3V
X5R
402
C4T23
6.3V
X5R
402
C4R44
6.3V
X5R
402
C4T24
6.3V
X5R
402
C4T19
6.3V
X5R
402
C4T18
6.3V
X5R
402
C4R62
6.3V
X5R
402
C4R43
6.3V
X5R
402
C4R56
6.3V
X5R
402
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
2
10%
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
1
.1UF
C4R13
6.3V
X5R
402
C5R17
6.3V
X5R
402
C4R53
6.3V
X5R
402
C4R41
6.3V
X5R
402
C4T26
6.3V
X5R
402
C4T25
6.3V
X5R
402
C4T4
6.3V
X5R
402
C4R58
6.3V
X5R
402
C4T10
6.3V
X5R
402
C4T15
6.3V
X5R
402
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
2
2
2
2
2
2
2
2
2
2
C5R9
2
1
.1UF
10%
6.3V
X5R
402
C5R16
2
1
.1UF
10% 10%
6.3V
X5R
402
C5R10
2
1
.1UF
10%
6.3V
X5R
402
C5R12
2
1
10%
.1UF
6.3V
X5R
402
C4R24
2
1
10%
.1UF
6.3V
X5R
402
C4R40
2
1
10%
.1UF
6.3V
X5R
402
C5R8
2
1
10%
.1UF
6.3V
X5R
402
C4R9
2
1
.1UF
10%
6.3V
X5R
402
C5R14
2
1
10%
.1UF
6.3V
X5R
402
C4R14
2
1
10%
.1UF
6.3V
X5R
402
1
.1UF
1
.1UF
2
.1UF
C4R39
6.3V
X5R
402
C4R49
6.3V
X5R
402
C4R67
6.3V
X5R
402
2
10%
2
1
10%
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
2
2
2
2
2
1
2
2
2
2
C5D2
6.3V
X5R
805
C4R30
6.3V
X5R
805
C5R5
6.3V
X5R
805
C5R4
6.3V
X5R
805
C5R20
6.3V
X5R
805
C5R2
6.3V
X5R
805
C5R1
6.3V
X5R
805
C5R3
6.3V
X5R
805
C5R11
6.3V
X5R
805
C5R6
6.3V
X5R
805
10%
10%
10%
10%
10%
10%
10%
10%
10%
10%
1
1
1
1
1
2
1
1
1
1
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
C4R29
2
C4T17
2
2
2
C6R47
2
C4R69
2
2
2
2
2
6.3V
X5R
805
6.3V
X5R
805
C6E2
6.3V
X5R
805
C6E1
6.3V
X5R
805
6.3V
X5R
805
6.3V
X5R
805
C5D3
6.3V
X5R
805
C5D4
6.3V
X5R
805
C5D6
6.3V
X5R
805
C5D5
6.3V
X5R
805
1
10%
1
10%
1
10%
1
10%
1
10%
1
10%
1
10%
1
10%
1
10%
1
10%
[PAGE_TITLE=GPU, DECOUPLING]
DRAWING
XENON_FABK
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAILWed Aug 24 09:27:12 2005
PAGE
18/73
REV
K7
V_1P8
FB1N1
2
1
1
C1N7
10UF
20%
6.3V
2
EMPTY
805
ENET_AVDD
1
2
C1N14
.1UF
10%
6.3V
EMPTY
402
EMPTY
60
603
0.5A
0.1DCR
1
C1N8
10UF
10%
6.3V
2
EMPTY
1206
OUT
19
ENET_CLK
46
39
IN
DB1N1
ENET_REF_C LK 2_O UT
1
3639
3639
IN
BI
IN
TP
3339
IN
3936
OUT
3936
OUT
3936
OUT
3936
OUT
3936
OUT
3936
OUT
3936
OUT
3639
IN
3639
IN
3639
IN
3639
IN
3639
IN
MII_MDC_CLK_OUT
MII_MDIO
3936
OUT
3936
OUT
ENET_AVDD
ENET_RST_N
MII_RX_CLK
MII_RXDV
MII_RXER
MII_RXD3
MII_RXD2
MII_RXD1
MII_TX_CLK
MII_T XEN
MII_T XD3
MII_T XD2
MII_T XD1
MII_T XD0
MII_COL
MII_CRS
1
V_ENET
39
1944
IN
3936
OUT
MII_RXD0
1
2
R1B12
4.7K
5%
EMPTY
402
19
2
U1B1
1
XTALI2
2
XTALO2
10
RESET_N
20
RXC
19
RX_DV/TEST0
21
RX_ER/TEST1
15
RXD3/ISOLATE
16
RXD2/F100
17
RXD1/ANEN
18
RXD0/PHYAD0
23
TXC
24
TX_EN
28
TXD3
27
TXD2
26
TXD1
25
TXD0
14
MDC_CLK_OUT
13
MDIO
29
COL/ENERGYDET
30
CRS/LOWPWR0
31
REGVDDIN
32
REGVDDOUT
C1N6
X801554-001 LCC32
.1UF
10%
6.3V
EMPTY
402
BCM5241
EMPTY
OVDD2
OVDD1
AVDD
LINK#
ACT#
RDAC
TDP
TDN
RDP
RDN
GND
22
9
7
12
11
3
4
6
5
8
33
ENET_AVDD
ENET_LINK_N
ENET_ACT_N
ENET_RX_DP
ENET_RX_DN
ENET_TX_DP
ENET_TX_DN
ENET_RDAC
1
R1N8
1.27K
1%
EMPTY
402
2
V_ENET
OUT
OUT
OUT
OUT
OUT
OUT
39 19
44
IN
19
IN
39
44
39
44
39
44
39
44
39
44
39
44
[PAGE_TITLE=DUAL ETHERNET PHY]
DRAWING
XENON_FABK
Wed Aug 24 09:27:13 2005
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAIL
PAGE
19/73
REV
K7
MEMORY PARTITION A, TOP
V_MEM
1
1
R4F3
R4F4
60.4
60.4
1%
1%
CH
CH
402
402
2
MA_CLK0_DP
14
IN
MA_CLK0_DN
14
IN
MEM_RST
1321
222324252627
IN
MA_A<11..0>
1421
IN
MA_BA<2..0>
1421
IN
14
21
IN
21
14
IN
14
21
IN
14
21
IN
14
IN
12222426
IN
12
21
27
2223242526
IN
20
21
IN
21
IN
2
11
10
9
8
7
6
5
4
2
1
0
2
1
MA_CKE
MA_WE_N
MA_CAS_N
MA_RAS_N
MA_CS0_N
0
MEM_SCAN_TOP_EN
MEM_SCAN_EN
MEM_A_VREF1
MEM_A_VREF0
U4F1
J11
CLK_DP
J10
CLK_DN
V9
RESET
L4
A11/A7
K2
A10/A8
M9
A9/A3
K11
A8/A10
L9
A7/A11
K10
A6/A2
H11
A5/A1
K9
A4/A0
M4
3
H10
H12
K3
H2
K4
G9
G4
H4
H9
F4
H3
F9
A9
V4
H1
A3/A9
A2/A6
A1/A5
A0/A4
BA2/RAS_N
BA1/BA0
BA0/BA1
CKE/WE_N
WE_N/CKE
CAS_N/CS_N
RAS_N/BA2
CS_N/CAS_N
MF
SCAN_EN
VREF1
VREF0
GDDR136
MF=0
V_MEM
1
R4U4
549
1%
CH
402
2
MEM_A_VREF1
1
R4U5
C4U9
.1UF
1.27K
10%
1%
6.3V
CH
X5R
402
2
402
X801995-006
OUT
20
21
CHIP SELECT = 0, MIRROR FUNCTION = 0
IC
MA_DQ31
T3
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WDQS1
RDQS1
WDQS0
RDQS0
DM3
DM2
DQ9
DQ8
DM1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
DM0
MA_DQ30
T2
MA_DQ29
R3
MA_DQ28
R2
MA_DQ27
M3
MA_DQ26
N2
MA_DQ25
L3
MA_DQ24
M2
MA_WDQS3
P2
P3
MA_RDQS3
MA_DM3
N3
T10
MA_DQ23
T11
MA_DQ22
R10
MA_DQ21
MA_DQ20
R11
M10
MA_DQ19
MA_DQ18
N11
MA_DQ17
L10
MA_DQ16
M11
P11
MA_WDQS2
P10
MA_RDQS2
N10
MA_DM2
G10
MA_DQ15
F11
MA_DQ14
MA_DQ13
F10
E11
MA_DQ12
C10
MA_DQ11
C11
MA_DQ10
MA_DQ9
B10
MA_DQ8
B11
MA_WDQS1
D11
MA_RDQS1
D10
MA_DM1
E10
MA_DQ7
G3
MA_DQ6
F2
MA_DQ5
F3
MA_DQ4
E2
MA_DQ3
C3
MA_DQ2
C2
MA_DQ1
B3
MA_DQ0
B2
D2
MA_WDQS0
MA_RDQS0
D3
E3
MA_DM0
A4
MA_ZQ_TOP
ZQ
1
2
R3F1
243
1%
CH
402
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
OUT
IN
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14
21
21 14
14
21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14
21
21 14
14
21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14
21
21 14
14
21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14 21
14
21
21 14
14
21
PARTITION A DECOUPLING
V_MEM
1
2
C4F12
10UF
10%
6.3V
X5R
1206
V_MEM
V_MEM
U4F1
V1
R12
VDDQ<20>
R9
VDDQ<19>
R4
R1
VDDQ<17>
N12
VDDQ<16> VSSQ<16>
N9
VDDQ<15>
V12
VDDQ<14>
N4
VDDQ<13>
N1
VDDQ<12>
J9
VDDQ<11>
J4
VDDQ<10>
E12
VDDQ<9>
E9
VDDQ<8>
E4
VDDQ<7>
E1
VDDQ<6>
C12
VDDQ<5>
C9
VDDQ<4>
C4
VDDQ<3>
C1
VDDQ<2>
A12
VDDQ<1>
A1
VDDQ<0>
V2
VDD<7>
M12
VDD<6>
M1
VDD<5>
V11
VDD<4>
F12
VDD<3>
F1
VDD<2>
A11
VDD<1>
A2
VDD<0>
K12
VDDA<1>
K1
VDDA<0>
J12
VSSA<1>
J1
VSSA<0>
X801995-006
MEMORY A, TOP, DECOUPLING
C3F3 C4F9 C4F11 C4F7
.22UF
.22UF
.22UF
10%
10%
6.3V
6.3V
X5R
X5R
402
402
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
GDDR136
MF=0VDDQ<21>
C3F1 C4F1
.22UF
10%
6.3V
X5R
402
VSSQ<19>
VSSQ<18>VDDQ<18>
VSSQ<17>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>
.22UF
10%
6.3V
X5R
402
VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>
NC<1>
NC<0>
C4F6 C4F3
.22UF
10%
6.3V
X5R
402
IC
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1
V3
L12
L1
G12
G1
A10
V10
A3
J3
J2
.22UF
10%
6.3V
X5R
402
[PAGE_TITLE=MEMORY PAR TITION A, TOP]
DRAWING
XENON_FABK
Wed Aug 24 09:27:13 2005
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAIL
PAGE
20/73
REV
K7
V_MEM
1
1
R4U2
R4U3
60.4
60.4
1%
1%
CH
CH
402
402
2
2
MA_CLK1_DP
14
IN
14
13
20222324
27
2526
14
20
MA_CLK1_DN
IN
MEM_RST
IN
MA_A<11..0>
IN
MA_BA<2..0>
14
20
IN
MA_CKE
1420
IN
MA_WE_N
1420
IN
MA_CAS_N
1420
IN
MA_RAS_N
1420
IN
MA_CS1_N
14
IN
MEM_SCAN_BOT_EN
12232527
IN
MEM_SCAN_EN
12202223242526
IN
27
MEM_A_VREF0
21
20
IN
MEM_A_VREF1
20
IN
U4U1
J11
CLK_DP
J10
CLK_DN
V9
RESET
L9
11
A7/A11
K11
10
A8/A10
M4
9
A3/A9
K2
8
A10/A8
L4
7
A11/A7
K3
6
A2/A6
H2
5
A1/A5
K4
4
A0/A4
M9
3
A9/A3
K10
2
A6/A2
H11
1
A5/A1
K9
0
A4/A0
H3
2
RAS_N/BA2
G4
1
BA0/BA1
G9
0
BA1/BA0
H9
WE_N/CKE
H4
CKE/WE_N
F9
CS_N/CAS_N
H10
BA2/RAS_N
F4
CAS_N/CS_N
A9
MF
V4
SCAN_EN
H1
VREF1
H12
VREF0
GDDR136
MF=1
V_MEM
1
R4F1
549
1%
CH
402
2
MEM_A_VREF0
1
R4F2
C4F2
.1UF1.27K
10%
1%
6.3V
CH
X5R
402
2
402
X801995-006
OUT
20
21
MEMORYPARTITION A, BOTTOM
CHIP SELECT = 1, MIRROR FUNCTION = 1
IC
MA_DQ23
T3
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
WDQS3
RDQS3
DM3
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
WDQS2
RDQS2
DM2
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
WDQS1
RDQS1
DM1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WDQS0
RDQS0
DM0
MA_DQ22
T2
MA_DQ21
R3
MA_DQ20
R2
MA_DQ19
M3
MA_DQ18
N2
MA_DQ17
L3
MA_DQ16
M2
MA_WDQS2
P2
MA_RDQS2
P3
MA_DM2
N3
MA_DQ31
T10
MA_DQ30
T11
MA_DQ29
R10
MA_DQ28
R11
MA_DQ27
M10
MA_DQ26
N11
MA_DQ25
L10
MA_DQ24
M11
MA_WDQS3
P11
MA_RDQS3
P10
MA_DM3
N10
MA_DQ7
G10
MA_DQ6
F11
MA_DQ5
F10
MA_DQ4
E11
MA_DQ3
C10
MA_DQ2
C11
MA_DQ1
B10
MA_DQ0
B11
MA_WDQS0
D11
MA_RDQS0
D10
MA_DM0
E10
MA_DQ15
G3
MA_DQ14
F2
MA_DQ13
F3
MA_DQ12
E2
MA_DQ11
C3
MA_DQ10
C2
MA_DQ9
B3
MA_DQ8
B2
MA_WDQS1
D2
MA_RDQS1
D3
MA_DM1
E3
MA_ZQ_BOT
A4
ZQ
1
R3U1
243
1%
CH
402
2
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14 20
IN
20 14
OUT
14 20
IN
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14 20
IN
20 14
OUT
14 20
IN
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14 20
IN
20 14
OUT
14 20
IN
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14
20
BI
14 20
IN
20 14
OUT
14 20
IN
V_MEM
U4U1
V1
R12
VDDQ<20>
R9
VDDQ<19>
R4
VDDQ<18>
R1
VDDQ<17>
N12
VDDQ<16>
N9
VDDQ<15>
V12
VDDQ<14>
N4
VDDQ<13>
N1
VDDQ<12>
J9
VDDQ<11>
J4
VDDQ<10>
E12
VDDQ<9>
E9
VDDQ<8>
E4
VDDQ<7>
E1
VDDQ<6>
C12
VDDQ<5>
C9
VDDQ<4>
C4
VDDQ<3>
C1
VDDQ<2>
A12
VDDQ<1>
A1
VDDQ<0>
V2
VDD<7>
M12
VDD<6>
M1
VDD<5>
V11
VDD<4>
F12
VDD<3>
F1
VDD<2>
A11
VDD<1>
A2
VDD<0>
K12
VDDA<1>
K1
VDDA<0>
J12
VSSA<1>
J1
VSSA<0>
X801995-006
V_MEM
MEMORY A, BOTTOM , DECOUPLING
C3U2 C4U8 C4U11 C4U6
.22UF
.22UF
10%
10%
6.3V
6.3V
X5R
X5R
402
402
.22UF
10%
6.3V
X5R
402
.22UF
10%
6.3V
X5R
402
GDDR136
MF=1VDDQ<21>
VSSQ<19>
VSSQ<18>
VSSQ<17>
VSSQ<16>
VSSQ<15>
VSSQ<14>
VSSQ<13>
VSSQ<12>
VSSQ<11>
VSSQ<10>
C3U1 C4U1
.22UF
.22UF
10%
10%
6.3V
6.3V
X5R
X5R
402
402
VSSQ<9>
VSSQ<8>
VSSQ<7>
VSSQ<6>
VSSQ<5>
VSSQ<4>
VSSQ<3>
VSSQ<2>
VSSQ<1>
VSSQ<0>
VSS<7>
VSS<6>
VSS<5>
VSS<4>
VSS<3>
VSS<2>
VSS<1>
VSS<0>
NC<1>
NC<0>
IC
T12
T9
T4
T1
P12
P9
P4
P1
L11
L2
G11
G2
D12
D9
D4
D1
B12
B9
B4
B1
V3
L12
L1
G12
G1
A10
V10
A3
J3
J2
C4U5 C4U2
.22UF
.22UF
10%
10%
6.3V
6.3V
X5R
X5R
402
402
[PAGE_TITLE=MEMORY PARITION A, BOTTOM]
DRAWING
XENON_FABK
Wed Aug 24 09:27:14 2005
MICROSOFT
CONFIDENTIAL
PROJECT NAME
XENON_RETAIL
PAGE
21/73
REV
K7
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