Microsoft Surface Pro 4 Schematic (i7-6650U CPU only )
5
Table of Contents
4
3
2
1
Page
01
D D
02
03
0
4
05
06
07
08
09
10
11
C C
12
13
Title
CHANGE HISTORY
BLOCK DIAGRAM
CLOCK DISTRIBUTION
SIGNAL & RESET MAP
POWER FLOW
POWER DISTRIBUTION
POWER SEQUENCE
I2C MAP
CPU(1)_MISC,JTAG,DDI.EDP
CPU(2)_LPDDR3
CPU(3)_SKL POWER1
CPU(4)_SKL_POWER2
Page
31
32
33
34
35
36
37
38
39
40
41
42
43
Title
Sensor-uC
On Board-Sensors
Debug Conn
Empty
SM BUS
EC-ITE 8528VG-1
EC-ITE 8528VG-2/SPI ROM
TPM
Temp Sensor/System Fan
REALTEK ALC298 CODEC
Audio Jack/Vol Button/Spkr
Microphones
M.2 SSD CONNECTOR
Page
61
62
63
64
65
66
67
68
69
70
71
72
73
Title
+1VSB
+1.8VSB & Load SW
CHARGER
+5V Load SW
+3P3V Load SW
VCPU Controller
VCORE VCCSA
VCVGT
EMPTY (was GTX Reg)
SL1 PWR/ BATT CONN.
SL1 SIGNALS
+3P3V_HPD/LCD backlight/TB
BLADE PWR
14
15
16
17
18
19
20
B B
21
22
23
24
25
26
27
28
CPU(5)_GND
CPU(6)_CFG_RESERVED
LPDDR3(1)_MEMORY DOWN
LPDDR3(2)_MEMORY DOWN
XDP
LPDDR3(3)_CA/DQ Voltage
PCH(1)_SD,HDA,RTC, CLK
PCH(2)_CLK,SMB,LPC, SPI
PCH(3)_SYS PWR CONTR
PCH(4)_CCI, HWID
PCH(5)_PCIE,USB
PCH(6)_CPU,GPIO,MISC
PCH(7)_POWER
PCH(8)_empty
Power Monitor
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Empty
USB3.0
DP Dongle Control
mDP
SDXC
Camera IR
Wi-Fi_BT
Components for ME/EMI
Camera Power
Camera Rear
Camera Front
3P3VA & BKL PWR
+VCCIO & 0P85VSB
eDP connector
+VCCEDRAM & +VCCEOPIO
74
75
76
BLADE
Power Protect
Test Points
29
30
A A
CAD Note:
Default component footprint is SMD 0201, X5R, 1% resistors.
Property: BUILD-OPT
DNP = Do Not Place
Empty
Touch Con & Key
5
59
60
+5VSB & +3P3VSB
+1P2V_DUAL&+VTT
4
S or DB = Replace after Debug
3
2
<Core Design>
<Core Design>
<Core Design>
Table of Contents
Table of Contents
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Table of Contents
Surface
Surface
Surface
1 76Monday, May 11, 2015
1 76Monday, May 11, 2015
1
1 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
Schematics Change History
4
3
2
1
Rev.
0p9 28 Oct 2014 1. Starting with G_EV1_1021-1630.DSN
D D
0p10 3 Nov 2014 1. Changing to NVDC
0p12 11 Nov 2014 1. Model DDR connection from Intel SDS
0p13 18 Nov 2014
0p14
C C
0p15 26 Nov 2014
0p16 03 Dec 2014
Date
20 Nov 2014
2. Added SL schematic from page 72 ...\T\MB\DV_RELEASED\Schematic\CASTLE2_DV_2014_1021_1100.DSN
3. Added External USB3 schematic from ...\T\MB\DV_RELEASED\Schematic\CASTLE2_DV_2014_1021_1100.DSN
4. Added external DP ...\T\MB\DV_RELEASED\Schematic\CASTLE2_DV_2014_1021_1100.DSN
5. Added IR_CAMERA from Front Camera...put in page 49
6. Removed page 73 PCIe GPU
7. Added Blade from T
8. Removed P72 T2B Pwr Transistors
2. Replaced GTX with GT, kept bypass caps
3. Replaced Charger with BQ24770
1. Replace SKL-U with SKL-Y0p11 3 Nov 2014
1. Added FUB information to all components
2. Changed Decretes.. sizing caps
1. Added +5VA_SHA
2. Added T Cost Down/XCN's
3. Added SL +5V load Switch & Caps
4. Added Blade +5V load Switch & Caps
1. Removed Boost
2. Re-adjusted usb ports on CPU
3. Removed Audio DSP
1. changed +1VSB regulator
2. changed IR Camera/added diode
3. added power numbers from 0.91 PDG, Oct14
4. changed BLADE connector
5. cpu decoupling caps changed
6. changed +5V/+3V inductors (place holder)
Comments
1. swapped M_A_CAA with MA_CAB on U1601/U1602
2. added two SAR chips, P32
3. remove tp's from csi lines on (p23)
4. change from 10 ceramic to 3 tantalum-poly on usb3 typeA (p45)
5. remove the RSENSE from output of +VCCIO(p56)/+0p85VSB(p56)/+VCCEDRAM (p58)/+VCCEOPIO (p58)/+1VSB(p61)/+1P8VSB(p62)
0p17 05 Dec 2014
B B
A A
0p18
0p19
0p20 15 Dec 2014
0p21 16 Dec 2014
0p22 17 Dec 2014 1. Replaced SD connector with AY531465T
0p23
current
09 Dec 2014
12 Dec 2014
-
6. change RSENSE input to 0402 from 0603 for +VCCIO(p56)/+0p85VSB(p56)/+VCCEDRAM (p58)/+VCCEOPIO (p58)/+1VSB(p61)/+1P8VSB(p62) input regulator
7. change inductor for +VCCIO(p56)/+0p85VSB(p56)/+VCCEDRAM (p58) to HMLE20161B-1R0MDR-01
8. change RSENSE input to 0402 from 0603 for +5V_TS,+5V_SDXC,+5V_AUDIO,+5V, +5V_FAN(p64)
9. change RSENSE input to 0402 from 0603 for +3P3V_PANEL,+3P3V,+3P3V_SENSOR,+1P8V_DMIC (p65)
10. Replacing the SL connector with X908351-001
11. Replace PL5901 and PL5902 with CMLE042T-2R2MS-01
12. Replace 0402 1uf 6.3V with 0201 1uF 6.3V X5R
13. Replace L7201 with TOKO #A919CY-100M
14. Added VSYS -> BLADE FANG supply (p73)
1. Reduced sizes of parts for Cameras (Resistors/Caps/Regulators)
1. All 47uF caps become 0805/1mmZ
2. All 10uF caps become 0402...4V/6.3V
1. changed SAM flash to reduce size to 2x3 from 5x4
2. Shui Changes
3. more Shui Changes
1. changed SAM flash to reduce size to 2x3 from 5x5
2. changes from EV_schematic_issue_check_1216_JDM1.xlsx
3. changed name of +6_12 to +V_ALWAYS_ON
4. Removed 2 Mikes & Front Mike & added FPC conn
5. Added 2nd BLADE connector
2. changes from EV_schematic_issue_check_viola_1217_JDM1.xlsx
1. See apexUfixes_revXpXX.xlsx
CAD Note:
Default component footprint is SMD 0201, X5R, 1% resistors
Property: BUILD-OPT
DNP = Not Installed Part.
5
4
S = Short after design fixed
3
CHANGE HISTORY-1
CHANGE HISTORY-1
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
CHANGE HISTORY-1
Surface
Surface
Surface
2 76Monday, May 11, 2015
2 76Monday, May 11, 2015
1
2 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
4
3
2
1
LPDDR3 2GB/4GB/8GB
2 x32 @1600MHz
page 16
LPDDR3 2GB/4GB/8GB
2 x32 @1600MHz
D D
16MB UEFI EEPROM
page 17
W25Q128FVPIQ
page 37
CH A
CH B
QSPI
eDP
Display TCON
Connector
page 57
DP 4 Lane + AUX(B)
USB2.0(0) LPM + USB3.0(1)
USB2.0(0) LPM + USB3.0(1)
ANX2875
page 47
page 45
page 71
page 70
Power
DP Connector
USB3
TYPE A
Connector
SPI / I2C4
Intel Processor
SKL
DP 4 Lane
PCH UART(Debug)
page 71
AUX(C)
HPD/CONFIG1
EC Debug UART
2:1 MUX
page 71
AUX(C)/PCH UART
2:1 MUX
DP/ EC Debug UART
SAM Debug UART
page 71
SURF LINK
Connector
page 47,71
SAR
ADI / ADUX1050
SAR
ADI / ADUX1051
Touch Connector
page 30
page 32
I2C0
page 32
15W (BGA1168)
C C
Accelerometer+Gyro
Bosch / BMI160
page 32
Sensor
Aggregator
Microcontroller
256/512/
1024GB SSD
Full size
mSATA card
E-compass (Magnetometer)
MEMSIC / MMC34160PJ
page 32
I2C_SCL_MCU
ALS/Proximity-Sensor
Intersil / ISL29033
B B
page 32
SAM
MKL33Z256VMP4
OR
MKL17Z256VMP4
HOST_AUTH_RX/TX
SAM_SPI
page 31
LPDDR3 Thermal Sensor
STTS751-1DP3F
Surrend Thermal Sensor
SEN_HALL_INT
STTS751-1DP3F
Hall Effect Sensor IC
ROHM / BU52058GWZ-E2
page 32
M2 2280
B-M Type
Connector
page 43
PCIe x2
or SATA
Authentication
ATECC108
page 31
SAM reflash
image backup
EEPROM
MX25L4006EZNI-12G
page 39
page 31
SMBUS3
SMBUS3
PROCHOT#
page 20~28
SMBUS2 PECI
LPC BUS
24MHz
MIPI
MIPI
MIPI
PCIe
USB2.0(5)
480Mb/s
TPM
SLB9665TT
USB3 (only)
Front Webcam
Connector
5MP
Rear Webcam
Con
8MP
IR VGA CAMERA
Connector
HD Audio
page 38
page 54
nector
page 53
page 49
Marvell 8897
WLAN 802.11 /b/g/n/AC
Bluetooth 4.0
page 50
AUDIO CODEC
Realtek
ALC298
USB2 to SDXC
RTS5304-GR
page 48
WIFI ANT1
WIFI ANT2
MIMO
page 40
SPKR L/R
Audio+mic
SDIO
Speaker
L+/-, R+/-
AUDIO IN/OUT
DMIC1 Onboard
SDIO CONN
page 49
page 42
page 41
page 43
SEN_HALL_INT_EC
System EC
Battery Charge
A A
40Wh
Battery
page 70
+7.4V
Controller
BQ24770
SMBUS1 + CTRL
page 63
ITE 8528
page 36
PWM/TACH
SPI
EC_SAM_I2C
5
4
3
FAN Connector
page 39
EC EEPROM
page 37
2
BLOCK DIAGRAM
BLOCK DIAGRAM
Title:
Title:
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
1
BLOCK DIAGRAM
Surface
Surface
Surface
3 76Monday, May 11, 2015
3 76Monday, May 11, 2015
3 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
4
3
2
1
HSW Buffer Through Mode for Pre-Silicon
D D
WIFI_32K_CLK
32 KHz
88W8897-XX-CBK2
M_CHA_CLK[0..1]/#
SUS_CLK
M_CHB_CLK[0..1]/#
DIMM2
DIMM1
CLKOUT_LPC_0
CK_24M_EC
24 MHz
ITE 8528VG/FX
32.768KHz
Intel
C C
SKL U/Y
CK_24M_DEBUG
24 MHz
CLKOUT_LPC_1
CLKOUT_ITXDP_N
CLKOUT_ITXDP_P
B B
CLKOUT_PCIE_N2
CLKOUT_PCIE_P2
CLK_XDP_N
CLK_XDP_P
PCIE_WIFI_RCLK_N
PCIE_WIFI_RCLK_P
CK_24M_TPM
24 MHz
XDP
100 MHz
WIFI
100 MHz
LPC DEBUG HEADER
TPM
CLKOUT_PCIE_N4
CLKOUT_PCIE_P4
HDA_BCLK
SPI_CLK
A A
PCIECLK_SL1_N
PCIECLK_SL1_P
100 MHz
AZ_BITCLK
24 MHz
SPI_CLK
50 MHz
SL1
AUDIO CODEC
SPI ROM
XTAL24_IN RTCX
<Core Design>
<Core Design>
<Core Design>
CLOCK DISTRIBUTION(TBD)
CLOCK DISTRIBUTION(TBD)
Title:
Title:
Title:
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
32.768KHz24MHz
5
4
3
2
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
Engineer:
Engineer:
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
CLOCK DISTRIBUTION(TBD)
Surface
Surface
Surface
4 76Monday, May 11, 2015
4 76Monday, May 11, 2015
1
4 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
Battery
VDD_
4
BATA_PACK
3
2
1
D D
SL1
PWR_SL1
PWR_SL1_F
CHG_BATDRV_R_ A
FET
SW
Switch
(Dio
USER_RESET
Charging
SL1_PWR_GOOD
EC_SL1_PWR_EN
C C
SW
EXT_DC_IN
circuit
& Switch
VCCDSW
POWER ON SEQUENCE (TBD)
STEP1Signal & Description
+6VA_12VA /TRANSLATE TO +3P3VAS,
+3P3V_EC /EC POWER
2
EC_RST# /EC INITIAL
3
+AC
4.
5.
6.
7.
8.
9.
10.
11.
B B
12
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
A A
_BAT_SYS /SYSTEM POWER READY
VCCDSW_EN /TURN ON DSW POWER for PCH
PCH_DPWROK /DEEP POWER GOOD TO PCH
SLP_SUS# /STANBY POWER REQUIRED
VSUS_ON/EC TURN ON STANBY POWER
ALL_SUS_PWRGD /STANDBY(SUS) POWER STABLE
RSMRST# /SUS POWER GOOD TO PCH
EC_SAM_INT_IN
PWRBTN# TO EC
SB_PWRBTN# /PASS PWRBTN SIGNAL TO PCH
PM_SUSC#(SLP_S4#) /EXIT S4 STATE, HIGH
SUSC_EC# /BYPASS SLP_S4#
PM_SUSB#(SLP_S3#) /EXIT S3 STATE, HIGH
SUSB_EC# /BYPASS SLP_S3#, MAIN PWR ON
ALL_SYS_PWRGD /SYSTEM POWER STABLE
VCCST_PWRGD/ INDICTOR TO CPU
VRM_PWRGN /POWER FOR CPU IS GOOD
PM_PCH_PWROK /PCH CORE POWER OK AT LEAST 5ms
SYS_PWROK /SYSTEM POWER STABLE
SVID /VR controller establish protocol to CPU
PLTRST# /ALL SET UP AND RESET TO INITIAL
+V_VDDQ_VTT
+1P2V_DUAL
+1P8V_DUAL
+VCCST_CPU
+AC_BAT_SYS
1-2
+VCCIO
+VCCSTG
+1P8V
+3P3V
+3P3V_SSD
+5V
de)
1-1
+V_ALWAYS_ON
VOLT REG.
MAX6443
3P3VA_EN
Step-Down
+3P3V_EC
5
VCCDSW_EN
+3P3VSB
+5VSB
+1P8VSB
+0P85VSB
+1VSB
+1VS
B is last one ramp up
+1P2V_DUAL_PW RGD
ALL_SUS_PWRGD
VRM_PWRGD
ALL_SYS_PWRGD
+VCCIO_PWRGD
+3P3VA, +1P8V A
+VCC_RTC
+5V_SHA
2
+3P3V_EC
Power
Button
11
SAM
EC_SAM_INT_IN
VSUS_ON
8
ALL_SUS_PWRGD
9
15
SUSC_EC#
17
SUSB_EC#
+VCCEDRAM
+VCCEOPIO
VCORE
VCCGT
VCCGTX
VCCSA
FORCE_OFF#
PWRBTN#_EC
PWRB
12
18
ALL_SYS_PWRGD
EN
20
VRDY
EC Reset
circuit
TN#
CPU_VRON
VRM_PWRGD
3
EC_RST#
WRST#
EC
IT8528
13
10
6
7
PM_PCH_PWROK
SYS_PWROK
VCCST_PWRGD
19
OD
STUFF
0 ohm
23
SVID
SB_PWRBTN#
RSMRST#
PCH_DPWROK
SLP_SUS#
21
22
PWRBTN#
RSMRST#
DSW_PWROK
SLP_SUS#
PCH_PWROK
SYS_PWROK
VCCST_PWRGD
Intel
SKL U
PM_SUSC#
14
PM_SUSB#
16
SLP_S3#
SLP_S4#
EC etc.
PLTRST#
24
PLTRST#
1V TO 3.3V
ER
SHIFT
Power On Sequence
1
24
TPM
<Core Design>
<Core Design>
<Core Design>
SIGNAL&RESET MAP
SIGNAL&RESET MAP
Title:
Title:
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A2
A2
A2
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
1
SIGNAL&RESET MAP
Surface
Surface
Surface
1.90.2
1.90.2
5 76Monday, May 11, 2015
5 76Monday, May 11, 2015
5 76Monday, May 11, 2015
1.90.2
5
12V
ADAPTER
+V_ALWAYS_ON
3A
0.45A
A B
Charger
PWR_SL1_F
D D
+AC_BAT_SYS
C C
B B
Switching
Linear
A A
Switch ON/OFF
0.564A
3.125A
5.16A
2.76A
1.7A
0.28A
4
0.075A
0.075A
+5VA_EN
3P3VAS_EN
NCP4623
TPS62175DQCR
Efficiency is about 90%
3P3VA_EN
NCP4623
TPS51624
Efficiency is about 80%
CPU_VR_EN
CSD87351Q5D
TPS51285
Efficiency is about 90%
CSD87351Q5D
TPS51285
Efficiency is about 90%
VSUS_ON
TPS51367
Efficiency is about 80%
SUSC_EC#
TPS51367
Efficiency is about 80%
SUSB_EC#
TPS62140
INT-MOS
Efficiency is about 80%
SUSC_EC#
3
3P3V_EC_EN
& 3P3VA_EN
VCCDSW_EN
3P3V_EC_EN
& 3P3VA_EN
SL1_3P3V_DIS
+3P3V_PANEL
RT9728
0.49A0.3A
BLADE_AUTH_PWR_EN
RST
32A
5.58A
0.7A
SUSB_EC#
0.9A
RTD3_CR_PWREN
1.07A
SUSB_EC#
0.9A
USB_PWREN
1.5A
SL1_5V_PWR_EN
0.5A
BLADE_5V_PWR_EN
0.0027A
4.51A
0.062A
2.013A
SUSB_EC#
0.0313A
0.0094A
RTD3_TPANEL_PWR
0.451A
EDP_VDD_EN
1.5A
WWAN_PWREN
0.007375A
SENSORS_PWR_EN
+3P3V_TS
SUSB_EC#
0.0033A
0.61A
RTD3_CAM_PWREN
06Dec14 jks: NEEDS UPDATE
6.8A
SUSC_EC#
0.0239A
DDR_PG_CTRL
MPHY_PWREN
SUSB_EC#
5.248A 1.148A
0.741A
NX3P1108UK
NX3P1108UK
ADP151
RT9728
P-MOS
SLG59M301
SLG59M301
SLG59M301
NCP380
NCP380
NCP380
G5244A31U
TPS22920
NX3P1108UK
NX3P1108UK
G5244A31U
TPS22920
NX3P1108UK
TPS22920
TPS51206
SLG5NT1477VTR
NX3P1108UK
2
0.023A
0.0012A
0.00368A
SN_AB_GPIO_6
0.122A
SN_A_GPIO_5
SN_B_GPIO_5
0.07A
SN_A_GPIO_6
0.07A
SN_B_GPIO_6
0.0882A
SN_AB_GPIO_6
+1P8V_AUDIO
+3P3V_CAM
+3P3V_CAM
CS_ENTRY#
+5V_AUDIO
SUSB_EC#
TPS62590DRVR
Efficiency is about 90%
RT9013-25GQW
RT9013-25GQW
RT9013-18GQW
RT9013-28GU5
RT9013-28GU5
RT9013-18GQW
RT9030-11GU5
+3P3V
SLG59M301
TPS79901
TPS79901
NCP380
0.625A0.232A
S0/S3/S5
S0/S3/S5
S0/S3/S5
S0/S3/S5
S0/S3/S5
S0/S3/S5
S0
S0
S0/S3/S5
S0
S0
S0
S0
S0
S0
S0
S0
S0
S0/S3/S5
S0
S0
S0
S0
S0
S0
S0
S0
S0/S3/S5
S0/S3
S0
S0
S0
S0/S3
S0
S0
1
+5VA_SHA
+5V_SHA_CONN
Imax =0.075A
+3P3VA
Imax=0.18805A
+3P3V_EC
Imax =0.0375A
+VCCDSW
Imax =0.15A
+1P8V_EC
Imax=0.11A
+VCC_RTC
+3P3V_HPD
Imax=0.075A
+VCC_EDP_BKLT_IN
TDC= 0.3948A Imax = 0.564A
+VCORE
TDC =10A Imax = 32A
+5VSB
+5V
+5V_FAN
Imax = 0.7A
+5V_SDXC
TDC= 0.63A Imax =0.9A
+5V_AUDIO
TDC=0.735A Imax = 1.05A
DMIC_3P3V
Imax = 0.02A
+5V_USBPWR
TDC= 0.63A Imax =0.9A
+5V_SL1
Imax =1.5A
+5V_KB_CONN
Imax =0.5A
+5V_TS
Imax = 0.0027A
+3P3VSB
Imax = 0.062A
+3P3V
Imax = 0.31A
+3P3V_SSD
Imax = 1.2A
+1P5V
TDC= 0.003A Imax = 0.003A
DP_3P3V_PWR_FUSE
Imax=0.5A
+3P3V_AUDIO
Imax =0.0313A
+3P3V_TS
TDC= 0.0094A
+3P3V_PANEL
Imax = 0.451A
+3P3V_WWAN
TDC= 1.05A Imax = 1.5A
+3P3V_SENSOR
Imax = 0.007375A
+3P3V_MUX
Imax = 0.0033A
S0
+3P3V_CAM
Imax =0.006A
S0
+3P3V_USB_CAM
Imax = 0.017A
S0
+1P1V_CAM
Imax = 0.61A
S0
+1P1V_USB_CAM
Imax = 0.014A
S0
+1P1V_PLLD_CAM
Imax = 0.0016A
S0
+2P5V_CAM
Imax = 0.001A
S0
+2P5V_PLL_CAM
Imax = 0.000168A
S0
+2P5V_MIPI_CAM_A
Imax = 0.00184A
S0
+2P5V_MIPI_CAM_B
Imax = 0.00184A
S0
+1P8V_VDD_CAM_A
Imax = 0.061A
S0
+1P8V_VDD_CAM_B
Imax = 0.061A
S0
+2P8V_CAM_A
Imax = 0.07A
S0
+2P8V_CAM_B
Imax = 0.07A
S0
+1P8V_CAM_A
Imax = 0.0441A
S0
+1P8V_CAM_B
Imax = 0.0441A
+1P2V_DUAL
TDC=4A Imax =5.71A
+V_VDDQ_VTT
Imax = 1A
+1P05V
TDC = 2.387A Imax = 3.41A
+1P05V_MODPHY
TDC= 1.29A Imax = 1.838A
+1P8V_DUAL
TDC=0.5A Imax = 0.717A
+1P8V_AUDIO
Imax = 0.005A
+1P1V_AUDIO
Imax =0.0189A
<Core Des ign>
<Core Des ign>
<Core Des ign>
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
1
POWER FLOW
POWER FLOW
POWER FLOW
Surface
Surface
Surface
6 76Monday, May 11, 201 5
6 76Monday, May 11, 201 5
6 76Monday, May 11, 201 5
1.90.2
1.90.2
1.90.2
5
4
3
2
1
CPU Haswell ULT
+VCORE
+1P05V
+DDR_V
(+1P2V_DUAL)
D D
+1P05V
+1P05V_MODPHY
+1P5V
+3P3V
+3P3VSB
+3P3VA
-> 32A
-> 0.6A
-> 2.5A
-> 2.81A
-> 1.838A
-> 0.003A
-> 0.200A
-> 0.062A
-> 0.099A
(+3P3V)
+5V_SDXC
+3P3V_WWAN
DMIC_+3P3V/+3P3V_AUDIO
+5V_FAN
LPDDR3
+1P8V_DUAL
+1P2V_DUAL
+VTT_DDQ_VTT(0.6V)
C C
+3P3V
06Dec14 jks: NEEDS UPDATE
+3P3V_EC
-> 0.717A
-> 3.210A
-> 1A
-> 1.2A
-> 0.012A
mSATA(SSD)
EC
+3P3V
VCC_EDP_BKLT_IN
+3P3V_PANEL
+3P3VA
EC ROM
+3P3V_EC
+3P3VA
-> 0.005A
-> 0.00025A
+3P3V_TS
+5V_TS
Temp sensor(STTS751)
+3P3V_EC
B B
+1P1V_CAM
+1P1V_PLLD_CAM
+1P1V_USB_CAM
+1P8V_CAM
+1P8V_VDD_CAM
+2P5V_CAM
+2P5V_PLL_CAM
+2P5V_MIPI_CAM
+2P8V_CAM
+3P3V_CAM
A A
+3P3V_USB_CAM
-> 0.00025A
-> 0.609A
-> 0.0016A
-> 0.0137A
-> 0.0882A
-> 0.122A
-> 0.001A
-> 0.000168A
-> 0.00368A
-> 0.14A
-> 0.006A
-> 0.0169A
Camera
+3P3V_AUDIO
+5V_AUDIO
+1P8V_AUDIO
+3P3V_AUDIO
+1P1V_AUDIO
TPM(Infineon SLB9665 ESS2) Sensor uC(ATUC256L3U-Z3UR)
-> 0.1A
-> 0.9A
+3P3VA+3P3V_TPM
SDXC
+3P3V_HPD
+5V_SL1
WiFi&BT
-> 0.061A
SL1
->0.075A
-> 1.5A
-> 1.5A
BLADE
DMIC
+5V_KB_CONN
-> 0.5A
-> 0.02A
Hall effect sensor(BU52058GWZ-E2)
->0.0028A
Compass(MMC3416XMA)
->0.0012A
Acceleromte&Gyro(LSM330TR)
-> 0.0061A
-> 0.7A
UEFI_SPI_BIOS_ROM
-> 0.04A
-> 0.564A
FAN
+3P3VA
+3P3V_SENSOR
Panel
+3P3V_SENSOR
-> 0.273A
Authentication IC
(ECC108)
-> 0.005A
Touch Interface
-> 0.0094A
-> 0.0027A
-> 0.005A
+3P3V_SENSOR
+3P3V_MUX
+3P3V
ALC3264 CODEC
+5VUSBPWR
ALS(ISL29033IROZ-T7) FPC CON
-> 0.000075A
MUX
-> 0.033A
mini DP
-> 0.5A
USB 3.0 connector
-> 0.9A
-> 1.05A
-> 0.005A
Transceiver SN74AVCT245
+1P8V_EC
DSP (ES320)
-> 0.11A
-> 0.0063A
-> 0.0189A
+V_ALWAYS_ON
Battery Charger BQ24735
-> 0.003A
<Core Design>
<Core Design>
<Core Design>
POWER DISTRIBUTION
POWER DISTRIBUTION
Title:
Title:
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Engineer:
Engineer:
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
POWER DISTRIBUTION
Surface
Surface
Surface
7 76Monday, May 1 1, 2015
7 76Monday, May 1 1, 2015
7 76Monday, May 1 1, 2015
1
1.90.2
1.90.2
1.90.2
5
4
3
2
1
S5 to S0 Power Sequence
SLP_SUS#
D D
+5VSB / +3P3VSB
RSMRST#
10mS
200mS
SUSWARN#
SUS_ACK#
SLP_A#(NC)
5mS
SLP_LAN#(NC)
SLP_S5#(NC)
PM_SUSC#
PM_SUSB#
+6V_12V
C C
30uS
PSU: <=20mS
+3P3V
+1P2V_DUAL
=500mS
+1P05V_CPUIO
+1P8V_DUAL
H_PWRGD assertion
06Dec14 jks: NEEDS UPDATE
VCCSA_VID
H_PWRGD must be stable (low) at this time
Recommended that +0P85VSA ramp after +1P05V_CPUIO has ramped to ensure VCCSA_VID[0] is stable
+0V85VSA
<5mS
CPU_VRON(NC)
VIDSCLK / VIDSOUT
B B
VIDALERT#
CPU SVID buffers are Hi-Z once VCCIO is
stable and VRM_PWRGD = 0
CPU SVID buffers are Hi-Z once VCCIO is
stable and VRM_PWRGD = 0
MISC ACK0/1...
<600uS
Set VID
slow packet sta
ACK0/1...
VCCSA_VID[0] FINAL
Typ 60uS
Get Reg
tus packet
S
<1u
ACK0/1...
Pay
loa
+0P85VSA FINAL
d
>400uS
: 100ms~500ms
PM_PCH_PWROK
PSU
1mS
CLK_EXP
Min 10 CLK_EXP
PM_DRAM_PWRGD
H_PWRGD
+VCORE
>1mS
<5u
S
<2mS
5mS
VRM_PWRGD
<5mS
A A
PLTRST#
<Core Design>
<Core Design>
<Core Design>
Title:
Title:
Title:
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Engineer:
Engineer:
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
1~100mS
POWER SEQUENCE
POWER SEQUENCE
POWER SEQUENCE
Surface
Surface
Surface
8 76Monday, May 11, 2015
8 76Monday, May 11, 2015
1
8 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
4
3
2
1
I2C & SMBUS Map
SML1_PCH_DATA
SML1
_PCH_CLK
Q3501
Q3504
PCH_I2C1_SDA_3V3
D D
S
M
PCH_
I2C1_SCL_3V3
R3001
R3003
TS_A_I2C_SDA_CON
TS_A_I2C_SCL_CON
Touch Connector
CON3001
0x60
Surrend
TEMP Sensor
U3901
0x4B
PCH
U1001
M
C C
0x4D
SH_I2C_SDA
SH_I
2C_SCL
Debug Connector
CON3302
SML3_EC_DATA
SML3
_EC_CLK
M
Skin
TEMP Sensor
U3902
0x3B
Skin
TEMP Sensor
U3903
0x3A
Skin
TEMP Sensor
U3501
SML0_EC_DATA
SML0_EC_CLK
S
I2C_SDA_MCU_R
R3122
R3124
M
B B
SAM
U310
5
I2C_SCL_MCU_R
ADUX1050
U3206
0x2D
ADUX6
I2C_SDA_MCU
I2C_S
R3229
R3230
R3285
R3287
CL_MCU
R3266
R3267
TEMP Sensor
U3211
R3210
R3211
R3212
R3213
MAG2_X_SDA
MAG2_X_SCL
0x3A
SML1_EC_DATA
SML1_EC_CLK
Accel & Gyro
U3202
0x68
EC
S
U3601
0x4E
M
R7032/L7005
R7033/L7006
PR6309
PR6310
0 ohm
CHG_SDA_A
CHG_SCL_A
MAG2_SCL_3V3
A A
0x28
U3207
0x2C
ADUX1050
ADUX7
R3286
R3288
MAG2_SDA_3V3
Magnetometer
U3203
0x30
EC_SMCLK_BAT
EC_S
MDATA_BAT
U3904
Charger
U6301
Battery
Connector
CON7001
0x4A
0x12
0x16
09. I2C MAP
09. I2C MAP
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Engineer:
09. I2C MAP
Surface
Surface
Surface
9 76Monday, May 11, 2015
9 76Monday, May 11, 2015
1
9 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
4
3
2
1
+VCCSTG
R1008
1K
RES_0201_12mil
TPS0P35
SAR_INDICATION_1[31]
SAR_INDICATION_2[31]
+VCCST_CPU
H_PECI_R[36]
XDP_TP1001TPS0P35
TS_IRQ_3V3_N[30]
XDP_TP1002
R1021 0
RES_0201_12mil
R1022 49.9
R1023 49.9
RES_0201_12mil
R1002 499
RES_0201_12mil
C1008 47pDNP,CPU
CAP_0201_14mil
R1035 0 RES_0201_12mil
R1024 49.9
RES_0201_12mil
RES_0201_12mil
D D
C C
H_PROCHOT#[63,66]
R1037
RES_0402_16mil
EC_PROCHOT[36]
Q1001
SOT-VMT3_1p2xp8xp5_p4mm
RUM002N02GT2L
100
G
D
S
+VCCST_CPU
R1025 49.9
RES_0201_12mil
DNP,CPU
R1016
49.9
RES_0201_12mil
PM_THRMTRIP#[10]
PROC_POPIRCOMP
PCH_OPIRCOMP
OPCE_RCOMP
OPC_RCOMP
TP_CATERR#_R
H_PROCHOT#_R
XDP_BPM0[18]
XDP_BPM1[18]
PROC_DETECT#
GPP_E3
GPP_E7
U1001D
SKL_
ULT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
D63
CATERR#
A54
PECI
C65
PROCHOT#
C63
THERMTRIP#
A65
SKTOCC#
C55
BPM#[0]
D55
BPM#[1]
B54
BPM#[2]
C56
BPM#[3]
A6
GPP_E3/CPU_GP0
A7
GPP_E7/CPU_GP1
BA5
GPP_B3/CPU_GP2
AY5
GPP_B4/CPU_GP3
AT16
PROC_POPIRCOMP
AU16
PCH_OPIRCOMP
H66
OPCE_RCOMP
H65
OPC_RCOMP
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
TBL1001,CPU
CPU MISC
TBL1001
CPU MSPN Inte l PN
SKL_ULT
4 OF 20
JTAG
PROC_TCK
PROC_TDI
PROC_TDO
PROC_TMS
PROC_TRST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS
PCH_TRST#
JTAGX
B61
D60
A61
C60
B59
B56
D59
A56
C59
C61
A59
i3 X904344-001 SKLU22i3
R1020
1K
RES_0201_12mil
H_THERMTRIP#[75]
B B
DDI Port 1: base port
DDI Port 2: SL1
+VCCIO
R1006
24.9
RES_0201_12mil
A A
5
R1018 0
RES_0201_12mil
DDI1_DATA0_DN[47]
DDI1_DATA0_DP[47]
DDI1_DATA1_DN[47]
DDI1_DATA1_DP[47]
DDI1_DATA2_DN[47]
DDI1_DATA2_DP[47]
DDI1_DATA3_DN[47]
DDI1_DATA3_DP[47]
DDI2_DATA0_DN[71]
DDI2_DATA0_DP[71]
DDI2_DATA1_DN[71]
DDI2_DATA1_DP[71]
DDI2_DATA2_DN[71]
DDI2_DATA2_DP[71]
DDI2_DATA3_DN[71]
DDI2_DATA3_DP[71]
DDPB_CTRL_CLK[46]
DDPB_CTRL_DATA[46]
DDPC_CTRL_CLK[46]
DDPC_CTRL_DATA[46]
PCH_CODEC_IRQ[40]
RTD3_CR_PWREN[64]
EDP_COMP
PM_THRMTRIP# [10]
E55
F55
E58
F58
F53
G53
F56
G56
C50
D50
C52
D52
A50
B50
D51
C51
L13
L12
INT. PD
INT
INT. PD
. PD
4
N7
N8
N11
N12
E52
U1001A
SKL_
ULT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
DDI1_TXN[0]
DDI1_TXP[0]
DDI1_TXN[1]
DDI1_TXP[1]
DDI1_TXN[2]
DDI1_TXP[2]
DDI1_TXN[3]
DDI1_TXP[3]
DDI2_TXN[0]
DDI2_TXP[0]
DDI2_TXN[1]
DDI2_TXP[1]
DDI2_TXN[2]
DDI2_TXP[2]
DDI2_TXN[3]
DDI2_TXP[3]
GPP_E18/DDPB_CTRLCLK
GPP_E19/DDPB_CTRLDATA
GPP_E20/DDPC_CTRLCLK
GPP_E21/DDPC_CTRLDATA
GPP_E22/DDPD_CTRLCLK
GPP_E23/DDPD_CTRLDATA
EDP_RCOMP
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
TBL1001,CPU
SKL_ULT
DDI
DISPLAY SIDEBANDS
1 OF 20
i5 X904343-001 SKLU22i5
i7 X904345-001 SKLU22i7
C47
C46
D46
C45
A45
B45
A47
B47
E45
F45
B52
G50
F50
E48
F48
G46
F46
L9
L7
L6
N9
L10
R12
R11
U13
EDP
EDP_TXN[0]
EDP_TXP[0]
EDP_TXN[1]
EDP_TXP[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]
EDP_AUXN
EDP_AUXP
EDP_DISP_UTIL
DDI1_AUXN
DDI1_AUXP
DDI2_AUXN
DDI2_AUXP
DDI3_AUXN
DDI3_AUXP
GPP_E13/DDPB_HPD0
GPP_E14/DDPC_HPD1
GPP_E15/DDPD_HPD2
GPP_E16/DDPE_HPD3
GPP_E17/EDP_HPD
EDP_BKLTEN
EDP_BKLTCTL
EDP_VDDEN
3
EDP_TX0_DN [57]
EDP_TX0_DP [57]
EDP_TX1_DN [57]
EDP_TX1_DP [57]
EDP_TX2_DN [57]
EDP_TX2_DP [57]
EDP_TX3_DN [57]
EDP_TX3_DP [57]
EDP_AUX_DN [57]
EDP_AUX_DP [57]
DDPB_AUX_DN [46]
DDPB_AUX_DP [46]
DDPC_AUX_DN [46]
DDPC_AUX_DP [46]
L_BKLTEN [72]
L_BKLT_CTRL_IN [57]
EDP_VDD_EN [65]
eDP x 4
EDP_DISP_UTIL
R1032 100K
MTP1012 SP_TP_SMDp58mm
MTP1013 SP_TP_SMDp58mm
MTP1014 SP_TP_SMDp58mm
MTP1015 SP_TP_SMDp58mm
MTP1016 SP_TP_SMDp58mm
DNP,CPU
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
R1028 49.9
R1039
10K
R1017 100K
R1005 49.9
RES_0201_12mil
R1026 49.9
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
+3VSUS_ORG
R1004 49.9
R1027 49.9
RES_0201_12mil
R1033 1M
RES_0201_12mil
2
PLACE TP's on BOTTOM,
XDP_TCK [18]
XDP_TDI [18]
XDP_TDO [18]
XDP_TMS [18]
XDP_TRST#_BUF [18]
PLACE TP's on BOTTOM,
+VCCSTG
DNP,CPU
R1030 1K
RES_0201_12mil
R1038
10K
RES_0201_12mil
DDPB_DP_HPD [47]
SL1_DP_HPD [71]
EXT_SMI# [36]
EXT_SCI# [36]
EDP_HPD [57]
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
MTP1004 SP_TP_SMDp58mm
MTP1001 SP_TP_SMDp58mm
MTP1005 SP_TP_SMDp58mm
MTP1003 SP_TP_SMDp58mm
MTP1000 SP_TP_SMDp58mm
MTP1002 SP_TP_SMDp58mm
PCH_JTAG_TCK [18]
PCH_JTAG_TDI [18]
PCH_JTAG_TDO [18]
PCH_JTAG_TMS [18]
XDP_TRST# [18]
PCH_JTAGX [18]
R1029
49.9
RES_0201_12mil
DNP,CPU
R1019
0
RES_0201_12mil
SMI and SCI can be set to HIGH in S5 in EC code
and they need to set LOW before go to deep sleep
CPU(1)_MISC,JTAG,DDI,EDP
CPU(1)_MISC,JTAG,DDI,EDP
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
CPU(1)_MISC,JTAG,DDI,EDP
Surface
Surface
Surface
1.90.2
1.90.2
1.90.2
10 76Monday, May 11, 2015
10 76Monday, May 11, 2015
1
10 76Monday, May 11, 2015
5
U1001B
SKL_U
LT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
M_A_D[7:0][16]
M_A_D[15:8][16]
D D
M_A_D[39:32][16]
M_A_D[47:40][16]
M_B_D[7:0][17]
M_B_D[15:8][17]
C C
M_B_D[39:32][17]
M_B_D[47:40][17]
M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
M_A_D15
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
M_B_D15
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47
AL71
DDR0_DQ[0]
AL68
DDR0_DQ[1]
AN68
DDR0_DQ[2]
AN69
DDR0_DQ[3]
AL70
DDR0_DQ[4]
AL69
DDR0_DQ[5]
AN70
DDR0_DQ[6]
AN71
DDR0_DQ[7]
AR70
DDR0_DQ[8]
AR68
DDR0_DQ[9]
AU71
DDR0_DQ[10]
AU68
DDR0_DQ[11]
AR71
DDR0_DQ[12]
AR69
DDR0_DQ[13]
AU70
DDR0_DQ[14]
AU69
DDR0_DQ[15]
BB65
DDR0_DQ[16]/DDR0_ DQ[32]
AW65
DDR0_DQ[17]/DDR0_ DQ[33]
AW63
DDR0_DQ[18]/DDR0_ DQ[34]
AY63
DDR0_DQ[19]/DDR0_ DQ[35]
BA65
DDR0_DQ[20]/DDR0_ DQ[36]
AY65
DDR0_DQ[21]/DDR0_ DQ[37]
BA63
DDR0_DQ[22]/DDR0_ DQ[38]
BB63
DDR0_DQ[23]/DDR0_ DQ[39]
BA61
DDR0_DQ[24]/DDR0_ DQ[40]
AW61
DDR0_DQ[25]/DDR0_ DQ[41]
BB59
DDR0_DQ[26]/DDR0_ DQ[42]
AW59
DDR0_DQ[27]/DDR0_ DQ[43]
BB61
DDR0_DQ[28]/DDR0_ DQ[44]
AY61
DDR0_DQ[29]/DDR0_ DQ[45]
BA59
DDR0_DQ[30]/DDR0_ DQ[46]
AY59
DDR0_DQ[31]/DDR0_ DQ[47]
AY39
DDR0_DQ[32]/DDR1_ DQ[0]
AW39
DDR0_DQ[33]/DDR1_ DQ[1]
AY37
DDR0_DQ[34]/DDR1_ DQ[2]
AW37
DDR0_DQ[35]/DDR1_ DQ[3]
BB39
DDR0_DQ[36]/DDR1_ DQ[4]
BA39
DDR0_DQ[37]/DDR1_ DQ[5]
BA37
DDR0_DQ[38]/DDR1_ DQ[6]
BB37
DDR0_DQ[39]/DDR1_ DQ[7]
AY35
DDR0_DQ[40]/DDR1_ DQ[8]
AW35
DDR0_DQ[41]/DDR1_ DQ[9]
AY33
DDR0_DQ[42]/DDR1_ DQ[10]
AW33
DDR0_DQ[43]/DDR1_ DQ[11]
BB35
DDR0_DQ[44]/DDR1_ DQ[12]
BA35
DDR0_DQ[45]/DDR1_ DQ[13]
BA33
DDR0_DQ[46]/DDR1_ DQ[14]
BB33
DDR0_DQ[47]/DDR1_ DQ[15]
AY31
DDR0_DQ[48]/DDR1_ DQ[32]
AW31
DDR0_DQ[49]/DDR1_ DQ[33]
AY29
DDR0_DQ[50]/DDR1_ DQ[34]
AW29
DDR0_DQ[51]/DDR1_ DQ[35]
BB31
DDR0_DQ[52]/DDR1_ DQ[36]
BA31
DDR0_DQ[53]/DDR1_ DQ[37]
BA29
DDR0_DQ[54]/DDR1_ DQ[38]
BB29
DDR0_DQ[55]/DDR1_ DQ[39]
AY27
DDR0_DQ[56]/DDR1_ DQ[40]
AW27
DDR0_DQ[57]/DDR1_ DQ[41]
AY25
DDR0_DQ[58]/DDR1_ DQ[42]
AW25
DDR0_DQ[59]/DDR1_ DQ[43]
BB27
DDR0_DQ[60]/DDR1_ DQ[44]
BA27
DDR0_DQ[61]/DDR1_ DQ[45]
BA25
DDR0_DQ[62]/DDR1_ DQ[46]
BB25
DDR0_DQ[63]/DDR1_ DQ[47]
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
SKL_ULT
DDR0_MA[5]/DDR0 _CAA[0]/DDR0_MA[5]
DDR0_MA[9]/DDR0 _CAA[1]/DDR0_MA[9]
DDR0_MA[6]/DDR0 _CAA[2]/DDR0_MA[6]
DDR0_MA[8]/DDR0 _CAA[3]/DDR0_MA[8]
DDR0_MA[7]/DDR0 _CAA[4]/DDR0_MA[7]
DDR0_BA[2]/DDR0_ CAA[5]/DDR0_BG[0]
DDR0_MA[12]/DDR 0_CAA[6]/DDR0_MA[12]
DDR0_MA[11]/DDR 0_CAA[7]/DDR0_MA[11]
DDR0_MA[15]/DDR 0_CAA[8]/DDR0_ACT#
DDR0_MA[14]/DDR 0_CAA[9]/DDR0_BG[1]
DDR0_MA[13]/DDR 0_CAB[0]/DDR0_MA[13]
DDR0_CAS#/DDR0_CA B[1]/DDR0_MA[15]
DDR0_WE#/DDR0 _CAB[2]/DDR0_MA[14]
DDR0_RAS#/DDR0_CA B[3]/DDR0_MA[16]
DDR0_BA[0]/DDR0_ CAB[4]/DDR0_BA[0]
DDR0_MA[2]/DDR0 _CAB[5]/DDR0_MA[2]
DDR0_BA[1]/DDR0_ CAB[6]/DDR0_BA[1]
DDR0_MA[10]/DDR 0_CAB[7]/DDR0_MA[10]
DDR0_MA[1]/DDR0 _CAB[8]/DDR0_MA[1]
DDR0_MA[0]/DDR0 _CAB[9]/DDR0_MA[0]
DDR0_DQSN[2]/DDR0_ DQSN[4]
DDR0_DQSP[2]/DDR0_ DQSP[4]
DDR0_DQSN[3]/DDR0_ DQSN[5]
DDR0_DQSP[3]/DDR0_ DQSP[5]
DDR0_DQSN[4]/DDR1_ DQSN[0]
DDR0_DQSP[4]/DDR1_ DQSP[0]
DDR0_DQSN[5]/DDR1_ DQSN[1]
DDR0_DQSP[5]/DDR1_ DQSP[1]
DDR0_DQSN[6]/DDR1_ DQSN[4]
DDR0_DQSP[6]/DDR1_ DQSP[4]
DDR0_DQSN[7]/DDR1_ DQSN[5]
DDR0_DQSP[7]/DDR1_ DQSP[5]
DDR CH - A
2 OF 20
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR0_CKN[0]
DDR0_CKP[0]
DDR0_CKN[1]
DDR0_CKP[1]
DDR0_CKE[0]
DDR0_CKE[1]
DDR0_CKE[2]
DDR0_CKE[3]
DDR0_CS#[0]
DDR0_CS#[1]
DDR0_ODT[0]
DDR0_ODT[1]
DDR0_MA[3]
DDR0_MA[4]
DDR0_DQSN[0]
DDR0_DQSP[0]
DDR0_DQSN[1]
DDR0_DQSP[1]
DDR0_ALERT#
DDR0_PAR
DDR_VREF_CA
DDR_VTT_CNTL
4
AU53
AT53
AU55
AT55
BA56
BB56
AW56
AY56
AU45
AU43
AT45
AT43
BA51
BB54
BA52
AY52
AW52
AY55
AW54
BA54
BA55
AY54
AU46
AU48
AT46
AU50
AU52
AY51
AT48
AT50
BB50
AY50
BA50
BB52
AM70
AM69
AT69
AT70
BA64
AY64
AY60
BA60
BA38
AY38
AY34
BA34
BA30
AY30
AY26
BA26
AW50
AT52
AY67
AY68
BA67
AW67
M_A_DIM0_CLK#0 [16]
M_A_DIM0_CLK0 [16]
M_A_DIM0_CLK#1 [16]
M_A_DIM0_CLK1 [16]
M_A_DIM0_CKE0 [16]
M_A_DIM0_CKE1 [16]
M_A_DIM0_CKE2 [16]
M_A_DIM0_CKE3 [16]
M_A_DIM0_CS#0 [16]
M_A_DIM0_CS#1 [16]
M_A_DIM0_ODT0 [16]
M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9
M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9
M_A_DQS#0 [16]
M_A_DQS0 [16]
M_A_DQS#1 [16]
M_A_DQS1 [16]
M_A_DQS#4 [16]
M_A_DQS4 [16]
M_A_DQS#5 [16]
M_A_DQS5 [16]
M_B_DQS#0 [17]
M_B_DQS#1 [17]
M_B_DQS1 [17]
M_B_DQS#4 [17]
M_B_DQS4 [17]
M_B_DQS#5 [17]
M_B_DQS5 [17]
DDR0_ALERT#
DIMM_VREF_CA [19]
DIMM0_VREF_DQ [19]
DIMM1_VREF_DQ [19]
M_A_CAA[9:0] [16]
M_A_CAB[9:0] [16]
R1135 0
RES_0201_12mil
M_A_D[23:16][16]
M_A_D[31:24][16]
M_A_D[55:48][16]
M_A_D[63:56][16]
M_B_D[23:16][17]
M_B_D[31:24][17]
M_B_D[55:48][17]
M_B_D[63:56][17]
3
M_A_D16
M_A_D17
M_A_D18
M_A_D19
M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30
M_A_D31
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63
M_B_D16
M_B_D17
M_B_D18
M_B_D19
M_B_D20
M_B_D21
M_B_D22
M_B_D23
M_B_D24
M_B_D25
M_B_D26
M_B_D27
M_B_D28
M_B_D29
M_B_D30
M_B_D31
M_B_D48
M_B_D49
M_B_D50
M_B_D51
M_B_D52
M_B_D53
M_B_D54
M_B_D55
M_B_D56
M_B_D57
M_B_D58
M_B_D59
M_B_D60
M_B_D61
M_B_D62
M_B_D63
U1001C
SKL_U
LT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
AF65
DDR1_DQ[0]/DDR0_DQ[ 16]
AF64
DDR1_DQ[1]/DDR0_DQ[ 17]
AK65
DDR1_DQ[2]/DDR0_DQ[ 18]
AK64
DDR1_DQ[3]/DDR0_DQ[ 19]
AF66
DDR1_DQ[4]/DDR0_DQ[ 20]
AF67
DDR1_DQ[5]/DDR0_DQ[ 21]
AK67
DDR1_DQ[6]/DDR0_DQ[ 22]
AK66
DDR1_DQ[7]/DDR0_DQ[ 23]
AF70
DDR1_DQ[8]/DDR0_DQ[ 24]
AF68
DDR1_DQ[9]/DDR0_DQ[ 25]
AH71
DDR1_DQ[10]/DDR0_ DQ[26]
AH68
DDR1_DQ[11]/DDR0_ DQ[27]
AF71
DDR1_DQ[12]/DDR0_ DQ[28]
AF69
DDR1_DQ[13]/DDR0_ DQ[29]
AH70
DDR1_DQ[14]/DDR0_ DQ[30]
AH69
DDR1_DQ[15]/DDR0_ DQ[31]
AT66
DDR1_DQ[16]/DDR0_ DQ[48]
AU66
DDR1_DQ[17]/DDR0_ DQ[49]
AP65
DDR1_DQ[18]/DDR0_ DQ[50]
AN65
DDR1_DQ[19]/DDR0_ DQ[51]
AN66
DDR1_DQ[20]/DDR0_ DQ[52]
AP66
DDR1_DQ[21]/DDR0_ DQ[53]
AT65
DDR1_DQ[22]/DDR0_ DQ[54]
AU65
DDR1_DQ[23]/DDR0_ DQ[55]
AT61
DDR1_DQ[24]/DDR0_ DQ[56]
AU61
DDR1_DQ[25]/DDR0_ DQ[57]
AP60
DDR1_DQ[26]/DDR0_ DQ[58]
AN60
DDR1_DQ[27]/DDR0_ DQ[59]
AN61
DDR1_DQ[28]/DDR0_ DQ[60]
AP61
DDR1_DQ[29]/DDR0_ DQ[61]
AT60
DDR1_DQ[30]/DDR0_ DQ[62]
AU60
DDR1_DQ[31]/DDR0_ DQ[63]
AU40
DDR1_DQ[32]/DDR1_ DQ[16]
AT40
DDR1_DQ[33]/DDR1_ DQ[17]
AT37
DDR1_DQ[34]/DDR1_ DQ[18]
AU37
DDR1_DQ[35]/DDR1_ DQ[19]
AR40
DDR1_DQ[36]/DDR1_ DQ[20]
AP40
DDR1_DQ[37]/DDR1_ DQ[21]
AP37
DDR1_DQ[38]/DDR1_ DQ[22]
AR37
DDR1_DQ[39]/DDR1_ DQ[23]
AT33
DDR1_DQ[40]/DDR1_ DQ[24]
AU33
DDR1_DQ[41]/DDR1_ DQ[25]
AU30
DDR1_DQ[42]/DDR1_ DQ[26]
AT30
DDR1_DQ[43]/DDR1_ DQ[27]
AR33
DDR1_DQ[44]/DDR1_ DQ[28]
AP33
DDR1_DQ[45]/DDR1_ DQ[29]
AR30
DDR1_DQ[46]/DDR1_ DQ[30]
AP30
DDR1_DQ[47]/DDR1_ DQ[31]
AU27
DDR1_DQ[48]
AT27
DDR1_DQ[49]
AT25
DDR1_DQ[50]
AU25
DDR1_DQ[51]
AP27
DDR1_DQ[52]
AN27
DDR1_DQ[53]
AN25
DDR1_DQ[54]
AP25
DDR1_DQ[55]
AT22
DDR1_DQ[56]
AU22
DDR1_DQ[57]
AU21
DDR1_DQ[58]
AT21
DDR1_DQ[59]
AN22
DDR1_DQ[60]
AP22
DDR1_DQ[61]
AP21
DDR1_DQ[62]
AN21
DDR1_DQ[63]
REV = JKS
BUILD-OPT = TBL1001,CPU
e Package = SKL_ULT_1356BGA_R1
Sourc
SKL_ULT
DDR1_MA[5]/DDR1 _CAA[0]/DDR1_MA[5]
DDR1_MA[9]/DDR1 _CAA[1]/DDR1_MA[9]
DDR1_MA[6]/DDR1 _CAA[2]/DDR1_MA[6]
DDR1_MA[8]/DDR1 _CAA[3]/DDR1_MA[8]
DDR1_MA[7]/DDR1 _CAA[4]/DDR1_MA[7]
DDR1_BA[2]/DDR1_ CAA[5]/DDR1_BG[0]
DDR1_MA[12]/DDR 1_CAA[6]/DDR1_MA[12]
DDR1_MA[11]/DDR 1_CAA[7]/DDR1_MA[11]
DDR1_MA[15]/DDR 1_CAA[8]/DDR1_ACT#
DDR1_MA[14]/DDR 1_CAA[9]/DDR1_BG[1]
DDR1_MA[13]/DDR 1_CAB[0]/DDR1_MA[13]
DDR1_CAS#/DDR1_CA B[1]/DDR1_MA[15]
DDR1_WE#/DDR1 _CAB[2]/DDR1_MA[14]
DDR1_RAS#/DDR1_CA B[3]/DDR1_MA[16]
DDR1_BA[0]/DDR1_ CAB[4]/DDR1_BA[0]
DDR1_MA[2]/DDR1 _CAB[5]/DDR1_MA[2]
DDR1_BA[1]/DDR1_ CAB[6]/DDR1_BA[1]
DDR1_MA[10]/DDR 1_CAB[7]/DDR1_MA[10]
DDR1_MA[1]/DDR1 _CAB[8]/DDR1_MA[1]
DDR1_MA[0]/DDR1 _CAB[9]/DDR1_MA[0]
DDR1_DQSN[0]/DDR0_ DQSN[2]
DDR1_DQSP[0]/DDR0_ DQSP[2]
DDR1_DQSN[1]/DDR0_ DQSN[3]
DDR1_DQSP[1]/DDR0_ DQSP[3]
DDR1_DQSN[2]/DDR0_ DQSN[6]
DDR1_DQSP[2]/DDR0_ DQSP[6]
DDR1_DQSN[3]/DDR0_ DQSN[7]
DDR1_DQSP[3]/DDR0_ DQSP[7]
DDR1_DQSN[4]/DDR1_ DQSN[2]
DDR1_DQSP[4]/DDR1_ DQSP[2]
DDR1_DQSN[5]/DDR1_ DQSN[3]
DDR1_DQSP[5]/DDR1_ DQSP[3]
DRAM_RESET#
DDR_RCOMP[0]
DDR CH - B
3 OF 20
DDR_RCOMP[1]
DDR_RCOMP[2]
2
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[0]
DDR1_CKP[1]
DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]
DDR1_CS#[0]
DDR1_CS#[1]
DDR1_ODT[0]
DDR1_ODT[1]
DDR1_MA[3]
DDR1_MA[4]
DDR1_DQSN[6]
DDR1_DQSP[6]
DDR1_DQSN[7]
DDR1_DQSP[7]
DDR1_ALERT#
DDR1_PAR
AN45
AN46
AP45
AP46
AN56
AP55
AN55
AP53
BB42
AY42
BA42
AW42
AY48
AP50
BA48
BB48
AP48
AP52
AN50
AN48
AN53
AN52
BA43
AY43
AY44
AW44
BB44
AY47
BA44
AW46
AY46
BA46
BB46
BA47
AH66
AH65
AG69
AG70
AR66
AR65
AR61
AR60
AT38
AR38
AT32
AR32
AR25
AR27
AR22
AR21
AN43
AP43
AT13
AR18
AT18
AU18
M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9
M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9
M_A_DQS#2 [16]
M_A_DQS2 [16]
M_A_DQS#3 [16]
M_A_DQS3 [16]
M_A_DQS#6 [16]
M_A_DQS6 [16]
M_A_DQS#7 [16]
M_A_DQS7 [16]
M_B_DQS#2 [17]
M_B_DQS2 [17]
M_B_DQS#3 [17]M_B_DQS0 [17]
M_B_DQS3 [17]
M_B_DQS#6 [17]
M_B_DQS6 [17]
M_B_DQS#7 [17]
M_B_DQS7 [17]
DDR1_ALERT#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
M_B_DIM0_CLK#0 [17]
M_B_DIM0_CLK#1 [17]
M_B_DIM0_CLK0 [17]
M_B_DIM0_CLK1 [17]
M_B_DIM0_CKE0 [17]
M_B_DIM0_CKE1 [17]
M_B_DIM0_CKE2 [17]
M_B_DIM0_CKE3 [17]
M_B_DIM0_CS#0 [17]
M_B_DIM0_CS#1 [17]
M_B_DIM0_ODT0 [17]
M_B_CAA[9:0] [17]
M_B_CAB[9:0] [17]
R1136 0
RES_0201_12mil
SM_DRAMRST#
R11112001% RES_0201_12mil
R113480.6 RES_0201_12MIL
R11121621%
RES_0402_16mil
1
DNP,CPU
R1118 1M
RES_0201_12mil
+1P2V_DUAL
+3P3VSB +3P3V+1P2V_DUAL
U1102
74AUP1G07GX
sot1226_p8xp8xp35_p48mm
B B
A A
DDR_PG_CTRL_S
DNP,CPU
R1117
10K
RES_0201_12mil
1
VCC
A2Y
NC
GND
5
4
3
C1101
0.1u
cap_0201_14mil
EV1.9
CHG MSPN
6.3V
DNP,CPU
R1114
220K
res_0201_12mil
DNP,CPU
R1113
2M
RES_0201_12mil
R1115
4.99K
RES_0201_12mil
DDR_PG_CTRL [60]
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
CPU(2)_LPDDR3
CPU(2)_LPDDR3
CPU(2)_LPDDR3
Surface
Surface
Surface
1
1.90.2
1.90.2
11 76Monday, May 11, 2015
11 76Monday, May 11, 2015
11 76Monday, May 11, 2015
1.90.2
+1P2V_DUAL
5
4
3
2
1
4V
C13017 22u
D D
6.3V
C1241 10u
CAP_0402_28mil
R1201 0
RES_0402_16mil
C C
B B
4V
cap_0603_40mil
C13018 22u
6.3V
C1240 10u
CAP_0402_28mil
DNP,CPU
R1202 0
RES_0402_16mil
4V
cap_0603_40mil
cap_0603_40mil
C13019 22u
Place on secondary side,
underneath the package
6.3V
C1239 10u
C13020 10u
6.3V
C1238 10u
cap_0402_0p65mm
CAP_0402_28mil
6.3V
DNP,CPU
C1245 1u
CAP_0201_14mil
+VCCPLL_OC
Place on secondary side,
underneath the package
CAP_0402_28mil
4V
4V
DNP,CPU
C1237 10u
+VCCST_CPU
C1246
6.3V
1u
CAP_0402_22mil
4V
DNP,CPU
C1236 10u
cap_0402_0p65mm
6.3V
DNP,CPU
C1244 1u
cap_0402_0p65mm
from 1VSB, control SLP_S4 (S3 rail)
+VCCSTG
Place on secondary side,
6.3V
DNP,CPU
C1243 1u
CAP_0201_14mil
DNP,CPU
C1247 1u
underneath the package
6.3V
DNP,CPU
C1242 1u
CAP_0201_14mil
6.3V
CAP_0402_22mil
6.3V
DNP,CPU
C1232 1u
CAP_0201_14mil
C1248
1u
CAP_0402_22mil
CAP_0201_14mil
VDDQC
+VCCST_CPU
6.3V
C1249
1u
CAP_0402_22mil
+VCC_CORE
Place on secondary side,
underneath the package
+VCCEDRAM
C1228
10u
4V
cap_0402_0p65mm
A A
5
C1252
6.3V
1u
CAP_0201_14mil
C1254
6.3V
1u
CAP_0201_14mil
C1253
6.3V
1u
CAP_0201_14mil
C1255
6.3V
1u
CAP_0201_14mil
+VCCEOPIO
C1231
10u
4V
cap_0402_0p65mm
Place on secondary side,
rneath the package
unde
C1250
6.3V
1u
CAP_0201_14mil
C1256
6.3V
1u
CAP_0201_14mil
CAP_0201_14mil
C1230
10u
4V
cap_0402_0p65mm
C1251
6.3V
+1P8V
1u
VCCOPC_SENSE[58]
VCCOPIO_SENSE[58]
4
U1001N
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
SKL_U
LT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
AU23
VDDQ_AU23
AU28
VDDQ_AU28
AU35
VDDQ_AU35
AU42
VDDQ_AU42
BB23
VDDQ_BB23
BB32
VDDQ_BB32
BB41
VDDQ_BB41
BB47
VDDQ_BB47
BB51
VDDQ_BB51
AM40
VDDQC
A18
VCCST
A22
VCCSTG_A22
AL23
VCCPLL_OC
K20
VCCPLL_K20
K21
VCCPLL_K21
6.3V
REV = JKS
U1001L
SKL_U
bga13
A30
VCC_A30
A34
VCC_A34
A39
VCC_A39
A44
VCC_A44
AK33
VCC_AK33
AK35
VCC_AK35
AK37
VCC_AK37
AK38
VCC_AK38
AK40
VCC_AK40
AL33
VCC_AL33
AL37
VCC_AL37
AL40
VCC_AL40
AM32
VCC_AM32
AM33
VCC_AM33
AM35
VCC_AM35
AM37
VCC_AM37
AM38
VCC_AM38
G30
VCC_G30
K32
RSVD_K32
AK32
RSVD_AK32
AB62
VCCOPC_AB62
P62
VCCOPC_P62
V62
VCCOPC_V62
H63
VCC_OPC_1P8_H63
G61
VCC_OPC_1P8_G61
AC63
VCCOPC_SENSE
AE63
VSSOPC_SENSE
AE62
VCCEOPIO
AG62
VCCEOPIO
AL63
VCCEOPIO_SENSE
AJ62
VSSEOPIO_SENSE
REV = JKS
BUILD-OPT = TBL1001,CPU
Source Package = SKL_ULT_1356BGA_R1
SKL_ULT
CPU POWER 3 OF 4
14 OF 20
LT_1356BGA_R1
56_47x30_42x24x1p27mm-SKL
SKL_ULT
CPU POWER 1 OF 4
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCIO_SENSE
VSSIO_SENSE
VSSSA_SENSE
VCCSA_SENSE
12 OF 20
3
AK28
AK30
AL30
AL42
AM28
AM30
AM42
AK23
AK25
G23
G25
G27
G28
J22
J23
J27
K23
K25
K27
K28
K30
AM23
AM22
H21
H20
VCC_G32
VCC_G33
VCC_G35
VCC_G37
VCC_G38
VCC_G40
VCC_G42
VCC_J30
VCC_J33
VCC_J37
VCC_J40
VCC_K33
VCC_K35
VCC_K37
VCC_K38
VCC_K40
VCC_K42
VCC_K43
VCC_SENSE
VSS_SENSE
VIDALERT#
VIDSCK
VIDSOUT
VCCSTG_G20
Place on secondary side,
underneath the package
4V
DNP,CPU
C1262 10u
4V
DNP,CPU
C1261 10u
cap_0402_0p65mm
cap_0402_0p65mm
6.3V
DNP,CPU
C1259 1u
Place on secondary side, underneath the package
6.3V
C1273 1u
VCCIO_SENSE [56]
VSSSA_SENSE [66]
VCCSA_SENSE [66]
+VCC_CORE
G32
G33
G35
G37
G38
G40
G42
J30
J33
J37
J40
K33
K35
K37
K38
K40
K42
K43
E32
E33
B63
A63
D64
G20
6.3V
CAP_0201_14mil
C1274 1u
CAP_0201_14mil
C1275 1u
VCC_CORE_SENSE [66]
VSS_CORE_SENSE [66]
H_CPU_SVIDALERT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
+VCCSTG
+VCCSTG is control by SLP_S0,
but it can overwrite by XDP, that
means it need power for XDP intrafece
6.3V
CAP_0201_14mil
6.3V
DNP,CPU
C1258 1u
CAP_0201_14mil
6.3V
C1268 1u
CAP_0201_14mil
C1281
10u
cap_0402_0p65mm
EV1.9
was:
6.3V
DNP,CPU
CAP_0201_14mil
C1257 1u
6.3V
C1269 1u
CAP_0201_14mil
4V
6.3V
DNP,CPU
CAP_0201_14mil
C1260 1u
6.3V
C1267 1u
CAP_0201_14mil
C1282
10u
cap_0402_0p65mm
CAP_0201_14mil
C1265 1u
6.3V
C1271 1u
CAP_0201_14mil
4V
X867508-004
R1216 220 res_0201_12mil
R1209 0 RES_0201_12mil
R1207 0 RES_0201_12mil
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
Date: Sheet of
Date: Sheet of
2
Dat
+VCCIO
6.3V
6.3V
C1266 1u
CAP_0402_22mil
C1283
10u
4V
cap_0402_0p65mm
Microsoft
Microsoft
Microsoft
B
B
B
e: Sheet of
6.3V
CAP_0402_22mil
C1263 1u
4V
C1272 10u
cap_0402_0p65mm
+VCCST_CPU
res_0201_12mil
R1215 56
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
6.3V
C1264 1u
CAP_0402_22mil
CAP_0402_22mil
4V
C1270 10u
C1284
10u
cap_0402_0p65mm
R1212 100
cap_0402_0p65mm
4V
RES_0201_12mil
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
C1277 10u
4V
4V
C1276 10u
cap_0402_0p65mm
C1286
10u
cap_0402_0p65mm
VIDALERT# [66]
VIDSCLK [66]
VIDSOUT [66]
CPU(3)_SKL POWER1
CPU(3)_SKL POWER1
CPU(3)_SKL POWER1
Surface
Surface
Surface
4V
C1278 10u
cap_0402_0p65mm
4V
1
cap_0402_0p65mm
+VCCSA
12 76Monday, May 11, 2015
12 76Monday, May 11, 2015
12 76Monday, May 11, 2015
+VCCSA
4V
C1279 10u
C1285
10u
cap_0402_0p65mm
4V
C1280 10u
cap_0402_0p65mm
4V
cap_0402_0p65mm
1.90.2
1.90.2
1.90.2
5
U1001M
SKL_
ULT_1356BGA_R1
+VCCGT +VCCGT
D D
C C
VCCGT_SENSE[66]
VSSGT_SENSE[66]
+VCC_CORE
C1315
10u
cap_0402_0p65mm
C13179
10u
cap_0402_0p65mm
C13188
B B
10u
cap_0402_0p65mm
Place on secondary side, underneath the package
4V
4V
4V
C1314
10u
4V
cap_0402_0p65mm
C13182
10u
4V
cap_0402_0p65mm
C13191
10u
4V
cap_0402_0p65mm
C1317
10u
cap_0402_0p65mm
C13180
10u
cap_0402_0p65mm
C13189
10u
cap_0402_0p65mm
bga1356_47x30_42x24x1p27mm-SKL
SKL_ULT
CPU POWER 2 OF 4
A48
VCCGT
A53
VCCGT
A58
VCCGT
A62
VCCGT
A66
VCCGT
AA63
VCCGT
AA64
VCCGT
AA66
VCCGT
AA67
VCCGT
AA69
VCCGT
AA70
VCCGT
AA71
VCCGT
AC64
VCCGT
AC65
VCCGT
AC66
VCCGT
AC67
VCCGT
AC68
VCCGT
AC69
VCCGT
AC70
VCCGT
AC71
VCCGT
J43
VCCGT
J45
VCCGT
J46
VCCGT
J48
VCCGT
J50
VCCGT
J52
VCCGT
J53
VCCGT
J55
VCCGT
J56
VCCGT
J58
VCCGT
J60
VCCGT
K48
VCCGT
K50
VCCGT
K52
VCCGT
K53
VCCGT
K55
VCCGT
K56
VCCGT
K58
VCCGT
K60
VCCGT
L62
VCCGT
L63
VCCGT
L64
VCCGT
L65
VCCGT
L66
VCCGT
L67
VCCGT
L68
VCCGT
L69
VCCGT
L70
VCCGT
L71
VCCGT
M62
VCCGT
N63
VCCGT
N64
VCCGT
N66
VCCGT
N67
VCCGT
N69
VCCGT
J70
VCCGT_SENSE
J69
VSSGT_SENSE
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
D-OPT = TBL1001,CPU
BUIL
C1316
10u
4V
4V
4V
4V
cap_0402_0p65mm
C13184
10u
4V
cap_0402_0p65mm
C13193
10u
4V
cap_0402_0p65mm
VCCGTX_AK42
VCCGTX_AK43
VCCGTX_AK45
VCCGTX_AK46
VCCGTX_AK48
VCCGTX_AK50
VCCGTX_AK52
VCCGTX_AK53
VCCGTX_AK55
VCCGTX_AK56
VCCGTX_AK58
VCCGTX_AK60
VCCGTX_AK70
VCCGTX_AM48
VCCGTX_AM50
VCCGTX_AM52
VCCGTX_AM53
VCCGTX_AM56
VCCGTX_AM58
VCCGTX_AU58
VCCGTX_AU63
VCCGTX_BB57
VCCGTX_BB66
VCCGTX_SENSE
VSSGTX_SENSE
13 OF 20
C1310
10u
4V
cap_0402_0p65mm
C13178
10u
4V
cap_0402_0p65mm
C13187
10u
4V
cap_0402_0p65mm
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGTX_AL43
VCCGTX_AL46
VCCGTX_AL50
VCCGTX_AL53
VCCGTX_AL56
VCCGTX_AL60
C1311
10u
cap_0402_0p65mm
C13183
10u
cap_0402_0p65mm
C13192
10u
cap_0402_0p65mm
N70
N71
R63
R64
R65
R66
R67
R68
R69
R70
R71
T62
U65
U68
U71
W63
W64
W65
W66
W67
W68
W69
W70
W71
Y62
AK42
AK43
AK45
AK46
AK48
AK50
AK52
AK53
AK55
AK56
AK58
AK60
AK70
AL43
AL46
AL50
AL53
AL56
AL60
AM48
AM50
AM52
AM53
AM56
AM58
AU58
AU63
BB57
BB66
AK62
AL61
4V
4V
4V
4
+VCCGT
C1312
10u
4V
cap_0402_0p65mm
C13181
10u
4V
cap_0402_0p65mm
C13190
10u
4V
cap_0402_0p65mm
C1313
10u
4V
cap_0402_0p65mm
C13185
10u
4V
cap_0402_0p65mm
C13194
10u
4V
cap_0402_0p65mm
C1318
4V
10u
cap_0402_0p65mm
C13186
10u
4V
cap_0402_0p65mm
C13195
10u
4V
cap_0402_0p65mm
+VCCGT
3
+VCCGT
U23E,CPU
C1390
10u
cap_0402_0p65mm
U23
C13101
22u
cap_0603_40mil
C1355
10u
4V
cap_0402_0p65mm
C1361
6.3V
1u
CAP_0201_14mil
C1366
6.3V
1u
CAP_0201_14mil
4V
,CPU
DNP,CPU
DNP
C13124 10u
cap_0402_0p65mm
6.3V
DNP,CPU
DNP,CPU
C13144 1u
CAP_0201_14mil
C1371
47u
cap_0805_36mil
C1382
22u
cap_0603_38mil
2
THIS IS PLACE ON VCCGTX pins (they are connected to +VCCGT)
Place on secondary side, underneath the package
only for 23e
U23E,CPU
C1391
10u
4V
E,CPU
4V
4V
cap_0402_0p65mm
onl
y for 23e
E,CPU
U23
C1376
22u
4V
cap_0603_40mil
Place on secondary side, underneath the package
C1353
10u
4V
cap_0402_0p65mm
C1360
6.3V
1u
CAP_0201_14mil
C1367
6.3V
1u
CAP_0201_14mil
4V
4V
DNP,CPU
C13127 10u
C13126 10u
cap_0402_0p65mm
Place on secondary side, underneath the package
6.3V
6.3V
DNP,CPU
C13147 1u
C13146 1u
CAP_0201_14mil
C1373
47u
6.3V
cap_0805_36mil
C1381
22u
6.3V
cap_0603_38mil
C13125 10u
C13145 1u
6.3V
6.3V
4V
DNP,CPU
cap_0402_0p65mm
6.3V
DNP,CPU
CAP_0201_14mil
C1352
10u
4V
cap_0402_0p65mm
C1357
1u
CAP_0201_14mil
C1364
1u
CAP_0201_14mil
4V
DNP,CPU
C13128 10u
cap_0402_0p65mm
cap_0402_0p65mm
6.3V
DNP,CPU
C13148 1u
CAP_0201_14mil
CAP_0201_14mil
C1372
47u
cap_0805_36mil
C1384
22u
cap_0603_38mil
U23E,CPU
C1389
10u
4V
cap_0402_0p65mm
E,CPU
U23
C1397
22u
4V
cap_0603_40mil
C1351
10u
cap_0402_0p65mm
6.3V
6.3V
4V
DNP,CPU
DNP,CPU
C13129 10u
C13130 10u
cap_0402_0p65mm
6.3V
DNP,CPU
DNP,CPU
C13149 1u
C13177 1u
CAP_0201_14mil
6.3V
6.3V
U23E,CPU
C1393
10u
cap_0402_0p65mm
E,CPU
U23
C1398
22u
cap_0603_40mil
4V
C1359
6.3V
1u
CAP_0201_14mil
C1365
6.3V
1u
CAP_0201_14mil
4V
4V
DNP,CPU
C13131 10u
cap_0402_0p65mm
6.3V
6.3V
DNP,CPU
C13151 1u
CAP_0201_14mil
C1374
47u
6.3V
cap_0805_36mil
C1383
22u
6.3V
cap_0603_38mil
4V
4V
C1350
10u
cap_0402_0p65mm
4V
DNP,CPU
C13132 10u
cap_0402_0p65mm
6.3V
DNP,CPU
C13152 1u
CAP_0201_14mil
U23E,CPU
C1392
10u
4V
cap_0402_0p65mm
E,CPU
U23
C1399
22u
4V
cap_0603_40mil
4V
C1349
6.3V
1u
CAP_0201_14mil
C1363
6.3V
1u
CAP_0201_14mil
4V
DNP,CPU
C13133 10u
cap_0402_0p65mm
6.3V
DNP,CPU
C13153 1u
CAP_0201_14mil
C1375
47u
6.3V
cap_0805_36mil
C1377
22u
6.3V
cap_0603_38mil
C1358
10u
4V
cap_0402_0p65mm
DNP,CPU
C13134 10u
cap_0402_0p65mm
DNP,CPU
C13154 1u
CAP_0201_14mil
C1378
22u
cap_0603_38mil
U23E,CPU
C1394
10u
4V
cap_0402_0p65mm
E,CPU
U23
C1308
22u
4V
cap_0603_40mil
C1354
10u
4V
cap_0402_0p65mm
C1356
6.3V
1u
CAP_0201_14mil
C1362
6.3V
1u
CAP_0201_14mil
4V
4V
DNP,CPU
C13135 10u
cap_0402_0p65mm
cap_0402_0p65mm
6.3V
6.3V
DNP,CPU
C13155 1u
CAP_0201_14mil
CAP_0201_14mil
6.3V
DNP,CPU
DNP,CPU
U23E,CPU
C1395
10u
4V
cap_0402_0p65mm
E,CPU
U23
C13100
22u
4V
cap_0603_40mil
C1368
10u
cap_0402_0p65mm
C13196
6.3V
1u
CAP_0201_14mil
C13197
6.3V
1u
CAP_0201_14mil
4V
DNP,CPU
C13137 10u
C13136 10u
cap_0402_0p65mm
6.3V
DNP,CPU
C13156 1u
C13157 1u
CAP_0201_14mil
C1379
22u
6.3V
cap_0603_38mil
4V
4V
DNP,CPU
C13138 10u
cap_0402_0p65mm
6.3V
DNP,CPU
C13158 1u
CAP_0201_14mil
U23E,CPU
C1396
10u
4V
cap_0402_0p65mm
E,CPU
U23
C13102
22u
4V
cap_0603_40mil
C1369
10u
4V
cap_0402_0p65mm
4V
4V
DNP,CPU
C13139 10u
cap_0402_0p65mm
cap_0402_0p65mm
6.3V
6.3V
DNP,CPU
C13159 1u
CAP_0201_14mil
CAP_0201_14mil
EV19
: 0402
WAS
EV1.9
was:X867508-004
C1370
10u
4V
cap_0402_0p65mm
4V
4V
DNP,CPU
DNP,CPU
DNP,CPU
C13140 10u
cap_0402_0p65mm
6.3V
DNP,CPU
C13160 1u
CAP_0201_14mil
C13142 10u
C13141 10u
cap_0402_0p65mm
6.3V
DNP,CPU
DNP,CPU
C13161 1u
C13162 1u
CAP_0201_14mil
1
4V
DNP,CPU
cap_0402_0p65mm
6.3V
DNP,CPU
CAP_0201_14mil
EV1.9
was:X867508-004
C13122
10u
4V
cap_0402_0p65mm
4V
EV1.9
was:X867508-003
C13143 10u
cap_0402_0p65mm
6.3V
C13163 1u
CAP_0201_14mil
C13123
10u
4V
cap_0402_0p65mm
C1328
10u
4V
cap_0402_0p65mm
C1334
6.3V
1u
CAP_0201_14mil
C1306
6.3V
1u
CAP_0201_14mil
C13108
6.3V
1u
CAP_0201_14mil
C13115
6.3V
1u
CAP_0201_14mil
A A
C13121
6.3V
1u
CAP_0201_14mil
C1327
10u
4V C13165
cap_0402_0p65mm
C1335
6.3V
1u
CAP_0201_14mil
C1307
6.3V
1u
CAP_0201_14mil
C1322
6.3V
1u
CAP_0201_14mil
C13109
6.3V
1u
CAP_0201_14mil
C13116
6.3V
1u
CAP_0201_14mil
C1326
10u
4V
cap_0402_0p65mm
C1332
6.3V
1u
CAP_0201_14mil
C1304
6.3V
1u
CAP_0201_14mil
C13104
6.3V
1u
CAP_0201_14mil
C13111
6.3V
1u
CAP_0201_14mil
C13119
6.3V
1u
CAP_0201_14mil
C1325
10u
4V
cap_0402_0p65mm
C1333
6.3V
1u
CAP_0201_14mil
C1305
6.3V
1u
CAP_0201_14mil
C13103
6.3V
1u
CAP_0201_14mil
C13110
6.3V
1u
CAP_0201_14mil
C13117
6.3V
1u
CAP_0201_14mil
C1324
10u
4V
cap_0402_0p65mm
C1323
6.3V
1u
CAP_0201_14mil
C1302
6.3V
1u
CAP_0201_14mil
C13106
6.3V
1u
CAP_0201_14mil
C13113
6.3V
1u
CAP_0201_14mil
C13120
6.3V
1u
CAP_0201_14mil
C1331
10u
4V
cap_0402_0p65mm
C1330
6.3V
1u
CAP_0201_14mil
C1303
6.3V
1u
CAP_0201_14mil
C13105
6.3V
1u
CAP_0201_14mil
C13112
6.3V
1u
CAP_0201_14mil
C13118
6.3V
1u
CAP_0201_14mil
C1329
4V
10u
cap_0402_0p65mm
C1301
6.3V
1u
CAP_0201_14mil
C1309
6.3V
1u
CAP_0201_14mil
C13107
6.3V
1u
CAP_0201_14mil
C13114
6.3V
1u
CAP_0201_14mil
EV1.9
was:X867508-004
C1300
6.3V
1u
CAP_0201_14mil
+VCC_CORE
4V
,CPU
DNP
C13167 10u
C1338
10u
4V
cap_0402_0p65mm
C1341
47u
6.3V
cap_0603_40mil
47u
6.3V
cap_0805_36mil
C1380
22u
6.3V
cap_0603_38mil
4V
DNP,CPU
C13168 10u
cap_0402_0p65mm
C1337
10u
4V
cap_0402_0p65mm
C1342
47u
6.3V
cap_0603_40mil
DNP,CPU
cap_0402_0p65mm
C13166
47u
6.3V
cap_0805_36mil
C1385
22u
6.3V
cap_0603_38mil
4V
DNP,CPU
C13170 10u
C13169 10u
cap_0402_0p65mm
C1336
10u
4V
cap_0402_0p65mm
C1343
47u
6.3V
cap_0603_40mil
C13164
47u
cap_0805_36mil
C1386
22u
cap_0603_38mil
4V
DNP,CPU
cap_0402_0p65mm
C1320
10u
cap_0402_0p65mm
C1344
47u
cap_0603_40mil
C13171 10u
6.3V
6.3V
4V
4V
6.3V
cap_0402_0p65mm
C1387
22u
cap_0603_38mil
4V
DNP,CPU
C13172 10u
cap_0402_0p65mm
6.3V
4V
DNP,CPU
C13173 10u
cap_0402_0p65mm
C1321
10u
4V
cap_0402_0p65mm
C1345
47u
6.3V
cap_0603_40mil
C1388
22u
6.3V
cap_0603_38mil
4V
DNP,CPU
C13174 10u
cap_0402_0p65mm
C1319
10u
4V
cap_0402_0p65mm
C1346
47u
6.3V
cap_0603_40mil
EV19
WAS: 0402
4V
DNP,CPU
C13175 10u
cap_0402_0p65mm
4V
DNP,CPU
C13176 10u
cap_0402_0p65mm
C1339
10u
4V
cap_0402_0p65mm
C1347
47u
6.3V
cap_0603_40mil
C1340
10u
4V
cap_0402_0p65mm
C1348
47u
6.3V
cap_0603_40mil
EV1.9
was:X867508-002
EV1.9
was:X867508-001
EV1.9 was:0805
CPU(4)_SKL_POWER2
CPU(4)_SKL_POWER2
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
te: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Da
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
CPU(4)_SKL_POWER2
Title:
Title:
Title:
Surface
Surface
Surface
Engineer:
Engineer:
Engineer:
1
1.90.2
1.90.2
13 76Monday, May 11, 2015
13 76Monday, May 11, 2015
13 76Monday, May 11, 2015
1.90.2
5
U1001P
SKL_
ULT_1356BGA_R1
356_47x30_42x24x1p27mm-SKL
bga1
SKL_ULT
GND 1 OF 3
A5
VSS
A67
VSS
A70
VSS
AA2
D D
C C
B B
AA4
AA65
AA68
AB15
AB16
AB18
AB21
AB8
AD13
AD16
AD19
AD20
AD21
AD62
AD8
AE64
AE65
AE66
AE67
AE68
AE69
AF1
AF10
AF15
AF17
AF2
AF4
AF63
AG16
AG17
AG18
AG19
AG20
AG21
AG71
AH13
AH6
AH63
AH64
AH67
AJ15
AJ18
AJ20
AJ4
AK11
AK16
AK18
AK21
AK22
AK27
AK63
AK68
AK69
AK8
AL2
AL28
AL32
AL35
AL38
AL4
AL45
AL48
AL52
AL55
AL58
AL64
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL65
AL66
AM13
AM21
AM25
AM27
AM43
AM45
AM46
AM55
AM60
AM61
AM68
AM71
AM8
AN20
AN23
AN28
AN30
AN32
AN33
AN35
AN37
AN38
AN40
AN42
AN58
AN63
AP10
AP18
AP20
AP23
AP28
AP32
AP35
AP38
AP42
AP58
AP63
AP68
AP70
AR11
AR15
AR16
AR20
AR23
AR28
AR35
AR42
AR43
AR45
AR46
AR48
AR5
AR50
AR52
AR53
AR55
AR58
AR63
AR8
AT2
AT20
AT23
AT28
AT35
AT4
AT42
AT56
AT58
4
AT63
AT68
AT71
AU10
AU15
AU20
AU32
AU38
AV1
AV68
AV69
AV70
AV71
AW10
AW12
AW14
AW16
AW18
AW21
AW23
AW26
AW28
AW30
AW32
AW34
AW36
AW38
AW41
AW43
AW45
AW47
AW49
AW51
AW53
AW55
AW57
AW6
AW60
AW62
AW64
AW66
AW8
AY66
B10
B14
B18
B22
B30
B34
B39
B44
B48
B53
B58
B62
B66
B71
BA1
BA10
BA14
BA18
BA2
BA23
BA28
BA32
BA36
F68
BA45
U1001Q
SKL_
ULT_1356BGA_R1
356_47x30_42x24x1p27mm-SKL
bga1
SKL_ULT
GND 2 OF 3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BA49
BA53
BA57
BA6
BA62
BA66
BA71
BB18
BB26
BB30
BB34
BB38
BB43
BB55
BB6
BB60
BB64
BB67
BB70
C1
C25
C5
D10
D11
D14
D18
D22
D25
D26
D30
D34
D39
D44
D45
D47
D48
D53
D58
D6
D62
D66
D69
E11
E15
E18
E21
E46
E50
E53
E56
E6
E65
E71
F1
F13
F2
F22
F23
F27
F28
F32
F33
F35
F37
F38
F4
F40
F42
BA41
3
U1001R
SKL_
ULT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
SKL_ULT
GND 3 OF 3
F8
VSS
G10
VSS
G22
VSS
G43
VSS
G45
VSS
G48
VSS
G5
VSS
G52
VSS
G55
VSS
G58
VSS
G6
VSS
G60
VSS
G63
VSS
G66
VSS
H15
VSS
H18
VSS
H71
VSS
J11
VSS
J13
VSS
J25
VSS
J28
VSS
J32
VSS
J35
VSS
J38
VSS
J42
VSS
J8
VSS
K16
VSS
K18
VSS
K22
VSS
K61
VSS
K63
VSS
K64
VSS
K65
VSS
K66
VSS
K67
VSS
K68
VSS
K70
VSS
K71
VSS
L11
VSS
L16
VSS
L17
VSS
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
18 OF 20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L18
L2
L20
L4
L8
N10
N13
N19
N21
N6
N65
N68
P17
P19
P20
P21
R13
R6
T15
T17
T18
T2
T21
T4
U10
U63
U64
U66
U67
U69
U70
V16
V17
V18
W13
W6
W9
Y17
Y19
Y20
Y21
2
1
REV = JKS
A A
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
16 OF 20
5
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
4
17 OF 20
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
CPU(5)_GND
CPU(5)_GND
CPU(5)_GND
Surface
Surface
Surface
14 76Monday, May 11, 2015
14 76Monday, May 11, 2015
1
14 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
TP1516
CFG0[18]
CFG1[18]
CFG2[18]
CFG3[18]
D D
CFG4
0 enable eDP
Default
C C
B B
A A
1
Disable eDP
CFG4[18]
CFG5[18]
CFG6[18]
CFG7[18]
CFG8[18]
CFG9[18]
CFG10[18]
CFG11[18]
CFG12[18]
CFG13[18]
CFG14[18]
CFG15[18]
CFG16[18]
CFG17[18]
CFG18[18]
CFG19[18]
+1P8VSUS_ORG
DNP,CPU
C1501
1u
CAP_0402_22mil
6.3V
5
R1507 49.9
RES_0201_12mil
R1501
1K
RES_0201_12mil
U1001T
SKL_
bga1356_47x30_42x24x1p27mm-SKL
AW69
RSVD_AW69
AW68
RSVD_AW68
AU56
RSVD_AU56
AW48
RSVD_AW48
C7
RSVD_C7
U12
RSVD_U12
U11
RSVD_U11
H11
RSVD_H11
REV = JKS
TBL1
Source Package = SKL_ULT_1356BGA_R1
ITP_PMODE[18]
ULT_1356BGA_R1
SKL_ULT
SPARE
20 OF 20
001,CPU
4
CFG_RCOMP
RSVD_F6
RSVD_E3
RSVD_C11
RSVD_B11
RSVD_A11
RSVD_D12
RSVD_C12
RSVD_F52
4
F6
E3
C11
B11
A11
D12
C12
F52
U1001S
SKL_
ULT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
E68
B67
D65
D67
E70
C68
D68
C67
F71
G69
F70
G68
H70
G71
H69
G70
E63
F63
E66
F66
E60
E8
AY2
AY1
D1
D3
K46
K45
AL25
AL27
C71
B70
F60
A52
BA70
BA68
J71
J68
F65
G65
F61
E61
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
CFG[18]
CFG[19]
CFG_RCOMP
ITP_PMODE
RSVD_AY2
RSVD_AY1
RSVD_D1
RSVD_D3
RSVD_K46
RSVD_K45
RSVD_AL25
RSVD_AL27
RSVD_C71
RSVD_B70
RSVD_F60
RSVD_A52
RSVD_TP_BA70
RSVD_TP_BA68
RSVD_J71
RSVD_J68
VSS_F65
VSS_G65
RSVD_F61
RSVD_E61
REV = JKS
TBL1001,CPU
ce Package = SKL_ULT_1356BGA_R1
Sour
RESERVED SIGNALS-1
SKL_ULT
19 OF 20
3
TP5
TP6
TP4
TP1
TP2
ZVM#
BB68
BB69
AK13
AK12
BB2
BA3
AU5
AT5
D5
D4
B2
C2
B3
A3
AW1
E1
E2
BA4
BB4
A4
C4
BB5
A69
B69
AY3
D71
C70
C54
D54
AY4
BB3
AY71
AR56
AW71
AW70
AP56
C64
RSVD_TP_AK13
RSVD_TP_AK12
MFang 8Jan15: [Intel] used in the HVM testing
should be left not connected.
RSVD_AY3
PROC_SELECT#
R1502 0
RES_0201_12mil
DNP,CPU
RSVD_TP_BB68
RSVD_TP_BB69
RSVD_TP_AK13
RSVD_TP_AK12
RSVD_BB2
RSVD_BA3
RSVD_D5
RSVD_D4
RSVD_B2
RSVD_C2
RSVD_B3
RSVD_A3
RSVD_AW1
RSVD_E1
RSVD_E2
RSVD_BA4
RSVD_BB4
RSVD_A4
RSVD_C4
RSVD_A69
RSVD_B69
RSVD_AY3
RSVD_D71
RSVD_C70
RSVD_C54
RSVD_D54
VSS_AY71
RSVD_TP_AW71
RSVD_TP_AW70
PROC_SELECT#
3
MSM#
2
TP1503 SP_TP_SMDp58mm
TP1502 SP_TP_SMDp58mm
+VCCST_CPU
R1540 100K
RES_0201_12mil
DNP,CPU
100k ohm resistor
only needed for
Cannonlake
2
1
ZVM# and MSM# may need to
ZVM# [58]
MSM# [58]
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
te: Sheet of
Date: Sheet of
Date: Sheet of
Da
control the VCCOPC and VCCEOPIO
CPU(6)_CFG_RESERVED
CPU(6)_CFG_RESERVED
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
CPU(6)_CFG_RESERVED
Surface
Surface
Surface
1
1.90.2
1.90.2
1.90.2
15 76Monday, May 11, 2015
15 76Monday, May 11, 2015
15 76Monday, May 11, 2015
5
U1601
H9CCNNN8JTALAR-NTD
M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9
M_A_DIM0_CLK1[11,16]
D D
C C
B B
M_A_DIM0_CLK#1[11,16]
M_A_DIM0_CKE2[ 11,16]
M_A_DIM0_CKE3[ 11,16] M_A_DIM0_CKE1[ 11,16]
M_A_DIM0_CS#0[11,16]
M_A_DIM0_CS#1[11,16]
GND
M_A_DQS2[11]
M_A_DQS#2[11]
M_A_DQS0[11]
M_A_DQS#0[11]
M_A_DQS3[11]
M_A_DQS#3[11]
M_A_DQS1[11]
M_A_DQS#1[11]
GND
bga178_13x17_11x11p5x1_p8xp65mm
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK
J2
CK#
K3
CKE0
K4
CKE1
L3
CS#0
L4
CS#1
L8
DM0
G8
DM1
P8
DM2
D8
DM3/NC
A1
DNU1
A2
DNU2
A12
DNU3
A13
DNU4
B1
DNU5
B13
DNU6
T1
DNU7
T13
DNU8
U1
DNU9
U2
DNU10
U12
DNU11
U13
DNU12
L10
DQS0
L11
DQS0#
G10
DQS1
G11
DQS1#
P10
DQS2/NC
P11
DQS2#/NC
D10
DQS3/NC
D11
DQS3#/NC
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ1
B12
VSSQ2
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ6
F12
VSSQ7
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ13
M12
VSSQ14
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ18
T12
VSSQ19
TBL1601,DDR
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC
VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8
VDD1_10
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VREFCA
VREFDQ
ODT
ZQ0
ZQ1
NC1
NC2
NC3
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
J8
B3
B4
C4
K9
R3
M_A_D16
M_A_D17
M_A_D23
M_A_D18
M_A_D21
M_A_D20
M_A_D22
M_A_D19
M_A_D7
M_A_D0
M_A_D4
M_A_D1
M_A_D6
M_A_D3
M_A_D5
M_A_D2
M_A_D29
M_A_D28
M_A_D31
M_A_D26
M_A_D25
M_A_D24
M_A_D27
M_A_D30
M_A_D9
M_A_D12
M_A_D15
M_A_D11
M_A_D13
M_A_D8
M_A_D14
M_A_D10
+1P8V_DUAL +1P8V_DUAL
C1660
100p
CAP_0201_14mil
+1P2V_DUAL
C1661
100p
CAP_0201_14mil
GND GND
+1P2V_DUAL
+1P2V_DUAL +1P2V_DUAL
+V_VREF_CA_DIMM
+V_VREF_DQ_DIMM0
M_A_DIM0_ODT0 [11,16]
ZQ1601
ZQ1602
DDR
R1601 243
R1602 243
TBL2301,DDR
25V
25V
M_A_D[23:16] [11]
M_A_D[7:0] [11]
M_A_D[31:24] [11]
M_A_D[15:8] [11]
RES_0402_16mil
RES_0402_16mil
GND
4
M_A_CAB[9:0][11,16]
M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9
M_A_DIM0_CLK0[11,16]
M_A_DIM0_CLK#0[11,16]
M_A_DIM0_CKE0[ 11,16]
M_A_DIM0_CS#0[11,16]
M_A_DIM0_CS#1[11,16]
GND
M_A_DQS7[11]
M_A_DQS#7[11]
M_A_DQS4[11]
M_A_DQS#4[11]
M_A_DQS6[11]
M_A_DQS#6[11]
M_A_DQS5[11]
M_A_DQS#5[11]
GND
U1602
H9CCNNN8JTALAR-NTD
bga178_13x17_11x11p5x1_p8xp65mm
R2
CA0
P2
CA1
N2
CA2
N3
CA3
M3
CA4
F3
CA5
E3
CA6
E2
CA7
D2
CA8
C2
CA9
J3
CK
J2
CK#
K3
CKE0
K4
CKE1
L3
CS#0
L4
CS#1
L8
DM0
G8
DM1
P8
DM2
D8
DM3/NC
A1
DNU1
A2
DNU2
A12
DNU3
A13
DNU4
B1
DNU5
B13
DNU6
T1
DNU7
T13
DNU8
U1
DNU9
U2
DNU10
U12
DNU11
U13
DNU12
L10
DQS0
L11
DQS0#
G10
DQS1
G11
DQS1#
P10
DQS2/NC
P11
DQS2#/NC
D10
DQS3/NC
D11
DQS3#/NC
B2
VSS1
B5
VSS2
C5
VSS3
E4
VSS4
E5
VSS5
F5
VSS6
H2
VSS7
J12
VSS8
K2
VSS9
L6
VSS10
M5
VSS11
N4
VSS12
N5
VSS13
R4
VSS14
R5
VSS15
T2
VSS16
T3
VSS17
T4
VSS18
T5
VSS19
C3
VSSCA1
D3
VSSCA2
F4
VSSCA3
G3
VSSCA4
G4
VSSCA5
J4
VSSCA6
M4
VSSCA7
P3
VSSCA8
B6
VSSQ1
B12
VSSQ2
C6
VSSQ3
D12
VSSQ4
E6
VSSQ5
F6
VSSQ6
F12
VSSQ7
G6
VSSQ8
G9
VSSQ9
H10
VSSQ10
K10
VSSQ11
L9
VSSQ12
M6
VSSQ13
M12
VSSQ14
N6
VSSQ15
P12
VSSQ16
R6
VSSQ17
T6
VSSQ18
T12
VSSQ19
TBL1601,DDR
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC
VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8
VDD1_10
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VREFCA
VREFDQ
ODT
ZQ0
ZQ1
NC1
NC2
NC3
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
J8
B3
B4
C4
K9
R3
M_A_D58
M_A_D61
M_A_D56
M_A_D57
M_A_D60
M_A_D59
M_A_D62
M_A_D63
M_A_D37
M_A_D38
M_A_D32
M_A_D36
M_A_D33
M_A_D39
M_A_D34
M_A_D35
M_A_D52
M_A_D51
M_A_D50
M_A_D48
M_A_D53
M_A_D54
M_A_D55
M_A_D49
M_A_D41
M_A_D45
M_A_D44
M_A_D46
M_A_D40
M_A_D47
M_A_D42
M_A_D43
ZQ1603
ZQ1604
3
C1659
25V
100p
CAP_0201_14mil
GNDGND
+1P2V_DUAL
C1658
25V
100p
CAP_0201_14mil
+1P2V_DUAL
+V_VREF_CA_DIMM
+V_VREF_DQ_DIMM0
M_A_DIM0_ODT0 [11,16]
DDR
R1603 243
R1604 243
TBL2301,DDR
GND
M_A_D[63:56] [11]M_A_CAA[9:0][11,16]
+V_VREF_CA_DIMM +V_VREF_DQ_DIMM0
M_A_D[39:32] [11]
M_A_D[55:48] [11]
M_A_D[47:40] [11]
+1P2V_DUAL
CAP_0402_22mil
RES_0402_16mil
RES_0402_16mil
CAP_0201_14mil
+1P8V_DUAL
CAP_0402_22mil
C1635
1u
6.3V
C1601
47000p
6.3V
C1608
1u
6.3V
CAP_0402_28mil
CAP_0402_22mil
CAP_0402_22mil
CAP_0402_22mil
C1612
10u
6.3V
C1618
1u
6.3V
C1631
1u
6.3V
C1633
1u
6.3V
CAP_0201_14mil
CAP_0402_22mil
CAP_0402_22mil
CAP_0402_22mil
C1602
47000p
6.3V
C1605
10u
CAP_0402_28mil
6.3V
C1609
1u
6.3V
C1613
10u
6.3V
CAP_0402_28mil
C1619
1u
6.3V
C1625
1u
6.3V
C1634
1u
6.3V
CAP_0402_22mil
CAP_0402_22mil
CAP_0402_28mil
CAP_0402_22mil
CAP_0402_22mil
CAP_0402_22mil
C1603
47000p
6.3V
CAP_0201_14mil
C1606
10u
CAP_0402_28mil
6.3V
C1610
1u
6.3V
C1614
10u
6.3V
C1621
1u
6.3V
C1627
1u
6.3V
C1632
1u
6.3V
CAP_0402_22mil
CAP_0402_22mil
GND
CAP_0402_22mil
GND
CAP_0402_28mil
cap_0201_14mil
2
GNDGNDGNDGND
CAP_0201_14mil
C1607
10u
CAP_0402_28mil
6.3V
C1611
1u
6.3V
C1615
10u
6.3V
C1620
1u
6.3V
C1626
1u
6.3V
C1636
0.1u
6.3V
C1604
47000p
6.3V
CAP_0402_22mil
CAP_0402_22mil
1
M_A_CAA[9:0][11,16]
M_A_CAB[9:0][11,16]
M_A_DIM0_ODT0[11,16]
M_A_DIM0_CS#0[11,16]
M_A_DIM0_CS#1[11,16]
M_A_DIM0_CKE0[ 11,16]
M_A_DIM0_CKE1[ 11,16]
M_A_DIM0_CKE2[ 11,16]
M_A_DIM0_CKE3[ 11,16]
M_A_DIM0_CLK0[11,16]
M_A_DIM0_CLK#0[11,16]
M_A_DIM0_CLK1[11,16]
C1616
10u
6.3V
CAP_0402_28mil
C1622
1u
6.3V
C1629
1u
6.3V
C1637
0.1u
6.3V
cap_0201_14mil
C1617
10u
6.3V
CAP_0402_28mil
GND
C1624
1u
6.3V
GND
CAP_0402_22mil
C1630
1u
6.3V
GND
CAP_0402_22mil
C1638
0.1u
6.3V
cap_0201_14mil
GND
M_A_DIM0_CLK#1[11,16]
C1623
1u
6.3V
CAP_0402_22mil
C1628
1u
6.3V
CAP_0402_22mil
C1639
0.1u
6.3V
cap_0201_14mil
M_A_CAA0
M_A_CAA1
M_A_CAA2
M_A_CAA3
M_A_CAA4
M_A_CAA5
M_A_CAA6
M_A_CAA7
M_A_CAA8
M_A_CAA9
M_A_CAB0
M_A_CAB1
M_A_CAB2
M_A_CAB3
M_A_CAB4
M_A_CAB5
M_A_CAB6
M_A_CAB7
M_A_CAB8
M_A_CAB9
R1605 68 5%
R1606 68 5%
R1607 68 5%
R1608 68 5%
R1609 68 5%
R1610 68 5%
R1611 68 5%
R1612 68 5%
R1613 68 5%
R1614 68 5%
R1615 68 5%
R1616 68 5%
R1617 68 5%
R1618 68 5%
R1619 68 5%
R1620 68 5%
R1621 68 5%
R1622 68 5%
R1623 68 5%
R1624 68 5%
R1629 80.6
R1634 80.6
R1635 80.6
R1637 80.6
R1638 80.6
R1639 80.6
R1640 80.6
R1630 37.4
R1631 37.4
R1632 37.4
R1633 37.4
+V_VDDQ_VTT
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12MIL
RES_0201_12MIL
RES_0201_12MIL
RES_0201_12MIL
RES_0201_12MIL
RES_0201_12MIL
RES_0201_12MIL
res_0201_12mil
res_0201_12mil
res_0201_12mil
res_0201_12mil
+V_VDDQ_VTT
C1641
1u
6.3V
CAP_0402_22mil
A A
C1643
1u
6.3V
CAP_0402_22mil
C1644
1u
6.3V
CAP_0402_22mil
5
C1646
1u
6.3V
CAP_0402_22mil
C1663
1u
6.3V
CAP_0402_22mil
C1664
1u
6.3V
CAP_0402_22mil
C1665
22u
6.3V
cap_0603_38mil
C1650
22u
cap_0603_38mil
+V_VDDQ_VTT+V_VDDQ_VTT
C1662
25V
6.3V
4
100p
CAP_0201_14mil
GNDGND GND
LPDDR3(1)_MEMORY DOWN
LPDDR3(1)_MEMORY DOWN
LPDDR3(1)_MEMORY DOWN
Title:
Title:
Title:
Surface
Surface
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Engineer:
Engineer:
Engineer:
1
Surface
1.90.2
1.90.2
16 76Monday, May 11, 2015
16 76Monday, May 11, 2015
16 76Monday, May 11, 2015
1.90.2
5
U1701
H9CCNNN8JTALAR-NTD
78_13x17_11x11p5x1_p8xp65mm
M12
A12
A13
B13
T13
U12
U13
L10
L11
G10
G11
P10
P11
D10
D11
J12
B12
D12
F12
H10
K10
P12
T12
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
J3
J2
K3
K4
L3
L4
L8
G8
P8
D8
A1
A2
B1
T1
U1
U2
B2
B5
C5
E4
E5
F5
H2
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
C3
D3
F4
G3
G4
J4
M4
P3
B6
C6
E6
F6
G6
G9
L9
M6
N6
R6
T6
bga1
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK
CK#
CKE0
CKE1
CS#0
CS#1
DM0
DM1
DM2
DM3/NC
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12
DQS0
DQS0#
DQS1
DQS1#
DQS2/NC
DQS2#/NC
DQS3/NC
DQS3#/NC
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSSCA1
VSSCA2
VSSCA3
VSSCA4
VSSCA5
VSSCA6
VSSCA7
VSSCA8
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
TBL1601,DDR
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC
VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8
VDD1_10
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VREFCA
VREFDQ
ODT
ZQ0
ZQ1
NC1
NC2
NC3
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
J8
B3
B4
C4
K9
R3
M_B_D0
M_B_D1
M_B_D4
M_B_D3
M_B_D2
M_B_D6
M_B_D5
M_B_D7
M_B_D25
M_B_D29
M_B_D27
M_B_D26
M_B_D24
M_B_D28
M_B_D30
M_B_D31
M_B_D19
M_B_D23
M_B_D21
M_B_D16
M_B_D22
M_B_D18
M_B_D17
M_B_D20
M_B_D13
M_B_D15
M_B_D10
M_B_D11
M_B_D12
M_B_D8
M_B_D9
M_B_D14
GND
GND GND
ZQ1701
R1701 243 RES_0402_16mil
ZQ1702
R1702 243
M_B_D[7:0] [11] M_B_D[55:48] [11]
M_B_D[31:24] [11]
M_B_D[23:16] [11]
M_B_D[15:8] [11]
+1P8V_DUAL +1P8V_DUAL
C1749
100p 25V
CAP_0201_14mil
+1P2V_DUAL
C1758
100p 25V
CAP_0201_14mil
+1P2V_DUAL
+1P2V_DUAL +1P2V_DUAL
+V_VREF_CA_DIMM
+V_VREF_DQ_DIMM1
DDR
TBL2301,DDR
M_B_CAA[9:0][11,17] M_B_CAB[9:0][11,17]
M_B_DIM0_CLK0[11,17]
D D
C C
B B
M_B_DIM0_CLK#0[11,17]
M_B_DIM0_CKE0[ 11,17]
M_B_DIM0_CKE1[ 11,17]
M_B_DIM0_CS#0[11,17]
M_B_DIM0_CS#1[11,17]
M_B_DQS0[11]
M_B_DQS#0[11]
M_B_DQS3[11]
M_B_DQS#3[11]
M_B_DQS2[11]
M_B_DQS#2[11]
M_B_DQS1[11]
M_B_DQS#1[11]
M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9
GND GND
GND GND
4
U1702
H9CCNNN8JTALAR-NTD
78_13x17_11x11p5x1_p8xp65mm
U12
U13
G10
G11
P10
P11
D10
D11
B12
D12
F12
H10
K10
M12
P12
T12
A12
A13
B13
T13
L10
L11
J12
R2
P2
N2
N3
M3
F3
E3
E2
D2
C2
J3
J2
K3
K4
L3
L4
L8
G8
P8
D8
A1
A2
B1
T1
U1
U2
B2
B5
C5
E4
E5
F5
H2
K2
L6
M5
N4
N5
R4
R5
T2
T3
T4
T5
C3
D3
F4
G3
G4
J4
M4
P3
B6
C6
E6
F6
G6
G9
L9
M6
N6
R6
T6
bga1
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK
CK#
CKE0
CKE1
CS#0
CS#1
DM0
DM1
DM2
DM3/NC
DNU1
DNU2
DNU3
DNU4
DNU5
DNU6
DNU7
DNU8
DNU9
DNU10
DNU11
DNU12
DQS0
DQS0#
DQS1
DQS1#
DQS2/NC
DQS2#/NC
DQS3/NC
DQS3#/NC
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSSCA1
VSSCA2
VSSCA3
VSSCA4
VSSCA5
VSSCA6
VSSCA7
VSSCA8
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19
TBL1601,DDR
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16/NC
DQ17/NC
DQ18/NC
DQ19/NC
DQ20/NC
DQ21/NC
DQ22/NC
DQ23/NC
DQ24/NC
DQ25/NC
DQ26/NC
DQ27/NC
DQ28/NC
DQ29/NC
DQ30/NC
DQ31/NC
VDD1_1
VDD1_3
VDD1_5
VDD1_7
VDD1_9
VDD1_2
VDD1_4
VDD1_6
VDD1_8
VDD1_10
VDD2_1
VDD2_2
VDD2_3
VDD2_4
VDD2_5
VDD2_6
VDD2_7
VDD2_8
VDD2_9
VDD2_10
VDD2_11
VDD2_12
VDD2_13
VDD2_14
VDD2_15
VDD2_16
VDD2_17
VDD2_18
VDD2_19
VDD2_20
VDDCA1
VDDCA2
VDDCA3
VDDCA4
VDDCA5
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VREFCA
VREFDQ
M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9
M_B_DIM0_CLK1[11,17]
M_B_DIM0_CLK#1[11,17]
M_B_DIM0_CKE2[ 11,17]
M_B_DIM0_CKE3[ 11,17]
M_B_DIM0_CS#0[11,17]
M_B_DIM0_CS#1[11,17]
M_B_DQS6[11]
M_B_DQS#6[11]
M_B_DQS5[11]
M_B_DQS#5[11]
M_B_DQS4[11]
M_B_DQS#4[11]
M_B_DQS7[11]
M_B_DQS#7[11]
RES_0402_16mil
GND GND
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
ODT
ZQ0
ZQ1
NC1
NC2
NC3
P9
N9
N10
N11
M8
M9
M10
M11
F11
F10
F9
F8
E11
E10
E9
D9
T8
T9
T10
T11
R8
R9
R10
R11
C11
C10
C9
C8
B11
B10
B9
B8
A3
A4
A5
A6
A10
U3
U4
U5
U6
U10
A8
A9
D4
D5
D6
G5
H5
H6
H12
J5
J6
K5
K6
K12
L5
P4
P5
P6
U8
U9
F2
G2
H3
L2
M2
A11
C12
E8
E12
G12
H8
H9
H11
J9
J10
K8
K11
L12
N8
N12
R12
U11
H4
J11
J8
B3
B4
C4
K9
R3
3
M_B_D54
M_B_D53
M_B_D49
M_B_D48
M_B_D55
M_B_D52
M_B_D50
M_B_D51
M_B_D45
M_B_D47
M_B_D42
M_B_D46
M_B_D44
M_B_D43
M_B_D41
M_B_D40
M_B_D33
M_B_D32
M_B_D37
M_B_D36
M_B_D34
M_B_D38
M_B_D39
M_B_D35
M_B_D56
M_B_D59
M_B_D60
M_B_D62
M_B_D57
M_B_D58
M_B_D61
M_B_D63
C1760
100p 25V
CAP_0201_14mil
GND
+1P2V_DUAL
C1759
100p 25V
CAP_0201_14mil
+1P2V_DUAL
+V_VREF_CA_DIMM
+V_VREF_DQ_DIMM1
M_B_DIM0_ODT0 [11,17]M_B_DIM0_ODT0 [11,17]
ZQ1703
ZQ1704
DDR
R1703 243 RES_0402_16mil
R1704 243
TBL2301,DDR
M_B_D[39:32] [11]
M_B_D[63:56] [11]
+1P2V_DUAL
C1727
1u
6.3V
CAP_0402_22mil
RES_0402_16mil
+V_VREF_CA_DIMM +V_VREF_DQ_DIMM1
C1701
6.3V
CAP_0402_22mil
CAP_0201_14mil
C1708
1u
6.3V
CAP_0402_28mil
C1712
1u
6.3V
CAP_0402_22mil
C1720
1u
6.3V
CAP_0402_22mil
C1730
1u
6.3V
CAP_0402_22mil
47000p
GND
+1P8V_DUAL
CAP_0402_22mil
C1744
10u
6.3V
CAP_0402_22mil
CAP_0402_22mil
CAP_0402_22mil
C1731
1u
6.3V
CAP_0402_22mil
CAP_0402_28mil
C1714
1u
6.3V
C1722
1u
6.3V
C1729
1u
6.3V
CAP_0402_28mil
C1709
1u
6.3V
CAP_0201_14mil
C1743
10u
6.3V
CAP_0402_22mil
M_B_D[47:40] [11]
C1745
10u
6.3V
CAP_0402_28mil
C1719
1u
6.3V
CAP_0402_22mil
C1726
1u
6.3V
CAP_0402_22mil
C1728
1u
6.3V
CAP_0402_22mil
47000p
C1705
10u
6.3V
CAP_0402_22mil
CAP_0402_22mil
cap_0201_14mil
CAP_0402_22mil
C1713
1u
6.3V
C1721
1u
6.3V
C1736
0.1u
6.3V
C1733
1u
6.3V
CAP_0402_28mil
6.3V
2
CAP_0402_28mil
C1710
1u
6.3V
C1746
10u
6.3V
CAP_0402_22mil
CAP_0402_22mil
CAP_0402_22mil
CAP_0201_14mil
C1706
10u
6.3V
cap_0201_14mil
C1703
47000p
CAP_0402_22mil
C1715
1u
6.3V
C1723
1u
6.3V
C1737
0.1u
6.3V
C1735
1u
6.3V
1
C1764
22u
4V
+V_VDDQ_VTT
+V_VDDQ_VTT+V_VDDQ_VTT +V_VDDQ_VTT
CAP_0201_14mil
GND
C1761
100p
25V
M_B_CAA[9:0][11,17]
C1704
GND
cap_0201_14mil
GNDGNDGND
CAP_0201_14mil
C1738
0.1u
6.3V
C1742
1u
6.3V
47000p
CAP_0402_28mil
GND
CAP_0402_22mil
GND
CAP_0402_22mil
GND
6.3V
C1748
10u
6.3V
C1716
1u
6.3V
C1724
1u
6.3V
CAP_0402_22mil
M_B_CAB[9:0][11,17]
C1739
0.1u
6.3V
cap_0201_14mil
C1762
1u
6.3V
C1763
1u
6.3V
CAP_0402_22mil
GND GND
6.3V
C1707
10u
6.3V
CAP_0402_28mil
GND
C1711
1u
6.3V
GND
C1747
10u
6.3V
CAP_0402_28mil
C1718
1u
6.3V
CAP_0402_22mil
C1725
1u
6.3V
CAP_0402_22mil
CAP_0402_22mil
M_B_CAA0
M_B_CAA1
M_B_CAA2
M_B_CAA3
M_B_CAA4
M_B_CAA5
M_B_CAA6
M_B_CAA7
M_B_CAA8
M_B_CAA9
M_B_CAB0
M_B_CAB1
M_B_CAB2
M_B_CAB3
M_B_CAB4
M_B_CAB5
M_B_CAB6
M_B_CAB7
M_B_CAB8
M_B_CAB9
M_B_DIM0_ODT0[11,17]
M_B_DIM0_CS#0[11,17]
M_B_DIM0_CS#1[11,17]
M_B_DIM0_CKE0[ 11,17]
M_B_DIM0_CKE1[ 11,17]
M_B_DIM0_CKE2[ 11,17]
M_B_DIM0_CKE3[ 11,17]
M_B_DIM0_CLK0[11,17]
M_B_DIM0_CLK#0[11,17]
M_B_DIM0_CLK1[11,17]
M_B_DIM0_CLK#1[11,17]
cap_0603_40mil
R1718 68 5% RES_0201_12mil
R1705 68 5% RES_0201_12mil
R1706 68 5% RES_0201_12mil
R1707 68 5% RES_0201_12mil
R1708 68 5% RES_0201_12mil
R1709 68 5% RES_0201_12mil
R1710 68 5% RES_0201_12milC1702
R1711 68 5% RES_0201_12mil
R1712 68 5% RES_0201_12mil
R1713 68 5% RES_0201_12mil
R1714 68 5% RES_0201_12mil
R1716 68 5% RES_0201_12mil
R1715 68 5% RES_0201_12mil
R1717 68 5% RES_0201_12mil
R1719 68 5% RES_0201_12mil
R1720 68 5% RES_0201_12mil
R1721 68 5% RES_0201_12mil
R1735 68 5% RES_0201_12mil
R1722 68 5% RES_0201_12mil
R1723 68 5% RES_0201_12mil
R1724 80.6 RES_0201_12MIL
R1725 80.6 RES_0201_12MIL
R1726 80.6 RES_0201_12MIL
R1727 80.6 RES_0201_12MIL
R1728 80.6 RES_0201_12MIL
R1729 80.6 RES_0201_12MIL
R1730 80.6 RES_0201_12MIL
R1731 37.4 res_0201_12mil
R1732 37.4 res_0201_12mil
R1733 37.4 res_0201_12mil
R1734 37.4 res_0201_12mil
C1751
22u
4V
cap_0603_40mil
EV1.9
A A
LPDDR3(2)_MEMORY DOWN
LPDDR3(2)_MEMORY DOWN
LPDDR3(2)_MEMORY DOWN
Title:
Title:
Title:
Surface
Surface
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
C
C
C
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Engineer:
Engineer:
Engineer:
1
Surface
1.90.2
1.90.2
17 76Monday, May 11, 2015
17 76Monday, May 11, 2015
17 76Monday, May 11, 2015
1.90.2
5
4
3
2
1
PRIMARY XDP connector
CFG3[15,18]
+1VSB
D D
DB,XDP
R1838 0
RES_0201_12mil
+1VSB_XDP +3P3VSB
DNP,XDP
C1803
1u
CAP_0201_14mil
C C
RSMRST#[22,36]
PCH_PWRBTN#[22]
PWR_SW_N[30,32,33]
SPI0_MOSI_XDP[21] PCH_SYS_RST# [22]
B B
R1842 1KDB,XDP RES_0201_12mil
R1807 0DB,XDP
R1804 0DNP,XDP
R1846 0DB,XDP
DB,XDP
PC1804
0.1u
6.3V
cap_0201_14mil
GND GND
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
DB,XDP
PC1805
0.1u
6.3V
cap_0201_14mil
6.3V
GND
PCH_JTAG_TCK[10]
XDP_TCK[10]
PCH_JTAGX[10]
+1VSB_XDP
DB,XDP
R1826
1.5K
RES_0201_12mil
PM_RSMRST_PWRGD_XDP
PM_PWRBTN#_XDP
CFG0[15,18]
R1821 0DB,XDP
RES_0201_12mil
R1853 0DNP,XDP
R1811 0DB,XDP
XDP_PREQ#[24]
XDP_PRDY#[24]
XDP_BPM0[10]
XDP_BPM1[10]
R1843 0DNP,XDP
SMBDATA[21]
SMBCLK[21]
RES_0201_12mil
RES_0201_12mil
CFG0[15,18]
CFG1[15]
CFG2[15]
CFG3[15,18]
CFG4[15]
CFG5[15]
CFG6[15]
CFG7[15]
+1VSB_XDP
DNP,XDP
R1803 49.9
XDP_MOSI_R
RES_0201_12mil
XDP_TCK1
RES_0201_12mil
XDP_CFG0
GND
XDP_SPI0_IO2[21]
ROUTE WITH MINIMAL STUB WITH RESPECT TO CFG<3>
DB,XDP
RES_0201_12mil
R1840 0
DB,XDP
J1801
B2B 60P
conn_b2b-r_60_4mtg_14p2x2p54xp88_p4mm
RECEPTACLE
1
XDP_PIN1
GND GND
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
1
3
3
5
5
7
7
9
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
MTG1
MTG3
DB,XDP
R1841
1K
RES_0201_12mil
X869110-001
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
XDP_TDI_R
56
56
58
58
XDP_PIN60
60
60
MTG2
MTG4
R1845 0DB,XDP
62
64
RES_0201_12mil
R1854 0DNP,XDP
RES_0201_12mil
CLK_XDP_R_DP
CLK_XDP_R_DN
XDP_RST#_R
XDP_DBRESET#_R
XDP_TDO_BUF
GND
CFG17 [15]
CFG16 [15]
CFG8 [15]
CFG9 [15]
CFG10 [15]
CFG11 [15]
CFG19 [15]
CFG18 [15]
CFG12 [15]
CFG13 [15]
CFG14 [15]
CFG15 [15]
+1VSB_XDP
+1VSB_XDP
DB,XDP
RES_0201_12mil
R1844 1K
+3P3V
+VCCSTG
DNP,XDP
R1825
49.9
DB,XDP
RES_0201_12mil
R1823 1K
R1805 0DB,XDP
R1806 0DB,XDP
R1837 0DB,XDP
R1808 1KDNP,XDP RES_0201_12mil
R1810 0DB,XDP
R1809 0DB,XDP
R1849 0DB,XDP
R1851 0DB,XDP
DB,XDP
C1801
0.01u
10V
CAP_0201_14mil
GND
R1822 0DB,XDP
RES_0201_12mil
R1848 0DB,XDP
RES_0201_12mil
R1847 0DB,XDP
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
Place R1825 within 1100mil from CPU
CLK_XDP_DP [20]
CLK_XDP_DN [20]
ITP_PMODE [15]
PLT_RST#_BUF [22,36,38,43,75]
XDP_TRST#_BUF [10]
XDP_TDO [10]
XDP_TRST# [10]
XDP_TDI [10]
XDP_TMS [10]
DNP,XDP
R1852
0
RES_0201_12mil
PCH_JTAG_TDI [10]
PCH_JTAG_TMS [10]
PCH_JTAG_TDO [10]
A A
XDP
XDP
Title:
Title:
Title:
Microsoft
Microsoft
For the signals only go to XDP, the 0R should be close to XDP connector.
For the signals to both XDP and target circuit, the option resistor locaction should follow the target signal routing.
5
4
3
2
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
te: Sheet of
Date: Sheet of
Date: Sheet of
Da
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Engineer:
Engineer:
Engineer:
XDP
Surface
Surface
Surface
1
1.90.2
1.90.2
1.90.2
18 76Monday, May 11, 2015
18 76Monday, May 11, 2015
18 76Monday, May 11, 2015
5
4
3
2
1
LPDDR3 Vref
M3: CPU driven VREF path is stuffed be default.
M1:
VREF_DQ driven by a Voltage Divider Network during Processor power-off
D D
+1P2V_DUAL
R1901
8.2K
res_0201_12mil
DIMM0_VREF_DQ[11] DIMM_VREF_CA [11]
EV1.9
WAS:X819201-001
C C
DIMM1_VREF_DQ[11]
EV1.9
WAS:X819201-001
N1902
B B
R1903 10
C1901
0.022u
cap_0201_14mil
R1904
24.9
RES_0402_16mil
C1902
0.022u
cap_0201_14mil
R1908
24.9
RES_0402_16mil
RES_0402_14mil
16V
R1907 10
RES_0402_14mil
16V
R1902
8.2K
res_0201_12mil
GND
+1P2V_DUAL
R1906
8.2K
res_0201_12mil
R1905
8.2K
res_0201_12mil
+V_VREF_DQ_DIMM0
DNP,DDR
R1913
0
RES_0201_12mil
+V_VREF_DQ_DIMM1
+V_VREF_CA_DIMM
+1P2V_DUAL
R1909
8.2K
res_0201_12mil
R1910
8.2K
res_0201_12mil
GND
R1911 5.1
res_0201_12mil
C1903
0.022u
16V
cap_0201_14mil
DIMM_VREF_CA_CDIMM0_VREF_DQ_C
R1912
24.9
RES_0402_16mil
EV1.9
:X819201-001
WAS
Intel 0203
M3+M1: Default Recommendation
GND
+VDDQ_VREF
A A
5
4
3
DNP,DDR
R1914 0
RES_0402_16mil
DNP,DDR
R1915 0
RES_0402_16mil
DNP,DDR
R1916 0
RES_0402_16mil
+V_VREF_DQ_DIMM0
+V_VREF_CA_DIMM
+V_VREF_DQ_DIMM1
LPDDR3(3)_CA/DQ Voltage
LPDDR3(3)_CA/DQ Voltage
Title:
Title:
Title:
Microsoft
Microsoft
Microsoft
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
te: Sheet of
Date: Sheet of
Date: Sheet of
2
Da
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Engineer:
Engineer:
Engineer:
LPDDR3(3)_CA/DQ Voltage
Surface
Surface
Surface
19 76Monday, May 11, 2015
19 76Monday, May 11, 2015
1
19 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
4
3
2
1
+3P3V
D D
SSD_PCIECLK_REQ_N[43]
PCIE_WIFI_CLKREQ_N[50]
C C
AZ_SYNC_1[40]
AZ_BITCLK_1[40]
AZ_SDATA_OUT_1[40]
AZ_SDATA_IN0[40]
AZ_RST#_1[40]
B B
DNP,CPU
R2003
RES_0201_12mil
100K
to EC PIN D9
A A
EC_UEFI_TOP_SWAP[36]
R2004
RES_0201_12mil
100K
G
R2052 10K
R2056 33
+3P3V
R2006
1K
RES_0201_12mil
TOP_SWAP_1A
D
DNP,CPU
RUM002N02GT2L
SOT-VMT3_1p2xp8xp5_p4mm
S
R2048 10K
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
HDA_SDO:
1.Flash descriptor security:
Sampled Low: in effect.
Sampled High: override
2.HDA_SDOwhich sample high on
the rising edge of PWROK
Will also disable Intel ME.
U2001A
SN74LVC2G66YZPR
BGA8_P9X1P9xp5_p5mm
A1
1A
B2
EN
PCIECLK_SSD_DN[43]
PCIE_WIFI_RCLK_DN[50]
PCIE_WIFI_RCLK_DP[50]
R2020 33RES_0201_12mil
R2053 33RES_0201_12mil
R2054 33RES_0201_12mil
A2
VCC
B1
1B
D1
GND
TOP_SWAP_2A
TOP_SWAP_EN#
DNP,CPU
R2008
100K
RES_0201_12mil
+3V_EC+3V_EC
C2005
25V
0.1u
CAP_0402_22mil
TOP_SWAP
D2
C1
STP_A16OVR:
A16 swap override Strap/
Top-Block swap override jumper
High=Enabled A16 swap override/
Top-Block swap override
Low=Default
5
4
U1001J
SKL_
ULT_1356BGA_R1
356_47x30_42x24x1p27mm-SKL
bga1
D42
CLKOUT_PCIE_N0
C42
CLKOUT_PCIE_P0
AR10
GPP_B5/SRCCLKREQ0#
B42
CLKOUT_PCIE_N1
A42
CLKOUT_PCIE_P1
AT7
GPP_B6/SRCCLKREQ1#
D41
CLKOUT_PCIE_N2
C41
CLKOUT_PCIE_P2
AT8
GPP_B7/SRCCLKREQ2#
D40
CLKOUT_PCIE_N3
C40
CLKOUT_PCIE_P3
AT10
GPP_B8/SRCCLKREQ3#
B40
CLKOUT_PCIE_N4
A40
CLKOUT_PCIE_P4
AU8
GPP_B9/SRCCLKREQ4#
E40
CLKOUT_PCIE_N5
E38
CLKOUT_PCIE_P5
AU7
GPP_B10/SRCCLKREQ5#
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
DNP,CPU
R2009 1K
RES_0201_12mil
HDA_SYNC_R
INT. PD
U2001B
SN74LVC2G66YZPR
BGA8_P9X1P9xp5_p5mm
2A
2EN
HDA_BCLK_R
HDA_SDO_R
was HDA_SDI0_R
HDA_RST#_R
DMIC1_CLK[20,32,40,42]
DMIC1_DATA[20,32,40,42]
DMIC2_CLK_XDP[20]
DMIC2_DATA_XDP[20]
C2
2B
INT. PD
SKL_ULT
CLOCK SIGNALS
R2007
49.9K
RES_0201_12milQ2001
CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P
GPD8/SUSCLK
XTAL24_IN
XTAL24_OUT
XCLK_BIASREF
SRTCRST#
10 OF 20
U1001G
SKL_
ULT_1356BGA_R1
356_47x30_42x24x1p27mm-SKL
bga1
AUDIO
BA22
HDA_SYNC/I2S0_SFRM
AY22
HDA_BLK/I2S0_SCLK
BB22
HDA_SDO/I2S0_TXD
BA21
HDA_SDI0/I2S0_RXD
AY21
HDA_SDI1/I2S1_RXD
AW22
HDA_RST#/I2S1_SCLK
J5
GPP_D23/I2S_MCLK
AY20
I2S1_SFRM
AW20
I2S1_TXD
AK7
GPP_F1/I2S2_SFRM
AK6
GPP_F0/I2S2_SCLK
AK9
GPP_F2/I2S2_TXD
AK10
GPP_F3/I2S2_RXD
H5
GPP_D19/DMIC_CLK0
D7
GPP_D20/DMIC_DATA0
D8
GPP_D17/DMIC_CLK1
C8
GPP_D18/DMIC_DATA1
AW5
GPP_B14/SPKR
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
DMIC1_CLK[20,32,40,42]
DMIC1_DATA[20,32,40,42]
TPS0P35
TPS0P35
TPS0P35
TPS0P35
3
RTCX1
RTCX2
RTCRST#
XDP_TP2001
XDP_TP2002
XDP_TP2003
XDP_TP2004
F43
E43
BA17
E37
E35
E42
AM18
AM20
AN18
AM16
SKL_ULT
7 OF 20
CLK_XDP_DN [18]
CLK_XDP_DP [18]PCIECLK_SSD_DP[43]
WIFI_32K_CLK_R
XTAL_24M_IN
XTAL_24M_OUT
XCLK_BIASREF
RTC_X1
RTC_X2
SRTC_RST# [20]
RTC_RST# [20,36]
EV1.9 WAS INSTALL
R2010 33
DNP,CPU
RES_0201_12mil
R2005 0
RES_0201_12mil
C2001
EV1.9
CHG MSPN
SDIO/SDXC
GPP_G0/SD_CMD
GPP_G1/SD_DATA0
GPP_G2/SD_DATA1
GPP_G3/SD_DATA2
GPP_G4/SD_DATA3
GPP_G5/SD_CD#
GPP_G6/SD_CLK
GPP_G7/SD_WP
GPP_A17/SD_PWR_EN#/ISH_GP7
GPP_A16/SD_1P8_SEL
DMIC2_CLK_XDP [20]
DMIC2_DATA_XDP [20]
15p
CAP_0201_14mil
2%
SD_RCOMP
GPP_F23
2
WIFI_32K_CLK [50]
EV1.9
CHG MSPN
R2001 10M
RES_0201_12mil
CTAL_1
25V
AB11
AB13
AB12
W12
W11
W10
W8
W7
BA9
BB9
AB7
AF13
xtal_3p2x1p5xp9_2p5mm
No SD support
SD_RCOMP
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
te: Sheet of
Date: Sheet of
Date: Sheet of
Da
+VCC_RTC+3P3VSB
XTAL_24M_IN
XTAL_24M_OUT
CAP_0201_14mil
21
X2001
32.7 KHz
R2021 20K
R2002 20K
R2080
200
RES_0201_12mil
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
R2035 1M
RES_0201_12mil
xtal_4_3p2x2p5xp8_2p2x1p7mm
C2007
50V
10p
this need 2.71K 0.5% resistor.
the power rail connector
to the rail of VCCCLK5
C2002
15p
25V
CAP_0201_14mil
2%
RES_0201_12mil
RES_0201_12mil
Title:
Title:
Title:
Engineer:
Engineer:
Engineer:
X200224MHZ
3 1
GND
R2036 2.7K
DNP,CPU
R2022
60.4
res_0201_12mil
EV1.9
CHG MSPN
SRTC_RST# [20]
C2003
6.3V
1u
CAP_0402_22mil
RTC_RST# [20,36]
C2004
6.3V
1u
CAP_0402_22mil
PCH(1)_SD,HDA,RTC,CLK
PCH(1)_SD,HDA,RTC,CLK
PCH(1)_SD,HDA,RTC,CLK
Surface
Surface
Surface
1
EV1.9
24
WAS
:X879083-001
C2006
10p
CAP_0201_14mil
1%
RES_0402_16MIL
20 76Monday, May 11, 2015
20 76Monday, May 11, 2015
20 76Monday, May 11, 2015
50V
+VCCCLK5_R
1.90.2
1.90.2
1.90.2
5
D D
Connected to device.
Default : Clock free run. (PD 10K).
Reserver 10K PU for power saving purpose.
XDP_SPI0_IO2[18]
SPI0_MOSI_XDP[18]
R2133
Close to PCH
SPI_CLK[37]
SPI_SO[37]
SPI_SI[37]
SPI_WP_IO2[37]
C C
B B
SPI_HOLD#_IO3[37]
SPI_CS#0[37]
TS_SPI_CLK[30]
TS_SPI_MISO[30]
TS_SPI_MOSI[30]
CAM_F_PWR_DN_N[25,53,54]
CAM_R_PWR_DN_N[25,53,54]
TS_SPI_CS_N[30]
RC_IN#[36]
R2136 15
R2135 15
R2139 15
R2137 15
R2138 15
R2141 15
EV1.9 ADD
R2109 15
R2105 15
R2101 15
R2111 330 res_0201_12milDNP,CPU
R2108 330 res_0201_12milDNP,CPU
R2112 15
DNP,CPU
C2105
CAP_0201_14mil
100p
RES_0201_12mil
PCH_SERIRQ[36,38]
1K
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
RES_0201_12mil
R2134
1K
RES_0201_12mil
SPI_CLK_R
SPI_SO_R
SPI_SI_R
SPI_WP_IO2_R
SPI_HOLD#_IO3_R
SPI_CS#0_R
TS_SPI_CLK_R
TS_SPI_MISO_R
TS_SPI_MOSI_R
GPP_D21_R
GPP_D22_R
TS_SPI_CS_N_R
+3P3V
R2132
8.2K
res_0201_12mil
Serial Interrupt Request
4
U1001E
SKL_
ULT_1356BGA_R1
PCB Footprint = bga1356_47x30_42x24x1p27mm-SKL
SPI - FLASH
AV2
SPI0_CLK
AW3
SPI0_MISO
AV3
SPI0_MOSI
AW2
SPI0_IO2
AU4
SPI0_IO3
AU3
SPI0_CS0#
AU2
SPI0_CS1#
AU1
SPI0_CS2#
SPI - TOUCH
M2
GPP_D1/SPI1_CLK
M3
GPP_D2/SPI1_MISO
J4
GPP_D3/SPI1_MOSI
V1
GPP_D21/SPI1_IO2
V2
GPP_D22/SPI1_IO3
M1
GPP_D0/SPI1_CS#
C LINK
G3
CL_CLK
G2
CL_DATA
G1
CL_RST#
AW13
GPP_A0/RCIN#
AY11
GPP_A6/SERIRQ
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
D-OPT = TBL1001,CPU
BUIL
SKL_ULT
LPC
5 OF 20
3
SMBUS, SMLINK
1
GPP_B23/SML1ALERT#/PCHHOT#
GPP_A5/LFRAME#/ESPI_CS#
GPP_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_C0/SMBCLK
GPP_C1/SMBDATA
GPP_C2/SMBALERT#
GPP_C3/SML0CLK
GPP_C4/SML0DATA
GPP_C5/SML0ALERT#
GPP_C6/SML1CLK
GPP_C7/SML1DATA
GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3
GPP_A10/CLKOUT_LPC1
GPP_A8/CLKRUN#
R7
R8
R10
R9
W2
W1
W3
V3
AM7
AY13
BA13
BB13
AY12
BA12
BA11
AW9
AY9
AW11
R2102
1K
RES_0201_12mil
INT. PD
INT
. PD
INT. PD
SUS_STAT#_R
2
R2103
1K
RES_0201_12mil
SMBALERT#
SML0CLK
SML0DAT
was SMB0ALERT#
SMB1ALERT#
CK_24M_EC_R
CK_24M_TPM_R
+3P3V
R2131
8.2K
res_0201_12mil
R2107
1K
RES_0201_12mil
TP2128
PM_CLKRUN# [36,38]
RES_0201_12mil
SP_TP_SMDp58mm
R2110
1K
LAD0 [36,38]
LAD1 [36,38]
LAD2 [36,38]
LAD3 [36,38]
LFRAME# [36,38]
RES_0201_12mil
R2104
1K
+3P3VSB
R2106
1K
RES_0201_12mil
R2140 150K
RES_0201_12mil
EV1.9
WAS 0402
R2123 22RES_0201_12mil 5%
R2129 22RES_0201_12mil 5%
DNP,CPU
C2103
10p
CAP_0201_14mil
50V
1
TP2101
SP_TP_SMDp58mm
SD_CD#_PCH [48]
SML1_PCH_CLK [35]
SML1_PCH_DATA [35]
+3P3VSB
CK_24M_EC [36]
CK_24M_TPM [38]
DNP,CPU
C2104
50V
10p
CAP_0201_14mil
SMBCLK [18]
SMBDATA [18]
GPP_C2/SMBALERT#
0 Disable ME crypto TLS
Default
A A
5
4
1
Enable ME crypto TLS
PCH(2)_CLK,SMB,LPC,SPI
PCH(2)_CLK,SMB,LPC,SPI
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
B
B
B
Date: Sheet of
Date: Sheet of
3
2
Date: Sheet of
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
Engineer:
PCH(2)_CLK,SMB,LPC,SPI
Surface
Surface
Surface
21 76Monday, May 11, 2015
21 76Monday, May 11, 2015
1
21 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
4
3
2
1
+3P3V
C2202 0.1u
cap_0201_14mil
D D
C C
PLT_RST#_BUF[18,36,38,43,75]
EC_RST#[33,36]
PCH_SYS_RST#[18]
RSMRST#[18,36]
PCH_DPWROK_R
SYS_PWROK[36]
6.3V
R2224
49.9K
RES_0201_12mil
DNP,CPU
R2218 0
RES_0201_12mil
EV1.9 WAS:0
R2228 0
RES_0201_12mil
U2202
SN74AUP1G08DRYR
sot886_1p45x1xp6_p5mm
6
VCC
5
NC
Y
+3P3V
R2225
10K
RES_0201_12mil
CPU
R2231 49.9
RES_0201_12mil
DNP,CPU
R2239 0
RES_0201_12mil
PLT_RST#[33]
1
A
2
B
34
GND
DNP,CPU
R2223 0
RES_0201_12mil
VCCST_PWRGD[75]
PCH_SYS_RST#
R2252 100K
RES_0201_12mil
R2251
49.9K
RES_0201_12mil
SP_TP_SMDp58mm
R2257 60.4
RES_0402_16mil
TP2211
EV1.9 ADD
PROCPWRGD
VCCST_PWRGD_R
SYS_PWROK_R
PCH_DPWROK_R
SP_TP_SMDp58mm
C2203
470p
25V
CAP_0201_14mil
PM_RSMRST_R
PM_PCH_PWROK_R
WAKE#
TP2216
R2259 20K
LANPHYPC
RES_0201_12mil
U1001K
SKL_
ULT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
SYSTEM POWER MANAGEMENT
AN10
GPP_B13/PLTRST#
B5
SYS_RESET#
AY17
RSMRST#
A68
PROCPWRGD
B65
VCCST_PWRGD
B6
SYS_PWROK
BA20
PCH_PWROK
BB20
DSW_PWROK
AR13
GPP_A13/SUSWARN#/SUSPWRDNACK
AP11
GPP_A15/SUSACK#
BB15
WAKE#
AM15
GPD2/LAN_WAKE#
AW17
GPD11/LANPHYPC
AT15
GPD7/RSVD
REV = JKS
Source Package = SKL_ULT_1356BGA_R1
BUILD-OPT = TBL1001,CPU
SKL_ULT
11 OF 20
GPP_B12/SLP_S0#
GPD4/SLP_S3#
GPD5/SLP_S4#
GPD10/SLP_S5#
SLP_SUS#
SLP_LAN#
GPD9/SLP_WLAN#
GPD6/SLP_A#
GPD3/PWRBTN#
GPD1/ACPRESENT
GPD0/BATLOW#
GPP_A11/PME#
INTRUDER#
GPP_B11/EXT_PWR_GATE#
GPP_B2/VRALERT#
AT11
AP15
BA16
AY16
AN15
AW15
BB17
AN16
BA15
AY15
AU13
AU11
AP16
AM10
AM11
SLP_S5#
SLP_LAN#
SLP_WLAN#
SLP_A#
AC_PRESENT_R
BATLOW#_R
PME#
INTRUDER#
VRALERT#_R
R2232 0
SP_TP_SMDp58mm
TP2208 SP_TP_SMDp58mm
TP2202 SP_TP_SMDp58mm
SLP_S0# [28,56,60,61]
PM_SUSB# [33,36]
TP2217 SP_TP_SMDp58mm
TP2219
SP_TP_SMDp58mm
TP2203
SP_TP_SMDp58mm
TP2218SP_TP_SMDp58mm
RES_0201_12mil
TP2209
+3P3VSB+VCCDSW
R2258
10K
RES_0201_12mil
PM_SUSC# [33,36]
SLP_SUS# [36]
PCH_PWRBTN# [18]
SB_PWRBTN# [33,36]
R2256 1M
RES_0201_12mil
MPHY_PWREN [61]
for VR hot indicator (may not be used)
+VCC_RTC
+VCCDSW
+VCCDSW
DNP,CPU
R2226 10K
R2254 10K
RES_0201_12mil
R2220
10K
RES_0201_12mil
RES_0201_12mil
PM_PCH_PWROK[36]
PCH_DPWROK[36]
+3P3VSB
DNP,CPU
R2203
10K
RES_0201_12mil
B B
SUSWARN#
If SUSWARN #/SUS_ACK # handshake
is not used, these signals are tied on the board
R2229 0
RES_0201_12mil
R2255 100K
RES_0201_12mil
R2235 0
RES_0201_12mil
R2253 100K
RES_0201_12mil
CPU
R2241 49.9
RES_0201_12mil
+VCCDSW
R2212
10K
RES_0201_12mil
PCH_DPWROK_R
SUSACK#
A A
PCH(3)_SYS PWR CONTR
PCH(3)_SYS PWR CONTR
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
e: Sheet of
Date: Sheet of
Date: Sheet of
5
4
3
2
Dat
Engineer:
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
PCH(3)_SYS PWR CONTR
Surface
Surface
Surface
22 76Monday, May 11, 2015
22 76Monday, May 11, 2015
1
22 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2
5
Processor
ID
Rev
Speed
0 = R3643
0 = R3641
0 = R2324
0 = R2301
R3816
R3814
0 = R2310
0 = R2309
0 = R2308
0 = R2302
0 = R2316
0 = R2317
0 = R2314
0 = R2313
0 = R2312
R1704
NationZ =
1
POP
EC Processor ID
TPM
PCH Board ID[3:0]
Manufacturer
RAM Size & Calibration
4
3
2
1
PCH
EC Board
DRAM
RAM
Rev 4
Signal EC_ID1 ED_ID0 PCB_ID5 PCB_ID4 R3619 PCB_ID3 PCB_ID2 PCB_ID1 PCB_ID0 MEM_ID1 MEM_ID0 MEM_ID4 MEM_ID3 MEM_ID2 ZQ1
D D
R3813
1 = R3642
1 = R3640
1 = R2323
1 = R2303
R3815
1 = R2307
1 = R2305
1 = R2306
1 = R2304
1 = R2315
1 = R2318
1 = R2321
1 = R2319
1 = R2320
1600
U22 = 0
U23E = 1
Y = 0
S = 1
EV 0.9 80.6 Ω 0 0 0 0
C C
U22 = 0
U23E=0
Y = 1
S = 1
U = 0
Y = 1
Infineon
= 0
Nation Z
= 1
Infineon
= DNP
POP
Infineon
= POP
NationZ
=DNP
Hynix = 0
Samsung
= 0
Hynix = 0
Samsung
= 1
LPDDR3 =
0
1866
LPDDR3 =
4GB = 0
8GB = 0
16GB = 1
4 GB = 0
8 GB = 1
16 GB = 0
R1602
R1604
R1702
4GB =
DNP
8GB =
POP
16GB =
EV 1.0 169 Ω 0 0 0 1
EV 1.5 698 Ω 0 0 1 0
EV 1.9 909 Ω 0 0 1 1
TBL2301
+1P8VSB +1P8VSB +1P8VSB+1P8VSB +1P8VSB
U1001I
SKL_
ULT_1356BGA_R1
bga1356_47x30_42x24x1p27mm-SKL
CSI-2
B B
A A
CSI2_R0_DN[53]
CSI2_R0_DP[53]
CSI2_R1_DN[53]
CSI2_R1_DP[53]
CSI2_R2_DN[53]
CSI2_R2_DP[53]
CSI2_R3_DN[53]
CSI2_R3_DP[53]
CSI2_F4_DN[54]
CSI2_F4_DP[54]
CSI2_F5_DN[54]
CSI2_F5_DP[54]
CSI2_IRCAM8_DN[49]
CSI2_IRCAM8_DP[49]
A36
CSI2_DN0
B36
CSI2_DP0
C38
CSI2_DN1
D38
CSI2_DP1
C36
CSI2_DN2
D36
CSI2_DP2
A38
CSI2_DN3
B38
CSI2_DP3
C31
CSI2_DN4
D31
CSI2_DP4
C33
CSI2_DN5
D33
CSI2_DP5
A31
CSI2_DN6
B31
CSI2_DP6
A33
CSI2_DN7
B33
CSI2_DP7
A29
CSI2_DN8
B29
CSI2_DP8
C28
CSI2_DN9
D28
CSI2_DP9
A27
CSI2_DN10
B27
CSI2_DP10
C27
CSI2_DN11
D27
CSI2_DP11
REV = 1
BUILD-OPT = TBL1001,CPU
ce Package = SKL_ULT_1356BGA_R1
Sour
SKL_ULT
9 OF 20
CSI2_CLKN0
CSI2_CLKP0
CSI2_CLKN1
CSI2_CLKP1
CSI2_CLKN2
CSI2_CLKP2
CSI2_CLKN3
CSI2_CLKP3
CSI2_COMP
GPP_D4/FLASHTRIG
EMMC
GPP_F13/EMMC_DATA0
GPP_F14/EMMC_DATA1
GPP_F15/EMMC_DATA2
GPP_F16/EMMC_DATA3
GPP_F17/EMMC_DATA4
GPP_F18/EMMC_DATA5
GPP_F19/EMMC_DATA6
GPP_F20/EMMC_DATA7
GPP_F21/EMMC_RCLK
GPP_F22/EMMC_CLK
GPP_F12/EMMC_CMD
EMMC_RCOMP
C37
D37
C32
D32
C29
D29
B26
A26
E13
B7
AP2
AP1
AP3
AN3
AN1
AN2
AM4
AM1
AM2
AM3
AP4
AT1
CSI2_COMP
MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3
MEM_ID4
PCB_ID4
PCB_ID0
PCB_ID1
PCB_ID2
PCB_ID3
PCB_ID5
EMMC_RCOMP_R
R2311
200
RES_0201_12mil
1%
CSI2_R0_CLK_DN [53]
CSI2_R0_CLK_DP [53]
CSI2_F1_CLK_DN [54]
CSI2_F1_CLK_DP [54]
CSI2_CLK2_IRCAM_DN [49]
CSI2_CLK2_IRCAM_DP [49]
R2322 100
RES_0201_12mil
MTP2301
SP_TP_SMDp58mm
RTD3_CAM_PWREN [25,52]
MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3
MEM_ID4
5 4 3 2 1 0
+1P8VSB
TBL2301,CPU
R2318
10K
RES_0201_12mil
TBL2301,CPU
R2317
10K
RES_0201_12mil
DNP,CPU
R2323
10K
RES_0201_12mil
CPU
R2324
10K
RES_0201_12mil
+1P8VSB +1P8VSB+1P8VSB +1P8VSB+1P8VSB
TBL2301,CPU
R2315
10K
RES_0201_12mil
TBL2301,CPU
R2316
10K
RES_0201_12mil
DNP,CPU
R2303
10K
RES_0201_12mil
CPU
R2301
10K
RES_0201_12mil
TBL2301,CPU
R2320
10K
RES_0201_12mil
DNP,CPU
R2307
10K
RES_0201_12mil
CPU
R2310
10K
RES_0201_12mil
TBL2301,CPU
R2312
10K
RES_0201_12mil
DNP,CPU
R2305
10K
RES_0201_12mil
CPU
R2309
10K
RES_0201_12mil
TBL2301,CPU
R2319
10K
RES_0201_12mil
TBL2301,CPU
R2313
10K
RES_0201_12mil
CPU
R2306
10K
RES_0201_12mil
DNP,CPU
R2308
10K
RES_0201_12mil
TBL2301,CPU
R2321
10K
RES_0201_12mil
TBL2301,CPU
R2314
10K
RES_0201_12mil
CPU
R2304
10K
RES_0201_12mil
EV1.9 WAS: 0b0_0010
DNP,CPU
R2302
10K
RES_0201_12mil
PCH(4)_CCI, HWID
PCH(4)_CCI, HWID
Title:
Title:
Title:
Engineer:
Engineer:
Size Project Name Rev
Size Project Name Rev
Size Project Name Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
5
4
3
2
Dat
U -- EV 1.90
U -- EV 1.90
U -- EV 1.90
e: Sheet of
Engineer:
PCH(4)_CCI, HWID
Surface
Surface
Surface
23 76Monday, May 11, 2015
23 76Monday, May 11, 2015
1
23 76Monday, May 11, 2015
1.90.2
1.90.2
1.90.2