Microchip Technology Inc PIC16C62B-20I-SO, PIC16C62B-20I-SP, PIC16C72A-04I-SO, PIC16C72A-20-SO, PIC16C72A-20I-SO Datasheet

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

1998 Microchip Technology Inc.

Preliminary

DS35008A-page 1

Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 2K x 14 words of Program Memory, 128 x 8 bytes of Data Memory (RAM)

• Interrupt capability (up to 7 internal/external interrupt sources)

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Brown-out detection circuitry for Brown-out Reset (BOR)

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• In-Circuit Serial Programming 

• Wide operating voltage range: 2.5V to 5.5V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temperature ranges

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

- 22.5 µ A typical @ 3V, 32 kHz

- < 1 µ A typical standby current

Pin Diagram

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Capture, Compare, PWM module

• Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM maximum resolution is 10-bit

• 8-bit multi-channel Analog-to-Digital converter

• Synchronous Serial Port (SSP) with Enhanced SPI



and I



PIC16C72A

MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI RC2/CCP1

RC3/SCK/SCL

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA

• 1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SDIP, SOIC, SSOP, Windowed CERDIP

PIC16C62B/72A

28-Pin 8-Bit CMOS Microcontrollers

PIC16C62B/72A

DS35008A-page 2

Preliminary



1998 Microchip Technology Inc.

Pin Diagrams

PIC16C62B

MCLR/VPP

RA0 RA1 RA2 RA3

RA4/T0CKI

RA5/SS

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA

• 1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SDIP, SOIC, SSOP, Windowed CERDIP

Key Features

PICmicro™ Mid-Range Reference Manual

(DS33023)

PIC16C62B PIC16C72A

Operating Frequency DC - 20 MHz DC - 20 MHz Resets (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST) Program Memory (14-bit words) 2K 2K Data Memory (bytes) 128 128 Interrupts 6 7 I/O Ports Ports A,B,C Ports A,B,C Timers 3 3 Capture/Compare/PWM modules 1 1 Serial Communications SSP SSP 8-bit Analog-to-Digital Module — 5 input channels

PIC16C62B/72A



1998 Microchip Technology Inc.

Preliminary

DS35008A-page 3

Table of Contents

1.0 Device Overview....................................................................................................................................................5

2.0 Memory Organization............................................................................................................................................7

3.0 I/O Ports .............................................................................................................................................................. 19

4.0 Timer0 Module.....................................................................................................................................................25

5.0 Timer1 Module.....................................................................................................................................................27

6.0 Timer2 Module.....................................................................................................................................................31

7.0 Capture/Compare/PWM (CCP) Module(s)..........................................................................................................33

8.0 Synchronous Serial Port (SSP) Module .............................................................................................................. 39

9.0 Analog-to-Digital Converter (A/D) Module...........................................................................................................49

10.0 Special Features of the CPU...............................................................................................................................55

11.0 Instruction Set Summary .....................................................................................................................................69

12.0 Development Support..........................................................................................................................................71

13.0 Electrical Characteristics .....................................................................................................................................75

14.0 DC and AC Characteristics Graphs and Tables..................................................................................................95

15.0 Packaging Information.........................................................................................................................................97

Appendix A: Revision History.....................................................................................................................................103

Appendix B: Conversion Considerations...................................................................................................................103

Appendix C: Migration from Base-line to Mid-Range Devices...................................................................................104

Index ........................................................................................................................................................................... 105

On-Line Support.......................................................................................................................................................... 109

Reader Response.......................................................................................................................................................110

PIC16C62B/72A Product Identification System..........................................................................................................111

To Our Valued Customers

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please check our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its liter ature number found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.

Errata

An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended workarounds. As de vice/documentation issues become known to us , we will publish an err ata sheet. The err ata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip .com

• Your local Microchip sales ofﬁce (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales ofﬁce or the literature center, please specify which device, revision of silicon and data sheet (include lit-

erature number) you are using.

Corrections to this Data Sheet

We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, w e realize that w e may have missed a fe w things . If you ﬁnd any information that is missing or appears in error, please:

• Fill out and mail in the reader response form in the back of this data sheet.

• E-mail us at webmaster@microchip.com. We appreciate your assistance in making this a better document.

PIC16C62B/72A

DS35008A-page 4

Preliminary



1998 Microchip Technology Inc.

NOTES:

PIC16C62B/72A



1998 Microchip Technology Inc.

Preliminary

DS35008A-page 5

1.0 DEVICE OVERVIEW

This document contains device-speciﬁc information. Additional information may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip website. The Reference Manual should be considered a complementary document to this data sheet, and is highly rec-

ommended reading for a better understanding of the device architecture and operation of the peripheral modules.

There are two devices (PIC16C62B, PIC16C72A) covered by this datasheet. The PIC16C62B does not have the A/D module implemented.

Figure 1-1 is the block diagram for both devices. The pinouts are listed in Table 1-1.

FIGURE 1-1: PIC16C62B/PIC16C72A BLOCK DIAGRAM

EPROM

Program Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR

VDD, VSS

PORTA

PORTB

PORTC

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

2: The A/D module is not available on the PIC16C62B.

CCP1

Synchronous

A/D

(2)

Timer0 Timer1 Timer2

Serial Port

RA4/T0CKI RA5/SS

/AN4

(2)

RA3/AN3/VREF

(2)

RA2/AN2

(2)

RA1/AN1

(2)

RA0/AN0

(2)

2K x 14

128 x 8

PIC16C62B/72A

DS35008A-page 6

Preliminary



1998 Microchip Technology Inc.

TABLE 1-1 PIC16C62B/PIC16C72A PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SOIC

Pin#

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 9 9 I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR

1 1 I/P ST Master clear (reset) input or programming voltage input. This

pin is an active low reset to the device. PORTA is a bi-directional I/O port.

RA0/AN0

(4)

2 2 I/O TTL RA0 can also be analog input0

RA1/AN1

(4)

3 3 I/O TTL RA1 can also be analog input1

RA2/AN2

(4)

4 4 I/O TTL RA2 can also be analog input2

RA3/AN3/V

REF

(4)

5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage

RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.

Output is open drain type.

RA5/SS/AN4

(4)

7 7 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.

RB0/INT 21 21 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin. RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3 24 24 I/O TTL RB4 25 25 I/O TTL Interrupt on change pin. RB5 26 26 I/O TTL Interrupt on change pin. RB6 27 27 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock. RB7 28 28 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1

clock input. RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 out-

put/PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output

for both SPI and I

C modes.

RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I

C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6 17 17 I/O ST RC7 18 18 I/O ST V

8, 19 8, 19 P — Ground reference for logic and I/O pins.

20 20 P — Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise. 4: The A/D module is not available on the PIC16C62B.

PIC16C62B/72A



1998 Microchip Technology Inc.

Preliminary

DS35008A-page 7

2.0 MEMORY ORGANIZATION

There are two memory blocks in each of these PICmicros. Each block (Program Memory and Data Memory) has its own bus so that concurrent access can occur.

Additional information on device memory may be found in the PICmicro  Mid-Range Reference Manual, (DS33023).

2.1 Pr

ogram Memory Organization

The PIC16C62B/72A PICmicros have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Each device has 2K x 14 w ords of program memory. Accessing a location above the physically implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK

PC<12:0>

0000h

0004h 0005h

07FFh 0800h

1FFFh

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

User Memory

Space

PIC16C62B/72A

DS35008A-page 8

Preliminary



1998 Microchip Technology Inc.

2.2 Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.

= 00 → Bank0 = 01 → Bank1 = 10 → Bank2 (not implemented) = 11 → Bank3 (not implemented)

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Abo ve the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle can be accessed either directly , or indi-

rectly through the File Select Register FSR (Section 2.5).

FIGURE 2-2: REGISTER FILE MAP

RP1

(1)

RP0 (STATUS<6:5>)

Note 1: Maintain this bit clear to ensure upward compati-

bility with future products.

Unimplemented data memory locations,

read as '0'.

Note 1: Not a physical register.

2: These registers are not implemented on the

PIC16C62B, read as '0'.

File

Address

File

Address

00h INDF

(1)

INDF

(1)

80h

01h TMR0

OPTION_REG

81h 02h PCL PCL 82h 03h STATUS STATUS 83h 04h FSR FSR 84h 05h PORTA TRISA 85h 06h PORTB TRISB 86h 07h PORTC TRISC 87h 08h 88h 09h 89h

0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Dh

8Dh

0Eh TMR1L PCON 8Eh 0Fh TRM1H 8Fh

10h T1CON 90h 11h TRM2 91h 12h T2CON PR2 92h 13h SSPBUF SSPADD 93h 14h SSPCON SSPSTAT 94h 15h CCPR1L 95h 16h CCPR1H 96h 17h CCP1CON 97h 18h 98h 19h 99h

1Ah 9Ah 1Bh 9Bh 1Ch 9Ch 1Dh 9Dh 1Eh ADRES

(2)

9Eh

1Fh ADCON0

(2)

ADCON1

(2)

9Fh 20h

General

Purpose

Registers

General

Purpose

Registers

A0h

BFh

C0h

7Fh FFh

Bank 0 Bank 1

PIC16C62B/72A



1998 Microchip Technology Inc.

Preliminary

DS35008A-page 9

2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is give in Table 2-1.

The special function registers can be classiﬁed into two sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in that peripheral feature section.

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

(4)

Bank 0

00h INDF

(1)

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

01h TMR0 Timer0 module’s register

xxxx xxxx uuuu uuuu

02h PCL

(1)

Program Counter's (PC) Least Signiﬁcant Byte

0000 0000 0000 0000

03h STATUS

(1)

IRP

(5)

RP1

(5)

RP0 T

O PD ZDCC

rr01 1xxx rr0q quuu

04h FSR

(1)

Indirect data memory address pointer

xxxx xxxx uuuu uuuu

05h PORTA

(6)

—

— PORTA Data Latch when written: PORTA pins when read

--0x 0000 --0u 0000

06h PORTB

(7)

PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

07h PORTC

(7)

PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h-09h — Unimplemented — — 0Ah PCLATH

(1,2)

— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh INTCON

(1)

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 — ADIF

(3)

— — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h-1Dh — Unimplemented — — 1Eh ADRES

(3)

A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0

(3)

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',

Shaded locations are unimplemented, read as '0'.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents

are transferred to the upper byte of the program counter.

3: A/D not implemented on the PIC16C62B, maintain as ’0’. 4: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 5: The IRP and RP1 bits are reserved. Always maintain these bits clear. 6: On any device reset, these pins are conﬁgured as inputs. 7: This is the value that will be in the port output latch.

PIC16C62B/72A

DS35008A-page 10 Preliminary  1998 Microchip Technology Inc.

Bank 1

80h INDF

(1)

Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h

OPTION_ REG

RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h PCL

(1)

Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000

83h STATUS

(1)

IRP

(5)

RP1

(5)

RP0 TO PD ZDCCrr01 1xxx rr0q quuu

84h FSR

(1)

Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h-89h — Unimplemented — — 8Ah PCLATH

(1,2)

— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

8Bh INTCON

(1)

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch PIE1 — ADIE

(3)

— — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh-91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 95h-9Eh — Unimplemented — — 9Fh ADCON1

(3)

— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',

Shaded locations are unimplemented, read as '0'.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents

are transferred to the upper byte of the program counter.

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(4)

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 11

2.2.2.1 STATUS REGISTER The STATUS register, shown in Figure 2-3, contains

the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T

O and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary."

FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h)

Note 1: These devices do not use bits IRP and

RP1 (STATUS<7:6>). Maintain these bits clear to ensure upward compatibility with future products.

Note 2: The C and DC bits operate as a borro

w and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear 0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes Note: RP1 = not implemented, maintain clear

bit 4: T

O: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 3: PD

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: F or borro

w the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

PIC16C62B/72A

DS35008A-page 12 Preliminary  1998 Microchip Technology Inc.

2.2.2.2 OPTION_REG REGISTER The OPTION_REG register is a readable and writable

register which contains various control bits to conﬁgure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB .

FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h)

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to the Watchdog Timer .

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 13

2.2.2.3 INTCON REGISTER The INTCON Register is a readable and writable regis-

ter which contains various enable and ﬂag bits for the TMR0 register overﬂow, RB Port change and External RB0/INT pin interrupts.

FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: IINTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

PIC16C62B/72A

DS35008A-page 14 Preliminary  1998 Microchip Technology Inc.

2.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the

peripheral interrupts.

FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIE

(1)

— — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ‘0’ bit 6: ADIE

(1)

: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt

bit 5-4: Unimplemented: Read as ‘0’ bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt 0 = Disables the SSP interrupt

bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overﬂow Interrupt Enable bit

1 = Enables the TMR1 overﬂow interrupt 0 = Disables the TMR1 overﬂow interrupt

Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this

bit clear.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 15

2.2.2.5 PIR1 REGISTER This register contains the individual ﬂag bits for the

Peripheral interrupts.

FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)

Note: Interrupt ﬂag bits get set when an interrupt

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF

(1)

— — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ‘0’ bit 6: ADIF

(1)

: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete

bit 5-4: Unimplemented: Read as ‘0’ bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive

bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred

bit 0: TMR1IF: TMR1 Overﬂow Interrupt Flag bit

1 = TMR1 register overﬂowed (must be cleared in software) 0 = TMR1 register did not overﬂow

Note 1: The PIC16C62B does not have an A/D module. This bit location is reserved on these devices. Always maintain this

bit clear.

PIC16C62B/72A

DS35008A-page 16 Preliminary  1998 Microchip Technology Inc.

2.2.2.6 PCON REGISTER The Power Control (PCON) register contains a ﬂag bit

to allow differentiation between a Power-on Reset (POR) to an external MCLR

Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition.

FIGURE 2-8: PCON REGISTER (ADDRESS 8Eh)

Note: If the BODEN conﬁguration bit is set, BOR

is ’1’ on Power-on Reset. If the BODEN conﬁguration bit is clear, BOR

is unknown

on Power-on Reset. The BOR

status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BODEN conﬁguration bit is clear). BOR

must then be set by the user and checked on subsequent resets to see if it

is clear, indicating a

brown-out has occurred.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — — POR BOR R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1: POR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BOR

: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 17

2.3 PCL and PCLATH

The program counter (PC) speciﬁes the address of the instruction to fetch for execution. The PC is 13 bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<12:8> bits and is not directly readable or writable. All updates to the PCH register go through the PCLATH register.

2.3.1 STACK The stack allows a combination of up to 8 program calls

and interrupts to occur. The stack contains the return address from this branch in program execution.

Midrange devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modiﬁed when the stack is PUSHed or POPed.

After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on).

2.4 Program Memory Paging

The CALL and GOTO instructions provide 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper bit of the address is provided by PCLATH<3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bit is programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<3> bit is not required for the return instructions (which POPs the address from the stack).

PIC16C62B/72A

DS35008A-page 18 Preliminary  1998 Microchip Technology Inc.

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a

pointer

). This is indirect addressing.

EXAMPLE 2-1: INDIRECT ADDRESSING

• Register ﬁle 05 contains the value 10h

• Register ﬁle 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value of

10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ; to RAM NEXT clrf INDF ;clear INDF register incf FSR ;inc pointer btfss FSR,4 ;all done? goto NEXT ;NO, clear next CONTINUE : ;YES, continue

An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-9. However, IRP is not used in the PIC16C62B/72A.

FIGURE 2-9: DIRECT/INDIRECT ADDRESSING

Note 1: For register ﬁle map detail see Figure 2-2.

2: Maintain clear for upward compatibility with future products. 3: Not implemented.

Data Memory(1)

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6

from opcode

IRP FSR register

bank select

location select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

not used

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

(2)

(3) (3)

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 19

3.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023).

3.1 PORTA and the TRISA Register

PORTA is a 6-bit wide bi-directional por t. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output, i.e., put the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modiﬁed, and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers.

On the PIC16C72A device, other PORTA pins are multiplexed with analog inputs and analog V

REF input. The

operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 3-1: INITIALIZING PORTA

BCF STATUS, RP0 ; CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as '0'.

FIGURE 3-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

FIGURE 3-2: BLOCK DIAGRAM OF

RA4/T0CKI PIN

Note: On a Power-on Reset, these pins are con-

ﬁgured as analog inputs and read as '0'.

Data bus

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VDD

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD

and V

SS.

Analog input mode

TTL input buffer

To A/D Converter (72A only)

(72B

only)

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt T rigger input buffer

I/O pin

(1)

TMR0 clock input

Note 1: Note 1: I/O pin has protection diodes to

SS only.

PIC16C62B/72A

DS35008A-page 20 Preliminary  1998 Microchip Technology Inc.

TABLE 3-1 PORTA FUNCTIONS

TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input

(1)

RA1/AN1 bit1 TTL Input/output or analog input

(1)

RA2/AN2 bit2 TTL Input/output or analog input

(1)

RA3/AN3/VREF bit3 TTL Input/output or analog input

(1)

or VREF

(1)

RA4/T0CKI bit4 ST

Input/output or external clock input for Timer0 Output is open drain type

RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input

(1)

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: On PIC16C72A only.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all

other resets

05h PORTA

(for PIC16C72A only)

— — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000

05h PORTA

(for PIC16C62B only)

— — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu

85h TRISA

— — PORTA Data Direction Register --11 1111 --11 1111

9Fh ADCON1

(1)

— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

Note 1: On PIC16C72A only.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 21

3.2 PORTB and the TRISB Register

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output, i.e., put the contents of the output latch on the selected pin.

EXAMPLE 3-1: INITIALIZING PORTB

BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU

(OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are disabled on a Power-on Reset.

FIGURE 3-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with ﬂag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared.

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

FIGURE 3-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

RBPU

(2)

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak pull-up

RD Port

RB0/INT

I/O pin

(1)

TTL Input Buffer

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

bit (OPTION_REG<7>).

Schmitt T rigger Buffer

TRIS Latch

Data Latch

From other

RBPU

(2)

I/O

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak pull-up

RD Port

Latch

TTL Input Buffer

(1)

Note 1: I/O pins have diode protection to VDD and VSS.

Buffer

RB7:RB6 in serial programming mode

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION_REG<7>).

PIC16C62B/72A

DS35008A-page 22 Preliminary  1998 Microchip Technology Inc.

TABLE 3-3 PORTB FUNCTIONS

TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST

(1)

Input/output pin or external interrupt input. Internal software

programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB6 bit6 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock. RB7 bit7 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h OPTION_

REG

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 23

3.3 PORTC and the TRISC Register

PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output, i.e., put the contents of the output latch on the selected pin.

PORTC is multiplex ed with se v eral peripheral functions (Table 3-5). PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be taken in deﬁning TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should ref er to the corresponding peripheral section for the correct TRIS bit settings.

EXAMPLE 3-1: INITIALIZING PORTC

BCF STATUS, RP0 ; Select Bank 0 CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs

FIGURE 3-5: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT OVERRIDE)

PORT/PERIPHERAL Select

(2)

Data bus

WR PORT

WR TRIS

Data Latch

TRIS Latch

RD TRIS

Schmitt T rigger

QD Q

Peripheral Data Out

0 1

VDD

VSS

PORT

Peripheral OE

(3)

Peripheral input

I/O pin

(1)

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral select signal selects between port

data and peripheral output.

3: Peripheral OE (output enable) is only activated if

peripheral select is active.

PIC16C62B/72A

DS35008A-page 24 Preliminary  1998 Microchip Technology Inc.

TABLE 3-5 PORTC FUNCTIONS

TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI

bit0

ST Input/output port pin or Timer1 oscillator output/Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1

output

RC3/SCK/SCL bit3 ST

RC3 can also be the synchronous serial clock for both SPI and I

modes.

RC4/SDI/SDA bit4 ST

RC4 can also be the SPI Data In (SPI mode) or data I/O (I

C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 25

4.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

• 8-bit timer/counter

• Readable and writable

• Internal or external clock select

• Edge select for external clock

• 8-bit software programmable prescaler

• Interrupt on overﬂow from FFh to 00h Figure 4-1 is a simpliﬁed block diagram of the Timer0

module. Additional information on timer modules is available in

the PICmicro™ Mid-Range Reference Manual, (DS33023).

4.1 Timer0 Operation

Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed below.

When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T

OSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

Additional information on external clock requirements is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

4.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 4-2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

The prescaler is not readable or writable. The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0

module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable.

Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to the WDT, prescale values of 1:1, 1:2, ..., 1:128 are selectable.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT.

FIGURE 4-1: TIMER0 BLOCK DIAGRAM

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 cycle delay)

PSout

Data bus

PSA

PS2, PS1, PS0

Set interrupt ﬂag bit T0IF

on overﬂow

PIC16C62B/72A

DS35008A-page 26 Preliminary  1998 Microchip Technology Inc.

4.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program execution.

4.3 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overﬂows from FFh to 00h. This overﬂow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP.

FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0

Note: To avoid an unintended device RESET, a

speciﬁc instruction sequence (shown in the PICmicro Mid-Range Reference Manual, DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh INTCON GIE

PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

RA4/T0CKI

T0SE

U X

CLKOUT (=Fosc/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

U X

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

M U

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS

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 1998 Microchip Technology Inc. Preliminary DS35008A-page 27

5.0 TIMER1 MODULE

The Timer1 module timer/counter has the f ollowing features:

• 16-bit timer/counter (Two 8-bit registers; TMR1H and TMR1L)

• Readable and writable (Both registers)

• Internal or external clock select

• Interrupt on overﬂow from FFFFh to 0000h

• Reset from CCP module trigger

Timer1 has a control register, shown in Figure 5-1. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).

Figure 5-2 is a simpliﬁed block diagram of the Timer1 module.

Additional information on timer modules is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

5.1 Timer1 Operation

Timer1 can operate in one of these modes:

• As a timer

• As a synchronous counter

• As an asynchronous counter The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>). In timer mode, Timer1 increments every instruction

cycle. In counter mode, it increments on every rising edge of the external clock input.

When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.

Timer1 also has an internal “reset input”. This reset can be generated by the CCP module (Section 7.0).

FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

R = Readable bit W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value

bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain

bit 2: T1SYNC

: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input

TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1: TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (F

OSC/4)

bit 0: TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

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DS35008A-page 28 Preliminary  1998 Microchip Technology Inc.

FIGURE 5-2: TIMER1 BLOCK DIAGRAM

TMR1H

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

SLEEP input

T1OSCEN Enable Oscillator

(1)

FOSC/4

Internal Clock

TMR1ON

on/off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

clock input

RC0/T1OSO/T1CKI

RC1/T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

Set ﬂag bit TMR1IF on Overﬂow

TMR1

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 1998 Microchip Technology Inc. Preliminary DS35008A-page 29

5.2 Timer1 Oscillator

A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (ampliﬁer output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 5-1 shows the capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.

TABLE 5-1 CAPACITOR SELECTION

FOR THE TIMER1 OSCILLATOR

5.3 Timer1 Interrupt

The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overﬂow which is latched in interrupt ﬂag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

5.4 Resetting Timer1 using a CCP Trigger Output

If the CCP module is conﬁgured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled).

Timer1 must be conﬁgured for either timer or synchronized counter mode to take advantage of this f eature. If Timer1 is running in asynchronous counter mode, this reset operation may not work.

In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.

In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for Timer1.

TABLE 5-2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

Note: The special event triggers from the CCP1

module will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF

-0-- 0000 -0-- 0000

8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE

-0-- 0000 -0-- 0000

0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

--00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

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NOTES:

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6.0 TIMER2 MODULE

The Timer2 module timer has the following features:

• 8-bit timer (TMR2 register)

• 8-bit period register (PR2)

• Readable and writable (Both registers)

• Software programmable prescaler (1:1, 1:4, 1:16)

• Software programmable postscaler (1:1 to 1:16)

• Interrupt on TMR2 match of PR2

• SSP module optional use of TMR2 output to generate clock shift

Timer2 has a control register, shown in Figure 6-1. Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption.

Figure 6-2 is a simpliﬁed block diagram of the Timer2 module.

Additional information on timer modules is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

FIGURE 6-2: TIMER2 BLOCK DIAGRAM

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale 0001 = 1:2 Postscale

•

• 1111 = 1:16 Postscale

bit 2: TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

Comparator

TMR2

Sets ﬂag

TMR2 reg

output

(1)

Reset

Postscaler

Prescaler

PR2 reg

OSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1: TMR2 register output can be software selected

by the SSP Module as a baud clock.

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DS35008A-page 32 Preliminary  1998 Microchip Technology Inc.

6.1 Timer2 Operation

Timer2 can be used as the PWM time-base for PWM mode of the CCP module.

The TMR2 register is readable and writable, and is cleared on any device reset.

The input clock (F

OSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).

The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in ﬂag bit TMR2IF, (PIR1<1>)).

The prescaler and postscaler counters are cleared when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (Power-on Reset, MCLR

reset,

Watchdog Timer reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

6.2 Timer2 Interrupt

The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset.

6.3 Output of TMR2

The output of TMR2 (bef ore the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock.

TABLE 6-1 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all other

resets

0Bh,8Bh INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1

— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF

-00- 0000 0000 0000

8Ch PIE1

— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE

-0-- 0000 0000 0000

11h TMR2 Timer2 module’s register

0000 0000 0000 0000

12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000 -000 0000

92h PR2 Timer2 Period Register

1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.

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7.0 CAPTURE/COMPARE/PWM

(CCP) MODULE(S)

Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the timer resources of the CCP module modes.

Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.

Additional information on the CCP module is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

TABLE 7-1 CCP MODE - TIMER

RESOURCE

FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h)

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1 Timer1 Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: CCP1X:CCP1Y: PWM Least Signiﬁcant bits

Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0: CCP1M3:CCP1M0: CCP1 Mode Select bits

0000 = Capture/Compare/PWM off (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 and starts an A/D

conversion (if A/D module is enabled))

11xx = PWM mode

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DS35008A-page 34 Preliminary  1998 Microchip Technology Inc.

7.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an e v ent occurs on pin RC2/CCP1. An event is deﬁned as:

• every falling edge

• every rising edge

• every 4th rising edge

• every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the interrupt request ﬂag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost.

FIGURE 7-2: CAPTURE MODE

OPERATION BLOCK DIAGRAM

7.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be conﬁg-

ured as an input by setting the TRISC<2> bit.

7.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized

counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work.

7.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the ﬂag bit CCP1IF following any such change in operating mode.

7.1.4 CCP PRESCALER There are four prescaler settings, speciﬁed by bits

CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter.

Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the ﬁrst capture may be from a non-zero prescaler. Example 7-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt.

EXAMPLE 7-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; mode value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this ; value

Note: If the RC2/CCP1 is conﬁgured as an out-

put, a write to the port can cause a capture condition.

CCPR1H CCPR1L

TMR1H TMR1L

Set ﬂag bit CCP1IF

(PIR1<2>)

Capture Enable

Q’s

CCP1CON<3:0>

RC2/CCP1

Prescaler

÷ 1, 4, 16

and

edge detect

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 35

7.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is:

• driven High

• driven Low

• remains Unchanged

The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt ﬂag bit CCP1IF is set.

FIGURE 7-3: COMPARE MODE

OPERATION BLOCK DIAGRAM

7.2.1 CCP PIN CONFIGURATION The user must conﬁgure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

7.2.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.

7.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if enabled).

7.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated

which may be used to initiate an action. The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmab le period register f or Timer1.

The special trigger output of CCP2 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled).

TABLE 7-2 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set ﬂag bit CCP1IF

(PIR1<2>)

match

RC2/CCP1

TRISC<2>

CCP1CON<3:0> Mode Select

Output Enable

Special event trigger will: reset Timer1, but not set interrupt ﬂag bit TMR1IF (PIR1<0>), and set bit GO/DONE

(ADCON0<2>)

which starts an A/D conversion

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the default low level. This is not the data latch.

Note: The special event trigger from the CCP2

module will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1

— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch PIE1

— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.

PIC16C62B/72A

DS35008A-page 36 Preliminary  1998 Microchip Technology Inc.

7.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the POR TC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output.

Figure 7-4 shows a simpliﬁed block diagram of the CCP module in PWM mode.

For a step by step procedure on how to set up the CCP module for PWM operation, see Section 7.3.3.

FIGURE 7-4: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 7-5) has a time base (per iod) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).

FIGURE 7-5: PWM OUTPUT

7.3.1 PWM PERIOD The PWM period is speciﬁed by writing to the PR2 reg-

ister. The PWM period can be calculated using the following formula:

PWM period = [(PR2) + 1] • 4 • T

OSC •

(TMR2 prescale value)

PWM frequency is deﬁned as 1 / [PWM period]. When TMR2 is equal to PR2, the following three ev ents

occur on the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into CCPR1H

7.3.2 PWM DUTY CYCLE

The PWM duty cycle is speciﬁed by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) • Tosc • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM frequency:

For an example PWM period and duty cycle calculation, see the PICmicro™ Mid-Range Reference Manual, (DS33023).

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty cycle registers

CCP1CON<5:4>

Clear Timer, CCP1 pin and latch D.C.

TRISC<2>

RC2/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note: The Timer2 postscaler (see Section 6.0) is

not used in the determination of the PWM frequency . The postscaler could be used to have a servo update rate at a different frequency than the PWM output.

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be cleared.

log(

PWM

log(2)

OSC

)

bits

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 37

7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when conﬁguring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2 register.

2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the TRISC<2> bit.

4. Set the TMR2 prescale value and enab le Timer2 by writing to T2CON.

5. Conﬁgure the CCP1 module for PWM operation.

TABLE 7-3 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

TABLE 7-4 REGISTERS ASSOCIATED WITH PWM AND TIMER2

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1111 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1

— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch PIE1

— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’s period register 1111 1111 1111 1111 12h T2CON

— TOUTPS3 T OUTPS2 TOUTPS1 T OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.

PIC16C62B/72A

DS35008A-page 38 Preliminary  1998 Microchip Technology Inc.

NOTES:

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 39

8.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE

8.1 SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I

For more information on SSP operation (including an I

C Overview), refer to the PICmicro™ Mid-Range Reference Manual, (DS33023). Also, refer to Application Note AN578,

“Use of the SSP Module in the I2C Multi-

Master Environment.”

PIC16C62B/72A

DS35008A-page 40 Preliminary  1998 Microchip Technology Inc.

FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A

P S R/W UA BF R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: SMP: SPI data input sample phase

SPI Master Oper

ation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Sla

ve Mode

SMP must be cleared when SPI is used in slave mode

bit 6: CKE: SPI Clock Edge Select

CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK

bit 5: D/A

: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address

bit 4: P: Stop bit (I

C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last

bit 3: S: Start bit (I

C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last

bit 2: R/W

: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or A

CK bit. 1 = Read 0 = Write

bit 1: UA: Update Address (10-bit I

C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated

bit 0: BF: Buffer Full Status bit

Receiv

e (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

ransmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 41

FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1

SSPM0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision

bit 6: SSPOV: Receive Overﬂow Indicator bit

In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the pre vious data. In case of ov erﬂow , the data in SSPSR is lost. Ov erﬂow can only occur in sla v e mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overﬂow. In master operation, the overﬂow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overﬂow

In I

C mode 1 = A byte is received while the SSPBUF register is still holding the pre vious byte. SSPO V is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overﬂow

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode 1 = Enables serial port and conﬁgures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins

In I

C mode 1 = Enables the serial port and conﬁgures the SDA and SCL pins as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins In both modes, when enabled, these pins must be properly conﬁgured as input or output.

bit 4: CKP: Clock Polarity Select bit

In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I

C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master operation, clock = F

OSC/4

0001 = SPI master operation, clock = F

OSC/16

0010 = SPI master operation, clock = F

OSC/64

0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS

pin control enabled.

0101 = SPI slave mode, clock = SCK pin. SS

pin control disabled. SS can be used as I/O pin

0110 = I

C slave mode, 7-bit address

0111 = I

C slave mode, 10-bit address

1011 = I

C firmware controlled master operation (slave idle)

1110 = I

C slave mode, 7-bit address with start and stop bit interrupts enabled

1111 = I

C slave mode, 10-bit address with start and stop bit interrupts enabled

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DS35008A-page 42 Preliminary  1998 Microchip Technology Inc.

8.2 SPI Mode

This section contains register deﬁnitions and operational characteristics of the SPI module.

Additional information on SPI operation may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023).

8.2.1 OPERATION OF SSP MODULE IN SPI MODE

A block diagram of the SSP Module in SPI Mode is shown in Figure 8-3.

The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO)RC5/SDO

• Serial Data In (SDI)RC4/SDI/SDA

• Serial Clock (SCK)RC3/SCK/SCL

Additionally a fourth pin may be used when in a slave mode of operation:

• Slave Select (SS

)RA5/SS/AN4

When initializing the SPI, several options need to be speciﬁed. This is done b y programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be speciﬁed:

• Master Operation (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock Edge (Output data on rising/falling edge of

SCK)

• Clock Rate (master operation only)

• Slave Select Mode (Slave mode only)

To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconﬁgure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This conﬁgures the SDI, SDO, SCK, and SS

pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (master operation) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

•SS

must have TRISA<5> set

FIGURE 8-3: SSP BLOCK DIAGRAM

(SPI MODE)

Note: When the SPI is in Slave Mode with SS pin

control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS

pin is set

to V

DD.

Note: If the SPI is used in Slave Mode with

CKE = '1', then the SS

pin control must be

enabled.

Read Write

Internal

data bus

RC4/SDI/SDA

RC5/SDO

RA5/SS

/AN4

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

Control Enable

Edge

Select

Clock Select

TMR2 output

TCY

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 43

TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1

—

ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch PIE1

—

ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.

PIC16C62B/72A

DS35008A-page 44 Preliminary  1998 Microchip Technology Inc.

8.3 SSP I2C Operation

The SSP module in I2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate ﬁrmware implementations of the master functions. The SSP module implements the standard mode speciﬁcations as well as 7-bit and 10-bit addressing.

Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA). The user must conﬁgure these pins as inputs or outputs through the TRISC<4:3> bits.

The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>).

FIGURE 8-4: SSP BLOCK DIAGRAM

(I2C MODE)

The SSP module has ﬁve registers for I2C operation. These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly acces-

sible

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I

C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I

C modes to be selected:

•I

C Slave mode (7-bit address)

•I

C Slave mode (10-bit address)

•I

C Slave mode (7-bit address), with start and

stop bit interrupts enabled

•I

C Slave mode (10-bit address), with start and

stop bit interrupts enabled

•I

C Firmware controlled master operation, slave

is idle

Selection of any I

C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits.

Additional information on SSP I

C operation may be found in the PICmicro™ Mid-Range Reference Manual, (DS33023).

8.3.1 SLAVE MODE In slave mode, the SCL and SDA pins must be conﬁg-

ured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter).

When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (A

CK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.

There are certain conditions that will cause the SSP module not to give this A

CK pulse. These are if either

(or both): a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overﬂow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 8-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPO V. The shaded cells show the condition where user software did not properly clear the overﬂow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I

C speciﬁcation as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101.

Read Write

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

SSPBUF reg

Internal

data bus

Addr Match

Set, Reset S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/

shift

clock

MSb

SDI/

LSb

SDA

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 45

8.3.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a

START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register. b) The buffer full bit, BF is set. c) An A

CK pulse is generated.

d) SSP interr upt ﬂag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) - on the falling

edge of the ninth SCL pulse. In 10-bit address mode, two address bytes need to be

received by the slave. The ﬁve Most Signiﬁcant bits (MSbs) of the ﬁrst address byte specify if this is a 10-bit address. Bit R/W

(SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the ﬁrst byte would equal

‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 f or slav e-transmitter:

1. Receive ﬁrst (high) byte of Address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low) byte of Address (clears bit UA and releases the SCL line).

3. Read the SSPBUF register (clears bit BF) and clear ﬂag bit SSPIF.

4. Receive second (low) byte of Address (bits SSPIF, BF, and UA are set).

5. Update the SSPADD register with the ﬁrst (high) byte of Address, if match releases SCL line, this will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and clear ﬂag bit SSPIF.

7. Receive repeated START condition.

8. Receive ﬁrst (high) byte of Address (bits SSPIF and BF are set).

9. Read the SSPBUF register (clears bit BF) and clear ﬂag bit SSPIF.

TABLE 8-2 DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate A

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

00 Yes Ye s Yes 10 No No Yes 11 No No Yes 0 1 Yes No Yes

Note:Shaded cells show the conditions where the user software did not properly clear the overﬂow condition.

PIC16C62B/72A

DS35008A-page 46 Preliminary  1998 Microchip Technology Inc.

8.3.1.2 RECEPTION When the R/W

bit of the address byte is clear and an

address match occurs, the R/W

bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register.

When the address byte overﬂow condition exists, then no acknowledge (A

CK) pulse is given. An ov erﬂow condition is deﬁned as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.

FIGURE 8-5: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4

A3 A2 A1SDA

SCL

1234

123

Bus Master terminates transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

Receiving Data

D3D4

D6D7

R/W=0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK is not sent.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 47

8.3.1.3 TRANSMISSION When the R/W

bit of the incoming address byte is set

and an address match occurs, the R/W

bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The A

CK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices ma y be holding off the master b y stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 8-6).

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse.

As a slave-transmitter, the A

CK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SD A line was high (not A

CK), then the

data transfer is complete. When the A

CK is latched by the slave, the sla ve logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (A

CK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 8-6: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>) BF (SSPSTAT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

CKTransmitting DataR/W = 1Receiving Address

123456789 123456789

cleared in software

SSPBUF is written in software

From SSP interrupt

service routine

Set bit after writing to SSPBUF

Data in sampled

SCL held low while CPU

responds to SSPIF

(the SSPBUF must be written-to before the CKP bit can be set)

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DS35008A-page 48 Preliminary  1998 Microchip Technology Inc.

8.3.2 MASTER OPERATION Master operation is supported in ﬁrmware using inter-

rupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I

C bus may be taken when the P bit is set, or the

bus is idle and both the S and P bits are clear. In master operation, the SCL and SDA lines are manip-

ulated in ﬁrmware by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit.

The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received Master operation can be done with either the slave

mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master operation and slave modes are used, the software needs to differentiate the source(s) of the interrupt.

For more information on master operation, see

AN554

- Software Implementation of I

C Bus Master

8.3.3 MULTI-MASTER OPERATION In multi-master operation, the interrupt generation on

the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and ST AR T (S) bits will toggle based on the START and STOP conditions. Control of the I

C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.

In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high le v el is expected and a lo w lev el is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are:

• Address T r ansfer

• Data T r ansfer When the slave logic is enabled, the sla v e contin ues to

receive. If arbitr ation was lost during the address transfer stage, communication to the device may be in progress. If addressed an A

CK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.

For more information on master operation, see

AN578

- Use of the SSP Module in the of I

C Multi-Master

Environment

TABLE 8-3 REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets

0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch

PIR1

—

ADIF

— —

SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch

PIE1

—

ADIE

— —

SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

93h SSPADD Synchronous Serial Port (I2C mode) Address Register

0000 0000 0000 0000

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

0000 0000 0000 0000

94h SSPSTAT SMP CKE D/A P S R/W UA BF

0000 0000 0000 0000

87h TRISC

PORTC Data Direction register

1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Shaded cells are not used by SSP module in SPI mode.

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9.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

This section applies to the PIC16C72A only. The

analog-to-digital (A/D) converter module has ﬁve inputs.

The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’ s positiv e supply v oltage (V

DD)

or the voltage level on the RA3/AN3/V

REF pin.

The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conv ersion clock must be derived from the A/D’s internal RC oscillator.

Additional information on the A/D module is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

The A/D module has three registers. These registers are:

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted.

The ADCON0 register, shown in Figure 9-1, controls the operation of the A/D module. The ADCON1 register, shown in Figure 9-2, conﬁgures the functions of the port pins. The port pins can be conﬁgured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.

FIGURE 9-1: ADCON0 REGISTER (ADDRESS 1Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

— ADON R =Readable bit

W =Writable bit U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = F

OSC/2

01 = F

OSC/8

10 = F

OSC/32

11 = F

RC (clock derived from an internal RC oscillator)

bit 5-3: CHS2:CHS0: Analog Channel Select bits

000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4)

bit 2: GO/DONE

: A/D Conversion Status bit

If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardw are when the A/D conversion

is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

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DS35008A-page 50 Preliminary  1998 Microchip Technology Inc.

FIGURE 9-2: ADCON1 REGISTER (ADDRESS 9Fh)

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit

W =Writable bit U =Unimplemented

bit, read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Conﬁguration Control bits

A = Analog input D = Digital I/O

PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF

000 AAAAA VDD 001 AAAAVREF RA3 010 AAAAA V

011 AAAAVREF RA3 100 AADDA V

101 AADDVREF RA3 11x DDDDD V

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 51

The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt ﬂag bit ADIF is set. The block diagram of the A/D module is shown in Figure 9-3.

The value that is in the ADRES register is not modiﬁed for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset.

After the A/D module has been conﬁgured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To deter mine acquisition time, see Section 9.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:

1. Conﬁgure the A/D module:

• Conﬁgure analog pins / voltage reference / and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Conﬁgure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE

bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is deﬁned as T

AD. A minimum wait of 2TAD is

required before next acquisition starts.

FIGURE 9-3: A/D BLOCK DIAGRAM

(Input voltage)

VREF

(Reference

voltage)

PCFG2:PCFG0

CHS2:CHS0

000 or 010 or 100

001 or 011 or 101

RA5/AN4

RA3/AN3/V

REF

RA2/AN2

RA1/AN1

RA0/AN0

100

011

010

001

000

A/D

Converter

PIC16C62B/72A

DS35008A-page 52 Preliminary  1998 Microchip Technology Inc.

9.1 A/D Acquisition Requirements

For the A/D converter to meet its speciﬁed accuracy, the charge holding capacitor (C

HOLD) must be allowed

to fully charge to the input channel voltage level. The analog input model is shown in Figure 9-4. The source impedance (R

S) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the capacitor C

HOLD. The sampling switch (RSS)

impedance varies over the device voltage (V

DD). The

source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum

recommended impedance for analog sources is 10 kΩ. After the analog input channel is selected

(changed) this acquisition must be done before the conversion can be started.

To calculate the minimum acquisition time, T

ACQ, see

the PICmicro™ Mid-Range Reference Manual, (DS33023). This equation calculates the acquisition time to within 1/2 LSb error (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its speciﬁed accuracy.

FIGURE 9-4: ANALOG INPUT MODEL

Note: When the conversion is started, the hold-

ing capacitor is disconnected from the input pin.

CPIN

ANx

5 pF

VT = 0.6V

T = 0.6V

I leakage

IC ≤ 1k

Sampling Switch

CHOLD = DAC capacitance

Sampling Switch

5V 4V 3V 2V

5 6 7 8 9 10 11

(kΩ)

VDD

= 51.2 pF

± 500 nA

Legend CPIN

VT I leakage

RIC SS C

HOLD

= input capacitance = threshold voltage

= leakage current at the pin due to

= interconnect resistance = sampling switch = sample/hold capacitance (from DAC)

various junctions

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 53

9.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is deﬁned as TAD. The A/D conversion requires 9.5T

AD per 8-bit conversion.

The source of the A/D conversion clock is software selectable. The four possible options for T

AD are:

•2T

OSC

•8TOSC

• 32TOSC

• Internal RC oscillator

For correct A/D conversions, the A/D conversion clock (T

AD) must be selected to ensure a minimum TAD time

of 1.6 µs. Table 9-1 shows the resultant T

AD times derived from

the device operating frequencies and the A/D clock source selected.

9.3 Configuring Analog Port Pins

The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (V

OH or VOL) will be converted.

The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.

TABLE 9-1 TAD vs. DEVICE OPERATING FREQUENCIES

Note 1: When reading the port register, all pins

conﬁgured as analog input channels will read as cleared (a low level). Pins conﬁgured as digital inputs, will convert an analog input. Analog levels on a digitally conﬁgured input will not affect the conversion accuracy.

Note 2: Analog levels on any pin that is deﬁned as

a digital input (including the AN4:AN0 pins), may cause the input buffer to consume current that is out of the devices speciﬁcation.

AD Clock Source (TAD) Device Frequency

Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz

OSC 00

100 ns

(2)

400 ns

(2)

1.6 µs6 µs

8TOSC 01

400 ns

(2)

1.6 µs 6.4 µs

24 µs

(3)

32TOSC 10 1.6 µs 6.4 µs

25.6 µs

(3)

96 µs

(3)

(5)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1)

Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical T

AD time of 4 µs.

2: These values violate the minimum required T

AD time.

3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep operation only.

5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

PIC16C62B/72A

DS35008A-page 54 Preliminary  1998 Microchip Technology Inc.

9.4 A/D Conversions

9.5 Use of the CCP Trigger

An A/D conversion can be started by the “special ev ent trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the

GO/DONE

bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the “special event trigger” sets the GO/DONE

bit (starts a conversion). If the A/D module is not enabled (ADON is cleared),

then the “special event trigger” will be ignored by the A/D module, but will still reset the Timer1 counter.

TABLE 9-2 SUMMARY OF A/D REGISTERS

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all

other Resets

0Bh,8Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch

PIR1

—

ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

8Ch

PIE1

—

ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

1Eh

ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh

ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

9Fh

ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0

--0x 0000 --0u 0000

85h TRISA — — PORTA Data Direction Register

--11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 55

10.0 SPECIAL FEATURES OF THE CPU

The PIC16C62B/72A devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are:

• OSC Selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming™

These devices have a Watchdog Timer which can be shut off only through conﬁguration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The

other is the Power-up Timer (PWRT), which provides a ﬁxed delay on pow er-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current power-down mode. The user can w ake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to ﬁt the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

Additional information on special features is av ailable in the PICmicro™ Mid-Range Reference Manual, (DS33023).

10.1 Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device conﬁgurations. These bits are mapped in program memory location 2007h.

The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/conﬁguration memory space (2000h 3FFFh), which can be accessed only during programming.

FIGURE 10-1: CONFIGURATION WORD

CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0

bit13 bit0

bit 13-8 CP1:CP0: Code Protection bits

(2)

5-4: 11 = Code protection off

10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected

bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit

(1)

1 = BOR enabled 0 = BOR disabled

bit 3: PWRTE: Power-up Timer Enable bit

(1)

1 = PWRT disabled 0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

PIC16C62B/72A

DS35008A-page 56 Preliminary  1998 Microchip Technology Inc.

10.2 Oscillator Conﬁgurations

10.2.1 OSCILLATOR TYPES The PIC16CXXX can be operated in four different oscil-

lator modes. The user can program two conﬁguration bits (FOSC1 and FOSC0) to select one of these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

10.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In XT, LP or HS modes a cr ystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 10-2). The PIC16CXXX Oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 10-3).

FIGURE 10-2: CRYSTAL/CERAMIC

RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)

FIGURE 10-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

TABLE 10-1 CERAMIC RESONATORS

TABLE 10-2 CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

Note1: See Table 10-1 and Table 10-2 for recom-

mended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen.

(1)

XTAL

OSC2

OSC1

(3)

SLEEP

logic

PIC16CXXX

(2)

internal

OSC1

OSC2

Open

Clock from ext. system

PIC16CXXX

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF 15 - 68 pF 15 - 68 pF

HS 8.0 MHz

16.0 MHz

10 - 68 pF 10 - 22 pF

These values are for design guidance only. See notes at bottom of page.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

Osc Type

Crystal

Freq

Cap. Range C1Cap. Range

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

These values are for design guidance only. See notes at bottom of page.

Crystals Used

32 kHz Epson C-001R32.768K-A ± 20 PPM

200 kHz STD XTL 200.000KHz ± 20 PPM

1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM

20 MHz EPSON CA-301 20.000M-C ± 30 PPM

Note 1: Recommended values of C1 and C2 are

identical to the ranges tested (Table 10-1).

2: Higher capacitance increases the stability

of oscillator but also increases the start-up time.

3: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

4: Rs may be required in HS mode as well as

XT mode to avoid overdriving crystals with low drive level speciﬁcation.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 57

10.2.3 RC OSCILLATOR For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (R

EXT) and capacitor (CEXT) values, and the operat-

ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Further more, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low C

EXT values. The user also needs to take into account

variation due to tolerance of external R and C components used. Figure 10-4 shows how the R/C combination is connected to the PIC16CXXX.

FIGURE 10-4: RC OSCILLATOR MODE

10.3 Reset

The PIC16CXXX differentiates between various kinds of reset:

• Power-on Reset (POR)

• MCLR

reset during normal operation

• MCLR

reset during SLEEP

• WDT Reset (during normal operation)

• WDT Wake-up (during SLEEP)

• Brown-out Reset (BOR) Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR

and

WDT Reset, on MCLR

reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The T

O and PD bits are set or cleared differently in different reset situations as indicated in Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full description of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 10-5.

The PICmicros have a MCLR

noise ﬁlter in the MCLR

reset path. The ﬁlter will detect and ignore small pulses. It should be noted that a WDT Reset

does not drive

MCLR

pin low.

OSC2/CLKOUT

Cext

Rext

PIC16CXX

OSC1

Fosc/4

Internal

clock

VDD

VSS

Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ

Cext > 20pF

PIC16C62B/72A

DS35008A-page 58 Preliminary  1998 Microchip Technology Inc.

FIGURE 10-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

VDD

OSC1

WDT

Module

DD rise

detect

OST/PWRT

On-chip RC OSC

WDT

Time-out

Power-on Reset

OST

10-bit Ripple counter

PWRT

Chip_Reset

10-bit Ripple counter

Reset

Enable OST

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset

BODEN

(1)

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 59

10.4 Power-On Reset (POR)

A Power-on Reset pulse is generated on-chip when V

DD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR

directly (or through a resistor) to V

DD. This will elimi-

nate external RC components usually needed to create a Power-on Reset. A maximum rise time for V

DD is

speciﬁed (parameter D004). For a slow rise time, see Figure 10-6.

When the device starts normal operation (exits the reset condition), device operating parameters (voltage , frequency , temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions.

FIGURE 10-6: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW VDD POWER-UP)

10.5 Power-up Timer (PWRT)

The Power-up Timer provides a ﬁxed nominal time-out (parameter #33), on power-up only, from the POR. The Power-up Timer operates on an inter nal RC oscillator. The chip is kept in reset as long as the PWRT is active . The PWRT’ s time delay allows V

DD to rise to an accept-

able level. A conﬁguration bit is provided to enable/disable the PWRT.

The power-up time delay will v ary from chip to chip due to V

DD, temperature, and process variation. See DC

parameters for details.

10.6 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is ov er (parameter #32). This ensures that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

10.7 Brown-Out Reset (BOR)

A conﬁguration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If V

DD falls below parameter D005 for greater

than parameter #35, the brown-out situation will reset the chip. A reset may not occur if V

DD falls below

parameter D005 for less than parameter #35. The chip will remain in Brown-out Reset until V

DD rises above

DD. The P ow er-up Timer will then be invok ed and will

keep the chip in RESET an additional time delay (parameter #33). If V

DD drops below BVDD while the

Power-up Timer is r unning, the chip will go back into a Brown-out Reset and the Po wer-up Timer will be initialized. Once V

DD rises above BVDD, the P o w er-up Timer

will execute the additional time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled.

Note 1: External Power-on Reset circuit is required

only if V

DD power-up slope is too slow . The

diode D helps discharge the capacitor quickly when V

DD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor C in the event of MCLR/

VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

MCLR

PIC16CXXX

PIC16C62B/72A

DS35008A-page 60 Preliminary  1998 Microchip Technology Inc.

10.8 Time-out Sequence

On power-up the time-out sequence is as follows: First PWRT time-out is invok ed after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator conﬁguration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 10-7, Figure 10-8, Figure 10-9 and Figure 10-10 depict timeout sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire . Then bringing MCLR

high will begin execution immediately (Figure 10-9). This is useful for testing purposes or to synchronize more than one PIC16CXXX device operating in parallel.

Table 10-5 shows the reset conditions for some special function registers, while Table 10-6 shows the reset conditions for all the registers.

10.9 Power Control/Status Register (PCON)

The Power Control/Status Register, PCON has up to two bits, depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR

. If the BODEN

conﬁguration bit is set, BOR

is ’1’ on Power-on Reset.

If the BODEN conﬁguration bit is clear, BOR

unknown on Power-on Reset. The BOR

status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BODEN conﬁguration bit is clear). BOR

must then be set by the user and checked on subsequent resets to see if it

is clear, indicating a brown-out has occurred.

Bit1 is POR

(Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.

TABLE 10-3 TIME-OUT IN VARIOUS SITUATIONS

TABLE 10-4 STATUS BITS AND THEIR SIGNIFICANCE

TABLE 10-5 RESET CONDITION FOR SPECIAL REGISTERS

Oscillator Conﬁguration

Power-up

Brown-out

Wake-up from

SLEEP

PWR

TE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024T

OSC 1024TOSC 72 ms + 1024TOSC 1024TOSC

RC 72 ms — 72 ms —

POR

BOR TO PD

0x11Power-on Reset 0x0xIllegal, T

O is set on POR

0xx0Illegal, PD is set on POR 1011Brown-out Reset 1101WDT Reset 1100WDT Wake-up 11uuMCLR

Reset during normal operation

1110MCLR

Reset during SLEEP or interrupt wake-up from SLEEP

Condition

Program

Counter

STATUS

PCON

Power-on Reset 000h 0001 1xxx ---- --0x MCLR

Reset during normal operation 000h 000u uuuu ---- --uu

MCLR

Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset 000h 0001 1uuu ---- --u0 Interrupt wake-up from SLEEP PC + 1

(1)

uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 61

TABLE 10-6 INITIALIZATION CONDITIONS FOR ALL REGISTERS

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

Wake-up via WDT or

Interrupt

W 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu INDF 62B 72A N/A N/A N/A TMR0 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PCL 62B 72A 0000h 0000h

PC + 1

(2)

STATUS 62B 72A 0001 1xxx

000q quuu

(3)

uuuq quuu

(3)

FSR 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu PORTA

(4)

62B 72A --0x 0000 --0u 0000 --uu uuuu

PORTB

(5)

62B 72A xxxx xxxx uuuu uuuu uuuu uuuu

PORTC

(5)

62B 72A xxxx xxxx uuuu uuuu uuuu uuuu

PCLATH 62B 72A ---0 0000 ---0 0000 ---u uuuu INTCON 62B 72A 0000 000x 0000 000u

uuuu uuuu

(1)

PIR1

62B

72A ---- 0000 ---- 0000

---- uuuu

(1)

62B 72A -0-- 0000 -0-- 0000

-u-- uuuu

(1)

TMR1L 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu T1CON 62B 72A --00 0000 --uu uuuu --uu uuuu TMR2 62B 72A 0000 0000 0000 0000 uuuu uuuu T2CON 62B 72A -000 0000 -000 0000 -uuu uuuu SSPBUF 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 62B 72A 0000 0000 0000 0000 uuuu uuuu CCPR1L 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 62B 72A xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 62B 72A --00 0000 --00 0000 --uu uuuu ADRES

62B 72A xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0

62B 72A 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 62B 72A 1111 1111 1111 1111 uuuu uuuu TRISA 62B 72A --11 1111 --11 1111 --uu uuuu TRISB 62B 72A 1111 1111 1111 1111 uuuu uuuu TRISC 62B 72A 1111 1111 1111 1111 uuuu uuuu

PIE1

62B

72A ---- 0000 ---- 0000 ---- uuuu

62B 72A -0-- 0000 -0-- 0000 -u-- uuuu PCON 62B 72A ---- --0q ---- --uq ---- --uq PR2 62B 72A 1111 1111 1111 1111 1111 1111 SSPADD 62B 72A 0000 0000 0000 0000 uuuu uuuu SSPSTAT 62B 72A 0000 0000 0000 0000 uuuu uuuu ADCON1

62B 72A ---- -000 ---- -000 ---- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 10-5 for reset value for speciﬁc condition.

4: On any device reset, these pins are conﬁgured as inputs. 5: This is the value that will be in the port output latch.

PIC16C62B/72A

DS35008A-page 62 Preliminary  1998 Microchip Technology Inc.

FIGURE 10-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 10-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR

NOT TIED TO VDD): CASE 1

FIGURE 10-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 63

FIGURE 10-10: SLOW RISE TIME (MCLR TIED TO VDD)

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

PIC16C62B/72A

DS35008A-page 64 Preliminary  1998 Microchip Technology Inc.

10.10 Interrupts

The PIC16C62B/72A devices have up to 7 sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in ﬂag bits. It also has individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt’s ﬂag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overﬂow interrupt ﬂags are contained in the INTCON register.

The peripheral interrupt ﬂags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON.

When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts.

For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit

FIGURE 10-11: INTERRUPT LOGIC

Note: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding mask bit or the GIE bit.

ADIF

(1)

ADIE

(1)

SSPIF SSPIE

CCP1IF CCP1IE

TMR2IF TMR2IE

TMR1IF TMR1IE

T0IF T0IE

INTF INTE

RBIF RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

Note 1: A/D not implemented on the PIC16C62B.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 65

10.10.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, ﬂag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 10.13 for details on SLEEP mode.

10.10.2 TMR0 INTERRUPT An overﬂow (FFh → 00h) in the TMR0 register will set

ﬂag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 4.0)

10.10.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets ﬂag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2)

10.11 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to sa v e k e y registers during an interrupt, i.e., W register and STATUS register. This will have to be implemented in software.

Example 10-1 stores and restores the W and STATUS registers. The register, W_TEMP, must be deﬁned in each bank and must be deﬁned at the same offset from the bank base address (i.e., if W_TEMP is deﬁned at 0x20 in bank 0, it must also be deﬁned at 0xA0 in bank

1). The example: a) Stores the W register.

b) Stores the STATUS register in bank 0. c) Stores the PCLATH register. d) Executes the interrupt service routine code

(User-generated).

e) Restores the STATUS register (and bank select

bit).

f) Restores the W and PCLATH registers.

EXAMPLE 10-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page BCF STATUS, IRP ;Return to Bank 0 MOVF FSR, W ;Copy FSR to W MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP : :(ISR) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W

PIC16C62B/72A

DS35008A-page 66 Preliminary  1998 Microchip Technology Inc.

10.12 Watchdog Timer (WDT)

The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction.

During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The T

O bit in the STATUS register

will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing

conﬁguration bit WDTE (Section 10.1).

WDT time-out period values may be found in the Electrical Speciﬁcations section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register.

FIGURE 10-12: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 10-13: SUMMARY OF WATCHDOG TIMER REGISTERS

Note: The CLRWDT and SLEEP instructions clear

the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.

Note: When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Conﬁg. bits

(1)

BODEN

(1)

CP1 CP0

PWRTE

(1)

WDTE FOSC1 FOSC0

81h

OPTION_REG

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 10-1 for operation of these bits.

From TMR0 Clock Source (Figure 4-2)

To TMR0 (Figure 4-2)

Postscaler

WDT Timer

WDT

Enable Bit

0 1

M U X

PSA

8 - to - 1 MUX

PS2:PS0

MUX

PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION_REG register.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 67

10.13 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but keeps running, the PD

bit (STATUS<3>) is cleared, the

O (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).

For lowest current consumption in this mode, place all I/O pins at either V

DD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to av oid switching currents caused by ﬂoating inputs. The T0CKI input should also be at V

DD or VSS for lowest

current consumption. The contribution from on-chip pull-ups on PORTB should be considered.

The MCLR

pin must be at a logic high level (VIHMC).

10.13.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of

the following events:

1. External reset input on MCLR

pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change, or some

Peripheral Interrupts.

External MCLR

Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The T

O and PD bits in the STATUS register can be used to determine the cause of device reset. The PD

bit, which is set on

power-up, is cleared when SLEEP is invoked. The T

O bit is cleared if a WDT time-out occurred (and caused wake-up).

The following peripheral interrupts can wake the de vice from SLEEP:

1. TMR1 interrupt. Timer1 must be operating as

an asynchronous counter.

2. CCP capture mode interrupt.

3. Special event trigger (Timer1 in asynchronous

mode using an external clock).

4. SSP (Start/Stop) bit detect interrupt.

5. SSP transmit or receive in slave mode (SPI/I

C).

6. USART RX or TX (synchronous slave mode).

Other peripherals cannot generate interrupts since during SLEEP, no on-chip clocks are present.

When the SLEEP instruction is being executed, the ne xt instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instr uction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

10.13.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit and interrupt ﬂag bit set, one of the following will occur:

• If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the T

O bit will not

be set and PD

bits will not be cleared.

• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the T

O bit will be set and the PD bit will

be cleared.

Even if the ﬂag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD

bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

PIC16C62B/72A

DS35008A-page 68 Preliminary  1998 Microchip Technology Inc.

FIGURE 10-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT

10.14 Pr

ogram Veriﬁcation/Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

10.15 ID Locations

Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identiﬁcation numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least signiﬁcant bits of the ID location are used.

For ROM devices, these values are submitted along with the ROM code.

10.16 In-Circuit Serial Programming™

PIC16CXXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmware or a custom ﬁrmware to be programmed.

For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSP™) Guide, DS30277.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTR

UCTION FLOW

Instruction fetched

Instruction executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

OST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: T

OST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.

Note: Microchip does not recommend code pro-

tecting windowed devices.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 69

11.0 INSTRUCTION SET SUMMARY

Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which speciﬁes the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 11-2 lists byte-oriented, bit-ori- ented, and literal and control operations. Table 11-1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator speciﬁes which ﬁle register is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register . If 'd' is one , the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.

TABLE 11-1 OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped into three basic categories:

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction

execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

Table 11-2 lists the instructions recognized by the MPASM assembler.

Figure 11-1 shows the general formats that the instructions can have.

All examples use the following format to represent a hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 11-1: GENERAL FORMAT FOR

INSTRUCTIONS

A description of each instruction is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

Field Description

f Register ﬁle address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label x Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

d Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f. Default is d = 1

PC Program Counter TO

Time-out bit

PD Power-down bit Z Zero bit DC Digit Carry bit C Carry bit

Note: To maintain upward compatibility with

future PIC16CXXX products, do not use the OPTION and TRIS instructions.

Byte-oriented ﬁle register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 7-bit ﬁle register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC16C62B/72A

DS35008A-page 70 Preliminary  1998 Microchip Technology Inc.

TABLE 11-2 PIC16CXXX INSTRUCTION SET

Mnemonic, Operands

Description Cycles 14-Bit Opcode Status

Affected

Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF

ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

f, d f, d f

f, d f, d f, d f, d f, d f, d f, d f

f, d f, d f, d f, d f, d

Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f

1 1 1 1 1 1

1(2)

1 1 1 1 1 1 1 1 1

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff

ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

C,DC,Z Z Z Z Z Z

Z Z

C C C,DC,Z

1,2 1,2 2

1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2

1,2 1,2 1,2 1,2 1,2

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

f, b f, b f, b f, b

Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set

1 1 (2) 1 (2)

01 01 01 01

00bb 01bb 10bb 11bb

bfff bfff bfff bfff

ffff ffff ffff ffff

1,2 1,2 3 3

LITERAL AND CONTROL OPERATIONS ADDLW

ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW

k k k

k k

Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W

11 11 10 00 10 11 11 00 11 00 00 11 11

111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010

kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk

kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

C,DC,Z Z

O,PD

TO,PD C,DC,Z Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

 1998 Microchip Technology Inc. DS35008A-page 71

PIC16C62B/72A

12.0 DEVELOPMENT SUPPORT

12.1 Development Tools

The PICmicrο microcontrollers are supported with a full range of hardware and software dev elopment tools:

• MPLAB™-ICE Real-Time In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

• PRO MATE



II Universal Programmer

• PICSTART



Plus Entry-Level Prototype

Programmer

• SIMICE

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System (

fuzzy

TECH−MP)

•K

EELOQ

Evaluation Kits and Programmer

12.2 MPLAB-ICE: High Performance

Universal In-Circuit Emulator with MPLAB IDE

The MPLAB-ICE Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). MPLAB-ICE is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable processor modules allow the system to be easily reconﬁgured for emulation of different processors. The universal architecture of the MPLAB-ICE allows expansion to support all new Microchip microcontrollers.

The MPLAB-ICE Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows



3.x or Windows 95 environment were chosen to best make these features available to you, the end user.

MPLAB-ICE is available in two versions. MPLAB-ICE 1000 is a basic, low-cost emulator system with simple trace capabilities. It shares processor modules with the MPLAB-ICE 2000. This is a full-featured emulator system with enhanced trace, trigger, and data monitoring features. Both systems will operate across the entire operating speed reange of the PICmicro MCU.

12.3 ICEPIC: Low-Cost PICmicro™ In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 386 through Pentium based machines under Windows 3.x, Windows 95, or Windows NT environment. ICEPIC features real time, nonintrusive emulation.

12.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant.

The PRO MATE II has programmable V

DD and VPP

supplies which allows it to verify programmed memory at V

DD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set conﬁguration and code-protect bits in this mode.

12.5 PICSTART Plus Entry Level Development System

The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICSTART Plus is not recommended for production programming.

PICST AR T Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.

12.6 SIMICE Entry-Level Hardware Simulator

SIMICE is an entry-level hardware development system designed to operate in a PC-based environment with Microchip’s simulator MPLAB™-SIM. Both SIMICE and MPLAB-SIM run under Microchip Technology’s MPLAB Integrated Development Environment (IDE) software. Speciﬁcally, SIMICE provides hardware simulation for Microchip’s PIC12C5XX, PIC12CE5XX, and PIC16C5X families of PICmicro™ 8-bit microcontrollers. SIMICE works in conjunction with MPLAB-SIM to provide non-real-time I/O port emulation. SIMICE enables a developer to run simulator code for driving the target system. In addition, the target system can

PIC16C62B/72A

DS35008A-page 72  1998 Microchip Technology Inc.

provide input to the simulator code. This capability allows for simple and interactive debugging without having to manually generate MPLAB-SIM stimulus ﬁles. SIMICE is a valuable debugging tool for entrylevel system development.

12.7 PICDEM-1 Low-Cost PICmicro Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test ﬁrmware. The user can also connect the PICDEM-1 board to the MPLAB-ICE emulator and download the ﬁrmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

12.8 PICDEM-2 Low-Cost PIC16CXX Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test ﬁrmware. The MPLAB-ICE emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the f eatures include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I

C bus and separate headers for connec-

tion to an LCD module and a keypad.

12.9 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test ﬁrmware. The MPLAB-ICE emulator may also be used with the PICDEM-3 board to test ﬁrmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

12.10 MPLAB Integrated Development Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.

 1998 Microchip Technology Inc. DS35008A-page 73

PIC16C62B/72A

12.11 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It suppor ts all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly , and se ver al source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.

MPASM allows full symbolic debugging from MPLABICE, Microchip’s Universal Emulator System.

MPASM has the following features to assist in developing software for speciﬁc use applications.

• Provides translation of Assembler source code to object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source and listing formats.

MPASM provides a rich directive language to suppor t programming of the PICmicro. Directives are helpful in making the development of your assemb le source code shorter and more maintainable.

12.12 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step , ex ecute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging using MPLAB-C17 and MPASM. The Software Simulator offers the low cost ﬂexibility to de v elop and deb ug code outside of the laboratory environment making it an excellent multi-project software development tool.

12.13 MPLAB-C17 Compiler

The MPLAB-C17 Code Development System is a complete ANSI ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.

12.14 Fuzzy Logic Development System (

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version,

fuzzy

TECH-MP, Edition for imple-

menting more complex systems. Both versions include Microchip’s

fuzzy

LAB demonstration board for hands-on experience with fuzzy logic systems implementation.

12.15 SEEVAL Evaluation and

Programming System

The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

12.16 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

PIC16C62B/72A

DS35008A-page 74  1998 Microchip Technology Inc.

TABLE 12-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX

24CXX

25CXX

93CXX

HCS200

HCS300

HCS301

Emulator Products

MPLAB™-ICE

ьььььььььь

ICEPIC Low-Cost

In-Circuit Emulator

ьььььь

Software Tools

MPLAB

Integrated

Development

Environment

ьььььььььь

MPLAB C17*

Compiler

üü

fuzzy

TECH



-MP

Explorer/Edition

Fuzzy Logic

Dev. Tool

ььььььььь

Total Endurance

Software Model

Programmers

PICSTART



Plus

Low-Cost

Universal Dev. Kit

ьььььььььь

PRO MATE



Universal

Programmer

ьььььььььььь

KEELOQ



Programmer

Demo Boards

SEEVAL



Designers Kit

SIMICE

üü

PICDEM-14A

PICDEM-1

üü ü ü

PICDEM-2

üü

PICDEM-3

EELOQ

Evaluation Kit

EELOQ

Transponder Kit

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 75

13.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

(†)

Ambient temperature under bias............................................................................................................ .-55˚C to +125˚C

Storage temperature.............................................................................................................................. -65˚C to +150˚C

Voltage on any pin with respect to V

SS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)

Voltage on V

DD with respect to VSS ......................................................................................................... -0.3V to +7.5V

Voltage on MCLR

with respect to VSS (Note 2)..........................................................................................0V to +13.25V

Voltage on RA4 with respect to Vss...............................................................................................................0V to +8.5V

Total power dissipation (Note 1)................................................................................................................................1.0W

Maximum current out of V

SS pin ...........................................................................................................................300 mA

Maximum current into V

DD pin..............................................................................................................................250 mA

Input clamp current, I

IK (VI < 0 or VI > VDD)......................................................................................................................±20 mA

Output clamp current, I

OK (VO < 0 or VO > VDD)..............................................................................................................±20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA and PORTB (combined).................................................................................200 mA

Maximum current sourced by PORTA and PORTB (combined)............................................................................200 mA

Maximum current sunk by PORTC........................................................................................................................200 mA

Maximum current sourced by PORTC..................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = V

DD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

Note 2: Voltage spikes below V

SS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up .

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR

/VPP pin rather

than pulling this pin directly to V

SS.

TABLE 13-1 CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR MODES AND

FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

OSC

PIC16C62B-04 PIC16C72A-04

PIC16C62B-20 PIC16C72A-20

PIC16LC62B-04 PIC16LC72A-04

Windowed (JW) Devices

VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V I

PD: 16 µA max. at 4V

Freq: 4 MHz max.

VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V I

PD: 1.5 µA typ. at 4V

Freq: 4 MHz max.

DD: 2.5V to 5.5V

IDD: 3.8 mA max. at 3V I

PD: 5 µA max. at 3V

Freq: 4 MHz max.

DD: 2.5V to 5.5V

IDD: 3.8 mA max. at 3V I

PD: 5 µA max. at 3V

Freq: 4 MHz max.

VDD: 4.0V to 5.5V IDD: 5 mA max. at 5.5V IPD: 16 µA max. at 4V Freq: 4 MHz max.

VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 µA typ. at 4V Freq: 4 MHz max.

VDD: 2.5V to 5.5V IDD: 3.8 mA max. at 3V IPD: 5 µA max. at 3V Freq: 4 MHz max.

VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V

Not recommended for use in

HS mode

VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 20 mA max. at 5.5V IDD: 20 mA max. at 5.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V Freq: 4 MHz max. Freq: 20 MHz max. Freq: 20 MHz max.

VDD: 4.0V to 5.5V IDD: 52.5 µA typ.

at 32 kHz, 4.0V IPD: 0.9 µA typ. at 4.0V Freq: 200 kHz max.

Not recommended for use in

LP mode

VDD: 2.5V to 5.5V IDD: 48 µA max. at 32 kHz,

3.0V IPD: 5 µA max. at 3.0V Freq: 200 kHz max.

VDD: 2.5V to 5.5V IDD: 48 µA max. at 32 kHz,

3.0V IPD: 5 µA max. at 3.0V Freq: 200 kHz max.

The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX speciﬁcations. It is recommended that the user select the device type that ensures the speciﬁcations required.

PIC16C62B/72A

DS35008A-page 76 Preliminary  1998 Microchip Technology Inc.

13.1 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ T

A ≤ +70˚C for commercial

-40˚C ≤ T

A ≤ +85˚C for industrial

-40˚C ≤ T

A ≤ +125˚C for extended

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

D001 D001A

DD Supply V oltage 4.0

4.5

BOR*

5.5

V V V

XT, RC and LP osc mode HS osc mode BOR enabled (Note 7)

D002* V

DR RAM Data Retention

Voltage (Note 1)

- 1.5 - V

D003 V

POR VDD Start Voltage to

ensure internal Power-on Reset signal

-VSS - V See section on Power-on Reset for details

D004* D004A*

VDD VDD Rise Rate to

ensure internal Power-on Reset signal

0.05 TBD--

--V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWR

TE bit set)

See section on Power-on Reset for details

D005 V

BOR Brown-out Reset

voltage trip point

3.65 - 4.35 V BODEN bit set

D010

D013

DD Supply Current

(Note 2, 5)

2.710520mAmAXT, RC osc modes F

OSC = 4 MHz, VDD = 5.5V (Note 4)

HS osc mode F

OSC = 20 MHz, VDD = 5.5V

D020 D021

D021B

PD Power-down Current

(Note 3, 5)

10.5

1.5

2.5

42 16 19 19

µA µA µA µA

DD = 4.0V, WDT enabled,-40°C to +85°C

DD = 4.0V, WDT disabled, 0°C to +70°C

DD = 4.0V, WDT disabled,-40°C to +85°C

DD = 4.0V, WDT disabled,-40°C to +125°C

D022* D022A*

∆I

WDT

∆IBOR

Module Differential Current (Note 6)

Watchdog Timer Brown-out Reset

6.0

TBD20200µAµA

WDTE bit set, V

DD = 4.0V

BODEN bit set, V

DD = 5.0V

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: This is the limit to which V

DD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V

DD,

MCLR

= VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD and VSS.

4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by

the formula Ir = V

DD/2Rext (mA) with Rext in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the speciﬁcation. This value is from charac-

terization and is for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base I

DD or IPD measurement.

7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will

operate correctly to this trip point.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 77

13.2 DC Characteristics: PIC16LC62B/72A-04 (Commercial, Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ TA ≤ +70˚C for commercial

-40˚C ≤ T

A ≤ +85˚C for industrial

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

D001 V

DD Supply V oltage 2.5

BOR*

5.5

5.5VV

LP, XT, RC osc modes (DC - 4 MHz) BOR enabled (Note 7)

D002* V

DR RAM Data Retention

Voltage (Note 1)

- 1.5 - V

D003 V

POR VDD Start Voltage to

ensure internal Power-on Reset signal

-VSS - V See section on Power-on Reset for details

D004* D004A*

VDD VDD Rise Rate to

ensure internal Power-on Reset signal

0.05

TBD--

--V/ms PWRT enabled (PWRTE bit clear) PWRT disabled (PWR

TE bit set)

See section on Power-on Reset for details

D005 V

BOR Brown-out Reset

voltage trip point

3.65 - 4.35 V BODEN bit set

D010

D010A

DD Supply Current

(Note 2, 5)

2.0

22.5

3.848mAµAXT, RC osc modes F

OSC = 4 MHz, VDD = 3.0V (Note 4)

LP osc mode F

OSC = 32 kHz, VDD = 3.0V, WDT disabled

D020 D021 D021A

PD Power-down Current

(Note 3, 5)

7.5

0.9

5 5

µA µA µA

VDD = 3.0V, WDT enabled, -40°C to +85°C V

DD = 3.0V, WDT disabled, 0°C to +70°C

DD = 3.0V, WDT disabled, -40°C to +85°C

D022* D022A*

∆I

WDT

∆IBOR

Module Differential Current (Note 6)

Watchdog Timer Brown-out Reset

6.0

TBD20200µAµA

WDTE bit set, V

DD = 4.0V

BODEN bit set, V

DD = 5.0V

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: This is the limit to which V

DD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V

DD,

MCLR

= VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD and VSS.

4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by

the formula Ir = V

DD/2Rext (mA) with Rext in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the speciﬁcation. This value is from charac-

terization and is for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base I

DD or IPD measurement.

7: This is the voltage where the device enters the Brown-out Reset. When BOR is enabled, the device will

operate correctly to this trip point.

PIC16C62B/72A

DS35008A-page 78 Preliminary  1998 Microchip Technology Inc.

13.3 DC Characteristics: PIC16C62B/72A-04 (Commercial, Industrial, Extended) PIC16C62B/72A-20 (Commercial, Industrial, Extended) PIC16LC62B/72A-04 (Commercial, Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ T

A ≤ +70˚C for commercial

-40˚C ≤ T

A ≤ +85˚C for industrial

-40˚C ≤ T

A ≤ +125˚C for extended

Operating voltage V

DD range as described in DC spec Section 13.1

and Section 13.2

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

Input Low Voltage

IL I/O ports

D030 D030A

with TTL buffer V

VSS

--0.15VDD

0.8V

VVFor entire V

DD range

4.5V ≤ V

DD ≤ 5.5V

D031 with Schmitt Trigger buffer V

SS - 0.2VDD V

D032 MCLR

, OSC1 (in RC mode) Vss - 0.2VDD V

D033 OSC1 (in XT, HS and LP

modes)

Vss - 0.3V

DD V Note1

Input High Voltage

IH I/O ports -

D040 with TTL buffer 2.0 - V

DD V 4.5V ≤ VDD ≤ 5.5V

D040A 0.25V

+ 0.8V

-VDD V For entire VDD range

D041 with Schmitt Trigger buffer 0.8V

DD -VDD V For entire VDD range

D042 MCLR

0.8VDD -VDD V

D042A OSC1 (XT, HS and LP modes) 0.7V

DD -VDD V Note1

D043 OSC1 (in RC mode) 0.9V

DD -VDD V

Input Leakage Current (Notes 2, 3)

D060 I

IL I/O ports - - ±1 µA Vss ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061 MCLR

, RA4/T0CKI - - ±5 µA Vss ≤ VPIN ≤ VDD

D063 OSC1 - - ±5 µA Vss ≤ VPIN ≤ VDD,

XT, HS and LP osc modes

D070 I

PURB PORTB weak pull-up current 50 250 400 µAVDD = 5V, VPIN = VSS

Output Low Voltage

D080 V

OL I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

- - 0.6 V I

OL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

D083 OSC2/CLKOUT

(RC osc mode)

- - 0.6 V I

OL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

- - 0.6 V I

OL = 1.2 mA, VDD = 4.5V,

-40°C to +125°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-

cro be driven with external clock in RC mode.

2: The leakage current on the MCLR

/VPP pin is strongly dependent on the applied voltage level. The speciﬁed levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as current sourced by the pin.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 79

Output High Voltage

D090 V

OH I/O ports (Note 3) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

DD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

D092 OSC2/CLKOUT (RC osc

mode)

DD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

DD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V,

-40°C to +125°C

D150* V

OD Open-Drain High Voltage - - 8.5 V RA4 pin

Capacitive Loading Specs on Output Pins

D100 C

OSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when

external clock is used to drive OSC1.

D101 C

IO All I/O pins and OSC2 (in RC

mode)

- - 50 pF

D102 Cb

SCL, SDA in I

C mode

- - 400 pF

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ T

A ≤ +70˚C for commercial

-40˚C ≤ T

A ≤ +85˚C for industrial

-40˚C ≤ T

A ≤ +125˚C for extended

Operating voltage V

DD range as described in DC spec Section 13.1

and Section 13.2

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi-

cro be driven with external clock in RC mode.

2: The leakage current on the MCLR

/VPP pin is strongly dependent on the applied voltage level. The speciﬁed levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as current sourced by the pin.

PIC16C62B/72A

DS35008A-page 80 Preliminary  1998 Microchip Technology Inc.

13.4 AC (Timing) Characteristics

13.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created fol-

lowing one of the following formats:

1. TppS2ppS

3. T

CC:ST (I

C speciﬁcations only)

2. TppS

4. Ts (I

C speciﬁcations only)

F Frequency T Time Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR

wr WR

Uppercase letters and their meanings:

F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance

C only

AA output access High High BUF Bus free Low Low

CC:ST (I

C speciﬁcations only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition STA START condition

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 81

13.4.2 TIMING CONDITIONS The temperature and voltages speciﬁed in Table 13-1

apply to all timing speciﬁcations unless otherwise noted. Figure 13-1 speciﬁes the load conditions for the timing speciﬁcations.

TABLE 13-1 TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

FIGURE 13-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ TA ≤ +70˚C for commercial

-40˚C ≤ TA ≤ +85˚C for industrial

-40˚C ≤ TA ≤ +125˚C for extended

Operating voltage V

DD range as described in DC spec Section 13.1 and Section 13.2.

LC parts operate for commercial/industrial temp’s only.

VDD/2

VSS

RL = 464Ω C

L = 50 pF for all pins except OSC2/CLKOUT

15 pF for OSC2 output

Load condition 1

Load condition 2

PIC16C62B/72A

DS35008A-page 82 Preliminary  1998 Microchip Technology Inc.

13.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 13-2: EXTERNAL CLOCK TIMING

TABLE 13-2 EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

1A Fosc External CLKIN Frequency

(Note 1)

DC — 4 MHz RC and XT osc modes DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode

Oscillator Frequency

(Note 1)

DC — 4 MHz RC osc mode

0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode

1 Tosc External CLKIN Period

(Note 1)

250 — — ns RC and XT osc modes 250 — — ns HS osc mode (-04)

50 — — ns HS osc mode (-20)

5— —µs LP osc mode

Oscillator Period

(Note 1)

250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04)

50 — 250 ns HS osc mode (-20)

5— —µs LP osc mode

2TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC

3* TosL,

TosH

External Clock in (OSC1) High or Low Time

100 — — ns XT oscillator

2.5 — — µs LP oscillator

15 — — ns HS oscillator

4* TosR,

TosF

External Clock in (OSC1) Rise or Fall Time

— — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: Instruction cycle period (T

CY) equals four times the input oscillator time-base period. All speciﬁed values are

based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. All de vices are tested to oper ate at "min." v alues with an e xternal clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

Q1 Q2 Q3 Q4

OSC1

CLKOUT

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 83

FIGURE 13-3: CLKOUT AND I/O TIMING

TABLE 13-3 CLKOUT AND I/O TIMING REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1 11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5T

CY + 20 ns Note 1

15* TioV2ckH Port in valid before CLKOUT ↑ Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1 17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1↑ (Q2 cycle) to Port input

invalid (I/O in hold time)

Standard 100 — — ns

18A* Extended (LC) 200 — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20* TioR Port output rise time Standard — 10 40 ns

20A* Extended (LC) — — 80 ns

21* TioF Port output fall time Standard — 10 40 ns

21A* Extended (LC) — — 80 ns 22††* Tinp INT pin high or low time TCY ——ns 23††* Trbp RB7:RB4 change INT high or low time TCY ——ns

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

†† These parameters are asynchronous events not related to any internal clock edge.

Note1: Measurements are taken in RC Mode where CLKOUT output is 4 x T

OSC.

Note: Refer to Figure 13-1 for load conditions.

OSC1

CLKOUT

I/O Pin (input)

I/O Pin (output)

Q2 Q3

20, 21

old value

new value

PIC16C62B/72A

DS35008A-page 84 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

FIGURE 13-5: BROWN-OUT RESET TIMING

TABLE 13-4 RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 — —

µs VDD = 5V, -40˚C to +125˚C

31* T wdt Watchdog Timer Time-out Period

(No Prescaler)

71833ms

VDD = 5V, -40˚C to +125˚C

32 Tost Oscillation Start-up Timer Period — 1024 T

OSC ——

TOSC = OSC1 period

33* Tpwrt Power-up Timer Period 28 72 132 ms

VDD = 5V, -40˚C to +125˚C

34 T

IOZ I/O Hi-impedance from MCLR

Low or WDT reset

— — 2.1

µs

35 T

BOR Brown-out Reset Pulse Width 100 — —

µs

DD ≤ BVDD (D005)

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

Note: Refer to Figure 13-1 for load conditions.

VDD

BVDD

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 85

FIGURE 13-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 13-5 TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI High Pulse Width No Prescaler 0.5T

CY + 20 — — ns Must also meet

parameter 42

With Prescaler 10 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5T

CY + 20 — — ns Must also meet

parameter 42

With Prescaler 10 — — ns

42* Tt0P T0CKI Period

No Prescaler

TCY + 40 — — ns

With Prescaler

Greater of: 20 or T

CY + 40

— — ns N = prescale value

(2, 4,..., 256)

45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5T

CY + 20 — — ns Must also meet

parameter 47

Synchronous, Prescaler = 2,4,8

Standard

15 — — ns

Extended (LC)

25 — — ns

Asynchronous

Standard

30 — — ns

Extended (LC)

50 — — ns

46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5T

CY + 20 — — ns Must also meet

parameter 47

Synchronous, Prescaler = 2,4,8

Standard

15 — — ns

Extended (LC)

25 — — ns

Asynchronous

Standard

30 — — ns

Extended (LC)

50 — — ns

47* Tt1P T1CKI input period Synchronous

Standard

Greater of:

30 OR TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Extended (LC)

Greater of:

50 OR TCY + 40

N = prescale value (1, 2, 4, 8)

Asynchronous

Standard

60 — — ns

Extended (LC)

100 — — ns

Ft1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN)

DC — 200 kHz

48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc —

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 13-1 for load conditions.

T0CKI

T1OSO/T1CKI

TMR0 or TMR1

PIC16C62B/72A

DS35008A-page 86 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-7: CAPTURE/COMPARE/PWM TIMINGS

TABLE 13-6 CAPTURE/COMPARE/PWM REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

50*

TccL CCP1 input low

time

No Prescaler 0.5TCY + 20 — — ns With Prescaler Standard 10 — — ns

Extended (LC) 20 — — ns

51* TccH

CCP1 input high time

No Prescaler 0.5TCY + 20 — — ns With Prescaler Standard 10 — — ns

Extended (LC) 20 — — ns

52* TccP

CCP1 input period

3TCY + 40N— — ns N = prescale value

(1,4, or 16)

53* TccR CCP1 output rise time Standard — 10 25 ns

Extended (LC) — 25 45 ns

54* TccF CCP1 output fall time Standard — 10 25 ns

Extended (LC) — 25 45 ns

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 13-1 for load conditions.

CCP1

(Capture Mode)

50 51

CCP1

(Compare or PWM Mode)

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 87

FIGURE 13-8: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 13-7 EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.

No.

Symbol Characteristic Min Typ† Max Units Conditions

TssL2scH, TssL2scL

SS↓ to SCK↓ or SCK↑ input TCY ——ns

TscH SCK input high time

(slave mode)

Continuous 1.25TCY + 30 — — ns

71A

Single Byte 40 — — ns Note 1

TscL SCK input low time

(slave mode)

Continuous 1.25TCY + 30 — — ns

72A

Single Byte 40 — — ns Note 1

TdiV2scH, TdiV2scL

Setup time of SDI data input to SCK edge 100 — — ns

73A

TB2B Last clock edge of Byte1 to the 1st clock

edge of Byte2

1.5TCY + 40 — — ns Note 1

TscH2diL, TscL2diL

Hold time of SDI data input to SCK edge 100 — — ns

TdoR SDO data output rise time Standard — 10 25 ns

Extended (LC) — 20 45 ns

TdoF SDO data output fall time — 10 25 ns

TscR SCK output rise time

(master mode)

Standard — 10 25 ns Extended (LC) — 20 45 ns

TscF SCK output fall time (master mode) — 10 25 ns

TscH2doV, TscL2doV

SDO data output valid after SCK edge

Standard — — 50 ns Extended (LC) — — 100 ns

† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: Speciﬁcation 73A is only required if speciﬁcations 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb LSb

BIT6 - - - - - -1

MSb IN

LSb IN

BIT6 - - - -1

Refer to Figure 13-1 for load conditions.

PIC16C62B/72A

DS35008A-page 88 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

TABLE 13-8 EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

No.

Symbol Characteristic Min Typ† Max Units Conditions

TscH SCK input high time

(slave mode)

Continuous 1.25TCY + 30 — — ns

71A

Single Byte 40 — — ns Note 1

TscL SCK input low time

(slave mode)

Continuous 1.25TCY + 30 — — ns

72A

Single Byte 40 — — ns Note 1

TdiV2scH, TdiV2scL

Setup time of SDI data input to SCK edge

100 — — ns

73A

TB2B Last clock edge of Byte1 to the 1st clock

edge of Byte2

1.5TCY + 40 — — ns Note 1

TscH2diL, TscL2diL

Hold time of SDI data input to SCK edge 100 — — ns

TdoR SDO data output rise

time

Standard — 10 25 ns Extended (LC) 20 45 ns

TdoF SDO data output fall time — 10 25 ns

TscR SCK output rise time

(master mode)

Standard — 10 25 ns Extended (LC) 20 45 ns

TscF SCK output fall time (master mode) — 10 25 ns

TscH2doV, TscL2doV

SDO data output valid after SCK edge

Standard — — 50 ns Extended (LC) — 100 ns

TdoV2scH, TdoV2scL

SDO data output setup to SCK edge TCY ——ns

† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note1: Speciﬁcation 73A is only required if speciﬁcations 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

MSb IN

BIT6 - - - - - -1

LSb IN

BIT6 - - - -1

LSb

Refer to Figure 13-1 for load conditions.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 89

FIGURE 13-10: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 13-9 EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)

Param.

No.

Symbol Characteristic Min Typ† Max Units Conditions

TssL2scH, TssL2scL

SS↓ to SCK↓ or SCK↑ input TCY ——ns

TscH SCK input high time

(slave mode)

Continuous 1.25TCY + 30 — — ns

71A

Single Byte 40 — — ns Note 1

TscL SCK input low time

(slave mode)

Continuous 1.25TCY + 30 — — ns

72A

Single Byte 40 — — ns Note 1

TdiV2scH, TdiV2scL

Setup time of SDI data input to SCK edge 100 — — ns

73A

TB2B Last clock edge of Byte1 to the 1st clock

edge of Byte2

1.5TCY + 40 — — ns Note 1

TscH2diL, TscL2diL

Hold time of SDI data input to SCK edge 100 — — ns

TdoR SDO data output rise time Standard — 10 25 ns

Extended (LC) 20 45 ns

TdoF SDO data output fall time — 10 25 ns

TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns

TscR SCK output rise time

(master mode)

Standard — 10 25 ns Extended (LC) 20 45 ns

TscF SCK output fall time (master mode) — 10 25 ns

TscH2doV, TscL2doV

SDO data output valid after SCK edge

Standard — — 50 ns Extended (LC) — 100 ns

TscH2ssH, TscL2ssH

SS ↑ after SCK edge 1.5TCY + 40 — — ns

† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: Speciﬁcation 73A is only required if speciﬁcations 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

SDI

MSb LSb

BIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

Refer to Figure 13-1 for load conditions.

PIC16C62B/72A

DS35008A-page 90 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 13-10 EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param.

No.

Symbol Characteristic Min Typ† Max Units Conditions

TssL2scH, TssL2scL

SS↓ to SCK↓ or SCK↑ input TCY ——ns

TscH SCK input high time

(slave mode)

Continuous 1.25TCY + 30 — — ns

71A

Single Byte 40 — — ns Note 1

TscL SCK input low time

(slave mode)

Continuous 1.25TCY + 30 — — ns

72A

Single Byte 40 — — ns Note 1

73A

TB2B Last clock edge of Byte1 to the 1st clock

edge of Byte2

1.5TCY + 40 — — ns Note 1

TscH2diL, TscL2diL

Hold time of SDI data input to SCK edge 100 — — ns

TdoR SDO data output rise

time

Standard — 10 25 ns Extended (LC) 20 45 ns

TdoF SDO data output fall time — 10 25 ns

TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns

TscR SCK output rise time

(master mode)

Standard — 10 25 ns Extended (LC) — 20 45 ns

TscF SCK output fall time (master mode) — 10 25 ns

TscH2doV, TscL2doV

SDO data output valid after SCK edge

Standard — — 50 ns Extended (LC) — — 100 ns

TssL2doV SDO data output valid

after SS

↓ edge

Standard — — 50 ns Extended (LC) — — 100 ns

TscH2ssH, TscL2ssH

SS ↑ after SCK edge 1.5TCY + 40 — — ns

† Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: Speciﬁcation 73A is only required if speciﬁcations 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

SDI

75, 76

MSb BIT6 - - - - - -1 LSb

MSb IN BIT6 - - - -1 LSb IN

Refer to Figure 13-1 for load conditions.

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 91

FIGURE 13-12: I2C BUS START/STOP BITS TIMING

TABLE 13-11 I2C BUS START/STOP BITS REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ Max Units Conditions

90* TSU:STA START condition 100 kHz mode 4700 — —

Only relevant for repeated START condition

Setup time 400 kHz mode 600 — —

91* THD:STA START condition 100 kHz mode 4000 — —

After this period the ﬁrst clock pulse is generated

Hold time 400 kHz mode 600 — —

92* TSU:STO STOP condition 100 kHz mode 4700 — —

Setup time 400 kHz mode 600 — —

93 THD:STO STOP condition 100 kHz mode 4000 — —

Hold time 400 kHz mode 600 — —

* These parameters are characterized but not tested.

Note: Refer to Figure 13-1 for load conditions.

SCL

SDA

START

Condition

STOP

Condition

PIC16C62B/72A

DS35008A-page 92 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-13: I2C BUS DATA TIMING

TABLE 13-12 I

C BUS DATA REQUIREMENTS

Parameter

No.

Sym Characteristic Min Max Units Conditions

100* THIGH Clock high time 100 kHz mode 4.0 — µs Device must operate at a mini-

mum of 1.5 MHz

400 kHz mode 0.6 — µs Device must operate at a mini-

mum of 10 MHz

SSP Module 1.5TCY —

101* TLOW Clock low time 100 kHz mode 4.7 — µs Device must operate at a mini-

mum of 1.5 MHz

400 kHz mode 1.3 — µs Device must operate at a mini-

mum of 10 MHz

SSP Module 1.5TCY —

102* TR SDA and SCL rise

time

100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is speciﬁed to be from

10-400 pF

103* TF SDA and SCL fall time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1Cb 300 ns Cb is speciﬁed to be from

10-400 pF

90* TSU:STA START condition

setup time

100 kHz mode 4.7 — µs Only relevant for repeated

START condition

400 kHz mode 0.6 — µs

91* THD:STA START condition hold

time

100 kHz mode 4.0 — µs After this period the ﬁrst clock

pulse is generated

400 kHz mode 0.6 — µs

106* THD:DAT Data input hold time 100 kHz mode 0 — ns

400 kHz mode 0 0.9 µs

107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2

400 kHz mode 100 — ns

92* TSU:STO STOP condition setup

time

100 kHz mode 4.7 — µs 400 kHz mode 0.6 — µs

109* TAA Output valid from

clock

100 kHz mode — 3500 ns Note 1 400 kHz mode — — ns

110* TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free

before a new transmission can start

400 kHz mode 1.3 — µs

Cb Bus capacitive loading — 400 pF

* These parameters are characterized but not tested.

Note1: As a transmitter, the device must provide this internal minimum delay time to bridge the undeﬁned region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I

C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a de vice does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus speciﬁcation) before the SCL line is released.

Note: Refer to Figure 13-1 for load conditions.

91 92

100

101

103

106

107

109

110

102

SCL

SDA In

SDA Out

PIC16C62B/72A



1998 Microchip Technology Inc.

Preliminary

DS35008A-page 93

TABLE 13-13 A/D CONVERTER CHARACTERISTICS:

PIC16C72A-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C72A-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC72A-04 (COMMERCIAL, INDUSTRIAL)

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

A01 N

Resolution — — 8-bits bit V

REF

= V

= 5.12V,

≤

AIN

≤

REF

A02 E

ABS

Total Absolute error

——

< ± 1 LSb

REF

= V

= 5.12V,

≤

AIN

≤

REF

A03 E

Integral linearity error — —

< ± 1 LSb

REF

= V

= 5.12V,

≤

AIN

≤

REF

A04 E

Differential linearity error — —

< ± 1 LSb

REF

= V

= 5.12V,

≤

AIN

≤

REF

A05 E

Full scale error — —

< ± 1 LSb

REF

= V

= 5.12V,

≤

AIN

≤

REF

A06 E

OFF

Offset error — —

< ± 1 LSb

REF

= V

= 5.12V,

≤

AIN

≤

REF

A10 — Monotonicity — guaranteed

(Note 3)

——V

≤

AIN

≤

REF

A20 V

REF

Reference voltage 2.5V — V

+ 0.3 V

A25 V

AIN

Analog input voltage V

- 0.3 — V

REF

+ 0.3 V

A30 Z

AIN

Recommended impedance of analog voltage source

— — 10.0 k Ω

A40 I

A/D conversion current (V

)

Standard — 180 —

A Average current consump-

tion when A/D is on. (Note 1)

Extended (LC) — 90 —

A50 I

REF

input current (Note 2) 10

—

1000

µ A µ

During V

AIN

acquisition. Based on differential of V

HOLD

to V

AIN

to charge

HOLD

, see Section 9.1.

During A/D Conversion cycle

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25 ° C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note1: When A/D is off, it will not consume any current other than minor leakage current.

The power-down current spec includes any such leakage from the A/D module.

2: V

REF

current is from RA3 pin or V

pin, whichever is selected as reference input.

3: The A/D conversion result never decreases with an increase in the Input V oltage , and has no missing codes.

PIC16C62B/72A

DS35008A-page 94 Preliminary  1998 Microchip Technology Inc.

FIGURE 13-14: A/D CONVERSION TIMING

TABLE 13-14 A/D CONVERSION REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period

Standard

1.6 — — µsTOSC based, VREF ≥ 3.0V Extended (LC) 2.0 — — µsTOSC based, VREF full range Standard 2.0 4.0 6.0 µs A/D RC Mode Extended (LC) 3.0 6.0 9.0 µs A/D RC Mode

131 TCNV Conversion time (not including S/H time)

(Note 1)

11 — 11 TAD

132 TACQ Acquisition time Note 25*20

—

µs

µs The minimum time is the ampliﬁer

settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e.,

20.0 mV @ 5.12V) from the last sampled voltage (as stated on C

HOLD).

134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected

as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.

135 TSWC Switching from convert → sample time 1.5 § — — TAD

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

§ This speciﬁcation ensured by design.

Note1: ADRES register may be read on the following TCY cycle.

2: See Section 9.1 for min conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

OSC/2)

(1)

7 6543210

Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This

allows the SLEEP instruction to be executed.

1 Tcy

134

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 95

14.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside speciﬁed operating range (i.e., outside speciﬁed V

range). This is for information only and devices are guaranteed to operate properly only within the speciﬁed range. The data presented in this section is a statistical summary of data collected on units from different lots over a period

of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C. 'Max' or 'min' represents (mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.

Graphs and Tables not available at this time.

Data is not available at this time but you may reference the

PIC16C72 Series Data Sheet

(DS39016) DC and AC char-

acteristic section which contains data similar to what is expected.

PIC16C62B/72A

DS35008A-page 96 Preliminary  1998 Microchip Technology Inc.

NOTES:

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 97

15.0 PACKAGING INFORMATION

15.1 Package Marking Information

28-Lead SOIC

XXXXXXXXXXXXXXXXXXXX

AABBCDE

MMMMMMMMMMMMMMMM

Example

PIC16C62B-20/SO

XXXXXXXXXXXXXXX

AABBCDE

28-Lead PDIP (Skinny DIP)

MMMMMMMMMMMM

Example

PIC16C72A-04/SP

Example28-Lead CERDIP Windowed

XXXXXXXXXXX XXXXXXXXXXX

AABBCDE

PIC16C72A/JW

AABBCDE

XXXXXXXXXXXX

28-Lead SSOP

20I/SS025

PIC16C62B

Example

Legend: MM...M Microchip part number information

XX...X Customer speciﬁc information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured

O = Outside Vendor C = 5” Line S = 6” Line

H = 8” Line D Mask revision number E Assembly code of the plant or country of origin in which

part was assembled

Note: In the event the full Microchip part number cannot be marked on one line,

it will be carried over to the next line thus limiting the number of available characters for customer speciﬁc information.

9817HAT

9817CAT

9810/SAA

9817SBP

* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask

rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Ofﬁce. For QTP devices, any special marking adders are included in QTP price.

XXXXXXXXXXX

PIC16C62B/72A

DS35008A-page 98 Preliminary  1998 Microchip Technology Inc.

15.2 K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil

* Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

0.320

0.270

0.280

1.345

0.125

0.015

0.070

0.140

0.008

0.000

0.040

0.016

Mold Draft Angle Bottom

Mold Draft Angle Top

Overall Row Spacing

Radius to Radius Width

Molded Package Width

Tip to Seating Plane

Base to Seating Plane

Top of Lead to Seating Plane

Top to Seating Plane

Upper Lead Width

Lower Lead Width

PCB Row Spacing

Package Length

Lead Thickness

Shoulder Radius

Number of Pins

Dimension Limits

Pitch

Units

‡

A1 A2 L D

‡

†

MIN MIN

0.2950.288

0.350

0.283

0.380

0.295

0.090

1.365

0.130

0.020

0.150

0.010

0.005

NOM

INCHES*

0.053

0.019

0.100

0.300

1.385

0.135

0.025

0.110

0.160

0.012

0.010

0.065

0.022

MAX

7.497.307.11

8.89

7.18

8.13

6.86

9.65

7.49

34.67

3.30

0.51

2.29

3.81

0.25

0.13

1.33

0.48

2.54

7.62

MILLIMETERS

1.78

34.16

3.18

0.38

3.56

0.20

0.00

1.02

0.41

NOM

2.79

35.18

3.43

0.64

4.06

0.30

0.25

MAX

1.65

0.56

n 1

PIC16C62B/72A

 1998 Microchip Technology Inc. Preliminary DS35008A-page 99

15.3 K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil

* Controlling Parameter.

n 1

Overall Row Spacing

Radius to Radius Width

Package Length

Tip to Seating Plane

Base to Seating Plane

Top of Lead to Seating Plane

Top to Seating Plane

Shoulder Radius

Upper Lead Width

Lower Lead Width

PCB Row Spacing

Dimension Limits

Window Width Window Length

Package Width

Lead Thickness

Pitch

Number of Pins

Units

0.170A

0.130W1

W2 0.290

E1 eB

A2 L

1.430

0.345

0.255

0.285

0.135

0.015

0.107

R c

n p

0.016

0.008

0.010

0.050

0.098

MIN

MILLIMETERS

4.320.1950.183

0.310

0.150

0.425

0.285

0.295

1.485

0.145

0.030

0.143

0.140

0.300

0.385

0.270

0.290

1.458

0.140

0.023

0.125

0.13

0.29

36.32

8.76

6.48

7.24

3.43

0.00

2.72

0.012

0.015

0.065

0.021

0.102

MAXNOM

0.010

0.013

0.058

0.019

0.100

0.300 28

INCHES*

0.41

0.20

0.25

1.27

2.49

MIN

4.954.64

0.31

0.15

10.80

7.24

7.49

37.72

3.68

0.76

3.63

0.14

0.3

37.02

6.86

9.78

7.37

0.57

3.56

3.18

0.30

0.38

1.65

0.53

2.59

NOM

0.47

0.32

0.25

1.46

2.54

7.62

MAX

PIC16C62B/72A

DS35008A-page 100 Preliminary  1998 Microchip Technology Inc.

15.4 K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil

MIN

pPitch

Mold Draft Angle Bottom

Mold Draft Angle Top

Lower Lead Width

Radius Centerline

Gull Wing Radius

Shoulder Radius

Chamfer Distance

Outside Dimension

Molded Package Width

Molded Package Length

Shoulder Height

Overall Pack. Height

Lead Thickness

Foot Angle

Foot Length

Standoff

Number of Pins

†

R1 R2

‡

Dimension Limits

Units

1.270.050

0.017

0.014 0

0.019

0.011

0.015

0.016

0.005

0.020

0.407

0.296

0.706

0.008

0.058

0.099

0.394

0.011

0.009

0.010

0.005

0.010

0.292

0.700

0.004

0.048

0.093

0.419

0.012

0.020

0.021

0.010

0.029

0.299

0.712

0.011

0.068

0.104

0.36

0.42

0.48

10.33

17.93

10.01

0.23

0.25

0.28

0.13

0.25

7.42

0.10

1.22

2.36

17.78

10.64

0.41 4

0.27

0.38

0.13

0.50

0.53

0.30

0.51

0.25

0.74

7.51

0.19

2.50

1.47

18.08

7.59

0.28

2.64

1.73

NOM

INCHES*

MAX NOM

MILLIMETERS

MIN MAX

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

Microchip Technology Inc PIC16C62B-20I-SO, PIC16C62B-20I-SP, PIC16C72A-04I-SO, PIC16C72A-20-SO, PIC16C72A-20I-SO Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual