Microchip Technology Inc PIC16C73-JW, PIC16C73A-04ISO, PIC16C72-JW, PIC16C72A-04-SO, PIC16C72A-04-SP Datasheet

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

1997 Microchip Technology Inc. DS30390E-page 1

PIC16C7X

8-Bit CMOS Microcontrollers with A/D Converter

Devices included in this data sheet:

PIC16C7X Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Up to 8K x 14 words of Program Memory, up to 368 x 8 bytes of Data Memory (RAM)

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• PIC16C72 • PIC16C74A

• PIC16C73 • PIC16C76

• PIC16C73A • PIC16C77

• PIC16C74

• Wide operating voltage range: 2.5V to 6.0V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temperature ranges

• Low-power consumption:

•

< 2 mA @ 5V, 4 MHz

•

15 µ A typical @ 3V, 32 kHz

•

< 1 µ A typical standby current

PIC16C7X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Capture, Compare, PWM module(s)

• Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, PWM max. resolution is 10-bit

• 8-bit multichannel analog-to-digital converter

• Synchronous Serial Port (SSP) with SPI



and I



• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with external RD

, WR and CS controls

• Brown-out detection circuitry for Brown-out Reset (BOR)

PIC16C7X Features 72 73 73A 74 74A 76 77

Program Memory (EPROM) x 14 2K 4K 4K 4K 4K 8K 8K Data Memory (Bytes) x 8 128 192 192 192 192 368 368 I/O Pins 22 22 22 33 33 22 33 Parallel Slave Port — — — Yes Yes — Yes Capture/Compare/PWM Modules 1 222222 Timer Modules 3 333333 A/D Channels 5 558858 Serial Communication SPI/I

C SPI/I

USART

SPI/I

USART

SPI/I

USART

SPI/I

USART

SPI/I

USART

SPI/I

USART In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Yes Brown-out Reset Yes — Yes — Yes Yes Yes Interrupt Sources 8 11 11 12 12 11 12

PIC16C7X

DS30390E-page 2

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1997 Microchip Technology Inc.

Pin Diagrams

PIC16C72

MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA

• 1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SDIP, SOIC, Windowed Side Brazed Ceramic

PIC16C72

MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3/SCK/SCL

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7 RC6 RC5/SDO RC4/SDI/SDA

• 1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

SSOP

PIC16C73

MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/SS/AN4

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

• 1 2 3 4 5 6 7 8 9 10 11 12 13 14

28 27 26 25 24 23 22 21 20 19 18 17 16 15

PIC16C73A

SDIP, SOIC, Windowed Side Brazed Ceramic

PIC16C76

PDIP , Windowed CERDIP

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V

VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2

MCLR/VPP

RA0/AN0 RA1/AN1

RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

RA5/SS

/AN4

RE0/RD

/AN5

RE1/WR/AN6

RE2/CS

/AN7

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0 RD1/PSP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

PIC16C74 PIC16C74A PIC16C77

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1997 Microchip Technology Inc. DS30390E-page 3

PIC16C7X

Pin Diagrams (Cont.’d)

NC RC0/T1OSO/T1CKI

OSC2/CLKOUT OSC1/CLKIN V

VDD RE2/CS/AN7 RE1/WR

/AN6

RE0/RD

/AN5

RA5/SS

/AN4

RA4/T0CKI

RC7/RX/DT

RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

VDD

RB0/INT

RB1 RB2 RB3

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

1 2 3 4 5 6 7 8 9 10 11

33 32 31 30 29 28 27 26 25 24 23

4443424140393837363534

2221201918171615141312

PIC16C74

MQFP

RB3 RB2 RB1 RB0/INT V

VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT

RA4/T0CKI

RA5/SS

/AN4

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS/AN7

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

RB7

RB6

RB5

RB4

7 8 9 10 11 12 13 14 15 16 17

39 38 37 36 35 34 33 32 31 30 29

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

65432

4443424140

2827262524232221201918

PIC16C74

NC RC0/T1OSO/T1CKI

OSC2/CLKOUT OSC1/CLKIN V

VDD RE2/CS/AN7 RE1/WR

/AN6

RE0/RD

/AN5

RA5/SS

/AN4

RA4/T0CKI

RC7/RX/DT

RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

VDD

RB0/INT

RB1 RB2 RB3

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

1 2 3 4 5 6 7 8 9 10 11

33 32 31 30 29 28 27 26 25 24 23

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

RB7

RB6

RB5

RB4

4443424140393837363534

2221201918171615141312

MQFP

PLCC

PIC16C74A

TQFP

PIC16C77

RC1/T1OSI/CCP2

RA3/AN3/V

REF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

RB7

RB6

RB5

RB4

PIC16C7X

DS30390E-page 4

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1997 Microchip Technology Inc.

Table of Contents

1.0 General Description....................................................................................................................................................................... 5

2.0 PIC16C7X Device Varieties...........................................................................................................................................................7

3.0 Architectural Overview................................................................................................................................................................... 9

4.0 Memory Organization................................................................................................................................................................... 19

5.0 I/O Ports....................................................................................................................................................................................... 43

6.0 Overview of Timer Modules......................................................................................................................................................... 57

7.0 Timer0 Module............................................................................................................................................................................. 59

8.0 Timer1 Module............................................................................................................................................................................. 65

9.0 Timer2 Module............................................................................................................................................................................. 69

10.0 Capture/Compare/PWM Module(s).............................................................................................................................................. 71

11.0 Synchronous Serial Port (SSP) Module....................................................................................................................................... 77

12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART)...................................................................................... 99

13.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 117

14.0 Special Features of the CPU ..................................................................................................................................................... 129

15.0 Instruction Set Summary............................................................................................................................................................ 147

16.0 Development Support................................................................................................................................................................ 163

17.0 Electrical Characteristics for PIC16C72..................................................................................................................................... 167

18.0 Electrical Characteristics for PIC16C73/74................................................................................................................................ 183

19.0 Electrical Characteristics for PIC16C73A/74A........................................................................................................................... 201

20.0 Electrical Characteristics for PIC16C76/77................................................................................................................................ 219

21.0 DC and AC Characteristics Graphs and Tables ........................................................................................................................ 241

22.0 Packaging Information............................................................................................................................................................... 251

Appendix A: ................................................................................................................................................................................... 263

Appendix B: Compatibility............................................................................................................................................................. 263

Appendix C: What’s New............................................................................................................................................................... 264

Appendix D: What’s Changed....................................................................................................................................................... 264

Appendix E: PIC16/17 Microcontrollers ....................................................................................................................................... 265

Pin Compatibility ................................................................................................................................................................................ 271

Index .................................................................................................................................................................................................. 273

List of Examples................................................................................................................................................................................. 279

List of Figures..................................................................................................................................................................................... 280

List of Tables...................................................................................................................................................................................... 283

Reader Response.............................................................................................................................................................................. 286

PIC16C7X Product Identification System........................................................................................................................................... 287

For register and module descriptions in this data sheet, device legends show which devices apply to those sections. As an example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and PIC16C74A devices.

Applicable Devices

73 73A 74 74A 76 77

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.



1997 Microchip Technology Inc. DS30390E-page 5

PIC16C7X

1.0 GENERAL DESCRIPTION

The PIC16C7X is a family of

low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family.

All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available . Additionally, a large register set gives some of the architectural innovations used to achie v e a very high performance.

PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

The PIC16C72 has 128 bytes of RAM and 22 I/O pins. In addition several peripheral features are available including: three timer/counters, one Capture/Compare/ PWM module and one serial port. The Synchronous Serial Port can be conﬁgured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I

C) bus. Also a 5-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.

The PIC16C73/73A devices have 192 bytes of RAM, while the PIC16C76 has 368 byes of RAM. Each de vice has 22 I/O pins. In addition, several peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be conﬁgured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I

C) bus. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. Also a 5-channel high-speed 8-bit A/ D is provided.The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.

The PIC16C74/74A devices have 192 bytes of RAM, while the PIC16C77 has 368 bytes of RAM. Each device has 33 I/O pins. In addition several peripheral features are available including: three timer/counters, two Capture/Compare/PWM modules and two serial ports. The Synchronous Serial Port can be conﬁgured as either a 3-wire Serial Peripheral Interface (SPI) or the two-wire Inter-Integrated Circuit (I

C) bus. The Universal Synchronous Asynchronous Receiver Transmitter (USART) is also known as the Serial Communications Interface or SCI. An 8-bit Parallel Slave Port is provided. Also an 8-channel high-speed

8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.

The PIC16C7X family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup.

A UV erasable CERDIP packaged version is ideal for code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume.

The PIC16C7X family fits perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high performance, ease of use and I/O ﬂexibility make the PIC16C7X very versatile ev en in areas where no microcontroller use has been considered before (e.g. timer functions, serial communication, capture and compare, PWM functions and coprocessor applications).

1.1 F

amily and Upward Compatibility

Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).

1.2 De

velopment Support

PIC16C7X devices are supported by the complete line of Microchip Development tools.

Please refer to Section 16.0 for more details about Microchip’s development tools.

PIC16C7X

DS30390E-page 6

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1997 Microchip Technology Inc.

TABLE 1-1: PIC16C7XX FAMILY OF DEVCES

PIC16C710

PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72

(1)

Clock

Maximum Frequency of Operation (MHz)

20 20 20 20 20 20

Memory

EPROM Program Memory (x14 words)

512 1K 1K 2K 2K —

ROM Program Memory (14K words)

—————2K

Data Memory (bytes) 36 36 68 128 128 128

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0,

TMR1, TMR2

TMR0, TMR1, TMR2

Capture/Compare/ PWM Module(s)

————1 1

Serial Port(s) (SPI/I

C, USART)

— — — — SPI/I

C SPI/I

Parallel Slave Port — — — — — — A/D Converter (8-bit) Channels 4 4 4 4 5 5

Features

Interrupt Sources 4 4 4 4 8 8 I/O Pins 13 13 13 13 22 22 Voltage Range (Volts) 3.0-6.0 3.0-6.0 3.0-6.0 3.0-5.5 2.5-6.0 3.0-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown-out Reset Yes — Yes Yes Yes Yes Packages 18-pin DIP,

SOIC; 20-pin SSOP

18-pin DIP, SOIC

18-pin DIP, SOIC; 20-pin SSOP

28-pin SDIP, SOIC, SSOP

PIC16C73A

PIC16C74A PIC16C76 PIC16C77

Clock

Maximum Frequency of Operation (MHz)

20 20 20 20

Memory

EPROM Program Memory (x14 words)

4K 4K 8K 8K

Data Memory (bytes) 192 192 368 368

Peripherals

Timer Module(s) TMR0,

TMR1, TMR2

TMR0, TMR1, TMR2

Capture/Compare/PWM Module(s)

2222

Serial Port(s) (SPI/I

C, US-

ART)

SPI/I

C, USART SPI/I

C, USART

Parallel Slave Port — Yes — Yes A/D Converter (8-bit) Channels 5858

Features

Interrupt Sources 11 12 11 12 I/O Pins 22 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Packages 28-pin SDIP,

SOIC

40-pin DIP; 44-pin PLCC, MQFP, TQFP

28-pin SDIP, SOIC

40-pin DIP; 44-pin PLCC, MQFP, TQFP

All PIC16/17 Family devices ha ve Pow er-on Reset, selectab le Watchdog Timer, selectab le code protect and high I/O current capability. All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales ofﬁce for availability of these devices.



1997 Microchip Technology Inc. DS30390E-page 7

PIC16C7X

2.0 PIC16C7X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available . Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C7X Product Identiﬁcation System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.

For the PIC16C7X family, there are two device “types” as indicated in the device number:

1. C , as in PIC16 C 74. These devices have

EPROM type memory and operate over the standard voltage range.

2. LC , as in PIC16 LC 74. These devices have

EPROM type memory and operate over an extended voltage range.

2.1 UV Erasab

le Devices

The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes.

Microchip's PICSTART



Plus and PRO MATE



II programmers both support programming of the PIC16C7X.

2.2 O

ne-Time-Programmable (OTP)

Devices

The availability of OTP devices is especially useful for customers who need the ﬂexibility for frequent code updates and small volume applications.

The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the conﬁguration bits must also be programmed.

2.3 Q

uick-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your local Microchip Technology sales ofﬁce for more details.

2.4 Serializ

ed Quick-Turnaround

Production (SQTP

)

Devices

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number.

PIC16C7X

DS30390E-page 8

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1997 Microchip Technology Inc.

NOTES:



1997 Microchip Technology Inc. DS30390E-page 9

PIC16C7X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) e xcept f or program branches.

The table below lists program memory (EPROM) and data memory (RAM) for each PIC16C7X device.

The PIC16CXX can directly or indirectly address its register ﬁles or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

Device

Program

Memory

Data Memory

PIC16C72 2K x 14 128 x 8 PIC16C73 4K x 14 192 x 8 PIC16C73A 4K x 14 192 x 8 PIC16C74 4K x 14 192 x 8 PIC16C74A 4K x 14 192 x 8 PIC16C76 8K x 14 368 x 8 PIC16C77 8K x 14 386 x 8

PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borro

w bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

PIC16C7X

DS30390E-page 10  1997 Microchip Technology Inc.

FIGURE 3-1: PIC16C72 BLOCK DIAGRAM

EPROM

Program

Memory

2K x 14

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

128 x 8

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

VDD, VSS

Timer0

A/D

Synchronous

Serial Port

PORTA

PORTB

PORTC

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

CCP1

Timer1 Timer2

RA4/T0CKI RA5/SS

/AN4

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

 1997 Microchip Technology Inc. DS30390E-page 11

PIC16C7X

FIGURE 3-2: PIC16C73/73A/76 BLOCK DIAGRAM

EPROM

Program

Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

VDD, VSS

USART

PORTA

PORTB

PORTC

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

Brown-out

Reset

(2)

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C73.

CCP1 CCP2

Synchronous

A/DTimer0 Timer1 Timer2

Serial Port

RA4/T0CKI RA5/SS

/AN4

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

Device Program Memory Data Memory (RAM)

PIC16C73 PIC16C73A PIC16C76

4K x 14 4K x 14 8K x 14

192 x 8 192 x 8 368 x 8

PIC16C7X

DS30390E-page 12  1997 Microchip Technology Inc.

FIGURE 3-3: PIC16C74/74A/77 BLOCK DIAGRAM

EPROM

Program

Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

VDD, VSS

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI RA5/SS/AN4

RB0/INT

RB7:RB1

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

RD7/PSP7:RD0/PSP0

RE0/RD

/AN5

RE1/WR

/AN6

RE2/CS

/AN7

Brown-out

Reset

(2)

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C74.

USART

CCP1 CCP2

Synchronous

A/DTimer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

Parallel Slave Port

Device Program Memory Data Memory (RAM)

PIC16C74 PIC16C74A PIC16C77

4K x 14 4K x 14 8K x 14

192 x 8 192 x 8 368 x 8

 1997 Microchip Technology Inc. DS30390E-page 13

PIC16C7X

TABLE 3-1: PIC16C72 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SSOP

Pin#

SOIC

Pin#

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 9 9 9 I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 10 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR

/VPP

1 1 1 I/P ST Master clear (reset) input or programming voltage input. This

pin is an active low reset to the device.

PORTA is a bi-directional I/O port. RA0/AN0 2 2 2 I/O TTL RA0 can also be analog input0 RA1/AN1 3 3 3 I/O TTL RA1 can also be analog input1 RA2/AN2 4 4 4 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 5 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 6 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.

Output is open drain type.

RA5/SS/AN4 7 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs. RB0/INT 21 21 21 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin. RB1 22 22 22 I/O TTL RB2 23 23 23 I/O TTL RB3 24 24 24 I/O TTL RB4 25 25 25 I/O TTL Interrupt on change pin. RB5 26 26 26 I/O TTL Interrupt on change pin. RB6 27 27 27 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock. RB7 28 28 28 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 11 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1

clock input. RC1/T1OSI 12 12 12 I/O ST RC1 can also be the Timer1 oscillator input. RC2/CCP1 13 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output. RC3/SCK/SCL 14 14 14 I/O ST RC3 can also be the synchronous serial clock input/output

for both SPI and I

C modes.

RC4/SDI/SDA 15 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode). RC5/SDO 16 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6 17 17 17 I/O ST RC7 18 18 18 I/O ST VSS 8, 19 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise.

PIC16C7X

DS30390E-page 14  1997 Microchip Technology Inc.

TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SOIC

Pin#

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 9 9 I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR

/VPP

1 1 I/P ST Master clear (reset) input or programming voltage input. This

pin is an active low reset to the device.

PORTA is a bi-directional I/O port. RA0/AN0 2 2 I/O TTL RA0 can also be analog input0 RA1/AN1 3 3 I/O TTL RA1 can also be analog input1 RA2/AN2 4 4 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.

Output is open drain type.

RA5/SS/AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin. RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3 24 24 I/O TTL RB4 25 25 I/O TTL Interrupt on change pin. RB5 26 26 I/O TTL Interrupt on change pin. RB6 27 27 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock. RB7 28 28 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1

clock input. RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2

input/Compare2 output/PWM2 output. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output

for both SPI and I

C modes.

RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data. VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise.

 1997 Microchip Technology Inc. DS30390E-page 15

PIC16C7X

TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

PLCC

Pin#

QFP Pin#

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 13 14 30 I ST/CMOS

(4)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/VPP 1 2 18 I/P ST Master clear (reset) input or programming voltage input.

This pin is an active low reset to the device.

PORTA is a bi-directional I/O port. RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0 RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1 RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference

voltage

RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/

counter. Output is open drain type.

RA5/SS/AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for

the synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be softw are

programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin. RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt on change pin. RB5 38 42 15 I/O TTL Interrupt on change pin. RB6 39 43 16 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock. RB7 40 44 17 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data. Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as an external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when conﬁgured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise.

PIC16C7X

DS30390E-page 16  1997 Microchip Technology Inc.

PORTC is a bi-directional I/O port.

RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a

Timer1 clock input.

RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or

Capture2 input/Compare2 output/PWM2 output.

RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/

output for both SPI and I2C modes.

RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or

data I/O (I2C mode).

RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out

(SPI mode).

RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data.

PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.

RD0/PSP0 19 21 38 I/O ST/TTL

(3)

RD1/PSP1 20 22 39 I/O ST/TTL

(3)

RD2/PSP2 21 23 40 I/O ST/TTL

(3)

RD3/PSP3 22 24 41 I/O ST/TTL

(3)

RD4/PSP4 27 30 2 I/O ST/TTL

(3)

RD5/PSP5 28 31 3 I/O ST/TTL

(3)

RD6/PSP6 29 32 4 I/O ST/TTL

(3)

RD7/PSP7 30 33 5 I/O ST/TTL

(3)

PORTE is a bi-directional I/O port.

RE0/RD/AN5 8 9 25 I/O ST/TTL

(3)

RE0 can also be read control for the parallel slave port, or analog input5.

RE1/WR/AN6 9 10 26 I/O ST/TTL

(3)

RE1 can also be write control for the parallel slave port, or analog input6.

RE2/CS/AN7 10 11 27 I/O ST/TTL

(3)

RE2 can also be select control for the parallel slave

port, or analog input7. VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17,28,4012,13,

33,34

— These pins are not internally connected. These pins should

be left unconnected.

TABLE 3-3: PIC16C74/74A/77 PINOUT DESCRIPTION (Cont.’d)

Pin Name

DIP

Pin#

PLCC

Pin#

QFP Pin#

I/O/P Type

Buffer

Type

Description

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as an external interrupt.

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise.

 1997 Microchip Technology Inc. DS30390E-page 17

PIC16C7X

3.1 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-4.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instr uction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the f etched instruction is latched into the “Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-4: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal phase clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP)

Fetch 4 Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

PIC16C7X

DS30390E-page 18  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30390E-page 19

PIC16C7X

4.0 MEMORY ORGANIZATION

4.1 Program Memory Organization

The PIC16C7X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The amount of program memory available to each device is listed below:

For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 4-1: PIC16C72 PROGRAM

MEMORY MAP AND STACK

Applicable Devices

72 73 73A 74 74A 76 77

Device

Program

Memory

Address Range

PIC16C72 2K x 14 0000h-07FFh PIC16C73 4K x 14 0000h-0FFFh PIC16C73A 4K x 14 0000h-0FFFh PIC16C74 4K x 14 0000h-0FFFh PIC16C74A 4K x 14 0000h-0FFFh PIC16C76 8K x 14 0000h-1FFFh PIC16C77 8K x 14 0000h-1FFFh

PC<12:0>

0000h

0004h 0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

0800h

User Memory

Space

FIGURE 4-2: PIC16C73/73A/74/74A

PROGRAM MEMORY MAP AND STACK

PC<12:0>

0000h

0004h 0005h

07FFh 0800h

0FFFh 1000h

1FFFh

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

On-chip Program

On-chip Program Memory (Page 1)

Memory (Page 0)

CALL, RETURN RETFIE, RETLW

User Memory

Space

PIC16C7X

DS30390E-page 20  1997 Microchip Technology Inc.

FIGURE 4-3: PIC16C76/77 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h 0005h

Stack Level 1

Stack Level 8

Reset V ector

Interrupt Vector

CALL, RETURN RETFIE, RETLW

1FFFh

Stack Level 2

Page 0

Page 1

Page 2

Page 3

07FFh 0800h

0FFFh 1000h

17FFh 1800h

User Memory

Space

On-Chip

4.2 Data Memory Organization

The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 and RP0 are the bank select bits.

RP1:RP0 (STATUS<6:5>) = 00 → Bank0 = 01 → Bank1 = 10 → Bank2 = 11 → Bank3

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another bank for code reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle can be accessed either directly , or indi-

rectly through the File Select Register FSR (Section 4.5).

Applicable Devices

72 73 73A 74 74A 76 77

 1997 Microchip Technology Inc. DS30390E-page 21

PIC16C7X

FIGURE 4-4: PIC16C72 REGISTER FILE

MAP

INDF

(1)

TMR0

PCL

STATUS

FSR PORTA PORTB PORTC

PCLATH INTCON

PIR1

TMR1L TMR1H T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR TRISA TRISB

TRISC

PCLATH INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

ADCON1

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah

0Bh 0Ch 0Dh 0Eh

0Fh

10h

11h 12h 13h 14h 15h 16h 17h 18h 19h

1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

BFh C0h

Unimplemented data memory locations, read as

'0'.

Note 1: Not a physical register.

File

Address

FIGURE 4-5: PIC16C73/73A/74/74A

INDF

(1)

TMR0

PCL

STATUS

FSR PORTA PORTB PORTC

PORTD

(2)

PORTE

(2)

PCLATH INTCON

PIR1

PIR2 TMR1L TMR1H T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

RCSTA TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR TRISA TRISB TRISC

TRISD

(2)

TRISE

(2)

PCLATH

INTCON

PIE1 PIE2

PCON

PR2

SSPADD

SSPSTAT

TXSTA

SPBRG

ADCON1

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh

10h

11h 12h 13h 14h 15h 16h 17h 18h 19h

1Ah 1Bh 1Ch 1Dh 1Eh 1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h A0h

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

File

Address

Unimplemented data memory locations, read as

'0'.

Note 1: Not a physical register.

2: These registers are not physically imple-

mented on the PIC16C73/73A, read as '0'.

PIC16C7X

DS30390E-page 22  1997 Microchip Technology Inc.

FIGURE 4-6: PIC16C76/77 REGISTER FILE MAP

Indirect addr.

(*)

TMR0

PCL

STATUS

FSR

PORTA PORTB PORTC

PCLATH

INTCON

PIR1

TMR1L TMR1H

T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION

PCL

STATUS

FSR TRISA TRISB TRISC

PCLATH

INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

7Fh

FFh

Bank 0

Bank 1

Unimplemented data memory locations, read as '0'.

* Not a physical register.

Note 1: PORTD, PORTE, TRISD, and TRISE are unimplemented on the PIC16C76, read as '0'.

Note: The upper 16 bytes of data memory in banks 1, 2, and 3 are mapped in Bank 0. This may require

relocation of data memory usage in the user application code if upgrading to the PIC16C76/77.

File

Address

Indirect addr.

(*)

Indirect addr.

(*)

PCL

STATUS

FSR

PCLATH INTCON

PCL

STATUS

FSR

PCLATH INTCON

100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh

180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh

120h

1A0h

17Fh

1FFh

Bank 2

Bank 3

Indirect addr.

(*)

PORTD PORTE

TRISD TRISE

TMR0

OPTION

PIR2

PIE2

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

ADCON0

TXSTA

SPBRG

ADCON1

General Purpose Register

1EFh 1F0h

accesses

70h - 7Fh

EFh F0h

accesses

70h-7Fh

16Fh 170h

accesses

70h-7Fh

General Purpose Register

TRISB

PORTB

96 Bytes

80 Bytes 80 Bytes 80 Bytes

16 Bytes

(1)

 1997 Microchip Technology Inc. DS30390E-page 23

PIC16C7X

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

The special function registers can be classiﬁed into two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.

TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(3)

Bank 0

00h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h

(1)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 03h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

04h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h — Unimplemented — — 09h — Unimplemented — — 0Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000 0Dh — Unimplemented — — 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.

PIC16C7X

DS30390E-page 24  1997 Microchip Technology Inc.

Bank 1

80h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h

(1)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 83h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD ZDCC0001 1xxx 000q quuu

84h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 88h — Unimplemented — — 89h — Unimplemented — — 8Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 8Bh

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000 8Dh — Unimplemented — — 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-1: PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

 1997 Microchip Technology Inc. DS30390E-page 25

PIC16C7X

TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

(2)

Bank 0

00h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h

(4)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 03h

(4)

STATUS IRP

(7)

RP1

(7)

RP0 TO PD ZDCC0001 1xxx 000q quuu

04h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA

— — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu 08h

(5)

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h

(5)

PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

0Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(3)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Data Register 0000 0000 0000 0000 1Ah RCREG USART Receive Data Register 0000 0000 0000 0000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter. 2: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 4: These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear.

PIC16C7X

DS30390E-page 26  1997 Microchip Technology Inc.

Bank 1

80h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h

(4)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 83h

(4)

STATUS IRP

(7)

RP1

(7)

RP0 TO PD ZDCC0001 1xxx 000q quuu

84h

(4)

(5)

TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h

(5)

TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE

(3)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR

(6)

---- --qq ---- --uu

8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-2: PIC16C73/73A/74/74A SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

 1997 Microchip Technology Inc. DS30390E-page 27

PIC16C7X

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

(2)

Bank 0

00h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h

(4)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 03h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu 04h

(4)

(5)

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu 09h

(5)

PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 0Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF

(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

PIC16C7X

DS30390E-page 28  1997 Microchip Technology Inc.

Bank 1

80h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h

(4)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 83h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu 84h

(4)

(5)

TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h

(5)

TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 8Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 8Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 PSPIE

(3)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

 1997 Microchip Technology Inc. DS30390E-page 29

PIC16C7X

Bank 2

100h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 102h

(4)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 103h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu 104h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 105h — Unimplemented — — 106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 107h — Unimplemented — — 108h — Unimplemented — — 109h — Unimplemented — — 10Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 10Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 10Ch-

10Fh

— Unimplemented — —

Bank 3

180h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 181h OPTION RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

182h

(4)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 183h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu 184h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 185h — Unimplemented — — 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 187h — Unimplemented — — 188h — Unimplemented — — 189h — Unimplemented — — 18Ah

(1,4)

PCLATH — — —

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

18Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 18Ch-

18Fh

— Unimplemented — —

TABLE 4-3: PIC16C76/77 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

PIC16C7X

DS30390E-page 30  1997 Microchip Technology Inc.

4.2.2.1 STATUS REGISTER

The ST ATUS register, shown in Figure 4-7, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T

O and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

Applicable Devices

72 73 73A 74 74A 76 77

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STA TUS register. For other instructions, not affecting any status bits, see the "Instruction Set Summary."

Note 1: For those devices that do not use bits IRP

and RP1 (STATUS<7:6>), maintain these bits clear to ensure upward compatibility with future products.

Note 2: The C and DC bits operate as a borro

w and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4: T

O: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 3: PD

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: For borro

w the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

 1997 Microchip Technology Inc. DS30390E-page 31

PIC16C7X

4.2.2.2 OPTION REGISTER

The OPTION register is a readable and writable register which contains various control bits to conﬁgure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.

Applicable Devices

72 73 73A 74 74A 76 77

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to the Watchdog Timer .

FIGURE 4-8: OPTION REGISTER (ADDRESS 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16C7X

DS30390E-page 32  1997 Microchip Technology Inc.

4.2.2.3 INTCON REGISTER

The INTCON Register is a readable and writable register which contains various enable and ﬂag bits for the TMR0 register overﬂow, RB Port change and Exter nal RB0/INT pin interrupts.

Applicable Devices

72 73 73A 74 74A 76 77

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

FIGURE 4-9: INTCON REGISTER

(ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE:

(1)

Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Note 1: For the PIC16C73 and PIC16C74, if an interrupt occurs while the GIE bit is being cleared, the GIE bit

may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. Refer to Section 14.5 for a detailed description.

Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

 1997 Microchip Technology Inc. DS30390E-page 33

PIC16C7X

4.2.2.4 PIE1 REGISTER

This register contains the individual enable bits for the peripheral interrupts.

Applicable Devices

72 73 73A 74 74A 76 77

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 4-10: PIE1 REGISTER PIC16C72 (ADDRESS 8Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt bit 5-4: Unimplemented: Read as '0' bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt

0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overﬂow Interrupt Enable bit

1 = Enables the TMR1 overﬂow interrupt

0 = Disables the TMR1 overﬂow interrupt

PIC16C7X

DS30390E-page 34  1997 Microchip Technology Inc.

FIGURE 4-11: PIE1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: PSPIE

(1)

: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt

bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt 0 = Disables the A/D interrupt

bit 5: RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4: TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt 0 = Disables the SSP interrupt

bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overﬂow Interrupt Enable bit

1 = Enables the TMR1 overﬂow interrupt 0 = Disables the TMR1 overﬂow interrupt

Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved

on these devices, always maintain this bit clear.

 1997 Microchip Technology Inc. DS30390E-page 35

PIC16C7X

4.2.2.5 PIR1 REGISTER

This register contains the individual ﬂag bits for the Peripheral interrupts.

Applicable Devices

72 73 73A 74 74A 76 77

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

FIGURE 4-12: PIR1 REGISTER PIC16C72 (ADDRESS 0Ch)

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion is not complete bit 5-4: Unimplemented: Read as '0' bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software)

0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM Mode

Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overﬂow Interrupt Flag bit

1 = TMR1 register overﬂowed (must be cleared in software)

0 = TMR1 register did not overﬂow

PIC16C7X

DS30390E-page 36  1997 Microchip Technology Inc.

FIGURE 4-13: PIR1 REGISTER PIC16C73/73A/74/74A/76/77 (ADDRESS 0Ch)

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: PSPIF

(1)

: Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred

bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete

bit 5: RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty

bit 4: TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full

bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit

1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive

bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred

bit 0: TMR1IF: TMR1 Overﬂow Interrupt Flag bit

1 = TMR1 register overﬂowed (must be cleared in software) 0 = TMR1 register did not overﬂow

Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved

on these devices, always maintain this bit clear.

 1997 Microchip Technology Inc. DS30390E-page 37

PIC16C7X

4.2.2.6 PIE2 REGISTER

This register contains the individual enable bit for the CCP2 peripheral interrupt.

Applicable Devices

72 73 73A 74 74A 76 77

FIGURE 4-14: PIE2 REGISTER (ADDRESS 8Dh)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IE R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt

0 = Disables the CCP2 interrupt

PIC16C7X

DS30390E-page 38  1997 Microchip Technology Inc.

4.2.2.7 PIR2 REGISTER

This register contains the CCP2 interrupt ﬂag bit.

Applicable Devices

72 73 73A 74 74A 76 77

Note: Interrupt ﬂag bits get set when an interrupt

FIGURE 4-15: PIR2 REGISTER (ADDRESS 0Dh)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit

Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred

Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM Mode Unused

 1997 Microchip Technology Inc. DS30390E-page 39

PIC16C7X

4.2.2.8 PCON REGISTER

The Power Control (PCON) register contains a ﬂag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset condition from a Power-on Reset condition.

Applicable Devices

73 73A 74 74A 76 77

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked on subsequent resets to see if BOR

is clear, indicating a brown-out has occurred. The BOR

status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Conﬁguration word).

FIGURE 4-16: PCON REGISTER (ADDRESS 8Eh)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — — POR BOR

(1)

R = Readable bit W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1: POR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BO

(1)

: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Note 1: Brown-out Reset is not implemented on the PIC16C73/74.

PIC16C7X

DS30390E-page 40  1997 Microchip Technology Inc.

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-17 shows the two situations for the loading of the PC. The upper example in the ﬁgure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower example in the ﬁgure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-17: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an off-

set to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the tab le location crosses a PCL memory boundary (each 256 byte block). Refer to the application note

“Implementing a Table Read"

(AN556).

4.3.2 STACK The PIC16CXX family has an 8 lev el deep x 13-bit wide

hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stac k when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buff er . This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on).

Applicable Devices

73 73A 74 74A 76 77

12 8 7 0

PCLATH<4:0>

PCLATH

Instr

uction with

ALU

GOTO, CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as Destination

4.4 Program Memory Paging

PIC16C7X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (which POPs the address from the stack).

Note 1: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.

Applicable Devices

73 73A 74 74A 76 77

Note: PIC16C7X devices with 4K or less of pro-

gram memory ignore paging bit PCLATH<4>. The use of PCLATH<4> as a general purpose read/write bit is not recommended since this may affect upward compatibility with future products.

 1997 Microchip Technology Inc. DS30390E-page 41

PIC16C7X

Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLA TH is sa ved and restored b y the interrupt service routine (if interrupts are used).

EXAMPLE 4-1: CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG 0x500 BSF PCLATH,3 ;Select page 1 (800h-FFFh) BCF PCLATH,4 ;Only on >4K devices CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : : ORG 0x900 SUB1_P1: ;called subroutine : ;page 1 (800h-FFFh) : RETURN ;return to Call subroutine ;in page 0 (000h-7FFh)

4.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register . Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-18.

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue

Applicable Devices

73 73A 74 74A 76 77

FIGURE 4-18: DIRECT/INDIRECT ADDRESSING

For register ﬁle map detail see Figure 4-4, and Figure 4-5.

Data Memory

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6

from opcode

IRP FSR register

bank select

location select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

not used

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

PIC16C7X

DS30390E-page 42  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30390E-page 43

PIC16C7X

5.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Registers

PORTA is a 6-bit latch. The RA4/T0CKI pin is a Schmitt Trigger input and an

open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers) which can conﬁgure these pins as output or input.

Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin(s).

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modiﬁed, and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin.

Other PORTA pins are multiplexed with analog inputs and analog V

REF input. The operation of each pin is

selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 5-1: INITIALIZING PORTA

BCF STATUS, RP0 ; BCF STATUS, RP1 ; PIC16C76/77 only CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as '0'.

Applicable Devices

73 73A 74 74A 76 77

Applicable Devices

73 73A 74 74A 76 77

Note: On a Power-on Reset, these pins are con-

ﬁgured as analog inputs and read as '0'.

FIGURE 5-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

FIGURE 5-2: BLOCK DIAGRAM OF RA4/

T0CKI PIN

Data bus

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VDD

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD and

VSS.

Analog input mode

TTL input buffer

To A/D Converter

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt T rigger input buffer

I/O pin

(1)

TMR0 clock input

Note 1: I/O pin has protection diodes to V

SS only.

PIC16C7X

DS30390E-page 44  1997 Microchip Technology Inc.

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input RA1/AN1 bit1 TTL Input/output or analog input RA2/AN2 bit2 TTL Input/output or analog input RA3/AN3/V

REF bit3 TTL Input/output or analog input or VREF

RA4/T0CKI bit4 ST Input/output or external clock input for Timer0

Output is open drain type

RA5/SS

/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input

Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

 1997 Microchip Technology Inc. DS30390E-page 45

PIC16C7X

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).

EXAMPLE 5-2: INITIALIZING PORTB

BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU

(OPTION<7>). The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are disabled on a Power-on Reset.

FIGURE 5-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Applicable Devices

73 73A 74 74A 76 77

Data Latch

RBPU

(2)

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak pull-up

RD Port

RB0/INT

I/O pin

(1)

TTL Input Buffer

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU bit (OPTION<7>).

Schmitt T rigger Buffer

TRIS Latch

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e. any RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with ﬂag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software conﬁgurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook,

"Implementing Wake-Up on Key

Stroke"

(AN552).

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

Note: For the PIC16C73/74, if a change on the

I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then interrupt ﬂag bit RBIF may not get set.

PIC16C7X

DS30390E-page 46  1997 Microchip Technology Inc.

FIGURE 5-4: BLOCK DIAGRAM OF

RB7:RB4 PINS (PIC16C73/74)

Data Latch

From other

RBPU

(2)

I/O

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak pull-up

RD Port

Latch

TTL Input Buffer

(1)

Note 1: I/O pins have diode protection to VDD and VSS.

Buffer

RB7:RB6 in serial programming mode

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

bit (OPTION<7>).

FIGURE 5-5: BLOCK DIAGRAM OF

RB7:RB4 PINS (PIC16C72/ 73A/74A/76/77)

Data Latch

From other

RBPU

(2)

I/O

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak pull-up

RD Port

Latch

TTL Input Buffer

(1)

Note 1: I/O pins have diode protection to VDD and VSS.

Buffer

RB7:RB6 in serial programming mode

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

bit (OPTION<7>).

TABLE 5-3: PORTB FUNCTIONS

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST

(1)

Input/output pin or external interrupt input. Internal software

programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB6 bit6 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock. RB7 bit7 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

 1997 Microchip Technology Inc. DS30390E-page 47

PIC16C7X

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

PIC16C7X

DS30390E-page 48  1997 Microchip Technology Inc.

5.3 PORTC and TRISC Registers

PORTC is an 8-bit bi-directional port. Each pin is individually conﬁgurable as an input or output through the TRISC register. PORTC is multiplexed with several peripheral functions (Table 5-5). PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be taken in deﬁning TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.

EXAMPLE 5-3: INITIALIZING PORTC

BCF STATUS, RP0 ; Select Bank 0 BCF STATUS, RP1 ; PIC16C76/77 only CLRF PORTC ; Initialize PORTC by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs

Applicable Devices

73 73A 74 74A 76 77

FIGURE 5-6: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT OVERRIDE)

PORT/PERIPHERAL Select

(2)

Data bus

WR PORT

WR TRIS

Data Latch

TRIS Latch

RD TRIS

Schmitt T rigger

QD Q

Peripheral Data Out

VDD

VSS

PORT

Peripheral OE

(3)

Peripheral input

I/O pin

(1)

Note 1: I/O pins have diode protection to VDD and VSS.

2: P ort/Peripheral select signal selects between port

data and peripheral output.

3: Peripheral OE (output enable) is only activated if

peripheral select is active.

TABLE 5-5: PORTC FUNCTIONS

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI

bit0

ST Input/output port pin or Timer1 oscillator output/Timer1 clock input

RC1/T1OSI/CCP2

(1)

bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/

Compare2 output/PWM2 output

RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1

output

RC3/SCK/SCL bit3 ST

RC3 can also be the synchronous serial clock for both SPI and I

modes.

RC4/SDI/SDA bit4 ST

RC4 can also be the SPI Data In (SPI mode) or data I/O (I

C mode).

RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output RC6/TX/CK

(2)

bit6 ST Input/output port pin or USART Asynchronous Transmit, or USART

Synchronous Clock

RC7/RX/DT

(2)

bit7 ST Input/output port pin or USART Asynchronous Receive, or USART

Synchronous Data

Legend: ST = Schmitt Trigger input Note 1: The CCP2 multiplexed function is not enabled on the PIC16C72.

2: The TX/CK and RX/DT multiplexed functions are not enabled on the PIC16C72.

 1997 Microchip Technology Inc. DS30390E-page 49

PIC16C7X

TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other resets

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged.

PIC16C7X

DS30390E-page 50  1997 Microchip Technology Inc.

5.4 PORTD and TRISD Registers

PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually conﬁgurable as an input or output.

PORTD can be conﬁgured as an 8-bit wide microprocessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.

Applicable Devices

72 73 73A 74 74A 76 77

FIGURE 5-7: PORTD BLOCK DIAGRAM (IN

I/O PORT MODE)

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt T rigger input buffer

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

TABLE 5-7: PORTD FUNCTIONS

TABLE 5-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Name Bit# Buffer Type Function

RD0/PSP0 bit0 ST/TTL

(1)

Input/output port pin or parallel slave port bit0

RD1/PSP1 bit1 ST/TTL

(1)

Input/output port pin or parallel slave port bit1

RD2/PSP2 bit2 ST/TTL

(1)

Input/output port pin or parallel slave port bit2

RD3/PSP3 bit3 ST/TTL

(1)

Input/output port pin or parallel slave port bit3

RD4/PSP4 bit4 ST/TTL

(1)

Input/output port pin or parallel slave port bit4

RD5/PSP5 bit5 ST/TTL

(1)

Input/output port pin or parallel slave port bit5

RD6/PSP6 bit6 ST/TTL

(1)

Input/output port pin or parallel slave port bit6

RD7/PSP7 bit7 ST/TTL

(1)

Input/output port pin or parallel slave port bit7

Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE

IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.

 1997 Microchip Technology Inc. DS30390E-page 51

PIC16C7X

5.5 PORTE and TRISE Register

PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 and RE2/CS

/AN7, which are individually conﬁgurable as inputs or outputs. These pins have Schmitt Trigger input buffers.

I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are conﬁgured as digital inputs) and that register ADCON1 is conﬁgured for digital I/O. In this mode the input buffers are TTL.

Figure 5-9 shows the TRISE register, which also controls the parallel slave port operation.

PORTE pins are multiplexed with analog inputs. The operation of these pins is selected by control bits in the ADCON1 register. When selected as an analog input, these pins will read as '0's.

TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins conﬁgured as inputs when using them as analog inputs.

Applicable Devices

72 73 73A 74 74A 76 77

FIGURE 5-8: PORTE BLOCK DIAGRAM (IN

I/O PORT MODE)

Note: On a Power-on Reset these pins are con-

ﬁgured as analog inputs.

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt T rigger input buffer

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

FIGURE 5-9: TRISE REGISTER (ADDRESS 89h)

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — bit2 bit1 bit0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7 : IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received

bit 6: OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word 0 = The output buffer has been read

bit 5: IBOV: Input Buffer Overﬂow Detect bit (in microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overﬂow occurred

bit 4: PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel slave port mode 0 = General purpose I/O mode

bit 3: Unimplemented: Read as '0'

PORTE Data Direction Bits

bit 2: Bit2: Direction Control bit for pin RE2/CS/AN7

1 = Input 0 = Output

bit 1: Bit1: Direction Control bit for pin RE1/WR/AN6

1 = Input 0 = Output

bit 0: Bit0: Direction Control bit for pin RE0/RD

/AN5 1 = Input 0 = Output

PIC16C7X

DS30390E-page 52  1997 Microchip Technology Inc.

TABLE 5-9: PORTE FUNCTIONS

TABLE 5-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit# Buffer Type Function

RE0/RD

/AN5 bit0 ST/TTL

(1)

Input/output port pin or read control input in parallel slave port mode or analog input:

RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected)

RE1/WR

/AN6 bit1 ST/TTL

(1)

Input/output port pin or write control input in parallel slave port mode or analog input:

WR 1 = Not a write operation

0 = Write operation. Writes PORTD register (if chip selected)

RE2/CS

/AN7 bit2 ST/TTL

(1)

Input/output port pin or chip select control input in parallel slave port mode or analog input:

CS 1 = Device is not selected 0 = Device is selected

Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other resets

09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.

 1997 Microchip Technology Inc. DS30390E-page 53

PIC16C7X

5.6 I/O Programming Considerations

5.6.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, ex ecute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs . However, if bit0 is switched to an output, the content of the data latch may now be unknown.

Reading the port register, reads the values of the port pins. Wr iting to the por t register wr ites the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-4 shows the effect of two sequential readmodify-write instructions on an I/O port.

Applicable Devices

73 73A 74 74A 76 77

EXAMPLE 5-4: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- -------- BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip.

5.6.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-

10). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/ O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ﬁle to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

FIGURE 5-10: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2

PC + 3

Q1 Q2

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to PORTB

NOP

Port pin sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

write to PORTB

NOP

MOVF PORTB,W

TPD

Note: This example shows a write to PORTB

followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) where T

CY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read ma y be problematic.

PIC16C7X

DS30390E-page 54  1997 Microchip Technology Inc.

5.7 Parallel Slave Port

PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. In slave mode it is asynchronously readable and writable by the external world through RD control input pin RE0/RD/AN5 and WR control input pin RE1/WR

/AN6.

It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD

/AN5 to be the RD input, RE1/

/AN6 to be the WR input and RE2/CS /AN7 to be the

(chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be conﬁgured as inputs (set) and the A/D port conﬁguration bits PCFG2:PCFG0 (ADCON1<2:0>) must be set, which will conﬁgure pins RE2:RE0 as digital I/O.

There are actually two 8-bit latches, one for data-out (from the PIC16/17) and one for data input. The user writes 8-bit data to PORTD data latch and reads data from the port pin latch (note that they have the same address). In this mode, the TRISD register is ignored, since the microprocessor is controlling the direction of data ﬂow.

A write to the PSP occurs when both the CS

and WR lines are ﬁrst detected low. When either the CS or WR lines become high (level triggered), then the Input Buffer Full status ﬂag bit IBF (TRISE<7>) is set on the Q4 clock cycle, following the next Q2 cycle, to signal the write is complete (Figure 5-12). The interrupt ﬂag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF can only be cleared by reading the PORTD input latch. The input Buffer Overﬂow status ﬂag bit IBOV (TRISE<5>) is set if a second write to the Par allel Slave P ort is attempted when the previous b yte has not been read out of the buffer.

A read from the PSP occurs when both the CS

and RD lines are ﬁrst detected low. The Output Buffer Full status ﬂag bit OBF (TRISE<6>) is cleared immediately (Figure 5-13) indicating that the PORTD latch is waiting to be read by the external bus. When either the CS

pin becomes high (level triggered), the interrupt ﬂag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user ﬁrmware.

When not in Parallel Slav e P ort mode, the IBF and OBF bits are held clear. However, if ﬂag bit IBOV was previously set, it must be cleared in ﬁrmware.

An interrupt is generated and latched into ﬂag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the user in ﬁrmware and the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).

Applicable Devices

72 73 73A 74 74A 76 77

FIGURE 5-11: PORTD AND PORTE BLOCK

DIAGRAM (PARALLEL SLAVE PORT)

Data bus

WR PORT

RDx

PORT

One bit of PORTD

Set interrupt ﬂag PSPIF (PIR1<7>)

Read

Chip Select

Write

Note: I/O pin has protection diodes to VDD and VSS.

TTL

 1997 Microchip Technology Inc. DS30390E-page 55

PIC16C7X

FIGURE 5-12: PARALLEL SLAVE PORT WRITE WAVEFORMS

FIGURE 5-13: PARALLEL SLAVE PORT READ WAVEFORMS

TABLE 5-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 0Ch PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.

Q1 Q2 Q3 Q4CSQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

WR RD

IBF

OBF

PSPIF

PORTD<7:0>

Q1 Q2 Q3 Q4CSQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

PSPIF

OBF

PORTD<7:0>

PIC16C7X

DS30390E-page 56  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30390E-page 57

PIC16C7X

6.0 OVERVIEW OF TIMER MODULES

The PIC16C72, PIC16C73/73A, PIC16C74/74A, PIC16C76/77 each have three timer modules.

Each module can generate an interrupt to indicate that an event has occurred (i.e. timer overﬂow). Each of these modules is explained in full detail in the following sections. The timer modules are:

• Timer0 Module (Section 7.0)

• Timer1 Module (Section 8.0)

• Timer2 Module (Section 9.0)

6.1 Timer0 Overview

The Timer0 module is a simple 8-bit overﬂow counter. The clock source can be either the internal system clock (Fosc/4) or an external clock. When the clock source is an external clock, the Timer0 module can be selected to increment on either the rising or falling edge.

The Timer0 module also has a programmable prescaler option. This prescaler can be assigned to either the Timer0 module or the Watchdog Timer. Bit PSA (OPTION<3>) assigns the prescaler, and bits PS2:PS0 (OPTION<2:0>) determine the prescaler value. Timer0 can increment at the following rates: 1:1 (when prescaler assigned to Watchdog timer), 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, and 1:256 (Timer0 only).

Synchronization of the external clock occurs after the prescaler. When the prescaler is used, the external clock frequency may be higher then the device’s frequency. The maximum frequency is 50 MHz, given the high and low time requirements of the clock.

6.2 Timer1 Overview

Timer1 is a 16-bit timer/counter. The clock source can be either the internal system clock (Fosc/4), an external clock, or an external crystal. Timer1 can operate as either a timer or a counter. When operating as a counter (external clock source), the counter can either operate synchronized to the device or asynchronously to the device. Asynchronous operation allo ws Timer1 to operate during sleep, which is useful for applications that require a real-time clock as well as the power savings of SLEEP mode.

Timer1 also has a prescaler option which allows Timer1 to increment at the following rates: 1:1, 1:2, 1:4, and 1:8. Timer1 can be used in conjunction with the Capture/Compare/PWM module. When used with a

Applicable Devices

73 73A 74 74A 76 77

Applicable Devices

73 73A 74 74A 76 77

Applicable Devices

73 73A 74 74A 76 77

CCP module, Timer1 is the time-base for 16-bit Capture or the 16-bit Compare and must be synchronized to the device.

6.3 Timer2 Overview

Timer2 is an 8-bit timer with a programmable prescaler and postscaler, as well as an 8-bit period register (PR2). Timer2 can be used with the CCP1 module (in PWM mode) as well as the Baud Rate Generator for the Synchronous Serial Port (SSP). The prescaler option allows Timer2 to increment at the following rates: 1:1, 1:4, 1:16.

The postscaler allows the TMR2 register to match the period register (PR2) a programmable number of times before generating an interrupt. The postscaler can be programmed from 1:1 to 1:16 (inclusive).

6.4 CCP Overview

The CCP module(s) can operate in one of these three modes: 16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation (PWM).

Capture mode captures the 16-bit value of TMR1 into the CCPRxH:CCPRxL register pair. The capture event can be programmed for either the falling edge, rising edge, fourth rising edge, or the sixteenth rising edge of the CCPx pin.

Compare mode compares the TMR1H:TMR1L register pair to the CCPRxH:CCPRxL register pair. When a match occurs an interrupt can be generated, and the output pin CCPx can be forced to given state (High or Low), TMR1 can be reset (CCP1), or TMR1 reset and start A/D conversion (CCP2). This depends on the control bits CCPxM3:CCPxM0.

PWM mode compares the TMR2 register to a 10-bit duty cycle register (CCPRxH:CCPRxL<5:4>) as well as to an 8-bit period register (PR2). When the TMR2 register = Duty Cycle register, the CCPx pin will be forced low. When TMR2 = PR2, TMR2 is cleared to 00h, an interrupt can be generated, and the CCPx pin (if an output) will be forced high.

Applicable Devices

73 73A 74 74A 76 77

Applicable Devices

73 73A 74 74A 76 77

PIC16C7X

DS30390E-page 58  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30390E-page 59

PIC16C7X

7.0 TIMER0 MODULE

The Timer0 module timer/counter has the f ollowing f eatures:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock

Figure 7-1 is a simpliﬁed block diagram of the Timer0 module.

Timer mode is selected by clearing bit T0CS (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 7-2 and Figure 7-3). The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0

Applicable Devices

73 73A 74 74A 76 77

Source Edge Select bit T0SE (OPTION<4>). Clear ing bit T0SE selects the rising edge. Restr ictions on the external clock input are discussed in detail in Section 7.2.

The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 7.3 details the operation of the prescaler.

7.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overﬂows from FFh to 00h. This overﬂow sets bit T0IF (INTCON<2>). The interr upt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. See Figure 7-4 for Timer0 interrupt timing.

Applicable Devices

73 73A 74 74A 76 77

FIGURE 7-1: TIMER0 BLOCK DIAGRAM

FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 cycle delay)

PSout

Data bus

PSA

PS2, PS1, PS0

Set interrupt ﬂag bit T0IF

on overﬂow

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

Instruction Executed

PIC16C7X

DS30390E-page 60  1997 Microchip Technology Inc.

FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 7-4: TIMER0 INTERRUPT TIMING

PC+

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

T0+1

NT0

Instruction Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit (INTCON<2>)

FEh

GIE bit (INTCON<7>)

INSTR

UCTION

Instruction fetched

PC +1 PC +1 0004h 0005h

Instruction executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.

FLO

 1997 Microchip Technology Inc. DS30390E-page 61

PIC16C7X

7.2 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T

OSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

7.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 7-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical speciﬁcation of the desired device.

Applicable Devices

73 73A 74 74A 76 77

When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Ref er to parameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

7.2.2 TMR0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 7-5 shows the dela y from the external clock edge to the timer incrementing.

FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or Prescaler output

(2)

External Clock/Prescaler Output after sampling

Increment Timer0 (Q4)

Timer0

T0 T0 + 1 T0 + 2

Small pulse misses sampling

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

(3)

(1)

PIC16C7X

DS30390E-page 62  1997 Microchip Technology Inc.

7.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

Applicable Devices

73 73A 74 74A 76 77

The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.

FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

M U

CLKOUT (=Fosc/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

U X

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS

 1997 Microchip Technology Inc. DS30390E-page 63

PIC16C7X

7.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program execution.

EXAMPLE 7-1: CHANGING PRESCALER (TIMER0→WDT)

To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 7-2.

EXAMPLE 7-2: CHANGING PRESCALER (WDT→TIMER0)

CLRWDT ;Clear WDT and prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and MOVWF OPTION_REG ;clock source BCF STATUS, RP0 ;Bank 0

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

Note: To avoid an unintended device RESET, the

following instruction sequence (shown in Example 7-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

1) BSF STATUS, RP0 ;Bank 1

Lines 2 and 3 do NOT have to be included if the ﬁnal desired prescale value is other than 1:1. If 1:1 is ﬁnal desired value, then a temporary prescale value is set in lines 2 and 3 and the ﬁnal prescale value will be set in lines 10 and 11.

2) MOVLW b'xx0x0xxx' ;Select clock source and prescale value of

3) MOVWF OPTION_REG ;other than 1:1

4) BCF STATUS, RP0 ;Bank 0

5) CLRF TMR0 ;Clear TMR0 and prescaler

6) BSF STATUS, RP1 ;Bank 1

7) MOVLW b'xxxx1xxx' ;Select WDT, do not change prescale value

8) MOVWF OPTION_REG ;

9) CLRWDT ;Clears WDT and prescaler

10) MOVLW b'xxxx1xxx' ;Select new prescale value and WDT

11) MOVWF OPTION_REG ;

12) BCF STATUS, RP0 ;Bank 0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other resets

01h,101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh,

10Bh,18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PIC16C7X

DS30390E-page 64  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30390E-page 65

PIC16C7X

8.0 TIMER1 MODULE

The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overﬂow which is latched in interrupt ﬂag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

Timer1 can operate in one of two modes:

• As a timer

• As a counter The operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

Applicable Devices

73 73A 74 74A 76 77

In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising edge of the external clock input.

Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).

Timer1 also has an internal “reset input”. This reset can be generated by either of the two CCP modules (Section 10.0). Figure 8-1 shows the Timer1 control register.

For the PIC16C72/73A/74A/76/77, when the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/ T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.

For the PIC16C73/74, when the Timer1 oscillator is enabled (T1OSCEN is set), RC1/T1OSI/CCP2 pin becomes an input, however the RC0/T1OSO/T1CKI pin will have to be conﬁgured as an input by setting the TRISC<0> bit.

FIGURE 8-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

R = Readable bit W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value

bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain

bit 2: T1SYNC

: Timer1 External Clock Input Synchronization Control bit

TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input

TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1: TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (F

OSC/4)

bit 0: TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

PIC16C7X

DS30390E-page 66  1997 Microchip Technology Inc.

8.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is F

OSC/4. The synchronize control bit T1SYNC

(T1CON<2>) has no effect since the internal clock is always in sync.

8.2 Timer1 Operation in Synchronized Counter Mode

Counter mode is selected by setting bit TMR1CS. In this mode the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2 when bit T1OSCEN is set or pin RC0/T1OSO/T1CKI when bit T1OSCEN is cleared.

If T1SYNC

is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple-counter.

In this conﬁguration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. The prescaler however will continue to increment.

Applicable Devices

73 73A 74 74A 76 77

Applicable Devices

72 73 73A 74 74A 76 77

8.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE

When an external clock input is used for Timer1 in synchronized counter mode, it must meet certain requirements. The external clock requirement is due to internal phase clock (Tosc) synchronization. Also, there is a delay in the actual incrementing of TMR1 after synchronization.

When the prescaler is 1:1, the external clock input is the same as the prescaler output. The synchronization of T1CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T1CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the appropriate electrical speciﬁcations, parameters 45, 46, and 47.

When a prescaler other than 1:1 is used, the external clock input is divided by the asynchronous ripplecounter type prescaler so that the prescaler output is symmetrical. In order for the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T1CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T1CKI high and low time is that the y do not violate the minimum pulse width requirements of 10 ns). Refer to the appropriate electrical speciﬁcations, parameters 40, 42, 45, 46, and 47.

FIGURE 8-2: TIMER1 BLOCK DIAGRAM

TMR1H

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

SLEEP input

T1OSCEN

Enable

Oscillator

(1)

FOSC/4

Internal

Clock

TMR1ON

on/off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

clock input

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

(2)

Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

2: The CCP2 module is not implemented in the PIC16C72. 3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode.

Set ﬂag bit TMR1IF on Overﬂow

TMR1

(3)

 1997 Microchip Technology Inc. DS30390E-page 67

PIC16C7X

8.3 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overﬂow which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 8.3.2).

In asynchronous counter mode, Timer1 can not be used as a time-base for capture or compare operations.

8.3.1 EXTERNAL CLOCK INPUT TIMING WITH UNSYNCHRONIZED CLOCK

If control bit T1SYNC

is set, the timer will increment completely asynchronously. The input clock must meet certain minimum high time and low time requirements. Refer to the appropriate Electrical Speciﬁcations Section, timing parameters 45, 46, and 47.

8.3.2 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L while the timer is running, from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself poses certain problems since the timer may overﬂow between the reads.

For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register.

Reading the 16-bit value requires some care. Example 8-1 is an example routine to read the 16-bit timer value. This is useful if the timer cannot be stopped.

Applicable Devices

73 73A 74 74A 76 77

EXAMPLE 8-1: READING A 16-BIT FREE-

RUNNING TIMER

; All interrupts are disabled MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; MOVF TMR1H, W ;Read high byte SUBWF TMPH, W ;Sub 1st read ; with 2nd read BTFSC STATUS,Z ;Is result = 0 GOTO CONTINUE ;Good 16-bit read ; ; TMR1L may have rolled over between the read ; of the high and low bytes. Reading the high ; and low bytes now will read a good value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupt (if required) CONTINUE ;Continue with your code

8.4 Timer1 Oscillator

A crystal oscillator circuit is built in between pins T1OSI (input) and T1OSO (ampliﬁer output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 8-1 shows the capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.

TABLE 8-1: CAPACITOR SELECTION

FOR THE TIMER1 OSCILLATOR

Applicable Devices

73 73A 74 74A 76 77

Osc Type Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitance increases the stability

of oscillator but also increases the start-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

PIC16C7X

DS30390E-page 68  1997 Microchip Technology Inc.

8.5 Resetting Timer1 using a CCP Trigger Output

The CCP2 module is not implemented on the PIC16C72 device.

If the CCP1 or CCP2 module is conﬁgured in compare mode to generate a “special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1.

Timer1 must be conﬁgured for either timer or synchronized counter mode to take advantage of this feature. If Timer1 is running in asynchronous counter mode, this reset operation may not work.

In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence.

In this mode of operation, the CCPRxH:CCPRxL registers pair effectively becomes the period register for Timer1.

Applicable Devices

73 73A 74 74A 76 77

Note: The special event triggers from the CCP1

and CCP2 modules will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

8.6 Resetting of Timer1 Register Pair (TMR1H, TMR1L)

TMR1H and TMR1L registers are not reset to 00h on a POR or any other reset except by the CCP1 and CCP2 special event triggers.

T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other resets, the register is unaffected.

8.7 Timer1 Prescaler

The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.

Applicable Devices

73 73A 74 74A 76 77

Applicable Devices

73 73A 74 74A 76 77

TABLE 8-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other

resets

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 PSPIF

(1,2)

ADIF RCIF

(2)

TXIF

(2)

SSPIF CCP1IF TMR2IF TMR1IF

0000 0000 0000 0000

8Ch PIE1 PSPIE

(1,2)

ADIE RCIE

(2)

TXIE

(2)

SSPIE CCP1IE TMR2IE TMR1IE

0000 0000 0000 0000

0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1 register

xxxx xxxx uuuu uuuu

10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

--00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.

2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.

 1997 Microchip Technology Inc. DS30390E-page 69

PIC16C7X

9.0 TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device reset.

The input clock (F

OSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).

The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon reset.

The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in ﬂag bit TMR2IF, (PIR1<1>)).

Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption.

Figure 9-2 shows the Timer2 control register.

Applicable Devices

73 73A 74 74A 76 77

9.1 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device reset (Power-on Reset, MCLR

reset,

Watchdog Timer reset, or Brown-out Reset)

TMR2 is not cleared when T2CON is written.

9.2 Output of TMR2

The output of TMR2 (bef ore the postscaler) is fed to the Synchronous Serial Port module which optionally uses it to generate shift clock.

FIGURE 9-1: TIMER2 BLOCK DIAGRAM

Applicable Devices

73 73A 74 74A 76 77

Applicable Devices

73 73A 74 74A 76 77

Comparator

TMR2

Sets ﬂag

TMR2 reg

output

(1)

Reset

Postscaler

Prescaler

PR2 reg

OSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1: TMR2 register output can be software selected

by the SSP Module as a baud clock.

PIC16C7X

DS30390E-page 70  1997 Microchip Technology Inc.

FIGURE 9-2: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)

TABLE 9-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale 0001 = 1:2 Postscale

•

• 1111 = 1:16 Postscale

bit 2: TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other

resets

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 PSPIF

(1,2)

ADIF RCIF

(2)

TXIF

(2)

SSPIF CCP1IF TMR2IF TMR1IF

0000 0000 0000 0000

8Ch PIE1

PSPIE

(1,2)

ADIE RCIE

(2)

TXIE

(2)

SSPIE CCP1IE TMR2IE TMR1IE

0000 0000 0000 0000

11h TMR2 Timer2 module’s register

0000 0000 0000 0000

12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000 -000 0000

92h PR2 Timer2 Period Register

1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.

2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'.

 1997 Microchip Technology Inc. DS30390E-page 71

PIC16C7X

10.0 CAPTURE/COMPARE/PWM MODULE(s)

Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Both the CCP1 and CCP2 modules are identical in operation, with the exception of the operation of the special event trigger. Table 10-1 and Table 10-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted.

Applicable Devices

72 73 73A 74 74A 76 77 CCP1 72 73 73A 74 74A 76 77 CCP2

CCP1 module:

Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable.

CCP2 module:

Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable.

For use of the CCP modules, refer to the Embedded Control Handbook,

"Using the CCP Modules"

(AN594).

TABLE 10-1: CCP MODE - TIMER

RESOURCE

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1 Timer1 Timer2

TABLE 10-2: INTERACTION OF TWO CCP MODULES

CCPx Mode CCPy Mode Interaction

Capture Capture Same TMR1 time-base. Capture Compare The compare should be conﬁgured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be conﬁgured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None

PIC16C7X

DS30390E-page 72  1997 Microchip Technology Inc.

FIGURE 10-1: CCP1CON REGISTER (ADDRESS 17h)/CCP2CON REGISTER (ADDRESS 1Dh)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Signiﬁcant bits

Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM off (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1

and starts an A/D conversion (if A/D module is enabled))

11xx = PWM mode

10.1 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an e v ent occurs on pin RC2/CCP1. An event is deﬁned as:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0

(CCP1CON<3:0>). When a capture is made, the interrupt request ﬂag bit CCP1IF (PIR1<2>) is set. It must be cleared in software. If another capture occurs bef ore the value in register CCPR1 is read, the old captured value will be lost.

10.1.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be conﬁg-

ured as an input by setting the TRISC<2> bit.

Applicable Devices

73 73A 74 74A 76 77

Note: If the RC2/CCP1 is conﬁgured as an out-

put, a write to the port can cause a capture condition.

FIGURE 10-2: CAPTURE MODE

OPERATION BLOCK DIAGRAM

10.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized

counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work.

10.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the ﬂag bit CCP1IF following any such change in operating mode.

CCPR1H CCPR1L

TMR1H TMR1L

Set ﬂag bit CCP1IF

(PIR1<2>)

Capture Enable

Q’s

CCP1CON<3:0>

RC2/CCP1

Prescaler ÷ 1, 4, 16

and

edge detect

 1997 Microchip Technology Inc. DS30390E-page 73

PIC16C7X

10.1.4 CCP PRESCALER

There are four prescaler settings, speciﬁed by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in capture mode, the prescaler counter is cleared. This means that any reset will clear the prescaler counter.

Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore the ﬁrst capture may be from a non-zero prescaler. Example 10-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt.

EXAMPLE 10-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with ; the new prescaler ; mode value and CCP ON MOVWF CCP1CON ;Load CCP1CON with this ; value

10.2 Compare Mode

In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is:

• Driven High

• Driven Low

• Remains Unchanged

The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt ﬂag bit CCP1IF is set.

FIGURE 10-3: COMPARE MODE

OPERATION BLOCK DIAGRAM

Applicable Devices

73 73A 74 74A 76 77

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set ﬂag bit CCP1IF (PIR1<2>)

match

RC2/CCP1

TRISC<2>

CCP1CON<3:0> Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt ﬂag bit TMR1IF (PIR1<0>), and set bit GO/DONE

(ADCON0<2>) which starts an A/D conversion (CCP1 only for PIC16C72, CCP2 only for PIC16C73/73A/74/74A/76/77).

10.2.1 CCP PIN CONFIGURATION The user must conﬁgure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

10.2.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.

10.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1

pin is not affected. Only a CCP interrupt is generated (if enabled).

10.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated

which may be used to initiate an action. The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1.

The special trigger output of CCP2 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled).

For the PIC16C72 only, the special event trigger output of CCP1 resets the TMR1 register pair, and starts an A/D conversion (if the A/D module is enabled).

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to the default low level. This is not the data latch.

Note: The special event trigger from the

CCP1and CCP2 modules will not set interrupt ﬂag bit TMR1IF (PIR1<0>).

PIC16C7X

DS30390E-page 74  1997 Microchip Technology Inc.

10.3 PWM Mode

In Pulse Width Modulation (PWM) mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the POR TC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output.

Figure 10-4 shows a simpliﬁed block diagram of the CCP module in PWM mode.

For a step by step procedure on how to set up the CCP module for PWM operation, see Section 10.3.3.

FIGURE 10-4: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 10-5) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).

FIGURE 10-5: PWM OUTPUT

Applicable Devices

73 73A 74 74A 76 77

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty cycle registers

CCP1CON<5:4>

Clear Timer, CCP1 pin and latch D.C.

TRISC<2>

RC2/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

10.3.1 PWM PERIOD The PWM period is speciﬁed by writing to the PR2 reg-

ister. The PWM period can be calculated using the following formula:

PWM period = [(PR2) + 1] • 4 • T

OSC •

(TMR2 prescale value)

PWM frequency is deﬁned as 1 / [PWM period]. When TMR2 is equal to PR2, the f ollowing three e v ents

occur on the next increment cycle:

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from CCPR1L into CCPR1H

10.3.2 PWM DUTY CYCLE

The PWM duty cycle is speciﬁed by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) • Tosc • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM frequency:

Note: The Timer2 postscaler (see Section 9.1) is

not used in the determination of the PWM frequency . The postscaler could be used to have a servo update rate at a different frequency than the PWM output.

Note: If the PWM duty cycle value is longer than

the PWM period the CCP1 pin will not be cleared.

log(

PWM

log(2)

OSC

)

bits

 1997 Microchip Technology Inc. DS30390E-page 75

PIC16C7X

EXAMPLE 10-2: PWM PERIOD AND DUTY

CYCLE CALCULATION

Desired PWM frequency is 78.125 kHz, Fosc = 20 MHz TMR2 prescale = 1

1/78.125 kHz= [(PR2) + 1] • 4 • 1/20 MHz • 1

12.8 µs = [(PR2) + 1] • 4 • 50 ns • 1 PR2 = 63

Find the maximum resolution of the duty cycle that can be used with a 78.125 kHz frequency and 20 MHz oscillator:

1/78.125 kHz= 2

PWM RESOLUTION

• 1/20 MHz • 1

12.8 µs= 2

PWM RESOLUTION

• 50 ns • 1

256 = 2

PWM RESOLUTION

log(256) = (PWM Resolution) • log(2)

8.0 = PWM Resolution

At most, an 8-bit resolution duty cycle can be obtained from a 78.125 kHz frequency and a 20 MHz oscillator, i.e., 0 ≤ CCPR1L:CCP1CON<5:4> ≤ 255. Any value greater than 255 will result in a 100% duty cycle.

In order to achieve higher resolution, the PWM frequency must be decreased. In order to achieve higher PWM frequency, the resolution must be decreased.

Table 10-3 lists example PWM frequencies and resolutions for Fosc = 20 MHz. The TMR2 prescaler and PR2 values are also shown.

10.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when conﬁguring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2 register.

2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the TRISC<2> bit.

4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON.

5. Conﬁgure the CCP1 module for PWM operation.

TABLE 10-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

TABLE 10-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1111 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all other

resets

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1

PSPIF

(1,2)

ADIF RCIF

(2)

TXIF

(2)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh

(2)

PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

8Ch PIE1

PSPIE

(1,2)

ADIE RCIE

(2)

TXIE

(2)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh

(2)

PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Signiﬁcant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Signiﬁcant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh

(2)

CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu

1Ch

(2)

CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu

1Dh

(2)

CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.

2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.

PIC16C7X

DS30390E-page 76  1997 Microchip Technology Inc.

TABLE 10-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

resets

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1

PSPIF

(1,2)

ADIF RCIF

(2)

TXIF

(2)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh

(2)

PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

8Ch PIE1

PSPIE

(1,2)

ADIE RCIE

(2)

TXIE

(2)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh

(2)

PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

11h TMR2 Timer2 module’s register 0000 0000 0000 0000 92h PR2 Timer2 module’ s period register 1111 1111 1111 1111 12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON

— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh

(2)

CCPR2L Capture/Compare/PWM register2 (LSB) xxxx xxxx uuuu uuuu

1Ch

(2)

CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu

1Dh

(2)

CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.

2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'.

 1997 Microchip Technology Inc. DS30390E-page 77

PIC16C7X

11.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE

11.1 SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I

The SSP module in I

C mode works the same in all PIC16C7X devices that have an SSP module . However the SSP Module in SPI mode has differences between the PIC16C76/77 and the other PIC16C7X devices.

The register deﬁnitions and operational description of SPI mode has been split into two sections because of the differences between the PIC16C76/77 and the other PIC16C7X devices. The default reset values of both the SPI modules is the same regardless of the device:

11.2 SPI Mode for PIC16C72/73/73A/74/74A..........78

11.3 SPI Mode for PIC16C76/77..............................83

11.4 I2C™ Overview................................................89

11.5 SSP I2C Operation...........................................93

Refer to Application Note AN578,

“Use of the SSP

Module in the I

C Multi-Master Environment.”

Applicable Devices

72 73 73A 74 74A 76 77

PIC16C7X

DS30390E-page 78  1997 Microchip Technology Inc.

11.2 SPI Mode for PIC16C72/73/73A/74/74A

This section contains register deﬁnitions and operational characteristics of the SPI module for the PIC16C72, PIC16C73, PIC16C73A, PIC16C74, PIC16C74A.

FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)

U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0

— — D/A P S R/W UA BF R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5: D/A: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address

bit 4: P: Stop bit (I

C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last

bit 3: S: Start bit (I

C mode only. This bit is cleared when the SSP module is disabled, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last

bit 2: R/W

: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is valid from the address match to the next start bit, stop bit, or A

CK bit. 1 = Read 0 = Write

bit 1: UA: Update Address (10-bit I

C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated

bit 0: BF: Buffer Full Status bit

Receiv

e (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

ransmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty

Applicable Devices

72 73 73A 74 74A 76 77

 1997 Microchip Technology Inc. DS30390E-page 79

PIC16C7X

FIGURE 11-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision

bit 6: SSPOV: Receive Overﬂow Detect bit

In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the pre vious data. In case of ov erﬂow , the data in SSPSR register is lost. Overﬂow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overﬂow. In master mode the overﬂow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overﬂow

In I

C mode 1 = A byte is received while the SSPBUF register is still holding the pre vious byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overﬂow

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode 1 = Enables serial port and conﬁgures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins

In I

C mode 1 = Enables the serial port and conﬁgures the SDA and SCL pins as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins In both modes, when enabled, these pins must be properly conﬁgured as input or output.

bit 4: CKP: Clock Polarity Select bit

In SPI mode 1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge. 0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.

In I

C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master mode, clock = Fosc/4 0001 = SPI master mode, clock = Fosc/16 0010 = SPI master mode, clock = Fosc/64 0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS

pin control enabled.

0101 = SPI slave mode, clock = SCK pin. SS

pin control disabled. SS can be used as I/O pin.

0110 = I

C slave mode, 7-bit address

0111 = I

C slave mode, 10-bit address

1011 = I

C firmware controlled Master Mode (slave idle)

1110 = I

C slave mode, 7-bit address with start and stop bit interrupts enabled

1111 = I

C slave mode, 10-bit address with start and stop bit interrupts enabled

Applicable Devices

72 73 73A 74 74A 76 77

PIC16C7X

DS30390E-page 80  1997 Microchip Technology Inc.

11.2.1 OPERATION OF SSP MODULE IN SPI MODE

The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO)

• Serial Data In (SDI)

• Serial Clock (SCK)

Additionally a fourth pin may be used when in a slave mode of operation:

• Slave Select (SS

)

When initializing the SPI, several options need to be speciﬁed. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>). These control bits allow the following to be speciﬁed:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Output/Input data on the Rising/

Falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

The SSP consists of a transmit/receive Shift Register (SSPSR) and a Buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb ﬁrst. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8-bits of data have been received, that b yte is mo v ed to the SSPBUF register. Then the Buffer Full bit, BF (SSPSTAT<0>) and ﬂag bit SSPIF are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON<7>) will be set. User software must clear bit WCOL so that it can be determined if the following write(s) to the SSPBUF completed successfully. When the application software is expecting to receive v alid data, the SSPB UF register should be read before the next byte of data to transfer is written to the SSPBUF register. The Buffer Full bit BF (SSPSTAT<0>) indicates when the SSPBUF register has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF register must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 11-1 shows the loading of the SSPBUF (SSPSR) register for data transmission. The shaded instruction is only required if the received data is meaningful.

Applicable Devices

73 73A 74 74A 76 77

EXAMPLE 11-1: LOADING THE SSPBUF

(SSPSR) REGISTER

The block diagram of the SSP module, when in SPI mode (Figure 11-3), shows that the SSPSR register is not directly readable or writable, and can only be accessed from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status conditions.

FIGURE 11-3: SSP BLOCK DIAGRAM

(SPI MODE)

BSF STATUS, RP0 ;Specify Bank 1

LOOP BTFSS SSPSTAT, BF ;Has data been

;received ;(transmit

;complete)? GOTO LOOP ;No BCF STATUS, RP0 ;Specify Bank 0 MOVF SSPBUF, W ;W reg = contents

;of SSPBUF MOVWF RXDATA ;Save in user RAM MOVF TXDATA, W ;W reg = contents

; of TXDATA MOVWF SSPBUF ;New data to xmit

Read Write

Internal

data bus

RC4/SDI/SDA

RC5/SDO

RA5/SS

/AN4

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

Control Enable

Edge

Select

Clock Select

TMR2 output

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

Applicable Devices

72 73 73A 74 74A 76 77

 1997 Microchip Technology Inc. DS30390E-page 81

PIC16C7X

To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconﬁgure SPI mode, clear enable bit SSPEN, re-initialize SSPCON register, and then set enable bit SSPEN. This conﬁgures the SDI, SDO, SCK, and SS

pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRIS register) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

•SS

must have TRISA<5> set (if implemented)

Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. An example would be in master mode where you are only sending data (to a display driver), then both SDI and SS

could be used as general purpose outputs by clearing their corresponding TRIS register bits.

Figure 11-4 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

The master can initiate the data transfer at any time because it controls the SCK. The master deter mines when the slave (Processor 2) is to broadcast data by the software protocol.

In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SCK output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a “line activity monitor” mode.

In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched interrupt ﬂag bit SSPIF (PIR1<3>) is set.

The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give waveforms for SPI communication as shown in Figure 11-5 and Figure 11-6 where the MSB is transmitted ﬁrst. In master mode, the SPI cloc k rate (bit r ate) is user programmable to be one of the following:

• Fosc/4 (or T

CY)

• Fosc/16 (or 4 • T

CY)

• Fosc/64 (or 16 • T

CY)

• Timer2 output/2 This allows a maximum bit clock frequency (at 20 MHz)

of 5 MHz. When in slave mode the external clock must meet the minimum high and low times.

In sleep mode, the slave can transmit and receive data and wake the device from sleep.

FIGURE 11-4: SPI MASTER/SLAVE CONNECTION

Serial Input Buffer

(SSPBUF register)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF register)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

Applicable Devices

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PIC16C7X

DS30390E-page 82  1997 Microchip Technology Inc.

The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set the for synchronous slave mode to be enabled. When the SS

pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS

pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ﬂoating output. If the SS

pin is taken low without resetting

SPI mode, the transmission will continue from the

point at which it was taken high. External pull-up/ pull-down resistors may be desirable , depending on the application.

To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver the SDO pin can be conﬁgured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function) since it cannot create a bus conﬂict.

FIGURE 11-5: SPI MODE TIMING, MASTER MODE OR SLAVE MODE W/O SS CONTROL

FIGURE 11-6: SPI MODE TIMING, SLAVE MODE WITH SS CONTROL

TABLE 11-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

resets

0Bh,8Bh INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1,2)

ADIF RCIF

(2)

TXIF

(2)

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE

(1,2)

ADIE RCIE

(2)

TXIE

(2)

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 94h SSPSTAT — — D/A P S R/W UA BF --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear.

2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'.

SCK (CKP = 0) SCK (CKP = 1)

SDO

SDI

SSPIF

bit7

bit7 bit0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

SCK (CKP = 0) SCK (CKP = 1)

SDO

SDI

SSPIF

bit7

bit7 bit0

bit6 bit5 bit4 bit3 bit2 bit1 bit0

Applicable Devices

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PIC16C7X

11.3 SPI Mode for PIC16C76/77

This section contains register deﬁnitions and operational characteristics of the SPI module on the PIC16C76 and PIC16C77 only.

FIGURE 11-7: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h)(PIC16C76/77)

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A

P S R/W UA BF R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: SMP: SPI data input sample phase

SPI Master Mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Sla

ve Mode

SMP must be cleared when SPI is used in slave mode

bit 6: CKE: SPI Clock Edge Select (Figure 11-11, Figure 11-12, and Figure 11-13)

CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK

bit 5: D/A

: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address

bit 4: P: Stop bit (I

C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last

bit 3: S: Start bit (I

C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last

bit 2: R/W

: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or A

CK bit. 1 = Read 0 = Write

bit 1: UA: Update Address (10-bit I

C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated

bit 0: BF: Buffer Full Status bit

Receiv

e (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

ransmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty

Applicable Devices

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PIC16C7X

DS30390E-page 84  1997 Microchip Technology Inc.

FIGURE 11-8: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)(PIC16C76/77)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision

bit 6: SSPOV: Receive Overﬂow Indicator bit

In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the pre vious data. In case of ov erﬂow , the data in SSPSR is lost. Ov erﬂow can only occur in sla v e mode . The user must read the SSPBUF, even if only transmitting data, to avoid setting overﬂow. In master mode the overﬂow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overﬂow

In I

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode 1 = Enables serial port and conﬁgures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and conﬁgures these pins as I/O port pins

In I

bit 4: CKP: Clock Polarity Select bit

In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I

C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master mode, clock = F

OSC/4

0001 = SPI master mode, clock = F

OSC/16

0010 = SPI master mode, clock = F

OSC/64

0011 = SPI master mode, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS

pin control enabled.

0101 = SPI slave mode, clock = SCK pin. SS

pin control disabled. SS can be used as I/O pin

0110 = I

C slave mode, 7-bit address

0111 = I

C slave mode, 10-bit address

1011 = I

C firmware controlled master mode (slave idle)

1110 = I

C slave mode, 7-bit address with start and stop bit interrupts enabled

1111 = I

C slave mode, 10-bit address with start and stop bit interrupts enabled

Applicable Devices

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PIC16C7X

11.3.1 SPI MODE FOR PIC16C76/77 The SPI mode allows 8-bits of data to be synchro-

nously transmitted and received simultaneously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK) RC3/SCK/SCL Additionally a fourth pin may be used when in a slave

mode of operation:

• Slave Select (SS

) RA5/SS/AN4

When initializing the SPI, several options need to be speciﬁed. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be speciﬁed:

• Master Mode (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of SCK)

• Clock Rate (Master mode only)

• Slave Select Mode (Slave mode only)

The SSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb ﬁrst. The SSPBUF holds the data that was written to the SSPSR until the received data is ready. Once the 8-bits of data have been received, that b yte is mo v ed to the SSPBUF register. Then the buffer full detect bit BF (SSPSTAT<0>) and interrupt ﬂag bit SSPIF (PIR1<3>) are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. An y write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit WCOL (SSPCON<7>) will be set. User software m ust clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit BF (SSPSTAT<0>) indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the SSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 11-2 shows the loading of the SSPBUF (SSPSR) for data transmission. The shaded instruction is only required if the received data is meaningful.

EXAMPLE 11-2: LOADING THE SSPBUF

(SSPSR) REGISTER (PIC16C76/77)

BCF STATUS, RP1 ;Specify Bank 1 BSF STATUS, RP0 ; LOOP BTFSS SSPSTAT, BF ;Has data been ;received ;(transmit ;complete)? GOTO LOOP ;No BCF STATUS, RP0 ;Specify Bank 0 MOVF SSPBUF, W ;W reg = contents ; of SSPBUF

MOVF TXDATA, W ;W reg = contents ; of TXDATA MOVWF SSPBUF ;New data to xmit

The block diagram of the SSP module, when in SPI mode (Figure 11-9), shows that the SSPSR is not directly readable or writable, and can only be accessed from addressing the SSPBUF register. Additionally, the SSP status register (SSPSTAT) indicates the various status conditions.

FIGURE 11-9: SSP BLOCK DIAGRAM

(SPI MODE)(PIC16C76/77)

MOVWF RXDATA ;Save in user RAM

Read Write

Internal

data bus

RC4/SDI/SDA

RC5/SDO

RA5/S

S/AN4

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

shift

clock

Control Enable

Edge

Select

Clock Select

TMR2 output

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

Applicable Devices

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PIC16C7X

DS30390E-page 86  1997 Microchip Technology Inc.

To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconﬁgure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This conﬁgures the SDI, SDO, SCK, and SS

pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

•SS

must have TRISA<5> set

could be used as general purpose outputs by clearing their corresponding TRIS register bits.

Figure 11-10 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application ﬁrmware. This leads to three scenar ios for data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

The master can initiate the data transfer at any time because it controls the SCK. The master deter mines when the slave (Processor 2) is to broadcast data by the ﬁrmware protocol.

In slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched the interrupt ﬂag bit SSPIF (PIR1<3>) is set.

The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then would give waveforms for SPI communication as shown in Figure 11-11, Figure 11-12, and Figure 11-13 where the MSB is transmitted ﬁrst. In master mode, the SPI clock rate (bit rate) is user programmable to be one of the following:

•F

OSC/4 (or TCY)

•F

OSC/16 (or 4 • TCY)

•F

OSC/64 (or 16 • TCY)

• Timer2 output/2 This allows a maximum bit clock frequency (at 20 MHz)

of 5 MHz. When in slave mode the external clock must meet the minimum high and low times.

In sleep mode, the slave can transmit and receive data and wake the device from sleep.

FIGURE 11-10: SPI MASTER/SLAVE CONNECTION (PIC16C76/77)

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

Applicable Devices

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 1997 Microchip Technology Inc. DS30390E-page 87

PIC16C7X

The SS pin allows a synchronous slave mode. The SPI must be in slave mode (SSPCON<3:0> = 04h) and the TRISA<5> bit must be set for the synchronous slave mode to be enabled. When the SS

pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS

pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a ﬂoating output. If the SS

pin is taken low without resetting SPI mode, the transmission will continue from the point at which it was taken high. External pull-up/ pull-down resistors may be desirable , depending on the application.

Note: When the SPI is in Slave Mode with SS pin

control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS

pin is set

to V

DD.

Note: If the SPI is used in Slave Mode with

CKE = '1', then the SS

pin control must be

enabled.

FIGURE 11-11: SPI MODE TIMING, MASTER MODE (PIC16C76/77)

FIGURE 11-12: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) (PIC16C76/77)

SCK (CKP = 0,

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5

bit4

bit3

bit2

bit1 bit0

SDI (SMP = 1)

SCK (CKP = 0,

SCK (CKP = 1,

SDO

bit7

bit7 bit0

bit0

CKE = 0)

CKE = 1)

CKE = 0)

CKE = 1)

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7 bit6 bit5

bit4

bit3

bit2

bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

SS (optional)

Applicable Devices

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PIC16C7X

DS30390E-page 88  1997 Microchip Technology Inc.

FIGURE 11-13: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) (PIC16C76/77)

TABLE 11-2: REGISTERS ASSOCIATED WITH SPI OPERATION (PIC16C76/77)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on

all other

resets

0Bh,8Bh. 10Bh,18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

— — PORTA Data Direction Register --11 1111 --11 1111

94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear.

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7

bit6 bit5

bit4

bit3

bit2

bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

SS (not optional)

Applicable Devices

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PIC16C7X

11.4 I2C™ Overview

This section provides an overview of the Inter-Integrated Circuit (I

C) bus, with Section 11.5 discussing

the operation of the SSP module in I

C mode.

The I

C bus is a two-wire serial interface developed by the Philips Corporation. The original speciﬁcation, or standard mode, was for data transfers of up to 100 Kbps. The enhanced speciﬁcation (fast mode) is also supported. This device will communicate with both standard and fast mode devices if attached to the same bus. The clock will determine the data rate.

The I

C interface employs a comprehensiv e protocol to ensure reliable transmission and reception of data. When transmitting data, one device is the “master” which initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the “slave.” All portions of the slave protocol are implemented in the SSP module’s hardware, except general call support, while portions of the master protocol need to be addressed in the PIC16CXX software. Table 11-3 deﬁnes some of the I

C bus terminology. For additional information on the

C interface speciﬁcation, refer to the Philips docu-

ment “

The I2C bus and how to use it.”

#939839340011,

which can be obtained from the Philips Corporation. In the I

C interface protocol each device has an address. When a master wishes to initiate a data transfer, it ﬁrst transmits the address of the device that it wishes to “talk” to. All devices “listen” to see if this is their address. Within this address, a bit speciﬁes if the master wishes to read-from/write-to the slave device. The master and slave are always in opposite modes (transmitter/receiver) of operation during a data transfer . That is they can be thought of as operating in either of these two relations:

• Master-transmitter and Slave-receiver

• Slave-transmitter and Master-receiver

In both cases the master generates the clock signal. The output stages of the clock (SCL) and data (SDA)

lines must have an open-drain or open-collector in order to perform the wired-AND function of the bus. External pull-up resistors are used to ensure a high level when no de vice is pulling the line do wn. The number of devices that may be attached to the I

C bus is limited only by the maximum bus loading speciﬁcation of 400 pF.

11.4.1 INITIATING AND TERMINATING DATA

TRANSFER

During times of no data transfer (idle time), both the clock line (SCL) and the data line (SDA) are pulled high through the external pull-up resistors. The START and STOP conditions determine the start and stop of data transmission. The STAR T condition is deﬁned as a high to low transition of the SDA when the SCL is high. The STOP condition is deﬁned as a low to high transition of the SDA when the SCL is high. Figure 11-14 shows the START and STOP conditions. The master generates these conditions for starting and terminating data transfer. Due to the deﬁnition of the START and STOP conditions, when data is being transmitted, the SDA line can only change state when the SCL line is low.

FIGURE 11-14: START AND STOP

CONDITIONS

SDA

SCL

Start

Condition

Change

of Data

Allowed

Change

of Data

Allowed

Stop

Condition

TABLE 11-3: I2C BUS TERMINOLOGY

Term Description

Transmitter The device that sends the data to the bus. Receiver The device that receives the data from the bus. Master The device which initiates the transfer, generates the clock and terminates the transfer. Slave The device addressed by a master. Multi-master More than one master device in a system. These masters can attempt to control the bus at the

same time without corrupting the message.

Arbitration Procedure that ensures that only one of the master devices will control the bus. This ensure that

the transfer data does not get corrupted.

Synchronization Procedure where the clock signals of two or more devices are synchronized.

Applicable Devices

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DS30390E-page 90  1997 Microchip Technology Inc.

11.4.2 ADDRESSING I2C DEVICES There are two address formats. The simplest is the

7-bit address format with a R/W

bit (Figure 11-15). The

more complex is the 10-bit address with a R/W

bit (Figure 11-16). For 10-bit address format, two bytes must be transmitted with the ﬁrst ﬁve bits specifying this to be a 10-bit address.

FIGURE 11-15: 7-BIT ADDRESS FORMAT

FIGURE 11-16: I

C 10-BIT ADDRESS FORMAT

11.4.3 TRANSFER ACKNOWLEDGE All data must be transmitted per byte, with no limit to the

number of bytes transmitted per data transfer. After each byte, the slave-receiver generates an acknowledge bit (A

CK) (Figure 11-17). When a slave-receiver doesn’t acknowledge the slave address or received data, the master must abort the transfer. The slave must leave SDA high so that the master can generate the STOP condition (Figure 11-14).

R/W

ACK

Sent by

Slave

slave address

S R/W

Read/Write pulse

MSb LSb

Start Condition

ACK

Acknowledge

S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK

sent by slave = 0 for write

S R/W ACK

- Start Condition

- Read/Write Pulse

- Acknowledge

FIGURE 11-17: SLAVE-RECEIVER

ACKNOWLEDGE

If the master is receiving the data (master-receiver), it generates an acknowledge signal for each received byte of data, except for the last byte. To signal the end of data to the slave-transmitter, the master does not generate an acknowledge (not acknowledge). The slave then releases the SDA line so the master can generate the STOP condition. The master can also generate the STOP condition during the acknowledge pulse for valid termination of data transfer.

If the slave needs to delay the transmission of the next byte, holding the SCL line low will f orce the master into a wait state. Data transfer continues when the slave releases the SCL line. This allows the slave to move the received data or fetch the data it needs to transfer before allowing the clock to start. This wait state technique can also be implemented at the bit level, Figure 11-18. The sla ve will inherently stretch the cloc k, when it is a transmitter, b ut will not when it is a receiver. The slave will have to clear the SSPCON<4> bit to enable clock stretching when it is a receiver.

Data

Output by

Transmitter

Data

Output by

Receiver

SCL from

Master

Start

Condition

Clock Pulse for

Acknowledgment

not acknowledge

acknowledge

FIGURE 11-18: DATA TRANSFER WAIT STATE

12 789 123 • 89

SDA

SCL

Start

Condition

Address R/W

ACK Wait

State

Data ACK

MSB acknowledgment

signal from receiver

acknowledgment signal from receiver

byte complete interrupt with receiver

clock line held low while interrupts are serviced

Stop

Condition

Applicable Devices

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PIC16C7X

Figure 11-19 and Figure 11-20 show Master-transmitter and Master-receiver data transfer sequences.

When a master does not wish to relinquish the bus (by generating a STOP condition), a repeated START condition (Sr) must be generated. This condition is identical to the start condition (SDA goes high-to-low while

SCL is high), but occurs after a data transfer acknowledge pulse (not the bus-free state). This allows a master to send “commands” to the slave and then receive the requested information or to address a different slave device. This sequence is shown in Figure 11-21.

FIGURE 11-19: MASTER-TRANSMITTER SEQUENCE

FIGURE 11-20: MASTER-RECEIVER SEQUENCE

FIGURE 11-21: COMBINED FORMAT

For 7-bit address:

Slave Address

First 7 bits

S R/W

A1Slave Address

Second byte

Data A Data P

A master transmitter addresses a slave receiver with a 10-bit address.

A/A

Slave AddressR/W A Data A Data A/A P

'0' (write) data transferred

(n bytes - acknowledge)

A master transmitter addresses a slave receiver with a 7-bit address. The transfer direction is not changed.

From master to slave

From slave to master

A = acknowledge (SDA low) A

= not acknowledge (SDA high) S = Start Condition P = Stop Condition

(write)

For 10-bit address:

For 7-bit address:

Slave Address

First 7 bits

S R/W

A1Slave Address

Second byte

A master transmitter addresses a slave receiver with a 10-bit address.

Slave AddressR/W

A Data A Data A P

'1' (read) data transferred

(n bytes - acknowledge)

A master reads a slave immediately after the ﬁrst byte.

From master to slave

From slave to master

A = acknowledge (SDA low) A

= not acknowledge (SDA high) S = Start Condition P = Stop Condition

(write)

For 10-bit address:

Slave Address

First 7 bits

Sr R/W A3 AData A PData

(read)

Combined format:

Combined format - A master addresses a slave with a 10-bit address, then transmits

Slave AddressR/W A Data A/A Sr P

(read) Sr = repeated

Transfer direction of data and acknowledgment bits depends on R/W

bits.

From master to slave From slave to master

A = acknowledge (SDA low) A

= not acknowledge (SDA high) S = Start Condition P = Stop Condition

Slave Address

First 7 bits

Sr R/W A

(write)

data to this slave and reads data from this slave.

Slave Address

Second byte

Data Sr Slave Address

First 7 bits

R/W

A Data A A PA A Data A/A Data

(read)

Slave Address R/W

A Data A/A

Start Condition

(write) Direction of transfer

may change at this point

(read or write)

(n bytes + acknowledge)

Applicable Devices

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PIC16C7X

DS30390E-page 92  1997 Microchip Technology Inc.

11.4.4 MULTI-MASTER The I

C protocol allows a system to have more than one master. This is called multi-master. When two or more masters try to transfer data at the same time, arbitration and synchronization occur.

11.4.4.1 ARBITRATION Arbitration takes place on the SDA line, while the SCL

line is high. The master which transmits a high when the other master transmits a low loses arbitration (Figure 11-22), and turns off its data output stage. A master which lost arbitration can generate clock pulses until the end of the data byte where it lost arbitration. When the master devices are addressing the same device, arbitration continues into the data.

FIGURE 11-22: MULTI-MASTER

ARBITRATION (TWO MASTERS)

Masters that also incorporate the slave function, and have lost arbitration must immediately switch over to slave-receiver mode. This is because the winning master-transmitter may be addressing it.

Arbitration is not allowed between:

• A repeated START condition

• A STOP condition and a data bit

• A repeated START condition and a STOP condi-

tion

Care needs to be taken to ensure that these conditions do not occur.

transmitter 1 loses arbitration

DATA 1 SDA

DATA 1

DATA 2

SDA

SCL

11.2.4.2 Clock Synchronization Clock synchronization occurs after the devices have

started arbitration. This is performed using a wired-AND connection to the SCL line. A high to low transition on the SCL line causes the concerned devices to start counting off their low period. Once a device clock has gone low, it will hold the SCL line low until its SCL high state is reached. The low to high transition of this clock may not change the state of the SCL line, if another device clock is still within its low period. The SCL line is held low by the device with the longest low period. Devices with shorter low periods enter a high wait-state, until the SCL line comes high. When the SCL line comes high, all devices start counting off their high periods. The ﬁrst device to complete its high period will pull the SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure 11-23.

FIGURE 11-23: CLOCK SYNCHRONIZATION

CLK

SCL

wait

state

start counting

HIGH period

counter

reset

Applicable Devices

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PIC16C7X

11.5 SSP I2C Operation

The SSP module in I2C mode fully implements all slave functions, except general call support, and provides interrupts on start and stop bits in hardware to facilitate ﬁrmware implementations of the master functions. The SSP module implements the standard mode speciﬁcations as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA). The user must conﬁgure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>).

FIGURE 11-24: SSP BLOCK DIAGRAM

(I2C MODE)

The SSP module has ﬁve registers for I2C operation. These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directly accessible

• SSP Address Register (SSPADD)

Read Write

SSPSR reg

Match detect

SSPADD reg

Start and

Stop bit detect

SSPBUF reg

Internal

data bus

Addr Match

Set, Reset

S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/

shift

clock

MSb

SDI/

LSb

SDA

The SSPCON register allows control of the I2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I

C modes to be selected:

•I

C Slave mode (7-bit address)

•I

C Slave mode (10-bit address)

•I

C Slave mode (7-bit address), with start and

stop bit interrupts enabled

•I

C Slave mode (10-bit address), with start and

stop bit interrupts enabled

•I

C Firmware controlled Master Mode, slave is

idle

Selection of any I

C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits.

The SSPSTAT register gives the status of the data transfer. This information includes detection of a START or STOP bit, speciﬁes if the received byte was data or address if the next byte is the completion of 10-bit address, and if this will be a read or write data transfer. The SSPSTAT register is read only.

The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered receiver. This allows reception of the next byte to begin before reading the last byte of received data. When the complete byte is received, it is transferred to the SSPBUF register and ﬂag bit SSPIF is set. If another complete byte is received before the SSPBUF register is read, a receiver overﬂow has occurred and bit SSPOV (SSPCON<6>) is set and the byte in the SSPSR is lost.

The SSPADD register holds the slave address. In 10-bit mode, the user first needs to write the high byte of the address (1111 0 A9 A8 0). Following the high byte address match, the low byte of the address needs to be loaded (A7:A0).

Applicable Devices

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PIC16C7X

DS30390E-page 94  1997 Microchip Technology Inc.

11.5.1 SLAVE MODE In slave mode, the SCL and SDA pins must be conﬁg-

ured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter).

When an address is matched or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (A

CK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register.

There are certain conditions that will cause the SSP module not to give this A

CK pulse. These are if either

(or both): a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overﬂow bit SSPO V (SSPCON<6>) w as set

before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 11-4 shows what happens when a data transfer byte is received, given the status of bits BF and SSPO V. The shaded cells show the condition where user software did not properly clear the overﬂow condition. Flag bit BF is cleared by reading the SSPBUF register while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I

C speciﬁcation as well as the requirement of the SSP module is shown in timing parameter #100 and parameter #101.

11.5.1.1 ADDRESSING Once the SSP module has been enabled, it waits for a

START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register. b) The buffer full bit, BF is set. c) An A

CK pulse is generated.

d) SSP interrupt ﬂag bit, SSPIF (PIR1<3>) is set

(interrupt is generated if enabled) - on the falling

edge of the ninth SCL pulse. In 10-bit address mode, two address bytes need to be

received by the slav e (Figure 11-16). The ﬁve Most Signiﬁcant bits (MSbs) of the ﬁrst address byte specify if this is a 10-bit address. Bit R/W

(SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address the ﬁrst byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave-transmitter:

1. Receive ﬁrst (high) byte of Address (bits SSPIF,

BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low)

byte of Address (clears bit UA and releases the SCL line).

3. Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

4. Receive second (low) byte of Address (bits

SSPIF, BF, and UA are set).

5. Update the SSPADD register with the ﬁrst (high)

byte of Address, if match releases SCL line, this will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

7. Receive repeated START condition.

8. Receive ﬁrst (high) byte of Address (bits SSPIF

and BF are set).

9. Read the SSPBUF register (clears bit BF) and

clear ﬂag bit SSPIF.

TABLE 11-4: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

SSPSR

→ SSPBUF

Generate A

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

00 Yes Yes Yes 10 No No Yes 11 No No Yes 0 1 No No Yes

Applicable Devices

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PIC16C7X

11.5.1.2 RECEPTION When the R/W

bit of the address byte is clear and an

address match occurs, the R/W

bit of the SSPST AT register is cleared. The received address is loaded into the SSPBUF register.

When the address byte overﬂow condition exists, then no acknowledge (A

CK) pulse is given. An ov erﬂo w condition is deﬁned as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set.

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) m ust be cleared in software. The SSPSTAT register is used to deter mine the status of the byte.

FIGURE 11-25: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4

A3 A2 A1SDA

SCL

1234

123

Bus Master terminates

transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

Receiving Data

D3D4

D6D7

R/W=0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK is not sent.

Applicable Devices

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PIC16C7X

DS30390E-page 96  1997 Microchip Technology Inc.

11.5.1.3 TRANSMISSION When the R/W

bit of the incoming address byte is set

and an address match occurs, the R/W

bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The A

CK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SD A signal is valid during the SCL high time (Figure 11-26).

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse.

As a slave-transmitter, the A

CK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not A

CK),

then the data transfer is complete. When the A

CK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the START bit. If the SDA line was low (A

CK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 11-26: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>) BF (SSPSTAT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

CKTransmitting DataR/W = 1Receiving Address

123456789 123456789

cleared in software

SSPBUF is written in software

From SSP interrupt service routine

Set bit after writing to SSPBUF

Data in sampled

SCL held low while CPU

responds to SSPIF

(the SSPBUF must be written-to before the CKP bit can be set)

Applicable Devices

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 1997 Microchip Technology Inc. DS30390E-page 97

PIC16C7X

11.5.2 MASTER MODE Master mode of operation is supported in firmware

using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and ST ART (S) bits will toggle based on the START and STOP conditions. Control of the I

C bus may be taken when the P bit is set, or the bus is idle and both the S and P bits are clear.

In master mode the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a '1' data bit must have the TRISC<4> bit set (input) and a '0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit.

The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received Master mode of operation can be done with either the

slave mode idle (SSPM3:SSPM0 = 1011) or with the slave active. When both master and slave modes are enabled, the software needs to differentiate the source(s) of the interrupt.

11.5.3 MULTI-MASTER MODE In multi-master mode, the interrupt generation on the

detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a reset or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I

C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.

In multi-master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low lev el is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are:

• Address T r ansfer

• Data T r ansfer When the slave logic is enabled, the slave continues to

receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed an A

CK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.

TABLE 11-5: REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all other resets

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch

PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch

PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

93h SSPADD Synchronous Serial Port (I2C mode) Address Register

0000 0000 0000 0000

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

0000 0000 0000 0000

94h SSPSTAT SMP

(2)

CKE

(2)

D/A P S R/W UA BF

0000 0000 0000 0000

87h TRISC

PORTC Data Direction register

1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Shaded cells are not used by SSP module in SPI mode.

Note 1: PSPIF and PSPIE are reserved on the PIC16C73/73A/76, always maintain these bits clear.

2: The SMP and CKE bits are implemented on the PIC16C76/77 only. All other PIC16C7X devices have these two bits unim-

plemented, read as '0'.

Applicable Devices

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PIC16C7X

DS30390E-page 98  1997 Microchip Technology Inc.

FIGURE 11-27: OPERATION OF THE I2C MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE

IDLE_MODE (7-bit): if (Addr_match) { Set interrupt;

if (R/W

= 1) { Send ACK = 0;

set XMIT_MODE; }

else if (R/W

= 0) set RCV_MODE;

}

RCV_MODE:

if ((SSPBUF=Full) OR (SSPOV = 1))

{ Set SSPOV;

Do not acknowledge;

}

else { transfer SSPSR → SSPBUF;

send A

CK = 0;

} Receive 8-bits in SSPSR; Set interrupt;

XMIT_MODE:

While ((SSPBUF = Empty) AND (CKP=0)) Hold SCL Low; Send byte; Set interrupt; if ( A

CK Received = 1) { End of transmission;

Go back to IDLE_MODE;

}

else if ( A

CK Received = 0) Go back to XMIT_MODE;

IDLE_MODE (10-Bit):

If (High_byte_addr_match AND (R/W

= 0))

{ PRIOR_ADDR_MATCH = FALSE;

Set interrupt; if ((SSPBUF = Full) OR ((SSPOV = 1))

{ Set SSPOV;

Do not acknowledge;

}

else { Set UA = 1;

Send A

CK = 0; While (SSPADD not updated) Hold SCL low; Clear UA = 0; Receive Low_addr_byte; Set interrupt; Set UA = 1; If (Low_byte_addr_match)

{ PRIOR_ADDR_MATCH = TRUE;

Send A

CK = 0; while (SSPADD not updated) Hold SCL low; Clear UA = 0;

Set RCV_MODE;

}

else if (High_byte_addr_match AND (R/W

= 1)

{ if (PRIOR_ADDR_MATCH)

{ send A

CK = 0;

set XMIT_MODE;

} else PRIOR_ADDR_MATCH = FALSE; }

Applicable Devices

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 1997 Microchip Technology Inc. DS30390E-page 99

PIC16C7X

12.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be conﬁgured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be conﬁgured

Applicable Devices

72 73 73A 74 74A 76 77

as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc.

The USART can be conﬁgured in the following modes:

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to

be set in order to conﬁgure pins RC6/TX/CK and RC7/ RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.

FIGURE 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC

— BRGH TRMT TX9D R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: CSRC: Clock Source Select bit

Asynchronous mode Don’t care

Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source)

bit 6: TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission 0 = Selects 8-bit transmission

bit 5: TXEN: Transmit Enable bit

1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode.

bit 4: SYNC: USART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode bit 3: Unimplemented: Read as '0' bit 2: BRGH: High Baud Rate Select bit

Asynchronous mode

1 = High speed

Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may expe-

rience a high rate of receive errors. It is recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77.

0 = Low speed

Synchronous mode

Unused in this mode bit 1: TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit.

PIC16C7X

DS30390E-page 100  1997 Microchip Technology Inc.

FIGURE 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN

— FERR OERR RX9D R = Readable bit

W =Writable bit U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7: SPEN: Serial Port Enable bit

1 = Serial port enabled (Conﬁgures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled

bit 6: RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception 0 = Selects 8-bit reception

bit 5: SREN: Single Receive Enable bit

Asynchronous mode Don’t care

Synchronous mode - master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete.

Synchronous mode - sla

Unused in this mode

bit 4: CREN: Continuous Receive Enable bit

Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive

Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive bit 3: Unimplemented: Read as '0' bit 2: FERR: Framing Error bit

1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)

0 = No framing error bit 1: OERR: Overrun Error bit

1 = Overrun error (Can be cleared by clearing bit CREN)

0 = No overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit)

Microchip Technology Inc PIC16C73-JW, PIC16C73A-04ISO, PIC16C72-JW, PIC16C72A-04-SO, PIC16C72A-04-SP Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual