The MX23C8000 is a 5V only, 8M-bit, Read Only
Memory. It is organized as 1M words by 8 bits, operates from a single +5V supply , has a static standby mode,
and has an access time of 100/120/150/200ns. It is
designed to be compatible with all microprocessors and
similar applications in which high performance, large bit
storage and simple interfacing are important design considerations.
PIN CONFIGURATION
32 PDIP
A19
A16
A15
A12
VSS
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX23C8000
VCC
32
A18
31
A17
30
A14
29
A13
28
A8
27
A9
26
A11
25
OE/OE
24
A10
23
CE/CE
22
Q7
21
Q6
20
Q5
19
Q4
18
Q3
17
• Operating current : 40mA
• Standby current : 100uA
• Package
- 32 pin plastic DIP
- 32 pin plastic SOP
- 32 pin plastic PLCC
- 32 pin plastic TSOP
MX23C8000 offers automatic pow er-down, with powerdown controlled by the chip enable (CE) input. When
CE goes high, the device automatically powers down
and remains in a low-power standby modes as long as
CE remains high.
MX23C8000 pin 24 may also be programmed either active HIGH or LOW in order to eliminate bus contention
in multiple-bus microprocessor systems.
Ambient Operating Temperature0°C to 70°C
Storage T emperature-65°C to 125°C
Applied Input Voltage-0.5V to VCC+0.5
Applied Output Voltage-0.5V to VCC+0.5
VCC to Ground Potential-0.5V to 7.0V
Power Dissipation1.0W
BLOCK DIAGRAM
CE/CE
OE/OE
A0~A19
ADDRESS
INPUTS
VCC
VSS
*Note:
Stress greater than those listed under ABSOLUTE MAXIMUM
RA TINGS ma y cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
period may affect reliability.
Cycle TimetCYC100ns -120ns-150ns-200ns Address Access TimetAA-100ns-120ns-150ns-200ns
Output Hold Time AftertOH0ns-0ns-0ns-0nsAddress Change
Chip Enable Access TimetACE-100ns-120ns-150ns-200ns
Output Enable/Chip SelecttAOE-80ns-80ns-80ns-100ns
Access Time
Output Low Z DelaytLZ0ns-0ns-0ns-0ns-Note 3
Output High Z DelaytHZ20ns-20ns-20ns-20nsNote 4
Note:
1. Measured with device selected at f=5MHz and output unloaded.
2. This parameter is periodically sampled and is not 100% teseted.
3. Output low-impedance delay (tLA) is measured from CE going low.
4. Output high-impedance delay (tHZ) is measured from CE going high.
AC T est Conditions
Input Pulse Levels0.4V~2.4V
Input Rise and Fall Times10ns
Input Timing Level1.5V
Output Timing Le v el0.8V and 2.0V
Output LoadSee Figure
TIMING DIAGRAM
PROPAGA TION DELAY FROM ADDRESS (CE/OE=ACTIVE)
tCYC
ADDRESS
INPUTS
tAA
DATA OUT
VALID ADDRESS
tOH
VALID DATA
P/N:PM0137
REV. 3.8, JUL. 16, 2001
3
PROPAGA TION DELAY FROM CHIP ENABLE (ADDRESS VALID)
MX23C8000
CE
OE
DATA OUT
tACE
tAOE
tHZ
tLZ
ORDER INFORMATION
Part No.Access TimeOperating Current MAX.STANDBY CURRENT MAX.Package