The LT®1055/LT1056 JFET input operational amplifiers
combine precision specifications with high speed performance.
For the first time, 16V/µs slew rate and 6.5MHz gain
bandwidth product are simultaneously achieved with offset voltage of typically 50µV, 1.2µV/°C drift, bias currents
of 40pA at 70°C and 500pA at 125°C.
The 150µV maximum offset voltage specification is the
best available on any JFET input operational amplifier.
The LT1055 and LT1056 are differentiated by their operating currents. The lower power dissipation LT1055 achieves
lower bias and offset currents and offset voltage. The
additional power dissipation of the LT1056 permits higher
slew rate, bandwidth and faster settling time with a slight
sacrifice in DC performance.
The voltage-to-frequency converter shown below is one of
the many applications which utilize both the precision and
high speed of the LT1055/LT1056.
TYPICAL APPLICATIO
1Hz to 10kHz Voltage-to-Frequency Converter
4.7k
15V
10kHZ
TRIM
75k
0V TO 10V
INPUT
*1% FILM
5k
= 1N4148
2N3906
–15V
0.1µF
22k
3.3M
0.1µF
THE LOW OFFSET VOLTAGE OF LT1056
CONTRIBUTES ONLY 0.1Hz OF ERROR
WHILE ITS HIGH SLEW RATE PERMITS
10kHz OPERATION.
U
3M
0.001 (POLYSTYRENE)
33pF
–
+
15V
7
LT1056
4
–15V
2
3
For a JFET input op amp with 23V/µs guaranteed slew rate,
refer to the LT1022 data sheet.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Distribution of Input Offset Voltage
(H Package)
140
VS = ±15V
= 25°C
T
A
120
634 UNITS TESTED
FROM THREE RUNS
OUTPUT
1Hz TO 10kHz
LM329
0.005%
LINEARITY
LT1055/56 TA01
1.5k
6
100
80
60
NUMBER OF UNITS
40
20
0
–400
INPUT OFFSET VOLTAGE (µV)
–200
0
50% TO ±60µV
200
400
LT1055/56 TA02
10556fc
1
LT1055/LT1056
WW
W
ABSOLUTE MAXIMUM RATINGS
U
(Note 1)
Supply Voltage ...................................................... ±20V
Differential Input Voltage ....................................... ±40V
Input Voltage ......................................................... ±20V
PSRRPower Supply Rejection RatioVS = ±10V to ±18V●87103dB
V
For MIL-STD components, please refer to LTC883 data sheet for test
listing and parameters.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Offset voltage is measured under two different conditions:
(a) approximately 0.5 seconds after application of power; (b) at T
only, with the chip heated to approximately 38°C for the LT1055 and to
45°C for the LT1056, to account for chip temperature rise when the device
is fully warmed up.
Average Temperature Coefficient of Input Offset Voltage●415µV/°C
Input Offset CurrentWarmed Up, TA = 70°C●18150pA
Input Bias CurrentWarmed Up, TA = 70°C●± 60±400pA
Large-Signal Voltage GainVO = ±10V, RL = 2k●60250V/mV
Output Voltage SwingRL = 2K●±12± 13.1V
The ● denotes the specifications which apply over the temperature range
LT1055CS8/LT1056CS8
Note 3: 10Hz noise voltage density is sample tested on every lot of A
grades. Devices 100% tested at 10Hz are available on request.
= 25°C
A
Note 4: This parameter is tested on a sample basis only.
Note 5: Current noise is calculated from the formula: i
q = 1.6 • 10
the contribution of current noise.
Note 6: Offset voltage drift with temperature is practically unchanged
when the offset voltage is trimmed to zero with a 100k potentiometer
between the balance terminals and the wiper tied to V
tighter drift specifications are available on request.
–19
coulomb. The noise of source resistors up to 1GΩ swamps
n
+
1/2
= (2qlB)
. Devices tested to
, where
10556fc
5
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