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Product Specification
1. General Description
The LC420WUN is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent
Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 42.02 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion (true) colors.
It has been designed to apply the 10-bit 2-port LVDS interface.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.
LC420WUN
Mini-LVDS(RGB)
Control
Signals
Power Signals
3PinX1CN(High)
3PinX1CN(High)
Source Driver Circuit
S1S1920
G1
TFT - LCD Panel
(1920 Ý RGB Ý 1080 pixels)
G1080
OPC Enable
ExtVBR-B
VBR-B out
LVDS
2Port
LVDS
Select
Bit
Select
+12.0V
CN1
(51pin)
+24.0V, GND
LVDS 1,2
Option
signal
I2C
EXTVBR-B
Status
EEPROM
SCL
Timing Controller
LVDS Rx + OPC + DGA + ODC
Power Circuit
SDA
Integrated
Block
Inverter
General Features
Active Screen Size42.02 inches(1067.31mm) diagonal
Outline Dimension983.0(H) x 576.0 (V) x 51.0 mm(D) (Typ.)
Pixel Pitch0.4845 mm x 0.4845 mm
Pixel Format1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Power ConsumptionTotal 156.8W (TYP.) (Logic=7.8W, Inverter=149W )
Weight9.1 Kg (Typ)
Display ModeTransmissive mode, Normally black
Surface TreatmentHard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)
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2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
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LC420WUN
Product Specification
ParameterSymbol
Power Input Voltage
Inverter Control Voltage
T-Con Option Selection VoltageVLOGIC-0.3+4.0VDC
Operating TemperatureTOP0+50¶C
Storage TemperatureTST-20+60¶C
Panel Front Temperature TSUR-+68¶C4
Operating Ambient HumidityHOP1090%RH
Storage HumidityHST1090%RH
Note
1. Ambient temperature condition (Ta =
LCD CircuitVLCD-0.3+14.0VDC
InverterVBL-0.3+ 27.0VDC
ON/OFFVOFF / VON-0.3+5.5VDC
BrightnessVBR0.0+5.0VDC
25 r 2 ¶C )
Value
UnitNote
MinMax
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39¶C, and no condensation of water.
3. Gravity mura can be guaranteed below 40¶C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68¶C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68. The range of operating temperature may degraded in case of
improper thermal management in final product design.
90%
1
2,3
2,3
60
60%
Ver. 1.0
Wet Bulb
Temperature [
10
0
10203040506070800-20
Dry Bulb Temperature [
¶C]
20
30
40
50
40%
Humidity [(%)RH]
10%
¶C]
Storage
Operation
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3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the EEFL
backlight and inverter circuit.
Table 2. ELECTRICAL CHARACTERISTICS
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LC420WUN
Product Specification
ParameterSymbol
MinTypMax
Circuit :
Power Input VoltageVLCD10.812.013.2VDC
Power Input Current (TBD)ILCD
Power ConsumptionPLCD7.89.2Watt1
Rush currentIRUSH--5.0A3
Note
1. The specified current and power consumption are under the V
455650845mA1
6689551240mA2
condition whereas mosaic pattern(8 x 6) is displayed and f
Value
=12.0V, Ta=25 r 2¶C, fV=60Hz
LCD
is the frame frequency.
V
UnitNote
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
White : 1023 Gray
Black : 0 Gray
Mosaic Pattern(8 x 6)
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Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
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LC420WUN
ParameterSymbol
Inverter :
Power Supply Input VoltageV
Power Supply
Input Current
Power Supply Input Current (In-Rush)IRUSH--11A
Power Consumption (TBD)P
Input Voltage for
Control System
Signals
Lamp:
After AgingI
Before AgingI
On/Off
Brightness AdjustEXTVBR-B30-100%
PWM Frequency for
NTSC & PAL
Pulse Duty
Level (PWM)
(Burst mode)
OnV
OffV
BL22.824.025.2VDC1
BL_A-6.2
BL_B-6.7
BL-
ON2.5-5.0VDC
OFF-0.30.00.8VDC
PAL100Hz5
NTSC120Hz5
High Level2.5-5.0V
Low Level0.0-0.8V
MinTypMax
Values
149164
6.8
7.3
UnitNote
A1
A2
V
EXTV
W1
DC
High: Lamp on
Low : Lamp off
DC
BL = 22.8V
BR-B = 100%
6
On Duty
7
Discharge Stabilization TimeTs
Life Time50,00060,000Hrs4
Note
1. Electrical characteristics are determined after the unit has been ‘ON’ and stable for approximately 120
3min3
minutes at 25·2¶C. The specified current and power consumption are under the typical supply Input voltage
24Vand V
BR (EXTVBR-B : 100%), it is total power consumption.
2. Electrical characteristics are determined within 30 minutes at 25·2¶C.
The specified currents are under the typical supply Input voltage 24V.
3. The brightness of the lamp after lighted for 5minutes is defined as 100%.
TS is the time required for the brightness of the center of the lamp to be not less than 95% at typical current.
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
4. Specified Values are for a single lamp which is aligned horizontally.
The life time is determined as the time which luminance of the lamp is 50% compared to that of initial value
at the typical lamp current (
EXTVBR-B :100%), on condition of continuous operating at 25· 2¶C
5. LGD recommend that the PWM freq. is synchronized with Two times harmonic of Vsync signal of system.
6. The duration of rush current is about 10ms.
EXTVBR-B is based on input PWM duty of the inverter.
7.
Ver. 1.0
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3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector is used for the module
electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector : FI-R51S-HF(manufactured by JAE) or KN25-51P-0.5SH(manufactured by Hirose)
(CN1) Refer to below table
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
NoSymbolDescriptionNoSymbolDescription
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NCNo Connection
NCNo Connection
NCNo Connection
NCNo Connection (Reserved for LGD)
NCNo Connection (Reserved for LGD)
NCNo Connection (Reserved for LGD)
LVDS Select
BR-BExternal VBR (From System)
EXTV
VBR-B outOPC output (From LCM)
OPC Enable‘H’ = Enable , ‘L’ or NC = Disable
GND
R1AN
R1AP
R1BN
R1BP
R1CN
R1CP
GND
R1CLKN
R1CLKP
GND
R1DN
R1DP
R1EN
R1EP
NC
‘H’ =JEIDA , ‘L’ or NC = VESA
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-)
FIRST LVDS Receiver Signal (E+)
No Connection
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Product Specification
27
Bit Select
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
R2CLKN
R2CLKP
---
‘H’ or NC= 10bit(D) , ‘L’ = 8bit
R2AN
R2AP
R2BN
R2BP
R2CN
R2CP
GND
GND
R2DN
R2DP
R2EN
R2EP
NC
NC
GNDGround
GNDGround
GNDGround
NCNo connection
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
VLCDPower Supply +12.0V
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)
No Connection
No Connection
LC420WUN
Note
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All V
LCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. Specific pins(pin No. #2~#6) are used for internal data process of the LCD module.
These pins should be no connection.
5. Specific pins(pin No. # 8~#10) are used for OPC function of the LCD module.
If not used, these pins are no connection. (Please see the Appendix III-4 for more information.)
6. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
7. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
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• •
• •
3-2-2. Backlight Module
[ Master ]
-Inverter Connector : 20022WR-14B1(Yeonho)
or Equivalent
- Mating Connector : 20022HS-14 or Equivalent
Table 5. INVERTER CONNECTOR PIN CONFIGULATION
Pin NoSymbolDescriptionMasterNote
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LC420WUN
Product Specification
Note
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VBLPower Supply +24.0VVBL
VBLPower Supply +24.0VVBL
VBLPower Supply +24.0VVBL
VBLPower Supply +24.0VVBL
VBLPower Supply +24.0VVBL
GNDBacklight GroundGND
GNDBacklight GroundGND
GNDBacklight GroundGND
GNDBacklight GroundGND
GNDBacklight GroundGND
NC
ON/OFF
V
EXTVBR-B
Status
No Connection
Backlight ON/OFF control
External PWM
Lamp Status
EXTV
NC
ON/OFF
V
BR-B3
Status2
1. GND should be connected to the LCD module’s metal frame.
2. Normal : Low (under 0.7V) / Abnormal : High (upper 3.0V)
Please see Appendix IV-1 for more information.
3. The impedance of pin #12 is over 50[K˟] & the impedance of Pin #13 is over 100[K˟].
1
3
Rear view of LCM
Rear view of LCM
14
…
PCB
…
PCB
1
…
…
1
<Master>
Ver. 1.0
12
<Slave>
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3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6-1. TIMING TABLE for NTSC (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
Display PeriodtHV-960-tclk
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LC420WUN
Product Specification
Blankt
Totalt
Display Periodt
HB100140240tclkHorizontal
HP106011001200tclk2200/2
VV-1080-tHP
BlanktVB114569tHPVertical
Frequency
Totalt
DCLKf
Horizontalf
Verticalf
VP109111251149tHP
CLK7074.2577MHz148.5/2
H6567.570KHz
V576063Hz
Table 6-2. TIMING TABLE for PAL (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
HV-960-tclk
HB100140240tclk
HP106011001200tclk2200/2
Horizontal
Display Periodt
Blankt
Totalt
VV-1080-tHP
Vertical
Display Periodt
BlanktVB228270300tHP
TotaltVP130813501380tHP
CLK7074.2577MHz148.5/2
H6567.570KHz
V475053Hz
Frequency
Note
DCLKf
Horizontalf
Verticalf
The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate.
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3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
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LC420WUN
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
DE(Data Enable)
0.5 VDD
Invalid data
Invalid data
Valid data
Pixel 0,0
Valid data
Pixel 1,0
tHP
Pixel 2,0
Pixel 3,0
Invalid data
Invalid data
tHV
DE(Data Enable)
Ver. 1.0
11080
tVV
tVP
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3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LVDS +
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LC420WUN
Product Specification
# VCM= {(LVDS +) + ( LVDS - )}/ 2
0V
V
CM
V
IN _MAXVIN _MIN
DescriptionSymbolMinMaxUnitNote
LVDS Common mode VoltageV
LVDS Input Voltage RangeV
CM
IN
1.01.5V-
0.71.8V-
Change in common mode VoltageȟVCM250mV-
2) AC Specification
T
clk
LVDS Clock
A
LVDS Data
(F
= 1/T
)
clk
A
LVDS 1’st Clock
LVDS 2nd/ 3rd/ 4thClock
tSKEW
tSKEW
t
SKEW_mintSKEW_max
clk
T
clk
80%
20%
t
RF
DescriptionSymbolMinMaxUnitNote
LVDS Differential Voltage
High Threshold
Low Threshold
LVDS Clock to Data Skew Margint
LVDS Clock/DATA Rising/Falling timet
Effective time of LVDSt
LVDS Clock to Clock Skew Margin (Even to Odd) t
1. All Input levels of LVDS signals are based on the EIA 644 Standard.
Note
2. If t
isn’t enough, t
RF
should be meet the range.
eff
V
TH
V
TL
SKEW
RF
eff
SKEW_EO
3. LVDS Differential Voltage is defined within t
Ver. 1.0
100300mV
-300-100mV
|(0.25*T
260(0.3*T
)/7|ps-
clk
)/7ps2
clk
·360ps-
1/7* T
clk
eff
T
clk
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LC420WUN
Product Specification
360ps
V+
data
Vcm
Vdata
V+
clk
Vcm
0.5tui
tui
VTH
VTL
360ps
teff
tui : Unit Interval
Vclk
Ver. 1.0
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