LG Display LC420WUH-SCM1 Specification

LC420WUH

Product Specification

SPECIFICATION

FOR

APPROVAL

)

(

(

Preliminary Specification

)

Final Specification

●

Title 42.0” WUXGA TFT LCD

BUYER General

MODEL

APPROVED BY

/

/

/

SIGNATURE

DATE

SUPPLIER LG Display Co., Ltd.

*MODEL LC420WUH

SUFFIX SCM1

*When you obtain standard approval,

please use the above model name without suffix

APPROVED BY

P. Y KIM / Team Leader

REVIEWED BY

S. J LEE / Project Leader

PREPARED BY

S. M Lee / Engineer

SIGNATURE

DATE

Please return 1 copy for your confirmation with

your signature and comments.

Ver.1.2

TV Products Development Dept.

LG Display LCD Co., Ltd

1 /41

Product Specification

CONTENTS

LC420WUH

Number ITEM

COVER 1

CONTENTS

RECORD OF REVISIONS

1 GENERAL DESCRIPTION

2 ABSOLUTE MAXIMUM RATINGS

3 ELECTRICAL SPECIFICATIONS

3-1 ELECTRICAL CHARACTERISTICS

3-2 INTERFACE CONNECTIONS

3-3 SIGNAL TIMING SPECIFICATIONS

3-4 DATA MAPPING AND TIMING

3-5 PANEL PIXEL STRUCTURE

3-6 POWER SEQUENCE

4 OPTICAL SPECIFICATIONS

5 MECHANICAL CHARACTERISTICS

Page

2

3

4

5

6

6

12

15

18

19

20

21

25

6 RELIABILITY

7 INTERNATIONAL STANDARDS

7-1 SAFETY

7-2 ENVIRONMENT

8 PACKING

8-1 INFORMATION OF LCM LABEL

8-2 PACKING FORM

9 PRECAUTIONS

9-1 MOUNTING PRECAUTIONS

9-2 OPERATING PRECAUTIONS

9-3 ELECTROSTATIC DISCHARGE CONTROL

9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE

9-5 STORAGE

9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM

Ver.1.2

28

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2 /41

Product Specification

RECORD OF REVISIONS

Revision No. Revision Date Page Description

1.2 Mar. 16..2010 - Final Specification

LC420WUH

Ver.1.2

3 /41

LC420WUH

Product Specification

1. General Description

The LC420WUH is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent
Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive type display operating in the normally black mode. It has a 42.02 inch diagonally measured
act i ve d is p la y are a w i th W U X GA r e s ol u t ion ( 1 0 8 0 vertica l by 1920 horizonta l pixel a r ray) .
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 8-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 16.7M(true) colors.
It is intended to support LCD TV, PCTV where high brightness, super wide viewing angle, high color gamut,
high color depth and fast response time are important.

Power (VCC,VDD,HVDD,VGH,VGL)

Source Control Signal

Gate Control Signal

Gamma Reference Voltage

mini-LVDS (RGB) for Left drive

CN1

(60pin)

S1 S1920

G1

Source Driver Circuit

Power (VCC,VDD,HVDD,VGH,VGL)

Source Control Signal

Gate Control Signal

Gamma Reference Voltage

mini-LVDS (RGB) for Right drive

High Input

High Input

CN4&5, 3pin*2ea, 8 Lamps/@ 68 mA

CN6&7, 3pin*2ea, 8 Lamps/@ 68 mA

CN2

(60pin)

G1080

TFT - LCD Panel

(1920 × RGB × 1080 pixels)

[Gate In Panel]

Scanning Block 2

Scanning Block 1

Scanning Block 2

General Features

Active Screen Size 42.02 inches(1067.31mm) diagonal

Outline Dimension 983.0(H) x 576.0 (V) x 35.5 mm(D) (Typ.)

Pixel Pitch 0.4845 mm x 0.4845 mm

Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement

Color Depth 8-bit, 16.7 M colors (※ 1.06B colors @ 10 bit (D) System Output )

Drive IC Data Interface

Luminance, White 500 cd/m2 (Center 1point ,Typ.)

Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))

Power Consumption

Weight 8.7Kg (Typ.)

Display Mode Transmissive mode, Normally black

Surface Treatment Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)

Source D-IC : 8-bit mini-LVDS, gamma reference voltage, and control signals
Gate D-IC : Gate In Panel

Total 158.0 W (Typ.)
(Logic=9.0 W with T-CON, Backlight=149W @ with Inverter Iout duty : 100%)

Ver.1.2

4 /41

LC420WUH

Product Specification

2. Absolute Maximum Ratings

The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.

Table 1. ABSOLUTE MAXIMUM RATINGS

Parameter Symbol

Logic Power Voltage VCC -0.5 +4.0 VDC

Gate High Voltage VGH +18.0 +30.0 VDC

Gate Low Voltage VGL -8.0 -4.0 VDC

Source D-IC Analog Voltage VDD -0.3 +18.0 VDC

Gamma Ref. Voltage (Upper) VGMH ½VDD-0.5 VDD+0.5 VDC

Gamma Ref. Voltage (Low) VGML -0.3 ½ VDD+0.5 VDC

BL Operating Input Voltage

(One Side)

Panel Front Temperature TSUR - +68 °C 4

Operating Temperature TOP 0 +50 °C

Storage Temperature TST -20 +60 °C

Operating Ambient Humidity HOP 10 90 %RH

Storage Humidity HST 10 90 %RH

VBL 600 1150 VRMS

Min Max

Value

Unit Note

1

2,3

Note:

1. Ambient temperature condition (Ta = 25 ± 2 °C )

2. Temperature and relative humidity range are shown in the figure below. Wet bulb temperature

should be Max 39 °C and no condensation of water.

3. Gravity mura can be guaranteed below 40℃ condition.

4. The maximum operating temperature is based on the test condition that the surface temperature

of display area is less than or equal to 68 ℃ with LCD module alone in a temperature controlled
chamber. Thermal management should be considered in final product design to prevent the surface

temperature of display area from being over 68 ℃. The range of operating temperature may

degrade in case of improper thermal management in final product design.

90%

60

60%

Ver.1.2

Wet Bulb
Temperature [°C]

20

10

0

10 20 30 40 50 60 70 800-20
Dry Bulb Temperature [°C]

30

40

50

40%

10%

Humidity

[(%)RH]

Storage

Operation

5 /41

LC420WUH

Product Specification

3. Electrical Specifications

3-1. Electrical Characteristics

It requires several power inputs. The VCC is the basic power of LCD Driving power sequence, Which is used
to logic power voltage of Source D-IC and GIP.

Table 2. ELECTRICAL CHARACTERISTICS

Parameter Symbol Condition MIN TYP MAX Unit Note

Logic Power Voltage VCC - 3.0 3.3 3.6
Logic High Level Input Voltage VIH 2.7 VCC
Logic Low Level Input Voltage VIL 0 0.6

Source D-IC Analog Voltage VDD - 16.05 16.25 16.45

VDC
VDC
VDC

VDC

Half Source D-IC Analog
Voltage

Gamma Reference Voltage

Common Voltage Vcom - 6.6 6.9 7.2 V

Mini-LVDS Clock frequency CLK 3.0V≤VCC ≤3.6V 312 MHz
mini-LVDS input Voltage

(Center)
mini-LVDS input Voltage

Distortion (Center)
mini-LVDS differential

Voltage range
mini-LVDS differential

Voltage range Dip

Gate High Voltage VGH

Gate Low Voltage VGL -5.5 -5.3 -5.1 VDC

GIP Bi-Scan Voltage

GIP Refresh Voltage

GIP Start Pulse Voltage VST - VGL - VGH V
GIP Operating Clock GCLK - VGL - VGH V
Total Power Current
Total Power Consumption

Note:

1. The specified current and power consumption are under the VLCD=12V., 25 ± 2°C, fV=120Hz

H_VDD - 7.9 8.00 8.1

V

GMH

V

GML

VIB

ΔVIB 0.8 V

VID 150 800 mV

ΔVID 25 800 mV

VGI_P
VGI_N

VGH

even/odd

ILCD - 525 750 975 mA 2

PLCD - 9.0 Watt 2

(GMA1 ~ GMA9) ½*VDD VDD-0.2

(GMA10 ~ GMA18) 0.2 ½*VDD

(VCC-1.2)

− VID / 2

27.99 @ 25℃

29.45 @ 0℃

Mini-LVDS Clock

and Data

- VGL - VGH VDC

- VGL - VGH V

0.7 + (VID/2)

27.39 @ 25℃

28.85 @ 0℃

27.69 @ 25℃

29.15 @ 0℃

VDC

V

VDC

condition whereas mosaic pattern(8 x 6) is displayed and fVis the frame frequency.

2. The above spec is based on the basic model.

3. All of the typical gate voltage should be controlled within 1% voltage level

4. Ripple voltage level is recommended under 10%

5. In case of mini-LVDS signal spec, refer to Fig 2 for the more detail.

6. Logic level Input Signal : SOE, POL, GSP, H_CONV, OPT_N

7. HVDD Voltage level is half of VDD and it should be between Gamma9 and Gamma10

5

Ver.1.2

6 /41

VCM (0V)

VCM (0V)

VCM (0V) VCM (0V)

VGH

VGHM

GND

VGL

VID

VID

VIDVID

Product Specification

Without GPM With GPM

FIG. 1 Gate Output Wave form without GPM and with GPM

△△△△VID

VID

VID VID

LC420WUH

△△△△VIB

VIB

VIB VIB

VIB

VIB

VIB VIB

VID

VID

VIDVID

* Differential Probe

* Differential Probe

* Differential Probe* Differential Probe

△△△△VID

VID

VID VID

* Active Probe

* Active Probe

* Active Probe* Active Probe

FIG. 2 Description of VID, ΔΔΔΔVIB, ΔΔΔΔVID

*

* Source PCB

Source PCB

* *

Source PCBSource PCB

FIG. 3 Measure point

Ver.1.2

7 /41

Product Specification

Table 3. ELECTRICAL CHARACTERISTICS (Continue)Table 3. ELECTRICAL CHARACTERISTICS (Continue)

Parameter Symbol

Min Typ Max

Backlight Assembly :

LC420WUH

Values

Unit Note

Operating Voltage

(one side,fBL=63KHz, IBL= 136 mA

RMS

VBL1 - 1000 -

)

VBL2 - 1000 -

V

RMS

IBL1 - 68 -

Operating Current (one side)

mA

RMS

IBL2 - 68 -

Striking Voltage @ 0℃

(Open Lamp Voltage @ one side)

VS - - 1110 V

RMS

Operating Frequency fBL 61 63 65 kHz 4

Striking Time S TIME 1.5 - - sec 3

Power Consumption PBL 149 Watt 6

Burst Dimming Duty {a/T} * 100 20 100 % 9

Burst Dimming Frequency

Parameter Symbol

PAL

NTSC 120

1/T

100

Values

Hz 9

Unit Note

Min Typ Max

Lamp : (APPENDIX-V)

Lamp Voltage (one side) VLAMP 815 1100 1135 V

Lamp Current (one side) ILAMP 3.0 8.5 9.0 mA

RMS

RMS

Discharge Stabilization Time TS - - 3 Min 5

Lamp Frequency f LAMP 661 63 65 KHz

Established Starting Voltage @ 0℃ VS 1110 V

RMS

Life Time 50,000 60,000 Hrs 7

1, 2

1

1, 3

2

3

Ver.1.2

8 /41

LC420WUH

Product Specification

Note : The design of the inverter must have specifications for the lamp in LCD Assembly.

The electrical characteristics of inverter are based on High-High Driving type.

The performance of the lamps in LCM, for example life time or brightness, is extremely influenced by

the characteristics of the DC-AC inverter. So, all the parameters of an inverter should be carefully

designed so as not to produce too much leakage current from high-voltage output of the inverter.

When you design or order the inverter, please make sure unwanted lighting caused by the mismatch

of the lamp and the inverter (no lighting, flicker, etc) has never been occurred. When you confirm it,

the LCD– Assembly should be operated in the same condition as installed in your instrument.

※ Do not attach a conductive tape to lamp connecting wire.

If you attach conductive tape to the lamp wire, not only luminance level can be lower than typical one
but also inverter operate abnormally on account of leakage current which is generated between lamp wire
and conductive tape.

1. Specified values are defined for a Backlight Assembly.

( SCAN Block1 IBL:8 lamps, 8.5mA/Lamp and SCAN Block2 IBL:8 lamps, 8.5mA/Lamp )

and each value is measured at duty 100%.
The lamp voltage must be synchronized between Block1 and Block2.
(The frequency and phase must be the same)

2. Operating voltage is measured at 25 ± 2°C(after 2hr.aging). The variance range for operating voltage

is ± 10%.

3. The Striking Voltage (Open Lamp Voltage) [ Vopen ] should be applied to the lamps more than Striking
time (S TIME) for start-up. Inverter Striking Voltage must be more than Established Starting Voltage of lamp.

Otherwise, the lamps may not be turned on. The used lamp current is typical value.
When the Striking Frequency is higher than the Operating Frequency, the parasitic capacitance
can cause inverter shut down, therefore It is recommended to check it.

Ver.1.2

Vs = (Vpk-pk) / [ 2*root(2)]

9 /41

LC420WUH

Product Specification

4. Lamp frequency may produce interference with horizontal synchronous frequency. As a result this may
cause beat on the display. Therefore, lamp frequency shall be away as much as possible from the
horizontal synchronous frequency and its harmonics range in order to prevent interference.
There is no reliability problem of lamp, if the operation frequency is typ ± 5KHz. But it should be applied
in less than ABSOLUTE MAXIMUM RATINGS max voltage

5. The brightness of the lamp after lighted for 5minutes is defined as 100%.

TSis the time required for the brightness of the center of the lamp to be not less than 95% at typical current.

The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.

6. Maximum level of power consumption is measured at initial turn on.
Typical level of power consumption is measured after 2hrs aging at 25 ± 2°C.(@I out duty : 100%)

7. The life time is determined as the time at which brightness of the lamp is 50% compared to that of initial

value at the typical lamp current on condition of continuous operating at 25 ± 2°C, based on duty 100%.

8.The output of the inverter must have symmetrical(negative and positive) voltage and current waveform

(Unsymmetrical ratio is less than 10%). Please do not use the inverter which has not only unsymmetrical

voltage and current but also spike wave.
Requirements for a system inverter design, which is intended to achieve better display performance,

power efficiency and more reliable lamp characteristics.
It can help increase the lamp lifetime and reduce leakage current.

a. The asymmetry rate of the inverter waveform should be less than 10%.
b. The distortion rate of the waveform should be within √2 ±10%.

* Inverter output waveform had better be more similar to ideal sine wave.

I p

I -p

* Asymmetry rate:

| I p– I –p| / I

RMS

* Distortion rate

I p(or I –p) / I

RMS

x 100%

Ver.1.2

10 /41

Product Specification

9. The reference method of burst dimming duty ratio.

SCAN_Block1 or
SCAN_Block2

Output of Inverter to Lamp

LC420WUH

T

A

+3.3V TTL

I-out

90%

Point A

SCAN Block1 or SCAN Block2 PWM duty ={ A/T } * 100

Point A : rising time 90% of Iout point .
Point B : falling starting point .

I out duty = { a/T } * 100

SCAN Block1 or SCAN Block2 Frequency = 1/T

※ We recommend not to be much different between SCAN BLK 1 or SCAN BLK2 duty and Iout duty .
※ Dimming current output rising and falling time may produce humming and inverter trans’ sound noise.
※ Burst dimming duty should be 100% for more than 1second after turn on.
※ Equipment

Oscilloscope :TDS3054B(Tektronix)
Current Probe : P6022 AC (Tektronix)
High Voltage Probe: P5100(Tektronix)

10. The Cable between the backlight connector and its inverter power supply should be connected directly
with a minimized length. The longer cable between the backlight and the inverter may cause the lower
luminance of lamp and may require more higher starting voltage ( Vs ).

a

Point B

11. The operating current must be measured as near as backlight assembly input.

12. The operating current unbalance between left and right side for each scanning block must be under 10%
of Typical current.

│Left(Master) current – Right(Slave) Current│ 〈 10% of typical current

Ver.1.2

11 /41

LC420WUH

Product Specification

3-2. Interface Connections

This LCD module employs two kinds of interface connection, two 60-pin FFC connector are used for the
module electronics and two 3-pin Balance PCB connectors are used for the integral backlight system.

3-2-1. LCD Module

-LCD Connector (CN1): TF06L-60S-0.5SH (Manufactured by HRS) or Equivalent

Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION

Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION

DescriptionSymbolNoDescriptionSymbolNo

10
11
12
13
14
15
16
17
18
19
20

21
22
23
24
25
26
27
28
29
30

1

LTD OUTPUTLTD_OUT2
3

4
5
6
7
8
9

48GroundGND

49Driver Power Supply VoltageVDD

50Driver Power Supply VoltageVDD

51Half Driver Power Supply VoltageH_VDD

52Half Driver Power Supply VoltageH_VDD

53GroundGND

54Logic Power Supply VoltageVCC

55Logic Power Supply VoltageVCC

56GroundGND

57Left Mini LVDS Receiver Signal(5-) LLV5 -

58Left Mini LVDS Receiver Signal(5+) LLV5 +

59Left Mini LVDS Receiver Signal(4-) LLV4 -

Left Mini LVDS Receiver Signal(3-) LLV3 -31GroundGND

Left Mini LVDS Receiver Signal(3+) LLV3 +32

Left Mini LVDS Receiver Clock Signal(-) LCLK -33GIP GATE Clock 1GCLK1

Left Mini LVDS Receiver Clock Signal(+) LCLK +34GIP GATE Clock 2GCLK2

Left Mini LVDS Receiver Signal(2-) LLV2 -35GIP GATE Clock 3GCLK3

Left Mini LVDS Receiver Signal(2+) LLV2 +36GIP GATE Clock 4GCLK4

Left Mini LVDS Receiver Signal(1-) LLV1 -37GIP GATE Clock 5GCLK5

Left Mini LVDS Receiver Signal(1+) LLV1 +38GIP GATE Clock 6GCLK6

Left Mini LVDS Receiver Signal(0-) LLV0 -39VGLVGI_N

Left Mini LVDS Receiver Signal(0+) LLV0 +40VGHVGI_P

GroundGND41GIP Panel VDD for Odd GATE TFTVGH_ODD

Source Output Enable SIGNALSOE42GIP Panel VDD for Even GATE TFTVGH_EVEN

Polarity Control SignalPOL43GATE Low VoltageVGL

GATE Start PulseGSP44VERTICAL START PULSEVST

"H“ H 2dot Inversion/ "L" H 1dot InversionH_CONV45GroundGND

“H” Normal DisplayOPT_N46VCOM Left Feed-Back OutputVCOM_L_FB

GroundGND47VCOM Left InputVCOM_L

GAMMA VOLTAGE 18 (Output From LCD)GMA 18
GAMMA VOLTAGE 16GMA 16
GAMMA VOLTAGE 15GMA 15

GAMMA VOLTAGE 14GMA 14
GAMMA VOLTAGE 12GMA 12
GAMMA VOLTAGE 10 (Output From LCD)GMA 10
GAMMA VOLTAGE 9 (Output From LCD)GMA 9
GAMMA VOLTAGE 7GMA 7
GAMMA VOLTAGE 5GMA 5
GAMMA VOLTAGE 4GMA 4
GAMMA VOLTAGE 3GMA 3
GAMMA VOLTAGE 1(Output From LCD)GMA 1

No ConnectionNC60Left Mini LVDS Receiver Signal(4+) LLV4 +

Note :

1. Please refer to application note (Half VDD & Gamma Voltage setting & Control signal) for details.

2. These 'input signal' (OPT_N,H_CONV) should be connected

Ver.1.2

12 /41

Product Specification

-LCD Connector (CN2): TF06L-60S-0.5SH(Manufactured by HRS) or Equivalent

Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION

LC420WUH

DescriptionSymbolNoDescriptionSymbolNo

14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1

GAMMA VOLTAGE 1 (Output From LCD)GMA 12
GAMMA VOLTAGE 3GMA 33

GAMMA VOLTAGE 4GMA 44
GAMMA VOLTAGE 5GMA 55
GAMMA VOLTAGE 7GMA 76
GAMMA VOLTAGE 9 (Output From LCD)GMA 97
GAMMA VOLTAGE 10 (Output From LCD)GMA 108
GAMMA VOLTAGE 12GMA 129
GAMMA VOLTAGE 14GMA 1410
GAMMA VOLTAGE 15GMA 1511
GAMMA VOLTAGE 16GMA 1612
GAMMA VOLTAGE 18 (Output From LCD)GMA 1813

39

40

47GATE Start PulseGSP

49Source Output Enable SIGNALSOE

50GroundGND

53Right Mini LVDS Receiver Signal(4-) RLV4 -

54Right Mini LVDS Receiver Signal(4+) RLV4 +

55Right Mini LVDS Receiver Signal(3-) RLV3 -

56Right Mini LVDS Receiver Signal(3+) RLV3 +

57Right Mini LVDS Receiver Clock Signal(-) RCLK -

58Right Mini LVDS Receiver Clock Signal(+) RCLK +

59Right Mini LVDS Receiver Signal(2-) RLV2 -

Right Mini LVDS Receiver Signal(1-) RLV1 -31No ConnectionNC

Right Mini LVDS Receiver Signal(1+) RLV1 +32

Right Mini LVDS Receiver Signal(0-) RLV0 -33

Right Mini LVDS Receiver Signal(0+) RLV0 +34

GroundGND35

Logic Power Supply VoltageVCC36

Logic Power Supply VoltageVCC37

GroundGND38

Half Driver Power Supply VoltageH_VDD

Half Driver Power Supply VoltageH_VDD

Driver Power Supply VoltageVDD41

Driver Power Supply VoltageVDD42

GroundGND43

VCOM Right InputVCOM_R44GroundGND

VCOM Right Feed-Back OutputVCOM_R_FB45“H” Normal DisplayOPT_N

GroundGND46"H“ H 2dot Inversion/ "L" H 1dot InversionH_CONV

VERTICAL START PULSEVST

GATE Low VoltageVGL48Polarity Control SignalPOL

GIP Panel VDD for Even GATE TFTVGH_EVEN

GIP Panel VDD for Odd GATE TFTVGH_ODD

VGHVGI_P51Right Mini LVDS Receiver Signal(5-) RLV5 -

VGLVGI_N52Right Mini LVDS Receiver Signal(5+) RLV5 +

GIP GATE Clock 6GCLK6

GIP GATE Clock 5GCLK5

GIP GATE Clock 4GCLK4

GIP GATE Clock 3GCLK3

GIP GATE Clock 2GCLK2

GIP GATE Clock 1GCLK1

LTD OUTPUTLTD_OUT

GroundGND60Right Mini LVDS Receiver Signal(2+) RLV2 +

Note :

1.Please refer to application note (Half VDD & Gamma Voltage setting & Control signal) for details.

2. These 'input signal' (OPT_N,H_CONV) should be connected

Source Right PCB

Ver.1.2

CN 2

#1 #60

CN 1

Source Left PCB

#1 #60

13 /41