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2
ABSOLUTE MAXIMUM RATINGS
5
9-3
ELECTROSTATIC DISCHARGE CONTROL
29
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LC420WUE
Product Specification
CONTENTS
NumberITEM
COVER1
CONTENTS
RECORD OF REVISIONS
1GENERAL DESCRIPTION
3ELECTRICAL SPECIFICATIONS
3-1ELECTRICAL CHARACTERISTICS
3-2INTERFACE CONNECTIONS
3-3SIGNAL TIMING SPECIFICATIONS
3-4LVDS SIGNAL SPECIFICATIONS
3-5COLOR DATA REFERENCE
3-6POWER SEQUENCE
4OPTICAL SPECIFICATIONS
5MECHANICAL CHARACTERISTICS
Page
2
3
4
6
6
10
12
13
16
17
18
22
6RELIABILITY
7INTERNATIONAL STANDARDS
7-1SAFETY
7-2EMC
7-3Environment
8PACKING
8-1INFORMATION OF LCM LABEL
8-2PACKING FORM
9PRECAUTIONS
9-1MOUNTING PRECAUTIONS
9-2OPERATING PRECAUTIONS
9-4PRECAUTIONS FOR STRONG LIGHT EXPOSURE
9-5STORAGE
9-6HANDLING PRECAUTIONS FOR PROTECTION FILM
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Revision No.Revision DatePageDescription
1.0Aug. 06. 2010-Final Specification
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LC420WUE
Product Specification
RECORD OF REVISIONS
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r
Itisintended
to
support
LCD
TV,PCTV
where
high
brightness
super
wide
viewing
angle
high
color
gamut
g
OutlineDimension
983.0(H)x576.0(V)x35.5mm(D)(Typ.)
p
p
()(g)
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Product Specification
1. General Description
The LC420WUE is a Color Active Matrix Liquid Crystal Display with an integral External Electrode Fluorescent
Lamp(EEFL) backlight system. The matrix employs a-Si Thin Film Transistor as the active element.
It is a transmissive display type which is operating in the normally black mode. It has a 42.02 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06BilionM(true) colors.
It has been designed to apply the 10-bit 2-port LVDS interface.
,
high color depth and fast response time are important.
,
LC420WUE
,
Mini-LVDS(RGB)
Control
Signals
Power Signals
Source Driver Circuit
S1S1920
G1
TFT - LCD Panel
(1920 Ý RGB Ý 1080 pixels)
[Gate In Panel]
G1080
Back light Assembly
OPC Enable
ExtVBR-B
VBR-B out
LVDS
2Port
LVDS
Select
Bit
Select
+12.0V
High Input
High Input
CN1
(51pin)
LVDS 1,2
Option
signal
I2C
EEPROM
SCL
Timing Controlle
LVDS Rx + OPC + DGA + ODC
Power Circuit
CN3, 3pin, 16 Lamps/@136 mA
CN4, 3pin, 16 Lamps/@136 mA
SDA
Integrated
Block
General Features
Active Screen Size42.02 inches(1067.31mm) diagonal
Pixel Pitch0.4845 mm x 0.4845 mm
Pixel Format1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Weight8.7 Kg (TYP.)
Display ModeTransmissive mode, Normally black
Surface TreatmentHard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)
tionTotal 157 W (TYP.) (Logic=7.8W, Inverter=149W )
2
(Center 1point ,Typ.)
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3. G
40
¶
C
diti
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or damage to the
LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
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LC420WUE
Product Specification
ParameterSymbol
Power Input VoltageLCD CircuitVLCD-0.3+14.0VDC
Backlight Input Voltage
T-Con Option Selection VoltageVLOGIC-0.3+4.0VDC
Operating TemperatureTOP0+50
Storage TemperatureT
Panel Front Temperature TSUR-+68
Operating Ambient HumidityHOP1090%RH
Storage HumidityH
Note
1. Ambient temperature condition (Ta =
Operating Voltage
( One Side )
25 r 2 ¶C )
BL6001150VRMS
V
ST-20+60
ST1090%RH
Value
UnitNote
MinMax
¶C
¶C
¶C
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39¶C, and no condensation of water.
ravity mura can be guaranteed below
con
on.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68¶C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68ć. The range of operating temperature may degraded in case of
improper thermal management in final product design.
90%
1
2,3
4
2,3
60
60%
Storage
Operation
40
50
40%
Humidity [(%)RH]
10%
¶C]
Wet Bulb
Temperature [
0
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¶C]
30
20
10
10203040506070800-20
Dry Bulb Temperature [
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3-1. Electrical Ch
Parameter
Symbol
Unit
Note
Power Consumption
P
LCD
7.8
Watt
1
3. Electrical Specifications
aracteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the EEFL
backlight and inverter circuit.
Table 2. ELECTRICAL CHARACTERISTICS
Circuit :
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LC420WUE
Product Specification
Value
MinTypMax
Power Input VoltageV
Power Input CurrentILCD
Rush currentIRUSH--3.0A3
Note
1. The specified current and power consumption are under the V
condition whereas mosaic pattern(8 x 6) is displayed and f
LCD10.812.013.2VDC
455650845mA1
6689551240mA2
=12.0V, Ta=25 r 2¶C, fV=60Hz
LCD
is the frame frequency.
V
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
White : 1023 Gray
Black : 0 Gray
Mosaic Pattern(8 x 6)
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Val
(Op
)
(ppg@)
L
y
f
434547
KH
The performance of the lamps in LCM, for example life time or brightness, is extremely influenced by the
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
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LC420WUE
Product Specification
ParameterSymbol
ues
UnitNote
MinTypMax
Backlight Assembly :
Operating Voltage
(one side, fBL=45KHz, IBL=136 mA
RMS
)
Operating Current (one side)IBL-136-mA
Striking Voltage @0ć
en Lamp Voltage @ one side
VBL93610401144V
VOPEN1125-1350V
RMS
RMS
RMS
Operating FrequencyfBL434547kHz4
Striking TimeS
Power ConsumptionP
Lamp Voltage (one side)V
Lamp Current (one side)I
Discharge Stabilization TimeT
amp Frequenc
Established Starting Voltage @ 0ć
LAMP75010751105V
LAMP38.59mA
S--3Min1, 5
LAMP
S1125V
V
RMS
RMS
z
RMS
Life Time50,00060,000Hrs7
1, 2
1
1, 3
1, 2
1
1, 3
Note :
The design of the inverter must have specifications for the lamp in LCD Assembly.
The electrical characteristics of inverter are based on High-High Driving type.
characteristics of the DC-AC inverter. So, all the parameters of an inverter should be carefully designed so
as not to produce too much leakage current from high-voltage output of the inverter.
When you design or order the inverter, please make sure unwanted lighting caused by the mismatch of the
lamp and the inverter (no lighting, flicker, etc) has never been occurred. When you confirm it, the LCD–
Assembly should be operated in the same condition as installed in your instrument.
Ć Do not attach a conductive tape to lamp connecting wire.
If you attach conductive tape to the lamp wire, not only luminance level can be lower than typical one but
also inverter operate abnormally on account of leakage current which is generated between lamp wire and
conductive tape.
1. Specified values are defined for a Backlight Assembly.( IBL : 16 lamp, 8.5 mA/Lamp)
2. Operating voltage is measured at 25 r 2¶C(after 2hr.aging).The variance range for operating voltage
is r 10%.
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Typical level of power consumption is measured after 2hrs aging at 25
r
2
C
10%
|
IpI
–
|/I
RMS
x
100
%
}T
Vs = (Vpk-pk) / [ 2*root(2)]
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LC420WUE
Product Specification
S TIME
3. The Striking Voltage (Open Lamp Voltage) [ Vopen ] should be applied to the lamps more than Striking
time (S
TIME) for start-up. Inverter Striking Voltage must be more than Established Starting Voltage of lamp.
Otherwise, the lamps may not be turned on. The used lamp current is typical value.
When the Striking Frequency is higher than the Operating Frequency , the parasitic capacitance
can cause inverter shut down, therefore It is recommended to check it.
4. Lamp frequency may produce interference with horizontal synchronous frequency.As a result this may
cause beat on the display. Therefore, lamp frequency shall be away as much as possible from the
horizontal synchronous frequency and its harmonics range in order to prevent interference.
5. The brightness of the lamp after lighted for 5minutes is defined as 100%.
is the time required for the brightness of the center of the lamp to be not less than 95% at typical
T
S
current.
The screen of LCD module may be partially dark by the time the brightness of lamp is stable after turn on.
6. Maximum level of power consumption is measured at initial turn on.
¶
.
7. The life time is determined as the time at which brightness of the lamp is 50% compared to that of initial
value at the typical lamp current on condition of continuous operating at 25 r 2¶C, based on duty 100%.
8.The output of the inverter must have symmetrical(negative and positive) voltage and current waveform
(Unsymmetrical ratio is less than 10%). Please do not use the inverter which has not only unsymmetrical
voltage and current but also spike wave.
Requirements for a system inverter design, which is intended to achieve better display performance,
power efficiency and more reliable lamp characteristics.
It can help increase the lamp lifetime and reduce leakage current.
a. The asymmetry rate of the inverter waveform should be less than
.
b. The distortion rate of the waveform should be within 2 ·10%.
* Inverter output waveform had better be more similar to ideal sine wave.
I p
* Asymmetry rate:
p
* Distortion rate
I -p
I
(or I–p)/I
p
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High Volt
P5100(Tekt
)
9. The reference method of burst dimming duty ratio.
It is recommended to use synchronous V-sync frequency to prevent waterfall
(Vsync x 2 =Burst Frequency)
Though PWM frequency is over 182Hz (max252Hz), function of backlight is not affected.
PWM
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LC420WUE
Product Specification
{
A
+3.3V TTL
I-out
Output of Inverter to Lamp
90%
PWM duty={ A/T } * 100
Point A : rising time 90% of Iout point .
Point B : falling starting point .
I out duty = { a/T } * 100
PWM Frequency = 1/T
Ć We recommend not to be much different between PWM duty and Iout duty .
Ć Dimming current output rising and falling time may produce humming and inverter trans’ sound noise.
Ć Burst dimming duty should be 100% for more than 1second after turn on.
Ć Equipment
Oscilloscope :TDS3054B(Tektronix)
Current Probe : P6022 AC (Tektronix)
age Probe:
10. The Cable between the backlight connector and its inverter power supply should be connected directly
with a minimized length. The longer cable between the backlight and the inverter may cause the lower
luminance of lamp and may require more higher starting voltage ( Vs ).
ronix
Point A
a
Point B
11. The operating current must be measured as near as backlight assembly input.
12. The operating current unbalance between left and right must be under 10% of Typical current
Left(Master) current – Right(Slave) Current ର 10% of typical current
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This LCD module employs two kinds of interface connection, 51
pin connector is used for the module
ೢHೣ
ಫHಬ
ಫ
25
R1EP
FIRST LVDS Receiver Signal (E+)
51
VLCD
PowerSupply12.0V
If not used, these pins are no connection. (Please see the
Appendix III
3
for more information.)
3-2. Interface Connections
electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector : FI-R51S-HF(manufactured by JAE) or KN25-51P-0.5SH(manufactured by Hirose)
(CN1) Refer to below table
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4. MODULE CONNECTOR(CN1) PIN CONFIGURATION
NoSymbolDescriptionNoSymbolDescription
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
NCNo Connection
NCNo Connection
NCNo Connection
NCNo Connection (Reserved for LGD)
NCNo Connection (Reserved for LGD)
NCNo Connection (Reserved for LGD)
=JEIDA , ಫLಬor NC = VESA
LVDS Select
BR-BExternal VBR (From System)
EXTV
VBR-B outOPC output (From LCM)
OPC Enable
GND
R1AN
R1AP
R1BN
R1BP
R1CN
R1CP
GND
R1CLKN
R1CLKP
GND
R1DN
R1DP
R1EN
NC
H’ = Enable , ‘L’ or NC = Disable
Ground
FIRST LVDS Receiver Signal (A-)
FIRST LVDS Receiver Signal (A+)
FIRST LVDS Receiver Signal (B-)
FIRST LVDS Receiver Signal (B+)
FIRST LVDS Receiver Signal (C-)
FIRST LVDS Receiver Signal (C+)
Ground
FIRST LVDS Receiver Clock Signal(-)
FIRST LVDS Receiver Clock Signal(+)
Ground
FIRST LVDS Receiver Signal (D-)
FIRST LVDS Receiver Signal (D+)
FIRST LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (A-)
SECOND LVDS Receiver Signal (A+)
SECOND LVDS Receiver Signal (B-)
SECOND LVDS Receiver Signal (B+)
SECOND LVDS Receiver Signal (C-)
SECOND LVDS Receiver Signal (C+)
Ground
SECOND LVDS Receiver Clock Signal(-)
SECOND LVDS Receiver Clock Signal(+)
Ground
SECOND LVDS Receiver Signal (D-)
SECOND LVDS Receiver Signal (D+)
SECOND LVDS Receiver Signal (E-)
SECOND LVDS Receiver Signal (E+)
No Connection
No Connection
+
LC420WUE
Note
1. All GND(ground) pins should be connected together to the LCD module’s metal frame.
2. All V
LCD (power input) pins should be connected together.
3. All Input levels of LVDS signals are based on the EIA 644 Standard.
4. Specific pins(pin No. #2~#6) are used for internal data process of the LCD module.
These pins should be no connection.
5. Specific pins(pin No. # 8~#10) are used for OPC function of the LCD module.
-
6. LVDS pin (pin No. #24,25,40,41) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
7. Specific pin No. #44 is used for “No signal detection” of system signal interface.
It should be GND for NSB(No Signal Black) during the system interface signal is not.
If this pin is “H”, LCD Module displays AGP(Auto Generation Pattern).
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ଝ
[Slave]
[Master]
[Sae]
3-2-2. Backlight Module
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LC420WUE
Product Specification
[ Master ]
1) Balance Connector
: 65002WS-03 (manufactured by YEONHO) or equivalent
2) Mating Connector
: 65002HS-03 (manufactured by YEONHO) or equivalent.
NoSymbolMasterSlaveNote
1
2
3FBNCNC
Rear view of LCM
H_Input
H_Input
High_Input High_Input
High_InputHigh_Input
123
1
23
[ Slave ]
1) Balance Connector
: 65002WS-03 (manufactured by YEONHO) or equivalent
2) Mating Connector
: 65002HS-03 (manufactured by YEONHO) or equivalent.
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Master
Slave
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Vertical
fV475053
Hz
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6-1. TIMING TABLE for NTSC (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
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LC420WUE
Product Specification
HV-960-tclk
HB100140240tclk
HP106011001200tclk2200/2
VV-1080-tHP
Horizontal
Vertical
Display Periodt
Blankt
Totalt
Display Periodt
BlanktVB114569tHP
TotaltVP109111251149tHP
Frequency
DCLKf
Horizontalf
Verticalf
CLK7074.2577MHz148.5/2
H6567.570KHz
V576063Hz
Table 6-2. TIMING TABLE for PAL (DE Only Mode)
ITEMSymbolMinTypMaxUnitNote
HV-960-tclk
HB100140240tclk
Horizontal
Display Periodt
Blankt
Totalt
Display Periodt
HP106011001200tclk2200/2
VV-1080-tHP
VerticalBlanktVB228270300tHP
TotaltVP130813501380tHP
CLK7074.2577MHz148.5/2
H6567.570KHz
Frequency
Note
DCLKf
Horizontalf
The Input of HSYNC & VSYNC signal does not have an effect on normal operation(DE Only Mode).
The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate.
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0.5VDD
Valid data
t
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
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LC420WUE
Product Specification
DE, Data
DCLK
First data
Second data
0.7VDD
0.3VDD
tCLK
Invalid data
Invalid data
DE(Data Enable)
Valid data
Pixel 0,0
Pixel 1,0
tHP
Pixel 2,0
Pixel 3,0
Invalid data
Invalid data
tHV
DE(Data Enable)
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11080
VV
tVP
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