LG KP202 Service Manual
Service Manual
Model : KP202
Service Manual
KP202
Date: April, 2007 / Issue 1.0
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1. INTRODUCTION ...............................5
1.1 Purpose .................................................. 5
1.2 Regulatory Information............................ 5
1.3 Abbreviations .......................................... 7
2. PERFORMANCE...............................9
2.1 H/W Features...........................................9
2.2 Technical Specification ..........................10
3. TECHNICAL BRIEF ........................15
3.1 Power Amplifier (SKY77318, U500).......15
3.2 Transceiver (AD6548, U501) .................17
3.3 FEM for Triband .....................................19
3.4 26 MHz Clock (Crystal, X500)................20
3.5 Baseband Processor (AD6720 , U104)..21
3.6 Display and Interface .............................28
3.7 Camera Interface(AIT701G , U402).......30
3.8 Keypad Switches and Scanning ............32
3.9 Microphone ............................................33
3.10 Main Speaker.......................................34
3.11 Headset Interface.................................35
3.12 Key Back-light Illumination...................36
3.13 LCD Back-light Illumination..................37
3.14 VIBRATOR...........................................38
4. TROUBLE SHOOTING ...................39
4.1 RF Component.......................................39
4.2 RX Trouble.............................................40
4.3 TX Trouble .............................................45
4.4 Power On Trouble..................................51
4.5 Charging Trouble ...................................53
4.6 Vibrator Trouble .....................................55
4.7 LCD Trouble...........................................57
4.8 Camera Trouble .....................................60
4.9 Speaker Trouble ....................................63
4.10 SIM Card Interface Trouble..................65
4.11 Earphone Trouble ................................67
4.12 KEY backlight Trouble .........................69
4.13 Receiver Trouble..................................71
4.14 Microphone Trouble .............................73
4.15 RTC Trouble ........................................75
4.16 Indicator LED Trouble ..........................77
4.17 Folder on/off Trouble............................79
5. DOWNLOAD.......................................81
5.1 Download ...............................................81
6. BLOCK DIAGRAM ..........................87
7. Circuit Diagram ..............................89
8. PCB LAYOUT..................................97
9. ENGINEERING MODE ..................103
9.1 BB Test [MENU 1]................................104
9.2 RF Test [MENU 2]................................106
9.3 MF mode [MENU 3] .............................106
9.4 Trace option [MENU 4] ........................107
9.5 Call timer [MENU 5] .............................107
9.6 Fact. Reset [MENU 6] ..........................107
9.7 S/W version..........................................107
10. STAND ALONE TEST .................108
10.1 Introduction ........................................108
10.2 Setting Method...................................108
10.3 Means of Test ....................................109
11. AUTO CALIBRATION..................111
11.1 Overview ............................................111
11.2 Equipment List ...................................111
11.3 Test Jig Operation..............................112
11.4 Procedure ..........................................113
11.5 AGC ...................................................115
11.6 APC....................................................115
11.7 ADC ...................................................115
12. EXPLODED VIEW &
REPLACEMENT PART LIST ..... 117
12.1 Exploded View .................................. 117
12.2 Replacement Parts ............................119
12.3 Accessory ......................................... 135
Table Of Contents
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1. INTRODUCTION
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1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download the
features of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,
persons other than your company’s employees, agents, subcontractors, or person working on your
company’s behalf) can result in substantial additional charges for your telecommunications services.
System users are responsible for the security of own system. There are may be risks of toll fraud
associated with your telecommunications system. System users are responsible for programming and
configuring the equipment to prevent unauthorized use. The manufacturer does not warrant that this
product is immune from the above case but will prevent unauthorized use of common-carrier
telecommunication service of facilities accessed through or connected to it.
The manufacturer will not be responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possibly
causing harm or interruption in service to the telephone network, it should disconnect telephone
service until repair can be done. A telephone company may temporarily disconnect service as long as
repair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If these
changes could reasonably be expected to affect the use of the this phone or compatibility with the
network, the telephone company is required to give advanced written notice to the user, allowing the
user to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on this model must be performed only by the manufacturer or its authorized
agent. The user may not make any changes and/or repairs expect as specifically noted in this manual.
Therefore, note that unauthorized alternations or repair may affect the regulatory status of the system
and may void any remaining warranty.
1. INTRODUCTION
1. INTRODUCTION
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E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by local
regulatory agencies. In accordance with these agencies, you may be required to provide information
such as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightly
different.
G. Interference and Attenuation
Phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from
unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.
Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system boards.
• When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.
• Use a suitable, grounded soldering iron.
• Keep sensitive parts in these protective packages until these are used.
• When returning system boards or parts like EEPROM to the factory, use the protective package as
described.
1. INTRODUCTION
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1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current - Constant Voltage
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milli watt
DSP Digital Signal Processing
EEPROM Electrical Erasable Programmable Read-Only Memory
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
1. INTRODUCTION
- 8 -
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
PSRAM Pseudo SRAM
STMR Side Tone Masking Rating
TA Travel Adapter
TDD Time Division Duplex
TDMA Time Division Multiple Access
UART Universal Asynchronous Receiver/Transmitter
VCO Voltage Controlled Oscillator
VCTCXO Voltage Control Temperature Compensated Crystal Oscillator
WAP Wireless Application Protocol
2. PERFORMANCE
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2.1 H/W Features
2. PERFORMANCE
Item Feature Comment
Standard Battery Li-ion, 3.7V 830mAh
Talk time Up to 200min : GSM Tx Level 7
Stand by time Up to 200 hours (Paging Period: 5, RSSI: -85 dBm)
Charging time Approx. 2.5 hours
RX Sensitivity GSM, EGSM: -102dBm, DCS: -102dBm, PCS: -102dBm
TX output power
GSM, EGSM: 32.5dBm(Level 5),
DCS , PCS: 29.5dBm(Level 0)
GPRS compatibility Class 10
SIM card type 3V,1.8V Small
Display MAIN : TFT 128 × 160 pixel 65K Color
SUB : MONO STN 96*64
Hard icons. Key Pad
0 ~ 9, #, *, Up/Down/Left/Right/Ok Navigation Key
Status Indicator
Menu Key, Clear Key, Back Key, Confirm Key
Send Key, Volume Key, PWR Key, Camera Key, Hot Key
ANT Internal
EAR Phone Jack Yes (mono)
PC Synchronization Yes
Speech coding EFR/FR/HR
Data Yes
Vibrator Yes
Loud Speaker Yes
Voice Recoding Yes
Microphone Yes
Speaker/Receiver One way speaker
Travel Adapter Yes
MIDI SW MIDI (Mono SPK)
Camera VGA
2. PERFORMANCE
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2.2 Technical Specification
Item Description Specification
GSM
TX: 890 + n x 0.2 MHz
RX: 935 + n x 0.2 MHz (n=1~124)
PCS
1Frequency Band TX: 1850 + (n-511) x 0.2 MHz
RX: 1930+ (n-511) x 0.2 MHz (n=512~810)
DCS
TX: 1710 + (n-511) x 0.2 MHz
RX: 1805 + (n-511) x 0.2 MHz (n=512~885)
2 Phase Error
RMS < 5 degrees
Peak < 20 degrees
3 Frequency Error < 0.1 ppm
GSM
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
4 Power Level 12 19 dBm 3dB
DCS/PCS
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB
2. PERFORMANCE
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Item Description Specification
GSM, EGSM
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -63
3,000~ <6,000 -65
5
Output RF Spectrum 6,000 -71
(due to modulation) DCS/PCS
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -65
3,000~ <6,000 -65
6,000 -73
GSM, EGSM
Offset from Carrier (kHz) Max. (dBm)
Output RF Spectrum 400 -19
6
(due to switching transient) 600 -21
1,200 -21
1,800 -24
2. PERFORMANCE
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Item Description Specification
DCS/PCS
Offset from Carrier (kHz). Max. (dBm)
Output RF Spectrum 400 -22
6
(due to switching transient) 600 -24
1,200 -24
1,800 -27
7 Spurious Emissions Conduction, Emission Status
GSM, EGSM
8Bit Error Ratio
BER (Class II) < 2.439% @-102 dBm
DCS,PCS
BER (Class II) < 2.439% @-102 dBm
9 RX Level Report Accuracy 3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 2 -7
500
*
-5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
*
Mean that Adopt a straight line in between 300 Hz
and 1,000 Hz to be Max. level in the range.
2. PERFORMANCE
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Item Description Specification
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
-35 17.5
-30 22.5
-20 30.7
16 Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side Tone Distortion Three stage distortion < 10%
18
System frequency
2.5ppm
(13 MHz) tolerance
19 32.768KHz tolerance 30ppm
At least 65 dBspl under below conditions:
20 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 50 cm
21 Charge Current
Fast Charge : < 600 mA
Slow Charge : < 120 mA
Antenna Bar Number Power
5 -85 dBm ~
4-90 dBm ~ -86 dBm
22 Antenna Display 3 -95 dBm ~ -91 dBm
2-100 dBm ~ -96 dBm
1-105 dBm ~ -101 dBm
0~ -105 dBm
Battery Bar Number Voltage
0 3.56V ~ 0.05 V
23 Battery Indicator 1 3.66V ~ 0.05 V
2 3.74V ~ 0.05 V
3 3.85V ~ 0.05 V
43.86V ~ 0.05 V ~
24 Low Voltage Warning
3.56 0.05 V (Call) every 1 minutes
3.50 0.05 V (Standby)
2. PERFORMANCE
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Item Description Specification
25 Forced shut down Voltage 3.35 0.03V
1 Li-ion Battery
26 Battery Type
Standard Voltage = 3.7 V
Battery full charge voltage = 4.2 V
Capacity: 830mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240 V, 50/60 Hz
Output: 5.2 V, 800 mA
3. TECHNICAL BRIEF
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3.1 Power Amplifier (SKY77318, U500)
The SKY77318 Power Amplifier Module (PAM) is designed in a low profile (1.2 mm), compact form
factor for quad-band cellular handsets comprising GSM850/900, DCS1800, and PCS1900 operation.
The PAM also supports Class 12 General Packet Radio Service (GPRS) multi-slot operation. The
module consists of separate GSM850/900 PA and DCS1800/PCS1900 PA blocks,
impedancematching circuitry for 50 Ω input and output impedances, and a Power Amplifier Control
(PAC) block with an internal current-sense resistor. The custom BiCMOS integrated circuit provides
the internal PAC function and interface circuitry. Fabricated onto a single Gallium Arsenide (GaAs) die,
one Heterojunction Bipolar Transistor (HBT) PA block supports the GSM850/900 bands and the other
supports the DCS1800 and PCS1900 bands. Both PA blocks share common power supply pins to
distribute current. The GaAs die, the Silicon (Si) die, and the passive components are mounted on a
multi-layer laminate substrate. The assembly is encapsulated with plastic over mold. RF input and
output ports of the SKY77318 are internally matched to a 50 Ω load to reduce the number of external
components for a quad-band design. Extremely low leakage current (2.5 µA, typical) of the dual PA
module maximizes handset standby time. The SKY77318 also contains band-select switching circuitry
to select GSM (logic 0) or DCS/PCS (logic 1) as determined from the Band Select (BS) signal. In
Figure 3.1 below, the BS pin selects the PA output (DCS/PCS OUT or GSM850/900 OUT) and the
Analog Power Control (VAPC) controls the level of output power. The VBATT pin connects to an
internal current-sense resistor and interfaces to an integrated power amplifier control (iPAC™)
function, which is insensitive to variations in temperature, power supply, process, and input power. The
ENABLE input allows initial turn-on of PAM circuitry to minimize battery drain.
3. TECHNICAL BRIEF
Figure 3.1 Functional Block Diagram
3. TECHNICAL BRIEF
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SKY77318 PAM Pin Configuration-20-Pin
Leadless (Top View)
Typical Case Makings
Table 4. SKY77318 Pin Names and Signal Descriptions
Pin Mame Description
1BSBand Select
2 VCC1A VCC (to GSM 1st stage, DCS/PCS 1st stages, BiCMOS PAC)
3 DCS/PCS IN RF input 1710-1910 MHz (DCS1800, PCS1900)
4 GSM IN RF input 880-915 MHz (GSM)
5 GND RF and DC Ground
6 VCC1B VCC (to GSM 2nd stage, DCS/PCS 2nd stages)
7 GND RF and DC Ground
8 GND RF and DC Ground
9 GND RF and DC Ground
10 GND RF and DC Ground
11 GSM OUT RF Output 880-915 MHz (GSM)
12 GND RF and DC Ground
13 GND RF and DC Ground
14 GND RF and DC Ground
15 DCS/PCS_OUT RF Output 1710-1910 MHz (DCS 1800, PCS1900)
16 GND RF and DC Ground
17 VBATT Battery input to high side of internal sense resistor
18 ENABLE BiCMOS Enable
19 RSVD(GND) RF and DC Ground
20 VAPC Power Control Bias Voltage
GMD PAD GND Ground Pad, device underside
3. TECHNICAL BRIEF
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3.2 Transceiver (AD6548, U501)
The AD6548 provides a highly integrated direct conversion radio solution that combines, on a single
chip, all radio and power management functions necessary to build the most com-pact GSM radio
solution possible. The only external components required for a complete radio design are the Rx
SAWs, PA, Switchplexer and a few passives enabling an extremely small cost effective GSM Radio
solution. The AD6548 uses the industry proven direct conversion receiver architecture of the
OthelloTM family. For Quad band applications the front end features four fully integrated
programmable gain differential LNAs. The RF is then down converted by quad-rature mixers and then
fed to the baseband programmable-gain amplifiers and active filters for channel selection. The
Receiver output pins can be directly connected to the baseband analog processor. The Receive path
features automatic calibration and tracking to remove DC offsets.
The transmitter features a translation-loop architecture for directly modulating baseband signals onto
the integrated TX VCO. The translation-loop modulator and TX VCO are extremely low noise removing
the need for external SAW filters prior to the PA. The AD6548 uses a single integrated LO VCO for
both the receive and the transmit circuits. The synthesizer lock times are optimized for GPRS
applications up to and including class 12. AD6548 incorporates a complete reference crystal
calibration system. This allows the external VCTCXO to be replaced with a low cost crystal. No other
external components are required. The AD6548 uses the traditional VCTCXO reference source. The
AD6548 also contains on-chip low dropout voltage regulators (LDOs) to deliver regulated supply
voltages to the functions on chip, with a battery input voltage of between 2.9V and 5.5V.
Comprehensive power down options are included to minimize power consumption in normal use. A
standard 3 wire serial interface is used to program the IC. The interface features low-voltage digital
interface buffers compatible with logic levels from 1.6V to 2.9V.
Figure 3.2 AD6548 Block Diagram
3. TECHNICAL BRIEF
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COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
AD6548/9 Pin Descriptions
3. TECHNICAL BRIEF
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3.3 FEM for Triband
Table 3.3.1 Band SW Logic Table
Figure 3.3.1 FEM CIRCUIT DIAGRAM
24
18
NC1
NC2
19
PCS_RX+
13
12
PCS_RX-
TX1G
6
TX2G
8
VCTRL1
22
21
VCTRL2
20
VCTRL3
3
VDD
YGHF-S006T
ANT
1
DCS_RX+
15
14
DCS_RX-
EGSM_RX+
17
16
EGSM_RX-
2
GND1
25
GND10
GND11
26
4
GND2
GND3
5
7
GND4
GND5
9
10
GND6
11
GND7
GND8
23
GND9
FL500
56p
C538
2V8_VEXT
0.1u
C539
Tx 900 Tx 1800/1900 RX EGSM RX DCS RX PCS
Vdd H H H H H
Vctrl1 H H L L L
Vctrl2 L H H L L
Vctrl3 L L L H L
3. TECHNICAL BRIEF
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3.4 26 MHz Clock (Crystal, X500)
The 26 MHz clock (X500) consists of a XO( Crystal Oscillator) which oscillates at a frequency of 26
MHz. The AD6548 requires only an external low cost crystal as the frequency reference. The circuitry
to oscillate the crystal and tune its frequency is fully integrated. The Oscillator is a balanced
implementation requiring the crystal to be connected across 2 pins. There is a programmable capacitor
array included for coarse tuning of fixed offsets (e.g. crystal manufacturing tolerance), and an
integrated varactor for dynamic control. The oscillator is designed for use with a 26MHz crystal.
Dedicated control software ensures excellent frequency stability under all circumstances.
Figure 3.4 CRYSTAL CIRCUIT DIAGRAM
X500
34
1
2
26MHz
NX3225DA(W-191-451)
3. TECHNICAL BRIEF
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3.5 Baseband Processor (AD6720 , U104)
• AD6720 is an ADI designed processor
• AD6720 consists of
1. Control Processor Subsystem including:
• 32-bit MCU ARM7TDMI® Control Processor
• 39 MHz operation at 1.8V
• 1Mb of on-chip System SRAM Memory
2. DSP Subsystem including:
• 16-bit Fixed Point DSP Processor
• 91 MIPS[1] at 1.8V
• Data and Program SRAM
• Program Instruction Cache
• Full Rate, Enhanced Full Rate and Half Rate
• Speech Encoding/Decoding
• Capable of Supporting AMR & PDC Speech Algorithms
3. Peripheral Functions
• Parallel and Serial Display Interface
• Keypad Interface
• Flash Memory Interface
• Page-Mode Flash Support
• 1.8V and 3.0V, 64 kbps SIM Interface
• Universal System Connector Interface
• Data Services Interface
• Battery Interface (e.g. Dallas)
4. Other
• Supports 13 MHz and 26 MHz Input Clocks
• 1.8V Typical Core Operating Voltages
• 289-Ball Package (12x12mm) , 0.65mm Ball pitch
5. The AD6720 baseband transmit section supports the following
• mobile station GMSK modulation power classes:
• GSM 900/850 power classes 4 and 5,
• DCS 1800 power classes 1 and 2, and
• PCS 1900 power classes 1 and 2
3. TECHNICAL BRIEF
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Figure 3.5 SYSTEM INTERCONECTION OF AD6720 EXTERNAL INTERFACE
3. TECHNICAL BRIEF
- 23 -
3.5.1 Interconnection with external devices
A. RTC block interface
Countered by external X-TAL
The X-TAL oscillates 32.768KHz
B. LCD module interface
The LCD module is controlled by CAMERA IC, AIT701G
If AIT701G is in the state of by-pass mode, the LCD control signals from AD6720
are by-passed through AIT701G.
In operating mode, the AIT701G controls the LCD module through L_MAIN_LCD_CS,
L_SUB_LCD_CS, LCD_RESET, LCD_RS, LCD_WR, LCD_RD, L_DATA[15-00],
2V8_VCAM, IF_MODE, LCD_ID[1:3].
Signals Description
L_MAIN_LCD_CS MAIN LCD driver chip enable. MAIN LCD driver IC has own CS pin
L_SUB_LCD_CS SUB LCD driver chip enable. SUB LCD driver IC has own CS pin
LCD_ID1 Select LCD module maker(2.4V : NEODIS, 0V : LGIT)
LCD_RESET This pin resets LCD module. This signal comes from AD6720 directly.
LCD_WR Enable writing to LCD Driver.
LCD_RD Enable reading to LCD Driver.
LCD_RS
This pin determines whether the data to LCD module are display data or
control data. LCD_RS can select 16 bit parallel bus.
2V8_CAM 2.8V voltage is supplied to LCD driver IC.
IF_MODE Select 16bits or 8bits interface mode for MAIN LCD. For the future
Table 3.5.B LCD CONTRON SIGNALS DISCRIPTION
3. TECHNICAL BRIEF
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The backlight of LCD module is controlled by AD6720 via AAT3157.
The control signals related to Backlight LED are given bellow.
C. RF interface
The AD6720 control RF parts through PA_BAND, ANT_SW1, ANT_SW2, ANT_SW3 , CLKON,
PA_EN, S_EN, S_DATA, S_CLK
Signals Description
MLED Current source for backlight LED
LCD_DIM_CTL Control LCD backlight level in 16 steps
MLED[1:3] This pins are returned-paths for backlight LED current source (MLED)
Table 3.5.B2 DESCRIPTION OF LCD BACKLIGHT LED CONTROL
Signals Description
PA_BAND (GPO 17) PAM Band Select
ANT_SW1 (GPO 9) Antenna switch Band Select
ANT_SW2 (GPO 10) Antenna switch Band Select
PA_EN (GPO 16) PAM Enable/Disable
S_EN (GPO 19) PLL Enable/Disable
S_DATA (GPO 20) Serial Data to PLL
S_CLK (GPO 21) Clock to PLL
Table 3.5.C RF CONTROL SIGNALS DESCRIPTION
3. TECHNICAL BRIEF
- 25 -
D. SIM interface
The AD6720 provides SIM Interface Module. The AD6720 checks status periodically during
established call mode whether SIM card is inserted or not, but it doesn't check during deep Sleep
mode. In order to communicate with SIM card, 3 signals SIM_DATA, SIM_CLK,
SIM_RST(GPIO_23) are required. The descriptions about the signals are given by bellow Table 3-5
in detail.
Signals Description
SIM_DATA
This pin receives and sends data to SIM card.
This model can support 3.0 volt and 1.8 volt interface SIM card.
SIM_CLK Clock 3.25MHz frequency.
SIM_RST
Reset SIM block
(GPIO_23)
Table 3.5.D SIM CONTROL SIGNALS DESCRIPTION
Figure 3.5.D2 SIM Interface of AD6720
SIM CONNECTOR
2V85_VSIM
0R128
C155
220n
C156
NA
18K
R126
NA
C157
89
GND4
GND5
10
IO
6
RST
2
1
VCC
5
VPP
J100
3
CLK
GND1
4
7
GND2
GND3
C158
1000p
NA
R127
2V85_VSIM
SIM_CLK
SIM_RST
SIM_DATA
3. TECHNICAL BRIEF
- 26 -
E. LDO Block
There are 8 LDOs in the AD6720.
- VCORE : supplies Digital baseband Processor core and AD6720 digital core(1.8V, 80mA)
- VMEM : supplies external memory and the interface to the external memory on the digital
baseband processor (2.8V, 150mA)
- VEXT : supplies Radio digital interface and high voltage interface (2.8V, 200mA)
- VSIM : supplies the SIM interface circuitry on the digital processor and SIM card (2.85V,1.8V,
20mA)
- VRTC : supplies the Real-Time Clock module (1.8 V, 20 µA)
- VABB : supplies the analog portions of the AD6720
- VMIC : supplies the microphone interface circuitry (2.5 V, 2 mA)
- VVCXO : supplies the voltage controlled crystal oscillator ( 2.75 V, 10 mA)
F. Battery Charging Block
1. It can be used to charge Lithium Ion batteries.
Charger initialization, trickle charging, and Li-Ion charging control are implemented in hardware.
2. Charging Process
- Check charger is inserted or not
- If AD6720 detects that Charger is inserted, the CC-CV charging starts.
- Exception : When battery voltage is lower than 3.2V, the precharge (low current charge mode)
starts firstly.
- And the battery voltage reach to 3.2V the CC-CV charging starts.
3. Pins used for charging
- VCHG : charger supply.
- GATEDRIVE : charge DAC output
- ISENSE : charge current sense input
- VBATSENSE : battery voltage sense input.
- BATTYPE : battery type identification input
- REFCHG : voltage reference output
4. TA (Travel Adaptor)
- Input voltage: AC 100V ~ 2400V, 50~60Hz
- Output voltage: DC 5.2V
- Output current: Max 800mA
5. Battery
- Li-ion battery (Max 4.2V, Nom 3.7V)
- Standard battery: Capacity - 830mAh
3. TECHNICAL BRIEF
- 27 -
Figure 3.5.F2 CIRCUIT FOR BATTERY CHARGING
Figure 3.5.F1 CIRCUIT FOR BATTERY CHARGING
PRE
CHARGING
NORMAL
CHARGING
CHARGE
VCHARGE
VBAT
R108
C128
0.1u
PRE_CHARGE_R INDLED_R
R110
1.5K
R111
10K
10
R109
Q101
3
25
1
UMX1NTN
1K
4
6
R112
7.5K
R113
10K
R117
0.2
C138
1u
4
3
2
1
Q102
G5S
D3
D2
D1
D101
CUS02
D4
D5
D6
TPCF8102-TE85L-F
1V8_VRTC
KEY_BACKLIGHT
VCHARGEVBAT
C136
(2125)
4.7u
R118
330
6
7
8
BATT_TEMP
C134
0.1u
R116
2.2K
R120 82K
C144
0.1u
C135
4.7u
(1608)
LCD_DIM_CTL
TCK
TMS
TDO1
JTAGEN
KEY_ROW0
POWERKEY
C131 1u
TDI
H13
LIGHT2
J15
LIGHT3
P8
GPO_22
R5
GPO_23
T12
VMEMSEL
D17
REF
C15
C14
A13
A14
B14
T13
C12
A12
C13
B13
F17
B12
G3
T16
U17
M5
F5
F2
F6
F4
REFOUT
TEMP1
TEMP2
AUXADC1
AUXADC2
VRTC
VCHG
GATEDRIVE
ISENSE
VBATSENSE
REFCHG
BATTYPE
GPIO_18
GPIO19_TMS
GPIO_20
GPIO_21_TDI
JTAGEN
KEYOUT
KEYON
1uC133
3. TECHNICAL BRIEF
- 28 -
3.6 Display and Interface
• Main LCD
• Sub LCD
Controlled by L_MAIN_LCD_CS, L_SUB_LCD_CS, LCD_RESET, LCD_RS, LCD_WR, LCD_RD,
IFMODE, L_DATA[00:15] ports
• L_MAIN_LCD_CS : MAIN LCD driver chip enable. MAIN LCD driver IC has own CS pin
• LCD_RESET : This pin resets LCD module. This signal comes from AD6720 directly.
• LCD_RS: This pin determines whether the data to LCD module are display data or control data.
• LCD_WR : Write control Signal
• LCD_RD : Read control Signal. But this pin used only for debugging.
• L_DATA[00:15] : Parallel data lines.
• LCD_ID[1:2] : LCD type selection signals
- LCD_ID1 : LCD maker(2.4V is NEODIS, 0V is LGIT)
- LCD_ID[2:3] : for the future using
• For using 262K color, data buses should be 16 bits.
Properties Spec. Unit
Active Screen Size 28.032mm(W) x 35.04mm(H) mm
Color Depth 262,144 colors
Resolution 128 x RGB x 160 dots
Properties Spec. Unit
Active Screen Size 18.902mm(W) x 13.43mm(H) mm
Color Depth 2 colors
Resolution 96 x 64 (mono) Pixels dots
3. TECHNICAL BRIEF
- 29 -
2V8_VCAM
Figure 3.6 LCD INTERFACE CIRCUIT
L_DATA13
L_DATA14
L_DATA15
L_DATA12
L_DATA09
L_DATA10
L_DATA11
L_DATA08
9
8
7
1
2
3
4
FL602
ICVE21054E250R401FR
5
G1
INOUT_A1
INOUT_A2
INOUT_A3
INOUT_A4
10
G2
INOUT_B3
INOUT_B4
INOUT_B1
INOUT_B2
6
9
8
7
LCD_RD
MOTOR
NAC602
VSYNCOUT
R601 0
1u
C601
2V8_AVDD
58
59660
100K
R600
1u
C600
1V8_DVDD
CN600
57
G1 G2
789
1
101112
13
INOUT_B1
INOUT_B2
INOUT_B36INOUT_B4
INOUT_A1
INOUT_A2
INOUT_A3
1
2
3
4
1415161718
FL603
ICVE21054E250R401FR
G2
10
G1
5
INOUT_A4
C_CD00
5
G1
INOUT_A4
10
G2
INOUT_B4
FL605 ICVE21184E070R100
MLED3
MLED2
MLED1
43444546474849550515253545556
394404142
192202122232425262728
C_CD01
4
INOUT_A3
INOUT_B3
6
C_CD02
3
INOUT_A2
INOUT_B2
7
C_CD03
2
INOUT_A1
INOUT_B1
8
C_CD04
C_CD05
C_CD06
C_CD07
9
8
7
6
1
G2
INOUT_B1
INOUT_B2
INOUT_B3
INOUT_B4
10
G1
5
INOUT_A1
INOUT_A2
INOUT_A3
INOUT_A4
FL607 ICVE21184E070R100
1
2
3
4
9
32333435363738
G3 G4
29330 31
C608 0.1u
39pC607
39pC606
1
2
3
4
5
G1
INOUT_A1
INOUT_A2
INOUT_A3
INOUT_A4
10
G2
INOUT_B1
INOUT_B2
INOUT_B3
INOUT_B4
FL600 ICVE21054E250R401FR
9
8
7
6
9
INOUT_B1
INOUT_A1
1
8
INOUT_B2
INOUT_A2
2
7
INOUT_B3
INOUT_A3
3
6
INOUT_B4
INOUT_A4
4
MLED
BACK_BATT
NAC605
G2
10
G1
5
FL601
CAM_PWR_EN
SPK_RCV_P
SPK_RCV_N
ICVE21054E250R401FR
L_DATA00
L_DATA01
L_DATA02
L_DATA03
L_DATA04
L_DATA05
L_DATA06
L_DATA07
27p
C604
LCD_ID1
LGIT : LOW
Neodis : HIGH
LCD_MAKER(TO GPIO_17)
FL604
1
2
3
4
9
8
7
6
5
G1
INOUT_A1
INOUT_A2
INOUT_A3
INOUT_A4
INOUT_B1
INOUT_B2
INOUT_B3
INOUT_B1
9
INOUT_A1
1
INOUT_A2
2
INOUT_A3
3
INOUT_B4
INOUT_A4
4
10
G2
INOUT_B2
INOUT_B3
INOUT_B4
8
7
6
ICVE21184E150R500FR
C603
100ohm
22p
R602
100K
R603
LCD_WR
L_SUB_LCD_CS
L_MAIN_LCD_CS
LCD_RS
C_PCLK
C_MCLK
C_HS
C_VS
LCD_RESET
2V8_AVDD
FL606
ICVE21184E070R100
G2
10
G1
5
R605
4.7K
4.7K
R604
9
8
7
INOUT_B1
INOUT_B2
INOUT_B3
FL608
INOUT_A1
INOUT_A2
INOUT_A3
ICVE21184E150R500FR
1
2
3
C_RST
C_SDA
C_SCK
6
INOUT_B4
INOUT_A4
4
G2
10
G1
5
3. TECHNICAL BRIEF
- 30 -
3.7 Camera Interface(AIT701G , U402)
This model has a built-in VGA(640 x 480) camera module. And the camera produces JPG pictures.
Camera module is controlled by AIT701G. Interface is done by I2C and YCbCr format. I2C is a control
signal and YCbCr is real data interface signal.
Figure 3.7.1 AIT701G BLOCK DIAGRAM
Figure 3.7.2 SENSOR CHIP BLOCK DIAGRAM
3. TECHNICAL BRIEF
- 31 -
Figure 3.7.3 AIT701G CIRCUIT
CAMERA CTL IC
TP408
2V8_VCAM
C404
1uF
2V8_VCAM
TP400
1uF
C410
TP402
R402
100K
1V8_VCAM
0.01u
C400
TP405
C408 1000p
TP403
TP407
1uF
C409
TP404
2V8_VCAM
TP406
R403
TP409
100K
TP401
100K
R404
TP410
PRST_
D3
PSCAN_EN
PSCK
G2
PSDA
H2
H1
PSEN
PS_RST_
F2
PTEST_EN
E10
G1
PVSYNC
H5
VDD_CORE
G3
VDD_IO0 VDD_IO1
H8
VDD_IO2
E8
PLCD17
PLCD1_CS_
B2
A9
PLCD2
PLCD2_CS_
A2
C9
PLCD3
PLCD4
D8
PLCD5
A8
PLCD6
B8
PLCD7
C8
C7
PLCD8
PLCD9
C6
B3
PLCD_A0
A3
PLCD_RD_
PLCD_WE_
A4
PMCLK
J2 F1
PPXL_CLK
K3
K8
J7
PHLCD_A0
K7
PHLCD_BY
J1
PHRD_
E3
PHSYNC
K9
PHWAIT_
PHWE_
K2
PLCD0
A10
PLCD1
B10
PLCD10
B6
C5
PLCD11
B5
PLCD12
PLCD13
A6
PLCD14
C4
A5
PLCD15
PLCD16
B4
C3
H10
H9
PHD11
PHD12
G10
G9
PHD13
PHD14
G8
PHD15
F10
PHD2
K4
PHD3
J4
K5
PHD4
J5
PHD5
PHD6
K6
PHD7
J6
PHD8
K10
J9
PHD9
PHGPIO_CS_
J10
PHINT
J8
PHLCD2_CS_
C2
C1
PD5
A1
PD6
B1
PD7
F3
PDCLK
E9
PGPIO0
D9
PGPIO1
PGPIO2
C10
B9
PGPIO3
A7
PGPIO4
B7
PGPIO5
F9
PGPIO6
PGPIO7
D10
K1
PHCS_
J3
PHD0
H3
PHD1
PHD10
U402 AIT701G
GND_CORE
H6
GND_IO0
H4 H7
GND_IO1
GND_IO2
F8
PD0
E2
E1
PD1
D1
PD2
PD3
D2
PD4
SUB_CS
L_SUB_LCD_CS
CAM_PWR_EN
CAM_INT
MAIN_CS
2V8_VCAM
C_VS
VSYNCOUT
CAM_RST
C_RST
13M_AIT
_WAIT
L_DATA15
L_MAIN_LCD_CS
L_DATA02
L_DATA03
L_DATA04
L_DATA05
L_DATA06
L_DATA07
L_DATA08
L_DATA09
LCD_RS
LCD_RD
LCD_WR
C_PCLK
C_SCK
C_SDA
C_CD01
C_CD02
C_CD03
C_CD04
C_CD05
C_CD06
C_CD07
C_MCLK
C_HS
L_DATA00
L_DATA01
L_DATA10
L_DATA11
L_DATA12
L_DATA13
L_DATA14
DATA15
DATA02
DATA03
DATA04
DATA05
DATA06
DATA07
DATA08
DATA09
C_CD00
_RD
_WR
ADD01
CAM_HOLD
DATA00
DATA01
DATA10
DATA11
DATA12
DATA13
DATA14
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