LG CG180 Service Manual
Date: November, 2007 / Issue 1.0
Service Manual
Model : CG180
Service Manual
CG180
Internal Use Only
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1. General Description........................ 5
2. Performance .................................... 6
2.1 Product Name ......................................... 6
2.2 Supporting Standard................................6
2.3 Main Parts : GSM Solution...................... 6
2.4 HW Feature..............................................7
2.6 Technical Specification ..........................12
3. Circuit Description........................ 17
3.1 RF Block ............................................... 17
3.2 Digital Baseband................................... 22
3.3 Ananlog Baseband.................................26
3.4 SIM interface......................................... 35
3.5 LCD Display .......................................... 36
3.6 Keypad Switching & Scanning...............37
3.7 Vibrator Interface ...................................38
3.8 Keypad LED Interface............................39
3.9 18pin Multi Media Interface connector ...40
3.10 Audio Circuits.......................................42
4. TROUBLE SHOOTING .................. 46
4.1 RF Part Technical Brief......................... 46
4.2 RF Part Trouble shooting...................... 52
4.3 Baseband Part Troubleshooting ........... 59
5. Downloading Software ................. 80
6. Block Diagram............................... 81
7. CIRCUIT DIAGRAM ....................... 83
8. BGA IC Pin Check ..........................87
9. PCB LAYOUT................................. 89
10. RF Calibration
...................................
91
10.1 What’s the Rx Calibration?
................
91
10.2 What’s the Tx Calibration?
................
91
10.3 Calibration program - HOT_KIMCHI ..92
11. EXPLODED VIEW &
REPLACEMENT PART LIST ....... 97
11.1 EXPLODED VIEW .............................. 97
11.2 Replacement Parts
<Mechanic component>...................... 99
<Main component> ........................... 101
Table of Contents
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1. General Description
The information in this manual is subject to change without notice and should not be construed as a
commitment by LGE Inc. Furthermore, LGE Inc.
reserves the right, without notice, to make changes to equipment design as advances in engineering
and manufacturing methods warrant.
✻ This manual provides the information necessary to install, program, operate and maintain the
CG180.
1. General Description
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2. Performance
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2. Performance
2.1 Product Name
CG180 : GPRS Class 10
2.2 Supporting Standard
2.3 Main Parts : GSM Solution
Item Feature Comment
Supporting Standard GSM850/PCS1900
with seamless handover
Phase 2+(include AMR)
SIM Toolkit : Class 1,2,3,E
Frequency Range GSM850 TX : 824 - 849 MHz
GSM850 RX : 869 - 894 MHz
PCS1900 TX : 1850 - 1910 MHz
PCS1900 RX : 1930 - 1990 MHz
Application Standard WAP 2.0
Item Part Name Comment
Digital Baseband Locosto (D6591BUZPH): TI
Analog Baseband Triton (T3031FZPH): TI
RF Chip Transceiver is integrated in Locosto
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2. Performance
2.4 HW Feature
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Item Feature Comment
Form Factor Bar
1) Capacity
Battery Standard : Li-Polymer, 750mAh
2) Packing Type : Hard Pack
Size
Standard :
99.5 X 45 X 14.9mm
Weight 2.37oz With Battery
Volume 66.7cc
PCB Staggered 6Layers , 0.8t
Stand by time 250 hrs @ Paging Period 5
Charging time 3 hrs @ Power Off / 750mAh
Talk time Min : 3.0 hrs @ Power Level 5 @ GSM850 / 750mAh
RX sensitivity GSM850 : -105 dBm
PCS 1900 : -105 dBm
GSM/ GSM850 : 33 dBm Class4 (EGSM)
TX output power
GPRS PCS 1900 : 30 dBm Class1 (PCS)
GPRS compatibility GPRS Class 10
SIM card type
Plug-In SIM
3V /1.8V
Main LCD
Display 65K Color STN (128 x 128)
Backlight : White LED
Built-in Camera None
Status Indicator None
Keypad Alphanumeric Key : 12 Function Key:
Function Key : 8 4 Key Navigation, F1, F2,
Total No of Keys :20 SND, PWR/END
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2. Performance
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ANT Main : Internal Fixed Type
System connector 18 Pin
Ear Phone Jack 18pin, Mono
PC synchronization None
Memory
NOR Flash : 128Mbit
pSRAM : 64Mbit
Speech coding FR, EFR, HR,AMR
Data & Fax None
Vibrator Built in Vibrator
Blue Tooth None
MIDI(for Buzzer Function) SW Decoded 32Poly
Music Player(Ring Tone) MP3
Camcorder None
Voice Recording Yes
Speaker Phone mode
Yes
Support
Travel Adapter Yes
CDROM None
Stereo Headset None
Data Cable None
T-Flash (External Memory)
None
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2. Performance
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Item Feature Comment
RSSI 0 ~ 4 Levels
Battery Charging 0 ~ 4 Levels
Key Volume 0 ~ 5 Level
Audio Volume 1 ~ 5 Level
Time / Date Display Yes NITZ
Multi-Language Yes English / French/ Spain
Quick Access Mode NA
PC Sync NA
Speed Dial Yes (2~9) Voice mail center -> 1 key
Profile
CLIP / CLIR Yes (different melody)
Phone Book 3 Numbers + 1 Memo + 1 e-mail + Total 1000 Member
Group Select
Last Dial Number Yes (20)
Last Received Number Yes (20)
Last Missed Number Yes (10)
Search by Number/Name Name only
Group 7 Possible Rename
Fixed Dial Number Yes
Service Dial Number Yes
Own Number Yes
Voice Memo
Yes
Call Reminder Yes
Network Selection Automatic
Mute Yes
Call Divert Yes
Call Barring No
Call Charge (AoC) No No for Cingular
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2. Performance
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Item Feature Comment
Call Duration Yes
SMS (EMS) 100 (6)
SMS Over GPRS Yes
EMS Melody / Picture Yes
Send / Receive / Save
MMS MPEG4 / Send / No
Receive / Save
Long Message MAX 918 Characters
Cell Broadcast Yes
Download Over the WAP
Game YES
Calendar Yes
Memo 20
Unit Convert Currency/Area/Length/Volume/Weight
/Temperature/Velocity
Tip Calculator Yes
Wall Paper Yes Default 5ea
WAP Browser Over WAP 2.0 Openwave
Download Melody / Yes Over WAP
Wallpaper
SIM Lock Yes Operator Dependent
SIM Toolkit Class 1, 2, 3, A-E
MMS None Openwave MMS Client
EONS Yes
CPHS
Yes V4.2
ENS Yes
Camera No
JAVA No
Voice Dial No
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2. Performance
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Item Feature Comment
IrDa None
Blue tooth None
GPRS Yes Class 10
EDGE None
Hold / Retrieve None
Conference Call Yes Max. 6
DTMF Yes
Memo pad Yes
TTY Yes
AMR Yes
Sync ML No
IM No
Email No
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2.6 Technical Specification
2. Performance
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Item Description Specification
GSM850
TX: 824 + n x 0.2 MHz (n=1 ~ 124)
RX: TX + 45 MHz
1Frequency Band PCS1900
TX: 1850 + ( n-511 ) x 0.2 MHz
RX: 1930 + ( n-511 ) x 0.2 MHz (n = 512 ~ 810)
RX: TX + 45 MHz
2 Phase Error
RMS < 5 degrees
Peak < 20 degrees
3 Frequency Error < 0.1ppm
GSM850
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
4 Power Level 12 19 dBm 3dB
PCS1900
Level Power Toler. Level Power Toler.
0 30 dBm 2dB 8 14 dBm 3dB
1 28 dBm 3dB 9 12 dBm 4dB
2 26 dBm 3dB 10 10 dBm 4dB
3 24 dBm 3dB 11 8 dBm 4dB
4 22 dBm 3dB 12 6 dBm 4dB
5 20 dBm 3dB 13 4 dBm 4dB
6 18 dBm 3dB 14 2 dBm 5dB
7 16 dBm 3dB 15 0 dBm 5dB
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2. Performance
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Item Description Specification
GSM850
Offset from Carrier (kHz). Max. dBc
100 0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -63
3,000~ <6,000 -65
5
Output RF Spectrum 6,000 -71
(due to modulation) PCS1900
Offset from Carrier (kHz). Max. dBc
100 0.5
200 -30
250 -33
400 -60
600~ <1,200 -60
1,200~ <1,800 -60
1,800~ <3,000 -65
3,000~ <6,000 -65
6,000 -73
GSM850
Offset from Carrier (kHz) Max. (dBm)
Output RF Spectrum 400 -19
6
(due to switching transient) 600 -21
1,200 -21
1,800 -24
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2. Performance
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Item Description Specification
PCS1900
Offset from Carrier (kHz). Max. (dBm)
Output RF Spectrum 400 -22
6
(due to switching transient) 600 -24
1,200 -24
1,800 -27
7 Spurious Emissions Conduction, Emission Status
8 Bit Error Ratio BER (Class II) < 2.439% @-102dBm
9 Rx Level Report accuracy 3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 2 -7
500
*
-5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
*
Mean that Adopt a straight line in between 300 Hz and
1,000 Hz to be Max. level in the range.
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2. Performance
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Item Description Specification
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
-35 17.5
-30 22.5
-20 30.7
16 Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side Tone Distortion Three stage distortion < 10%
18
<Change> System frequency
2.5ppm
(13 MHz) tolerance
19 <Change>32.768KHz tolerance 30ppm
Full power
- 245mA(GSM850), 150mA(DCS/PCS)
20 Power consumption
Standby
- Normal mode 3.3mA(Max.power)
GSM850/Lvl 5 (Battery Capacity 750mA) : 180 min
20 Talk Time
GSM850/Lvl 12 (Battery Capacity 750mA) : 450 min
PCS1900/Level5 (Battery 750mA) : 360 min
PCS1900/Level10(Battery 800mA) : 530 min
Under conditions, at least 200 hours:
1. Brand new and full 750mAh battery
2. Full charge, no receive/send and keep GSM in idle mode.
21 Standby Time
3. Broadcast set off.
4. Signal strength display set at 3 level above.
5. Backlight of phone set off.
At least 70 dB under below conditions:
22 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 100 cm
23 Charge Voltage
Fast Charge : < 600 mA
Slow Charge: < 60 mA
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2. Performance
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Item Description Specification
Antenna Bar Number Power
4 -89 dBm ~
24 Antenna Display 3 -94 dBm ~ -90 dBm
2 -99 dBm ~ -95 dBm
1 -104 dBm ~ -100 dBm
0~ 104 dBm
0(included Blinking) 3.62V~3.33V
1 3.70V ~ 3.63V
25 Battery Indicator 2 3.76V ~ 3.71V
3 3.89V ~ 3.77V
4 4.20V ~ 3.90V
26 Low Voltage Warning
3.60V↓ 0.03V (Standby)
3.50V↓ 0.03V (Call)
27 Forced shut down Voltage 3.0 0.03 V
1 Li-polymer Battery, Hardpack
28 Battery Type
Standard Voltage = 3.7 V
Battery full charge voltage = 4.2 V
Capacity: 750mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240 V, 50/60Hz
Output: 5.1V, 700mA
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3. Technical Brief
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3. Technical Brief
3.1 RF Block
3.1.1 Transceiver(TI Locosto plus)
3.1.1.1 Transmitter
The transmitter is based on an All-Digital PLL (ADPLL), which has a wideband frequency modulation
capability. The frequency/phase modulation is done using a two-point modulation scheme to create the
GMSK modulated transmit digital signal.
[Fig.4.1] Functional block diagram
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The synthesizer is based on an All-Digital PLL (ADPLL) with a Digitally Controlled Oscillator (DCO) at
1.8GHz as the RF frequency source. The frequency setting is done through the fixed-point Frequency
Command Word (FCW), which is the normalized frequency to the FREF. In another view, LSB bit of
it’s integer part corresponds to an FREF frequency. The phase correction mechanism is performed
entirely in digital domain by phase locking the generated DCO clock to the reference input. The integer
part of the phase detector computes the phase difference between the DCO output clock and the
retimed reference clock (reference clock resynchronized with the DCO clock). The fractional phase
error between the reference and DCO output clocks is estimated by the TDC (Time to Digital
Converter) and added to the integer phase error.
The frequency/phase modulation is done using a two-point modulation scheme to create the GMSK
modulated transmit digital signal.
The input NRZ data is over-sampled and then passed through a digital Gaussian/linearized GMSK
shaping filter DTX. The shaped data is then fed to two points of the PLL. One point is added to the
FCW channel select word to realize the desired frequency deviation. The other is fed-forward directly
to the oscillator.
In order for the modulation index to be accurate there is a need to know the DCO gain (KDCO) at the
current frequency. For this purpose, the ADPLL embeds a hardware Kdco calculation machine.
3. Technical Brief
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[Fig.4.2] Transmitter’s Block Diagram
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3. Technical Brief
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3.1.1.2 Power Domain
VDD_PLL DBB PLL power domain. This power domain is separated from the VDD_CORE domain,
thus having the same voltage, to avoid noise injection potential cause of PLL unlocks.
VCORE DRP core digital supply. This power domain is directly connected to the DBB core voltage
VDD_CORE.
VR1 Preregulated input to LDOOS, LDOA, and LDORF DRP embedded LDOs. This power domain is
isolated from the VCORE, thus allowing the VR1 to be switched off while keeping VCORE active or in
low-consumption mode.
VR2 Preregulated input to LDOX DRP-embedded LDO. This power domain is isolated from the
VCORE, thus allowing the VR2 to be switched off while keeping VCORE active or in low-consumption
mode.
VRAPC Preregulated supply to APC DAC analog output stage. This power domain is isolated from the
VCORE, thus allowing the VRAPC domain to be switched off while keeping VCORE active or in lowconsumption mode.
VDD_APC APC output amplifier power supply. This power domain is isolated from the VCORE, thus
allowing the VDD_APC domain to be switched off while keeping VCORE active or in low-consumption
mode. Table 632 compares the characteristics of the TWL3031 power domains and the LOCOSTO
power domains.
VDD_IO System I/O supply. This power domain is shared by all system I/Os (including system highand low-frequency clock I/Os) and interfaces.
3.1.1.3 Reference clock
The reference clock is based on a Digitally-Controlled-Crystal-Oscillator (DCXO) architecture. The
oscillator uses an external 26 MHz crystal. The AFC is done by programming the corresponding
register through the control interface. The frequency correction is done by switching the oscillator capa
citors in a digital manner.
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3.1.1.4 Ramping
The Automatic Power Control (APC) module is included in the DRP wrapper. The module is used to
control the PA RAMP and the PA output power level. The APC module is split into a digital part and an
analog part.
The automatic power control (APC) generates an envelope signal to control the power ramp-up, power
ramp down and the power level of the TX radio burst. The APC structure is intended to support singleslot and multi-slot transmission with smooth power transition when consecutive bursts are transmitted
at different power levels.
3. Technical Brief
- 20 -
[Fig.4.3] DRP Block
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3. Technical Brief
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3.1.2 PAM(SKY77318)
The SKY77318 Power Amplifier Module (PAM) is designed in a low profile (1.2 mm), compact form
factor for quad-band cellular handsets comprising GSM850/900, DCS 1800, and PCS1900 operation.
The PAM also supports Class 12 General Packet Radio Service (GPRS) multi-slot operation. The
module consists of separate GSM PA and DCS1800/PCS1900 PA blocks, impedance-matching
circuitry for 50 Ω input and output impedances and a Power Amplifier Control (PAC) block with an
internal current-sense resistor. The custom BiCMOS integrated circuit provides the internal PAC
function and interface circuitry. Fabricated onto a single Gallium Arsenide (GaAs) die, one
Heterojunction Bipolar Transistor (HBT) PA block supports the GSM bands and the other supports the
DCS1800 and PCS1900 bands. Both PA blocks share common power supply pins to distribute
current. The GaAs die, the Silicon (Si) die, and the passive components are mounted on a multi-layer
laminate substrate. The assembly is encapsulated with plastic overmold. RF input and output ports of
the SKY77318 are internally matched to a 50 Ω load to reduce the number of external components for
a quad-band design. Extremely low leakage current (2.5 µA, typical) of the dual PA module maximizes
handset standby time. The SKY77318 also contains bandselect switching circuitry to select GSM (logic
0) or DCS/PCS (logic 1) as determined from the Band Select (BS) signal.
The VBATT pin connects to an internal current-sense resistor and interfaces to an integrated power
amplifier control (iPAC¢‚) function, which is insensitive to variations in temperature, power supply,
process, and input power. The ENABLE input allows initial turn-on of PAM circuitry to minimize battery
drain.
[Fig.4.4] PAM’s Functional Block Diagram
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3.1.3 ASM(LMSP2PAA)
This equipment uses a single antenna to support all handset operating modes, with an antenna switch
module select the operating frequency and band. The control logic is followed.
3.2 Digital Baseband
3. Technical Brief
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[Table 4.1] AMS Control Logic
[Fig. 4.5] Top level block diagram of the Locosto
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3. Technical Brief
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3.2.1 General Description
The LOCOSTO device is an integrated solution that embeds a digital baseband LOCOSTO device
targets solutions for GSM/GPRS (low-cost global system for mobile communications/general packet
radio service).
The DRP is a digital radio-frequency (RF) transceiver that supports up to a GPRS class12. The DRP is
designed for quad-band operation, supporting both the European and the US bands (E-GSM 900 and
DCS 1800 bands, GSM 850 and PCS 1900 bands, respectively).
The enhanced computing performances mainly rely on :
[MPU Sub-system]
- 2.5M-bit internal SRAM, single-cycle access at 104 MHz
- 1.5M-bit internal ROM single-cycle access at 104 MHz
- 16-Kw application programming interface (API), 2-cycle at 104 MHz
- Peripheral access: TI peripheral bus (TIPB) and memory-like peripherals ; 2-cycle at 104 MHz, single
cycle at 52 MHz
- Up to 124M-byte external memory accessed at 52 MHz max (~15 ns access time)
[DSP Sub-system]
- 30K 16-bit word RAM (including 16-Kw API) at 104 MHz
- 154-K 16-bit word ROM at 104 MHz
- 10-K 16-bit word RAM (external to the cDSP macro, intended for application MP3, etc.) at 104 MHz
- 154-K 16-bit word ROM at 104 MHz
- Memory-mapped control and status register (XIO/TIPB at 52 MHz)
3.2.2 Memory Interface (EMIF)
The EMIF is an asynchronous/synchronous-burst EMIF that supports most common memory interface
protocols through a flexible programming and timing signal control.
The EMIF controls up to four memory devices for a total address range up to 124M bytes (1 x 28M
bytes + 3 x 32M bytes) without adding external logic. 8-bit, 16-bit, and 32-bit read/write from the MPU
or the DMA 16-bit word data bus; burst read/write from the DMA; supports instruction / data prefetch
from the MPU.
Enhanced least recently used (ELRU) priority between the MPU/DMACSs (CS0, CS1, CS2, and CS3)
with 32M bytes for each CS (except CS0 with 28M bytes)
The external memory mapping is composed to as follow.
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CG180 uses stacked memory MCP(pSRAM + NOR-Flash) as its external memory interface, the
external devices are connected to as table 2, figure 1.
3. Technical Brief
- 24 -
[Table 4.2] External Memory Mapping
[Table 4.3] External Device Spec. connected to memory interface
8/16 R/W32M Byte
0x07FF
FFFF
0x0600 0000
nCS3
8/16 R/W32M Byte
0x05FF
FFFF
0x0400 0000
mCS2
8/16 R/W32M Byte
0x03FF
FFFF
0x0200 0000
nCS1
8/16 R/W28M Byte
0x01FF
FFFF
0x0040 0000
nCS0
Data accessSize
Stop
address
Start
address
Chip Select
128Mbit NOR Flash
nCS3
N.U
nCS1
N.U
nCS2
64Mbit SRAM
nCS0
External DevicenCSExternal Device
nCS
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3. Technical Brief
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[Fig.4.6] Memory interface scheme
V_MEM
TP212
TP205
TP208
VCCQ1
E3
VCCQ2
G10
VSS1
D5
VSS2
F3
VSSQ1
G5
VSSQ2
E12
WE_
D8
E8
F_RST_
F_WP_
E9
NC1
A1
NC2
A14
NC3
C3
NC4
C12
NC5
H3
NC6
H12
K1
NC7
K14
NC8
OE_
F12
R_CE_
H7
H8
R_CRE
C7
R_LB_
R_UB_
C8
D7
VCC
F8
A_DQ3
G7
A_DQ4
G6
A_DQ5
F5
A_DQ6
A_DQ7
F4
F11
A_DQ8
F10
A_DQ9
D6
CLK
C4
DNU1
C11
DNU2
DNU3
E7
DNU4
H4
H11
DNU5
D9
F_ACC
E11
F_CE_
D3
F_RDY_R_WAIT
A17
D11
E10
A18
A19
D10
E5
A20
D4
A21
D12
A22
AVD_
E6
G12
A_DQ0
A_DQ1
G11
G9
A_DQ10
A_DQ11
G8
A_DQ12
F7
A_DQ13
F6
G4
A_DQ14
G3
A_DQ15
A_DQ2
F9
U201 S71NS128PC0
A16
E4
TP202
0.1uF
C203
TP211
TP201
TP206
R205
10K
TP203
TP210
TP209
R210
100K
1u
C202
TP207
V_MEM
100K
R207
TP204
0.1uF
C204
FDP
nCS3 DATA_ADD(14)
DATA_ADD(15)
ADD(16)
ADD(17)
ADD(18)
ADD(19)
ADD(20)
ADD(21)
ADD(22)
nBHE
nBLE
CKM
nRDYMEM
RnW
nMOE
nFADV
DATA_ADD(0)
DATA_ADD(1)
DATA_ADD(2)
DATA_ADD(3)
DATA_ADD(4)
DATA_ADD(5)
DATA_ADD(6)
DATA_ADD(7)
DATA_ADD(8)
DATA_ADD(9)
DATA_ADD(10)
DATA_ADD(11)
DATA_ADD(12)
DATA_ADD(13)
nCS0
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3.3 Ananlog Baseband
3.3.1 General Description
The T3031 (TRITON_LITE) chip is the analog and power management part of the Texas Instruments
next generation Cellular System Solutions TCS2300/TCS2310. These GSM/GPRS platforms are also
composed by a single chip embedding Digital Baseband and RT transceiver and offer different
peripheral devices like a LCD panel, Camera, USB, Keypad, Vibrator and Bluetooth.
Block Description
A power management system
- Power supply resources
- A voice and audio interface
- A battery charger
- A monitoring system
- A real time clock resource
- USB 2.0 Full speed transceiver with carkit detection
- Three White-LEDs drivers
- A vibrator driver
- A SIM-Card detection system
- A thermal shutdown
- An I2C interface
- A JTAG and boundary scan
3.3.2 Audio and Voice Interface
The voice path processes the analog audio signals in the uplink path and transmits the converted data
to the DSP speech coder through the Voice Serial Port VSP. In the downlink path, the voice path
converts the digital samples of speech data received from the DSP via the VSP into analog audio
signals.
The voice path supports a 8 kHz (default narrowband mode) or a 16 kHz (wideband mode) sampling
frequency. The Stereo path converts the audio digital samples received from the I2S serial interface
into analog audio signals. It supports all the standard frequencies from 8kHz to 48kHz (allowed
frequencies: 8, 11.025, 12, 22.05, 24, 32, 44.1 and 48 kHz).
Two included PLLs provide the suitable system clocks to the voice and stereo circuitry (ADC, DAC,
Digital Filters, Digital interfaces).
The following two figures are block diagram of the Voice uplink and Voice downlink path.
3. Technical Brief
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3. Technical Brief
- 27 -
[Fig.4.7] Voice Uplink path Block Diagram
[Fig.4.8] Voice Downlink path Block Diagram
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3. Technical Brief
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3.3.3 Power Resources
There are 10 LDOs(Low Drop Output) regulators and 1 DC-DC converter in ABB chip. The output of
these 10 LDOs and 1 DC-DC converter is as following table.
[Fig.4.9] shows the power supply related blocks of DBB/ABB and their interfaces in CG180.
[Table 4.5] LDO Output Table
Output Voltage Usage
VREXTL 1.8V/2.8V, 1.3V/1.05V Digital Core of DBB
VREXTH 1.8V/2.8V Peripheral devices
VRMEM 1.8V External memory
VRMMC 1.8V/2.85V RF
VRABB 2.8V Analog Block of ABB
VRSIM 1.8V/2.85V SIM card driver
VRUSB 3.3V USB block
VRPLL 1.3V/1.4V/1.05V PLL
VRIO 1.8V I/O interface
VRWLED 20V White LED driver
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3. Technical Brief
- 29 -
[Fig.4.9] Power Supply Scheme
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3. Technical Brief
3.3.4 Power Management System
The power management T3031 (Triton_Lite) chip controls the power up, power down and power
transitions of other devices associated to a specific functionality.
At the first valid main battery insertion, the internal reset is released and the VRRTC power domain
rises up providing the supply to the 32 kHz oscillator. The T3031 chip is ready to accept global
hardware requests of power transitions, in this state the power bus is still in the slave mode and the
32kHz clock is not provided externally. The power bus is in the master mode when a global hardware
request of power state transition is detected. The T3031 chip actives the reference resources, next the
power resources and finally the ON_nOFF reset signal and the CLK_EN signal. Those signals active
the power resources for both T3031 and the external devices and enable the RF clock signal. The 32
kHz clock is now provided externally.
The power state change requests
1. The global hardware inputs HW :
- ON/OFF button press PWON, accessory insertion RPWON, charger insertion , detection of USB
- RTC ALARM event, RTC (internal signal)
2. The single hardware WAKEUP input
- WAKEUP1 is the digital base band processor request, the VRIO regulator supplying the I/Os has
to be enabled
- PCLKREQ is the peripheral request or WAKEUP2, the VRIO regulator supplying the I/Os has to be
enabled
3. The software inputs SW, the processor has to be supplied.
- these requests are sent to the T3031 chip through the I2C bus
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[Fig.4.10] Power management schematic
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3.3.5 Monitoring ADC
ABB ADC block is composed of 6 internal ADC(Analog to Digital Converter) chan nels and 3 external
ADC channel. This block operates charging process and other related process by reading battery
voltage and other analog values
3.3.6 Vibrator Motor Driver
A LDO based vibrator motor driver has been embedded to drive an external vibrator motor. The output
voltage of this regulator is programmable, based on a nominal 4-Hz cycle. The output voltage level,
which is controlled via register, can be 1.2V, 1.3V, 1.4V and 2.7V. The vibrator driver is capable to
provide up to 75 mA.
The duty-cycle of the nominal 4-Hz frequency is controlled via register and can be 25%, 50%, 75%
and 100%. This vibrator driver allows a soft turn-on (500s max) and turn-off (2ms max).
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3. Technical Brief
LGE Internal Use Only
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
[Table 4.6] ADC Channel Spec.
[Fig.4.11] Vibrator Motor Driver block scheme
Battery presence checkBATT_TEMPADIN5
LCD_ID checkLCD_IDADIN4
Temperature SensingTEMPSENSEADIN3
Thermal shut downHOTDIEHOTDIE
USB VBUS voltageUSBVBUSUSBVBUS
Backup BatteryVBACKUP
VBACKUP
ICTL
ICTL
VBAT
VBAT
Charging Management
VCHG
VCHG
DescriptionNameResource
ADC 9 channels
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