LG 43UF6400-S Schematic

Internal Use Only

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LED TV

SERVICE MANUAL

CHASSIS : LJ5ZR

MODEL : 43UF6400 43UF6400-S*

CAUTION

BEFORE SERVICING THE CHASSIS, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Printed in KoreaP/NO : MFL69323901 (1505-REV00)

CONTENTS

CONTENTS .............................................................................................. 2

PRODUCT SAFETY

SPECIFICATION

ADJUSTMENT INSTRUCTION

BLOCK DIAGRAM

EXPLODED VIEW

................................................................................. 3

....................................................................................... 6

.............................................................. 14

................................................................................. 25

.................................................................................. 27

SCHEMATIC CIRCUIT DIAGRAM

TROUBLESHOOTING

...............................................................APPENDIX

............................................APPENDIX

Only for training and service purposes

- 2 -

SAFETY PRECAUTIONS

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and Exploded View. It is essential that these special safety parts should be replaced with the same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

General Guidance

An isolation Transformer should always be used during the servicing of a receiver whose chassis is not isolated from the AC power line. Use a transformer of adequate power rating as this protects the technician from accidents resulting in personal injury from electrical shocks.

It will also protect the receiver and it's components from being damaged by accidental shorts of the circuitry that may be inadvertently introduced during the service operation.

If any fuse (or Fusible Resistor) in this TV receiver is blown, replace it with the specified.

When replacing a high wattage resistor (Oxide Metal Film Resistor, over 1 W), keep the resistor 10 mm away from PCB.

Keep wires away from high voltage or high temperature parts.

Before returning the receiver to the customer,

always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, etc., to be sure the set is safe to operate without damage of electrical shock.

Leakage Current Cold Check(Antenna Cold Check)

With the instrument AC plug removed from AC source, connect an electrical jumper across the two AC plug prongs. Place the AC switch in the on position, connect one lead of ohm-meter to the AC plug prongs tied together and touch other ohm-meter lead in turn to each exposed metallic parts such as antenna terminals, phone jacks, etc. If the exposed metallic part has a return path to the chassis, the measured resistance should be between 1 MΩ and 5.2 MΩ. When the exposed metal has no return path to the chassis the reading must be infinite. An other abnormality exists that must be corrected before the receiver is returned to the customer.

Leakage Current Hot Check (See below Figure)

Plug the AC cord directly into the AC outlet.

Do not use a line Isolation Transformer during this check. Connect 1.5 K / 10 watt resistor in parallel with a 0.15 uF capacitor between a known good earth ground (Water Pipe, Conduit, etc.) and the exposed metallic parts. Measure the AC voltage across the resistor using AC voltmeter with 1000 ohms/volt or more sensitivity. Reverse plug the AC cord into the AC outlet and repeat AC voltage measurements for each exposed metallic part. Any voltage measured must not exceed 0.75 volt RMS which is corresponds to

0.5 mA. In case any measurement is out of the limits specified, there is possibility of shock hazard and the set must be checked and repaired before it is returned to the customer.

Leakage Current Hot Check circuit

Only for training and service purposes

- 3 -

SERVICING PRECAUTIONS

CAUTION: Before servicing receivers covered by this service manual and its supplements and addenda, read and follow the

SAFETY PRECAUTIONS on page 3 of this publication. NOTE: If unforeseen circumstances create conict between the

following servicing precautions and any of the safety precautions on page 3 of this publication, always follow the safety precautions. Remember: Safety First.

General Servicing Precautions

1. Always unplug the receiver AC power cord from the AC power source before;

a. Removing or reinstalling any component, circuit board mod-

ule or any other receiver assembly.

b. Disconnecting or reconnecting any receiver electrical plug or

other electrical connection.

c. Connecting a test substitute in parallel with an electrolytic

capacitor in the receiver. CAUTION: A wrong part substitution or incorrect polarity installation of electrolytic capacitors may result in an explosion hazard.

2. Test high voltage only by measuring it with an appropriate high voltage meter or other voltage measuring device (DVM, FETVOM, etc) equipped with a suitable high voltage probe. Do not test high voltage by "drawing an arc".

3. Do not spray chemicals on or near this receiver or any of its assemblies.

4. Unless specied otherwise in this service manual, clean

electrical contacts only by applying the following mixture to the contacts with a pipe cleaner, cotton-tipped stick or comparable non-abrasive applicator; 10 % (by volume) Acetone and 90 % (by volume) isopropyl alcohol (90 % - 99 % strength)

CAUTION: This is a ammable mixture. Unless specied otherwise in this service manual, lubrication of

contacts in not required.

5. Do not defeat any plug/socket B+ voltage interlocks with which receivers covered by this service manual might be equipped.

6. Do not apply AC power to this instrument and/or any of its electrical assemblies unless all solid-state device heat sinks are correctly installed.

7. Always connect the test receiver ground lead to the receiver chassis ground before connecting the test receiver positive lead. Always remove the test receiver ground lead last.

8. Use with this receiver only the test xtures specied in this

service manual.

CAUTION: Do not connect the test xture ground strap to any

heat sink in this receiver.

Electrostatically Sensitive (ES) Devices

Some semiconductor (solid-state) devices can be damaged easily by static electricity. Such components commonly are called Electrostatically Sensitive (ES) Devices. Examples of typical ES

devices are integrated circuits and some eld-effect transistors

and semiconductor “chip” components. The following techniques should be used to help reduce the incidence of component damage caused by static by static electricity.

1. Immediately before handling any semiconductor component or semiconductor-equipped assembly, drain off any electrostatic charge on your body by touching a known earth ground. Alternatively, obtain and wear a commercially available discharging wrist strap device, which should be removed to prevent potential shock reasons prior to applying power to the unit under test.

2. After removing an electrical assembly equipped with ES devices, place the assembly on a conductive surface such as aluminum foil, to prevent electrostatic charge buildup or exposure of the assembly.

3. Use only a grounded-tip soldering iron to solder or unsolder ES devices.

4. Use only an anti-static type solder removal device. Some solder

removal devices not classied as “anti-static” can generate electrical charges sufcient to damage ES devices.

5. Do not use freon-propelled chemicals. These can generate

electrical charges sufcient to damage ES devices.

6. Do not remove a replacement ES device from its protective package until immediately before you are ready to install it. (Most replacement ES devices are packaged with leads electrically shorted together by conductive foam, aluminum foil or comparable conductive material).

7. Immediately before removing the protective material from the leads of a replacement ES device, touch the protective material to the chassis or circuit assembly into which the device will be installed. CAUTION: Be sure no power is applied to the chassis or circuit, and observe all other safety precautions.

8. Minimize bodily motions when handling unpackaged replacement ES devices. (Otherwise harmless motion such as the brushing together of your clothes fabric or the lifting of your

foot from a carpeted oor can generate static electricity sufcient to damage an ES device.)

General Soldering Guidelines

1. Use a grounded-tip, low-wattage soldering iron and appropriate tip size and shape that will maintain tip temperature within the range or 500 °F to 600 °F.

2. Use an appropriate gauge of RMA resin-core solder composed of 60 parts tin/40 parts lead.

3. Keep the soldering iron tip clean and well tinned.

4. Thoroughly clean the surfaces to be soldered. Use a mall wirebristle (0.5 inch, or 1.25 cm) brush with a metal handle. Do not use freon-propelled spray-on cleaners.

5. Use the following unsoldering technique

a. Allow the soldering iron tip to reach normal temperature.

(500 °F to 600 °F) b. Heat the component lead until the solder melts. c. Quickly draw the melted solder with an anti-static, suction-

type solder removal device or with solder braid.

CAUTION: Work quickly to avoid overheating the circuit

board printed foil.

6. Use the following soldering technique. a. Allow the soldering iron tip to reach a normal temperature

(500 °F to 600 °F)

b. First, hold the soldering iron tip and solder the strand against

the component lead until the solder melts.

c. Quickly move the soldering iron tip to the junction of the

component lead and the printed circuit foil, and hold it there only until the solder ows onto and around both the component lead and the foil. CAUTION: Work quickly to avoid overheating the circuit board printed foil.

d. Closely inspect the solder area and remove any excess or

splashed solder with a small wire-bristle brush.

Only for training and service purposes

- 4 -

IC Remove/Replacement

Some chassis circuit boards have slotted holes (oblong) through which the IC leads are inserted and then bent at against the circuit foil. When holes are the slotted type, the following technique should be used to remove and replace the IC. When working with boards using the familiar round hole, use the standard technique as outlined in paragraphs 5 and 6 above.

Removal

1. Desolder and straighten each IC lead in one operation by gently prying up on the lead with the soldering iron tip as the solder melts.

2. Draw away the melted solder with an anti-static suction-type solder removal device (or with solder braid) before removing the IC.

Replacement

1. Carefully insert the replacement IC in the circuit board.

2. Carefully bend each IC lead against the circuit foil pad and solder it.

3. Clean the soldered areas with a small wire-bristle brush. (It is not necessary to reapply acrylic coating to the areas).

"Small-Signal" Discrete Transistor Removal/Replacement

1. Remove the defective transistor by clipping its leads as close as possible to the component body.

2. Bend into a "U" shape the end of each of three leads remaining on the circuit board.

3. Bend into a "U" shape the replacement transistor leads.

4. Connect the replacement transistor leads to the corresponding leads extending from the circuit board and crimp the "U" with long nose pliers to insure metal to metal contact then solder each connection.

Power Output, Transistor Device Removal/Replacement

1. Heat and remove all solder from around the transistor leads.

2. Remove the heat sink mounting screw (if so equipped).

3. Carefully remove the transistor from the heat sink of the circuit board.

4. Insert new transistor in the circuit board.

5. Solder each transistor lead, and clip off excess lead.

6. Replace heat sink.

Diode Removal/Replacement

1. Remove defective diode by clipping its leads as close as possible to diode body.

2. Bend the two remaining leads perpendicular y to the circuit board.

3. Observing diode polarity, wrap each lead of the new diode around the corresponding lead on the circuit board.

4. Securely crimp each connection and solder it.

5. Inspect (on the circuit board copper side) the solder joints of the two "original" leads. If they are not shiny, reheat them and if necessary, apply additional solder.

3. Solder the connections. CAUTION: Maintain original spacing between the replaced component and adjacent components and the circuit board to prevent excessive component temperatures.

Circuit Board Foil Repair

Excessive heat applied to the copper foil of any printed circuit board will weaken the adhesive that bonds the foil to the circuit board causing the foil to separate from or "lift-off" the board. The following guidelines and procedures should be followed whenever this condition is encountered.

At IC Connections

To repair a defective copper pattern at IC connections use the following procedure to install a jumper wire on the copper pattern side of the circuit board. (Use this technique only on IC connections).

1. Carefully remove the damaged copper pattern with a sharp knife. (Remove only as much copper as absolutely necessary).

2. carefully scratch away the solder resist and acrylic coating (if used) from the end of the remaining copper pattern.

3. Bend a small "U" in one end of a small gauge jumper wire and carefully crimp it around the IC pin. Solder the IC connection.

4. Route the jumper wire along the path of the out-away copper pattern and let it overlap the previously scraped end of the good copper pattern. Solder the overlapped area and clip off any excess jumper wire.

At Other Connections

Use the following technique to repair the defective copper pattern at connections other than IC Pins. This technique involves the installation of a jumper wire on the component side of the circuit board.

1. Remove the defective copper pattern with a sharp knife. Remove at least 1/4 inch of copper, to ensure that a hazardous condition will not exist if the jumper wire opens.

2. Trace along the copper pattern from both sides of the pattern break and locate the nearest component that is directly connected to the affected copper pattern.

3. Connect insulated 20-gauge jumper wire from the lead of the nearest component on one side of the pattern break to the lead of the nearest component on the other side. Carefully crimp and solder the connections. CAUTION: Be sure the insulated jumper wire is dressed so the it does not touch components or sharp edges.

Fuse and Conventional Resistor Removal/Replacement

1. Clip each fuse or resistor lead at top of the circuit board hollow stake.

2. Securely crimp the leads of replacement component around notch at stake top.

Only for training and service purposes

- 5 -

SPECIFICATION

NOTE : Specifications and others are subject to change without notice for improvement

1. Application range

This spec sheet is applied to the LED TV used LJ5ZR chassis

2. Test condition

Each part is tested as below without special notice.

1) Temperature : 25 ºC ± 5 ºC(77±9ºF), CST : 40 ºC±5 ºC

2) Relative Humidity: 65 % ± 10 %

3) Power Voltage Standard input voltage (100~240V@ 50/60Hz) * Standard Voltage of each products is marked by models.

4) Specification and performance of each parts are followed

each drawing and specification by part number in accordance with BOM.

5) The receiver must be operated for about 20 minutes prior to

the adjustment.

3. Test method

1) Performance: LGE TV test method followed

2) Demanded other specification

- Safety : CE, IEC specification

- EMC: CE, IEC

.

4. Model Specification

No Item Specication Remark

1. Market Central and South AMERICA

2. Broadcasting system Digital : SBTVD /

3. Available Channel BAND NTSC

4. Receiving system Digital : SBTVD /

5. Input Voltage AC 100 - 240V 50/60Hz

Analog : NTSC / PAL-M / PAL-N

VHF UHF DTV

CATV

Analog : NTSC / PAL-M / PAL-N

2 ~ 13

14 ~ 69

2 ~ 69

1 ~ 135

Only for training and service purposes

- 6 -

5. External input format

5.1. CVBS input

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed Remarks

1. 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I) NTSC-M

2. 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I) NTSC-M

3. 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz PAL-BDGHI

5.2. Component input(Y, CB/PB, CR/PR)

No Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed

1. 720*480i 15.73 59.94 13.50 SDTV, DVD 480I(525I)

2. 720*480i 15.73 60.00 13.51 SDTV, DVD 480I(525I)

3. 720*576i 15.63 50.00 13.50 SDTV, DVD 576I(625I) 50Hz

4. 720*480p 31.47 59.94 27.00 SDTV 480P

5. 720*480p 31.50 60.00 27.03 SDTV 480P

6. 720*576p 31.25 50.00 27.00 SDTV 576P 50Hz

7. 1280*720 44.96 59.94 74.18 HDTV 720P

8. 1280*720 45.00 60.00 74.25 HDTV 720P

9. 1280*720 45.00 50.00 74.25 HDTV 720P 50Hz

10. 1920*1080 28.13 50.00 74.25 HDTV 1080I 50Hz,

11. 1920*1080 33.72 59.94 74.18 HDTV 1080I

12. 1920*1080 33.75 60.00 74.25 HDTV 1080I

13. 1920*1080 56.25 50.00 148.50 HDTV 1080P

14. 1920*1080 67.50 60.00 148.50 HDTV 1080P

Only for training and service purposes

- 7 -

5.3. HDMI Input (DTV)

No Resolution H-freq(kHz) V-freq.(Hz)

1 640*480 31.46 59.94 25.13 SDTV 480P

2 640*480 31.50 60.00 25.13 SDTV 480P

3 720*480 15.73 59.94 13.50 SDTV, DVD 480I(525I) Spec. out but display

4 720*480 15.75 60.00 13.51 SDTV, DVD 480I(525I)

5 720*576 15.62 50.00 13.50 SDTV, DVD 576I(625I) 50Hz

6 720*480 31.47 59.94 27.00 SDTV 480P

7 720*480 31.50 60.00 27.03 SDTV 480P

8 720*576 31.25 50.00 27.00 SDTV 576P

9 1280*720 44.96 59.94 74.18 HDTV 720P

10 1280*720 45.00 60.00 74.25 HDTV 720P

11 1280*720 37.50 50.00 74.25 HDTV 720P

12 1920*1080 28.12 50.00 74.25 HDTV 1080I

13 1920*1080 33.72 59.94 74.18 HDTV 1080I

14 1920*1080 33.75 60.00 74.25 HDTV 1080I

15 1920*1080 26.97 23.97 63.30 HDTV 1080P

16 1920*1080 27.00 24.00 63.36 HDTV 1080P

17 1920*1080 33.71 29.97 79.12 HDTV 1080P

18 1920*1080 33.75 30.00 79.20 HDTV 1080P

19 1920*1080 56.25 50.00 148.50 HDTV 1080P

20 1920*1080 67.43 59.94 148.35 HDTV 1080P

21 1920*1080 67.50 60.00 148.50 HDTV 1080P

22 3840*2160 53.95 23.98 297.00 UDTV 2160P UHD only

23 3840*2160 54.00 24.00 297.00 UDTV 2160P UHD only

24 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only

25 3840*2160 61.43 29.97 297.00 UDTV 2160P UHD only

26 3840*2160 67.50 30.00 297.00 UDTV 2160P UHD only

27 3840*2160 112.50 50.00 594.00 UDTV 2160P(DVB) UHDonly(Port1,2)-LM15U Only

28 3840*2160 135.00 59.94 593.41 UDTV 2160P UHDonly(Port1,2)-LM15U Only

29 3840*2160 135.00 60.00 594.00 UDTV 2160P UHDonly(Port1,2)-LM15U Only

30 4096*2160 53.95 23.98 297.00 UDTV 2160P UHD only

31 4096*2160 54.00 24.00 297.00 UDTV 2160P UHD only

32 4096*2160 56.25 25.00 297.00 UDTV 2160P UHD only

33 4096*2160 61.43 29.97 297.00 UDTV 2160P UHD only

34 4096*2160 67.50 30.00 297.00 UDTV 2160P UHD only

35 4096*2160 112.50 50.00 594.00 UDTV 2160P(DVB) UHDonly(Port1,2)-LM15U Only

36 4096*2160 135.00 59.94 593.41 UDTV 2160P UHDonly(Port1,2)-LM15U Only

37 4096*2160 135.00 60.00 594.00 UDTV 2160P UHDonly(Port1,2)-LM15U Only

Pixel

clock(MHz)

Proposed Remark

Only for training and service purposes

- 8 -

5.4. HDMI Input (PC)

No. Resolution H-freq(kHz) V-freq.(kHz) Pixel clock Proposed Remarks

1 640*350 31.46 70.09 25.17 EGA

2 720*400 31.46 70.08 28.32 DOS

3 640*480 31.46 59.94 25.17 VESA(VGA)

4 800*600 37.87 60.31 40.00 VESA(SVGA)

5 1024*768 48.36 60.00 65.00 VESA(XGA)

6 1152*864 54.34 60.05 80.00 VESA

7 1280*1024 63.98 60.02 109.00 VESA(SXGA) FHD only

8 1360*768 47.71 60.01 85.00 VESA(WXGA)

9 1920*1080 67.50 60.00 158.40 WUXGA(CEA 861D) FHD only

10 3840*2160 67.50 30.00 297.00 UDTV 2160P UHD only

11 3840*2160 56.25 25.00 297.00 UDTV 2160P UHD only

12 3840*2160 54.00 24.00 297.00 UDTV 2160P UHD only

13 4096*2160 53.95 23.97 296.703 UDTV 2160P UHD only

14 4096*2160 54.00 24.00 297.00 UDTV 2160P UHD only

Only for training and service purposes

- 9 -

6. 3D mode(3D MODEL Only)

6.1. RF Input

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode

1 1280*720 37.50 50 74.25 HDTV 720P 2D to 3D, Side by Side, Top & Bottom

2 1920*1080 28.13 50 74.25 HDTV 1080I 2D to 3D, Side by Side, Top & Bottom

6.2. HDMI Input (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock

(MHz)

1 640*480 31.46 / 31.50 59.94/ 60.00 25.13/25.20 1 Top-and-Bottom

31.46 / 31.50 59.94/ 60.00 50.35/50.40 1 Side-by-side(Full) (SDTV 480P)

62.93 / 63.00 59.94/ 60.00 50.35/50.40 1 Frame packing

2 720*480 31.46 / 31.50 59.94 / 60.00 27.00/27.03 2,3 Top-and-Bottom

31.46 / 31.50 59.94 / 60.00 27.00/27.03 2,3 Side-by-side(Full) (SDTV 480P)

62.93 /63.00 59.94 / 60.00 54.00/54.06 2,3 Frame packing

3 720*576 15.62 50.00 27.00 21 Top-and-Bottom

4 720*576 31.25 50.00 27.00 17,18 Top-and-Bottom

62.50 50.00 54.00 17,18 Frame packing

5 1280*720 37.50 50.00 74.25 19 Top-and-Bottom

37.50 50.00 148.50 19 Side-by-side(Full) (HDTV 720P)

44.96 / 45.00 59.94 / 60.00 74.17/74.25 4 Top-and-Bottom

44.96 / 45.00 59.94 / 60.00 148.35/148.50 4 Side-by-side(Full) (HDTV 720P)

75.00 50.00 148.50 19 Frame packing

89.91/90.00 59.94 / 60.00 148.35/148.50 4 Frame packing

6 1920*1080 28.12 50.00 74.25 20 Top-and-Bottom

28.12 50.00 148.50 20 Side-by-side(Full) (HDTV 1080I)

33.72 / 33.75 59.94 / 60.00 74.17/74.25 5 Top-and-Bottom

33.72 / 33.75 59.94 / 60.00 148.35/148.50 5 Side-by-side(Full) (HDTV 1080I)

56.25 50.00 148.50 20 Frame packing

67.43/67.50 59.94 / 60.00 148.35/148.50 5 Frame packing

VIC 3D input proposed

mode

Side-by-side(half)

Line alternative

Side-by-side(half)

Line alternative

Side-by-side(half) Side-by-side(Full) Frame packing Field alternative

Side-by-side(half) Side-by-side(Full)

Line alternative

Side-by-side(half)

Line alternative

Side-by-side(half)

Field alternative

Proposed

Secondary(SDTV 480P) Secondary(SDTV 480P)

Secondary(SDTV 480P) (SDTV 480P)

Secondary(SDTV 480P) Secondary(SDTV 480P)

Secondary(SDTV 480P) (SDTV 480P)

(SDTV 576I) Secondary(SDTV 576I) (SDTV 576I) Secondary(SDTV 576I) Secondary(SDTV 576I)

Secondary(SDTV 576P) Secondary(SDTV 576P) (SDTV 576P)

Secondary(SDTV 576P) (SDTV 576P)

Primary(HDTV 720P) Primary(HDTV 720P)

Primary(HDTV 720P) (HDTV 720P)

Secondary(HDTV 1080I) Primary(HDTV 1080I)

Primary(HDTV 1080I) (HDTV 1080I)

Only for training and service purposes

- 10 -

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock

(MHz)

7 1920*1080 26.97 / 27.00 23.97 / 24.00 74.17 / 74.25 32 Top-and-Bottom

26.97 / 27.00 23.97 / 24.00 148.35 /

148.50

28.12 25.00 74.25 33 Top-and-Bottom

28.12 25.00 148.50 33 Side-by-side(Full) (HDTV 1080P)

33.72 / 33.75 29.98 / 30.00 74.18/74.25 34 Top-and-Bottom

33.72 / 33.75 29.98 / 30.00 148.35/148.50 34 Side-by-side(Full) (HDTV 1080P)

43.94/54.00 23.97 / 24.00 148.35/148.50 32 Frame packing

56.25 25.00 148.50 33 Frame packing

67.43 / 67.5 29.98 / 30.00 148.35/148.50 34 Frame packing

56.25 50.00 148.50 31 Top-and-Bottom

67.43 / 67.50 59.94 / 60.00 148.35/148.50 16 Top-and-Bottom

VIC 3D input proposed

Side-by-side(half)

32 Side-by-side(Full) (HDTV 1080P)

Side-by-side(half)

Line alternative

Side-by-side(half)

6.3. Component Input ( 3D) (3D supported mode manually)

mode

Proposed

Primary(HDTV 1080P) Primary(HDTV 1080P)

Secondary(HDTV 1080P) Secondary(HDTV 1080P)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

Primary(HDTV 1080P) (HDTV 1080P)

Secondary(HDTV 1080P) (HDTV 1080P)

Primary(HDTV 1080P) (HDTV 1080P)

Primary(HDTV 1080P) Secondary(HDTV 1080P)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode Proposed

1 1280*720 37.50 50.00 74.25 2D to 3D,

HDTV 720P

Side by Side(half), Top & Bottom

2 1280*720 45.00 60.00 74.25 2D to 3D,

HDTV 720P

Side by Side(half), Top & Bottom

3 1280*720 44.96 59.94 74.18 2D to 3D,

HDTV 720P

Side by Side(half), Top & Bottom

4 1920*1080 33.75 60.00 74.25 2D to 3D,

HDTV 1080I

Side by Side(half), Top & Bottom

5 1920*1080 33.72 59.94 74.18 2D to 3D,

HDTV 1080I

Side by Side(half), Top & Bottom

6 1920*1080 28.12 50.00 74.25 2D to 3D,

HDTV 1080I

Side by Side(half), Top & Bottom

7 1920*1080 67.50 60.00 148.50 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

8 1920*1080 67.43 59.94 148.35 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

9 1920*1080 27.00 24.00 74.25 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

10 1920*1080 28.12 25.00 74.25 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

11 1920*1080 56.25 50.00 74.25 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

12 1920*1080 26.97 23.98 74.18 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

13 1920*1080 33.75 30.00 74.25 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

14 1920*1080 33.71 29.97 74.18 2D to 3D,

HDTV 1080P

Side by Side(half), Top & Bottom

Only for training and service purposes

- 11 -

6.4. HDMI-PC Input (3D) (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel

1 1024*768 48.36 60.00 65.00 HDTV 768P 2D to 3D,

2 1360*768 47.71 60.00 HDTV 768P

3 1920*1080 67.50 60.00 148.50 HDTV 1080P 2D to 3D,

4 3840*2160

(Ultea HD model only)

5 4096*2160

(Ultea HD model only)

6 Others - - - 640*350

54.00 24.00 296.70 HDTV 2160P 2D to 3D,

56.25 25.00 297.00

67.50 30.00 296.70

54 24.00 297.00 HDTV 2160P

clock(MHz)

Proposed Proposed

Side by Side(half),

Top & Bottom

Side by Side(half),

Top & Bottom,

Checker Board,

Frame Sequential,

Row Interleaving,

Column Interleaving

Top & Bottom(half)

Side by Side(half)

720*400 640*480 800*600 1152*864

Side by Side(half),

Top & Bottom

2D to 3D,

6.5. HDMI-DTV (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) Proposed 3D input proposed mode

1 720*480 31.50 60.00 27.03 SDTV 480P 2D to 3D, Side by Side(Half), Top & Bottom,

2 720*576 31.25 50.00 27.00 SDTV 576P

3 1280*720 45.00 60.00 74.25 HDTV 720P

37.50 50.00 74.25 HDTV 720P

4 1920*1080 33.75 60.00 74.25 HDTV 1080I 2D to 3D, Side by Side(Half), Top & Bottom

28.13 50.00 74.25 HDTV 1080I

5 1920*1080 27.00 24.00 74.25 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,

28.12 25.00 74.25 HDTV 1080P

33.75 30.00 74.25 HDTV 1080P

67.50 60.00 148.50 HDTV 1080P 2D to 3D, Side by Side(Half), Top & Bottom,

56.25 50.00 148.50 HDTV 1080P

6 3840*2160

4096*2160

53.95 23.98 297.00 HDTV 2160P 2D to 3D,

54.00 24.00 296.70

56.25 25.00 297.00

61.43 29.97 297.00

67.50 30.00 296.70

112.50 50.00 594.00 HDTV 2160P 2D to 3D,

135.00 60.00 594.00

Checker Board, Frame Sequential, Row Interleaving, Column Interleaving

Checker Board, Row Interleaving, Column Interleaving

Checker Board, Single Frame Sequential, Row Interleaving, Column Interleaving

Top & Bottom(half), Side by Side(half),

Top & Bottom(half), Side by Side(half) (8 bit, YCbCr 4:2:0)

Only for training and service purposes

- 12 -

6.6. USB – Movie (3D) (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 Under 704x480 - - - 2D to 3D

2 Over 704x480

Under 1080P

interlaced

3 Over 704x480

Under 1080P

progressive

4 - others - 2D to 3D, Side by Side(Half), Top & Bottom,

5 Over 2160P - 24/25/30 - 2D to 3D, Side by Side(Half), Top & Bottom

- - - 2D to 3D, Side by Side(Half), Top & Bottom

- 50 / 60 - 2D to 3D, Side by Side(Half), Top & Bottom, Checker Board, Row Interleaving, Column Interleaving, Frame Sequential

Checker Board, Row Interleaving, Column Interleaving

6.7. Miracast Intel WIDI (3D supported mode manually)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1024*768p - 30/60 - 2D to 3D, Side by Side(Half), Top & Bottom

2 1280*720p - 30/60 -

3 1920*1080p - 30/60 -

4 Others - - - 2D to 3D

6.8. USB, DLNA (3D) (3D supported mode automatically)

No Resolution H-freq(kHz) V-freq.(Hz) Pixel clock(MHz) 3D input proposed mode

1 1080p 33.75 30.00 74.25 Side by Side(Half), Top & Bottom, Checker Board,

2 2160p 67.50 30.00 297.00

MPO(Photo), JPS(Photo)

**Remark: 3D Input mode

No. Side by Side Top & Bottom Checker-

board

1

Single Frame

Sequential

Frame Pack-

ing

Line

Interleaving

Column

Interleaving

2D to 3D

Only for training and service purposes

- 13 -

ADJUSTMENT INSTRUCTION

1. Application Range

This spec. sheet applies to LJ5ZR Chassis applied TV all models manufactured in TV factory

2. Specification.

1) Because this is not a hot chassis, it is not necessary to use an isolation transformer. However, the use of isolation transformer will help protect test instrument

2) Adjustment must be done in the correct order.

3) The adjustment must be performed in the circumstance of 25 ±5ºC of temperature and 65±10% of relative humidity if there is no specific designation

4) The input voltage of the receiver must keep 100~240V, 50/60Hz

5) The receiver must be operated for about 5 minutes prior to the adjustment when module is in the circumstance of over 15ºC

▪ In case of keeping module is in the circumstance of 0°C, it

should be placed in the circumstance of above 15°C for 2 hours

▪ In case of keeping module is in the circumstance of below

-20°C, it should be placed in the circumstance of above 15°C for 3 hours

* Caution) When still image is displayed for a period of 20

minutes or longer (especially where W/B scale is strong. Digital pattern 13ch and/or Cross hatch pattern 09ch), there can some afterimage in the black level area.

4. Automatic Adjustment

4.1. ADC Adjustment

1) Enter the ADC Calibration in ADJ Menu

2) Check the ‘Internal’ at ADC Type and push Start button.

3) Check ‘ OK ‘

4.1.1. Equipment & Condition

1) USB to RS-232C Jig

2) MSPG-925 Series Pattern Generator(MSPG-925FA, pattern

-65)

- Resolution : 480i Comp1 1080P Comp1

- Pattern : Horizontal 100% Color Bar Pattern

- Pattern level : 0.7±0.1 Vp-p

- Image

3. Adjustment items

3.1. Main PCB check process

▪ MAC Address Download ▪ ADC adjustment : 480i Comp1, 1920*1080 Comp1 ▪ EDID/DDC download

Above adjustment items can be also performed in Final Assembly if needed. Both Board-level and Final assembly adjustment items can be check using In-Start Menu 1.ADJUST CHECK.

3.2. Final assembly adjustment

▪ White Balance adjustment ▪ RS-232C functionality check ▪ PING Test ▪ Factory Option setting per destination ▪ Ship-out mode setting (In-Stop)

3.3. Etc.

▪ Ship-out mode ▪ Service Option Default ▪ USB Download(S/W Update, Option, Service only) ▪ ISP Download (Option)

4.1.2. Adjustment method

Protocol Command Set ACK

Enter adj. mode aa 00 00 a 00 OK00x

Source change xb 00 04

xb 00 06

Begin adj. ad 00 10

Return adj. result OKx (Case of Success)

Read adj. data (main)

ad 00 20

(sub ) ad 00 21

Conrm adj. ad 00 99 NG 03 00x (Fail)

End adj. ad 00 90 a 00 OK90x

Ref.) ADC Adj. RS232C Protocol_Ver1.0

Adj. order

▪ aa 00 00 [Enter ADC adj. mode] ▪ xb 00 04 [Change input source to Component1(480i&1080p)] ▪ ad 00 10 [Adjust 480i&1080p Comp1] ▪ xb 00 06 [Change input source to RGB(1024*768)] ▪ ad 00 10 [Adjust 1920*1080 RGB] ▪ aa 00 90 End adj.

b 00 OK04x (Adjust 480i, 1080p Comp1 ) b 00 OK06x (Adjust 1920*1080 RGB)

NGx (Case of Fail)

(main) 000000000000000000000000007c007b006dx

(Sub) 000000070000000000000000007c0083 0077x

NG 03 01x (Fail) NG 03 02x (Fail) OK 03 03x (Success)

Only for training and service purposes

- 14 -

4.2. MAC address, ESN, Widevine, HDCP2.0 key D/L

4.2.1. Equipment & Condition

1) Play file: keydownload.exe

4.2.2. Communication Port connection

1) Key Write: Com 1,2,3,4 and 115200 (Baudrate)

2) Barcode: Com 1,2,3,4 and 9600 (Baudrate)

4.2.3. Download process

1) Select the download items.

2) Mode check: Online Only

3) Check the test process : DETECT -> MAC -> Widevine

4) Play: START

5) Check of result: Ready, Test, OK or NG

4.2.4. Communication Port connection

1) Connect: PCBA Jig -> RS-232C Port == PC -> RS-232C Port

4.3. LAN Inspection

4.3.1. Equipment & Condition

▪ Each other connection to LAN Port of IP Hub and Jig

4.3.2. LAN inspection solution

▪ LAN Port connection with PCB ▪ Network setting at MENU Mode of TV ▪ Setting automatic IP ▪ Setting state confirmation

- If automatic setting is finished, you confirm IP and MAC Address.

4.2.5. Download

1) TW/CO Models (15Y LCD TV + MAC + Widevine + ESN + HDCP2.0)

4.3.3. LAN PORT INSPECTION (PING TEST)

1) Play the LAN Port Test PROGRAM.

2) Input IP set up for an inspection to Test Program. *IP Number : 12.12.2.2.

4.3.4. LAN PORT inspection (PING TEST)

1) Play the LAN Port Test Program.

2) connect each other LAN Port Jack.

3) Play Test (F9) button and confirm OK Message.

4) remove LAN CABLE

Only for training and service purposes

- 15 -

4.4. Model name & Serial number Download

4.4.1. Model name & Serial number D/L

▪ Press “Power on” key of service remocon.(Baud rate :

115200 bps)

▪ Connect RS-232C Signal to USB Cable to USB. ▪ Write Serial number by use USB port. ▪ Must check the serial number at Instart menu.

■ Method & Notice

A. Serial number D/L is using of scan equipment. B. Setting of scan equipment operated by Manufacturing

Technology Group.

C. Serial number D/L must be conformed when it is produced

in production line, because serial number D/L is mandatory by D-book 4.0

* Manual Download (Model Name and Serial Number)

If the TV set is downloaded By OTA or Service man, sometimes model name or serial number is initialized. ( not always) It is impossible to download by bar code scan, so It need Manual download.

a. Press the ‘INSTART’ key of ADJ remote controller. b. Go to the menu ‘7. Model Number D/L’ like below photo. c. Input the Factory model name or Serial number like below

photo.

5. Manual Adjustment

5.1. ADC adjustment is not needed because of OTP (Auto ADC adjustment)

5.2. EDID

(The Extended Display Identification Data) / DDC (Display Data Channel) download

5.2.1. Overview

It is a VESA regulation. A PC or a MNT will display an optimal resolution through information sharing without any necessity of user input. It is a realization of “Plug and Play”.

5.2.2. Equipment

▪ Since embedded EDID data is used, EDID download JIG,

HDMI cable and D-sub cable are not need.

▪ Adjust remocon

5.2.3. Download method

1) Press Adj. key on the Adjust remocon, then select “12.EDID D/L”.

By pressing Enter key, enter EDID D/L menu

d. Check the model name INSTART menu -> Factory name

displayed

e. Check the Diagnostics (DTV country only) -> Buyer model

displayed

4.5. WIFI MAC ADDRESS CHECK

4.5.1. Using RS232 Command

Command Set ACK

Transmission [A][l][][Set ID][][20][Cr] [O][K][x] or [N][G]

■ Check the menu on in-start

Only for training and service purposes

- 16 -

2) Select [Start] button by pressing Enter key, HDMI1 / HDMI2

/ HDMI3 / HDMI4 are Writing and display OK or NG.

5.2.4. EDID DATA

▪ Reference

- HDMI1 ~ HDMI3

- HDMI1 ~ HDMI4

- In the data of EDID, bellows may be different by Input mode

# HDMI 1(C/S : A0 9E) – 6G

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

ⓐ Product ID ⓑ Serial No: Controlled on production line. ⓒ Month, Year: Controlled on production line:

ex) Monthly : ‘01’ -> ‘01’ Year : ‘2015’ -> ‘19

ⓓ Model Name(Hex): LGTV ⓔ Checksum(LG TV): Changeable by total EDID data. ⓕ Vendor Specific(HDMI)

5.2.4.1. EDID for 3D Model olny # HDMI 1(C/S : E6 F4) – 3G

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

# HDMI 2(C/S : E6 E4) -3G

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

Only for training and service purposes

- 17 -

# HDMI 2(C/S : A0 8E) – 6G

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

# HDMI 3(C/S : E6 D4 ) -3G/6G

EDID Block 0, Bytes 0-127 [00H-7FH]

5.2.4.2. EDID for Non 3D Model # HDMI 1(C/S : E6 1D) – 3G

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

# HDMI 1(C/S : A0 C7) – 6G

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

* Checksum(HDMI 1/2/3)

Input FFh (Checksum)

3G

HDMI1 E6 F4 A0 9E

HDMI2 E6 E4 A0 8E

HDMI3 E6 D4 E6 D4

FFh (Checksum)

6G(HDMI Deep Color)

EDID Block 1, Bytes 128-255 [80H-FFH]

# HDMI 2(C/S : E6 0D) -3G/6G

EDID Block 0, Bytes 0-127 [00H-7FH]

Only for training and service purposes

- 18 -

EDID Block 1, Bytes 128-255 [80H-FFH]

# HDMI 3(C/S : E6 FD) -3G/6G

EDID Block 0, Bytes 0-127 [00H-7FH]

EDID Block 1, Bytes 128-255 [80H-FFH]

5.3. Green Eye Inspection Guide

Step 1. Turn on the TV set. Step 2. Press “EYE” button on the Adjustment remote controller.

Step 3. Block the Intelligent Sensor module on the front C/A about

6 seconds. When the “Sensor Data” is lower than 20, you can see the “OK” message

=> If it doesn’t show “OK” message, the Sensor Module is

defected one. You have to replace that with a good one.

* Checksum(HDMI 1/2/3)

Input FFh (Checksum)

3G

HDMI1 E6 1D A0 C7

HDMI2 E6 0D E6 0D

HDMI3 E6 FD E6 FD

FFh (Checksum)

6G(HDMI Deep Color)

Step 4. After check the “OK” message come out, take out your hand from the Sensor module. => Check “Backlight” value change from “0” to “100” or

not. If it doesn’t change the value, the sensor is also defected one. You have to replace it.

Only for training and service purposes

- 19 -

5.4. Camera Function Inspection (TBD)

1) Objective : To check how it connects between Camera and PCBA normally, and their Function

2) Test Method : This Inspection is available only Power-Only Status.

i) Push Camera Up ii) Camera’s Preview picture appears on TV Set iii) Push Camera Down

3) RS-232C Command

RS-232C COMMAND

CMD DATA ID

Ai 00 23 Camera Function Start.

Ai 00 24 Camera Function End.

Explanation

5.5. V-COM Adjust

(*) ONLY FOR GP2 2010year model. GP3 LW Series

[2011year] spec out !

5.6. Adjustment White balance

5.6.1. Overview

▪ W/B adj. Objective & How-it-works

1) Objective: To reduce each Panel’s W/B deviation

2) How-it-works: When R/G/B gain in the OSD is at 192, it means the panel is at its Full Dynamic Range. In order to prevent saturation of Full Dynamic range and data, one of R/G/B is fixed at 192, and the other two is lowered to find the desired value.

[ Test condition ]

Temperature : 20 ± 5ºC Heat run mode : Vivid Measurement mode : Adjust > White Balance mode Measurement Point : center Measurement Device : CA-210 / CA-310 Heat run time : continue 24 hours(for new-born module) 2 hours(for module UTT is over 24 hrs)

[ Spec]

- Color coordinate x, y ± 0.015 (after 24 hours aging)

- Color coordinate x ± 0.020, y ± 0.030 (within 24 hours aging)

5.6.2. Equipment

1) Color Analyzer: CA-210 (LED Module : CH 14)

2) Adj. Computer (During auto adj., RS-232C protocol is needed)

3) Adjust Remocon

4) Video Signal Generator MSPG-925F 720p/216-Gray (Model:217, Pattern:78)

-> Only when internal pattern is not available

※ Color Analyzer Matrix should be calibrated using CS-1000

5.6.3. Equipment connection MAP

5.6.4. Adj. Command (Protocol)

<Command Format> START 6E A 50 A LEN A 03 A CMD A 00 A VAL A CS A STOP

- LEN: Number of Data Byte to be sent

- CMD : Command

- VAL : FOS Data value

- CS : Checksum of sent data

- A : Acknowledge

Ex) [Send: JA_00_DD] / [Ack: A_00_okDDX]

1) RS-232C Command used during auto-adj.

RS-232C COMMAND

CMD DATA ID

wb 00 00 Begin White Balance adj.

wb 00 10 Gain adj.(internal white pattern)

wb 00 1f Gain adj. completed

wb 00 20 Offset adj.(internal white pattern)

wb 00 2f Offset adj. completed

wb 00 ff End White Balance adj.

(internal pattern disappears )

Ex) wb 00 00 -> Begin white balance auto-adj. wb 00 10 -> Gain adj. ja 00 ff -> Adj. data jb 00 c0 ... ... wb 00 1f -> Gain adj. complete *(wb 00 20(start), wb 00 2f(endc)) -> Off-set adj. wb 00 ff -> End white balance auto adj.

2) Adjustment Map (Applied Model : LJ5ZR Chassis ALL MODELS)

Adj. item Command

(lower caseASCII)

CMD1 CMD2 MIN MAX

Cool R Gain j g 00 C0

G Gain j h 00 C0

B Gain j i 00 C0

Medium R Gain j a 00 C0

G Gain j b 00 C0

B Gain j c 00 C0

Warm R Gain j d 00 C0

G Gain j e 00 C0

B Gain j f 00 C0

Explanation

Data Range (Hex.)

Only for training and service purposes

- 20 -

5.6.5. Adjustment method

5.6.5.1. Auto WB calibration

1) Set TV in adj. mode using POWER ONNY key

2) Zero calibrate probe then place it on the center of the Display

3) Connect Cable (RS-232C to USB)

4) Select mode in adj. Program and begin adj.

5) When adj. is complete (OK Sign), check adj. status pre mode(Warm, Medium, Cool)

(6) Remove probe and RS-232C to USB cable to complete adj.

▪ W/B Adj. must begin as start command “wb 00 00” , and

finish as end command “wb 00 ff”, and Adj. offset if need

5.6.6. Reference (White Balance Adj. coordinate and color temperature)

▪ Luminance: 206 Gray ▪ Standard color coordinate and temperature using CS-1000

(over 26 inch)

Mode

Cool 0.271 0.270 13000K 0.0000

Medium 0.286 0.289 9300K 0.0000

Warm 0.313 0.329 6500K 0.0000

Coordinate

X Y

Temp △uv

5.6.5.2. Manual adj. method

1) Set TV in Adj. mode using POWER ON

2) Zero Calibrate the probe of Color Analyzer, then place it on the center of LCD module within 10cm of the surface..

3) Press ADJ key -> EZ adjust using adj. R/C -> 7. White-

Balance then press the cursor to the right (KEY►).

(When KEY(►) is pressed 216 Gray internal pattern will be

displayed)

4) One of R Gain / G Gain / B Gain should be fixed at 192, and the rest will be lowered to meet the desired value.

5) Adj. is performed in COOL, MEDIUM, WARM 3 modes of color temperature.

** G-fix adjustment Adjust modes (Cool), Fix the G gain to 172 (default data) and change the others (G/B Gain). Adjust two modes(Medium / Warm), Fix the one of R/G/B gain to 192 (default data) and decrease the others.

▪ If internal pattern is not available, use RF input. In EZ Adj.

menu 7.White Balance, you can select one of 2 Test-pattern: ON, OFF. Default is inner(ON). By selecting OFF, you can adjust using RF signal in 216 Gray pattern.

▪ Adj. condition and cautionary items

1) Lighting condition in surrounding area

Surrounding lighting should be lower 10 lux. Try to isolate

adj. area into dark surrounding.

2) Probe location

- PDP : Color Analyzer (CA-100, CA-100+, CA210) probe

should be firmly attached to the Module

- LCD : Color Analyzer (CA-210) probe should be within 10cm

and perpendicular of the module surface (90+/-2.5°)

3) Aging time

- After Aging Start, Keep the Power ON status during 5

Minutes.

- In case of LCD, Back-light on should be checked using no

signal or Full-white pattern.

▪ Standard color coordinate and temperature using CA-210

(CH 14)

Mode

Cool 0.271±0.002 0.270±0.002 13000K 0.0000

Medium 0.286±0.002 0.289±0.002 9300K 0.0000

Warm 0.313±0.002 0.329±0.002 6500K 0.0000

Coordinate

X Y

Temp △uv

(Normal line) Edge & ALEF LED White balance table

-gumi & Global Model : (normal line) - UF85,UF77,UF69, UF68, UF64

webOS

Aging time

(Min)

1 0-2 282 289 297 308 324 348

2 3-5 281 287 296 306 323 346

3 6-9 279 284 294 303 321 343

4 10-19 277 280 292 299 319 339

5 20-35 275 277 290 296 317 336

6 36-49 274 274 289 293 316 333

7 50-79 273 272 288 291 315 331

8 80-119 272 271 287 290 314 330

9 Over 120 271 270 286 289 313 329

Cool Medium Warm

X Y X Y X Y

271 270 286 289 313 329

Only for training and service purposes

- 21 -

(*) AUO, INX, Sharp, CSOT, BOE(Cool 1300K)

Cool Medium Warm

webOS

Target 278 280 293 299 320 339

Model : 79UF95, UG87 only(LJ53V)

webOS

1 0-2 285 296 300 315 327 355

2 3-5 284 294 299 313 326 353

3 6-9 283 293 298 312 325 352

4 10-19 283 292 298 311 325 351

5 20-35 281 288 296 307 323 347

6 36-49 279 286 294 305 321 345

7 50-79 278 284 293 303 320 343

8 80-119 277 282 292 301 319 341

9 Over 120 271 270 286 289 313 329

*) AUO, INX, Sharp, CSOT, BOE(Cool 1300K)

webOS

Target 278 280 293 299 320 339

x y x y x y

271 270 285 293 313 329

Aging time

(Min)

Cool Medium Warm

x y x y x y

271 270 285 293 313 329

Cool Medium Warm

X Y X Y X Y

271 270 286 289 313 329

5.8. Magic Motion Remocon test

5.8.1. Automatically Test Using Golden remocon(for line inspection)

1) Place the Golden remocon in the line inspection step.

2) check instart menu “ Wi-Fi/Magic Search : OK/OK “

5.8.2. Manually test

- Equipment : RF Remocon for test, IR-KEY-Code Remocon for test

- You must confirm the battery power of RF-Remocon before test

(recommend that change the battery per every lot)

- Sequence (test)

a) if you select the ‘start key(OK)’ on the controller, you can

pairing with the TV SET.

b) You can check the cursor on the TV Screen, when select

the ‘OK Key’ on the controller

c) You must remove the pairing with the TV Set by select

‘Mute + OK Key’ on the controller

5.9. 3D function test (3D model Olny)

(Pattern Generator MSHG-600, MSPG-6100 [SUPPORT HDMI1.4])

* HDMI mode NO. 872 , pattern No.83

1) Please input 3D test pattern like below (HDMI mode NO. 872 , pattern No.83)

5.7. Local Dimming Function Check

Step 1) Turn on TV Step 2) At the Local Dimming mode, module Edge Backlight

moving right to left Back light of IOP module moving Step 3) confirm the Local Dimming mode Step 4) Press “exit” Key

2) When 3D OSD appear automatically , then select green button

3) Don’t wear a 3D Glasses, Check the picture like below

Only for training and service purposes

- 22 -

5.10. Option selection per country

5.10.1. Overview

▪ Option selection is only done for models in AJ/JA/IL

5.10.2. Method

1) Press ADJ key on the Adj. R/C, then select Country Group Meun

2) Depending on destination, select Country Group Code or Country Group then on the lower Country option, select US,

CA, MX. Selection is done using +, - or ►◄ KEY

5.11. HDMI ARC Function Inspection

5.11.1. Test equipment

- Optic Receiver Speaker

- MSHG-600 (SW: 1220 ↑)

- HDMI Cable (for 1.4 version)

5.11.2. Test method

1) Insert the HDMI Cable to the HDMI ARC port from the

master equipment (HDMI1)

6. GND and Internal Pressure check

6.1. Method

1) GND & Internal Pressure auto-check preparation

- Check that Power Cord is fully inserted to the SET. (If loose, re-insert)

2) Perform GND & Internal Pressure auto-check

- Unit fully inserted Power cord, Antenna cable and A/V arrive to the auto-check process.

- Connect D-terminal to AV JACK TESTER

- Auto CONTROLLER(GWS103-4) ON

- Perform GND TEST

- If NG, Buzzer will sound to inform the operator.

- If OK, changeover to I/P check automatically.

(Remove CORD, A/V form AV JACK BOX)

- Perform I/P test

- If NG, Buzzer will sound to inform the operator.

- If OK, Good lamp will lit up and the stopper will allow the pallet to move on to next process.

6.2. Checkpoint

1) Test voltage

- GND: 1.5KV/min at 100mA

- SIGNAL: 3KV/min at 100mA

2) TEST time: 1 second

3) TEST POINT

- GND Test = POWER CORD GND and SIGNAL CABLE GND.

- Hi-pot Test = POWER CORD GND and LIVE & NEUTRAL.

(4) LEAKAGE CURRENT: At 0.5mArms

2) Check the sound from the TV Set

3) Check the Sound from the Speaker or using AV & Optic TEST program (It’s connected to MSHG-600)

5.12. Ship-out mode check (In-stop)

▪ After final inspection, press In-Stop key of the Adj. R/C and

check that the unit goes to Stand-by mode.

7. AUDIO output check

No Item Min Ty p Max Unit Remark

1 Audio practi-

cal max Output, L/R (Distortion=10% max Output)

2

Speaker (8Ω Impedance)

*Measurement condition:

1) RF input: Mono, 1KHz sine wave signal, 100% Modulation

2) CVBS, Component: 1KHz sine wave signal (0.4Vrms)

3) RGB PC: 1KHz sine wave signal (0.7Vrms)

10.0

12.0

8.10

10.8WVrms

10 12 W EQ On

EQ Off AVL Off Clear Voice Off

AVL On Clear Voice On

Only for training and service purposes

- 23 -

8. USB S/W Download (optional, Service only)

(1) Put the USB Stick to the USB socket (2) Automatically detecting update file in USB Stick

- If your downloaded program version in USB Stick is lower than that of TV set, it didn’t work. Otherwise USB data is automatically detected.

(3) Show the message “Copying files from memory”

(4) Updating is staring

(5) Updating Completed, The TV will restart automatically

(6) If your TV is turned on, check your updated version and

Tool option.

* If downloading version is more high than your TV have, TV

can lost all channel data. In this case, you have to channel recover. If all channel data is cleared, you didn’t have a DTV/ ATV test on production line.

* After downloading, TOOL OPTION setting is needed again. (1) Push "IN-START" key in service remote controller. (2) Select "Tool Option 1" and Push “OK” button. (3) Punch in the number. (Each model has their number.)

Only for training and service purposes

- 24 -

Block Diagram

1. LM14A + URSA Circuit Block Diagram

Only for training and service purposes

- 25 -

1-1. LM14A Circuit Block Diagram

Only for training and service purposes

- 26 -

400

EXPLODED VIEW

IMPORTANT SAFETY NOTICE

Many electrical and mechanical parts in this chassis have special safety-related characteristics. These parts are identified by in the Schematic Diagram and EXPLODED VIEW. It is essential that these special safety parts should be replaced with t he same components as recommended in this manual to prevent Shock, Fire, or other Hazards. Do not modify the original design without permission of manufacturer.

900

901

570

800

571

521

120

540

121

530

LV1

820

500

A10

Set + Stand

200

Only for training and service purposes

- 27 -

A2

CHIP CONFIG

LGE Internal Use Only

CHIP_CONFIG[3:0] {LED1, SPI_DI,LED0, PWM_PM}

Value Mode Description 4’b1000 SB51_ExtSPI 51 boot from SPI 4’b1001 HEMCU_ExtSPI ARM boot from SPI 4’b1010 HEMCU_ROM_EMMC ARM boot from ROM; outer storage is eMMC 4’b1011 HEMCU_ROM_NAND ARM boot from ROM; outer storage is NAND 4’b1100 DBUS for test only 4’b0000 SB51_ExtSPI + Authentication 51 boot from SPI with ARM authentication 4’b0001 SB51_ExtSPI + Authentication HEMCU_ExtSPI + Authentication 4’b0011 HEMCU_ROM_NAND + Authentication ARM boot from ROM with authentication;

+3.3V_NORMAL

OPT

R108 4.7K

R110 4.7K

OPT

R109 4.7K

R111 4.7K

OPT

R115 4.7K

R122 4.7K

OPT

R116 4.7K

R123 4.7K

LED1 SPI_DI_SOC LED0 PWM_PM

LM14 HW Option

+3.3V_NORMAL

10K

BIT2_1

BIT0 BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT9

BIT10

BIT11

20150123 version

BIT(0/1)

00

TW/COL

CN/HK

01

10

11

Display

BIT4

Resolution

BIT5

DVB

EU

AJJA

BIT0_1

BIT0_0

ATSC

US

KR

BR

CI

Low

LCD

FHD

BIT1_1

R105 10K

BIT1_0

R106 10K

R112

10K

R113

JP

High

OLED

UHD

R119 10K

BIT2_0

R120 10K

BIT3_1

BIT3_0

BIT5_1

BIT6_1

BIT4_1

R132 10K

R128 10K

BIT4_0

R129 10K

BIT5_0

R133 10K

BIT(6/7)

00

01

10

11

R135 10K

BIT6_0

R136 10K

LM14A+URSA11 4K@60Hz LM14A+URSA11 4K@120Hz

R125 10K

R126 10K

BIT8_1

BIT7_1

R138 10K

BIT8_0

BIT7_0

R139 10K

B/E(FRC)

LM14A only

N/A

BIT9_1

R140 10K

BIT9_0

R141 10K

NVRAM

Atmel_NVRAM

IC101

AT24C256C-SSHL-T

EAN61133501

ATMEL CORPORATION

A0

1

A1

A2

GND

R142 10K

R143 10K

8

2

7

A0’h

3

6

4

5

BIT10_1

BIT11_1

R146 10K

R148 10K

BIT10_0

BIT11_0

R147 10K

R149 10K

BIT(2/3)

00

10

11 OS(DDR)

+3.3V_NORMAL

C100

0.1uF

VCC

Write Protection

WP

- Low : Normal Operation

- High : Write Protection

SCL

SDA

AR101

EU/CIS

T2/C/S2 PIP

T2/C/S2

T/C

33

AJJA

T2/C PIP

T2/C/S2

T

T2

Rohm_NVRAM

IC101-*1

BR24G256FJ-3

EAN62389502

ROHM Semiconductor KOREA CORPORATION

A0

VCC

1

8

WP

A1

7

2

SCL

A2

6

3

GND

SDA

4

5

I2C_SCL1

I2C_SDA1

M_RFModule_RESET

TW/COL KR

T2/C PIP

T2/C

T/C

PWM_DIM

PWM_DIM2

FAN_ON

AMP_RESET_N

PWM_PM

/USB_OCD2

USB_CTL2

FRC_FLASH_WP

DDTS_TX

SPI_CK_SOC SPI_DI_SOC SPI_DO_SOC

/TU_RESET1

/SPI_CS

DDCA_CK DDCA_DA

SOC_TX

SOC_RX

FRC_FLASH_SEL_SOC

/TU_RESET2

I2C_SCL6 I2C_SDA6

I2C_SCL3 I2C_SDA3

I2C_SCL1

I2C_SDA1 I2C_SCL2 I2C_SDA2

I2C_SCL5

I2C_SDA5

CPU_VID0

CORE_VID0

LED0 LED1

WOL_WAKE_UP_SOC

CN/HK

ATSC NIM+T2

Default

ATSC+T201

ATSC

ATSC PIP

CPU_VID1

R167

D9

PWM0/GPIO152

F10

PWM1/GPIO153

F8

PWM2/GPIO154

E9

PWM3/GPIO155

N5

PWM_PM/GPIO7

F4

SAR0/GPIO46

G5

SAR1/GPIO47

E5

SAR2/GPIO48

E4

SAR3/GPIO49

G4

SAR5

W5

PM_SPI_CK/GPIO1

V4

PM_SPI_DI/GPIO2

V5

PM_SPI_DO/GPIO3

Y6

PM_SPI_CZ/GPIO0

0

Y4

GPIO_PM[6]/[SPI-CZ1N]/GPIO16

Y5

OPT

GPIO_PM[10]/[SPI-CZ2N]/GPIO20

AL8

DDCA_CK/GPIO8

AK8

DDCA_DA/GPIO9

AH28

GPIO3/TX1/GPIO58

AH29

GPIO4/RX1

AA4

GPIO23/[TX3]/GPIO78

W6

GPIO24/[RX3]/GPIO79

F14

DIM2/TX4/GPIO112

F12

DIM3/RX4/GPIO113

AJ27

GPIO2/GPIO57

AJ7

GPIO28/SCK0/GPIO83

AH8

GPIO29/SDA0/GPIO84

E11

DDCR_CK/SCK3/GPIO54

E10

DDCR_DA/SDA3/GPIO53

AJ6

GPIO30/SCK4/GPIO85

AG8

GPIO31/SDA4/GPIO86

AH7

GPIO32/SCK5/GPIO87

AJ8

GPIO33/SDA5/GPIO88

L6

VID0/GPIO50

M6

VID1/GPIO51

AD5

LED0/GPIO29

AD4

LED1/GPIO30

AB5

WOL_INT_OUT/[GPIO]/GPIO52

North.AM

ISDB PIP

Default

ISDB EXT

ISDB INT

BR

IC100

LGE5332(LM14A)

JP

Default

SPI_CK_SOC SPI_DI_SOC SPI_DO_SOC

LVSYNC/[VX1_0-] LHSYNC/[VX1_0+]

LDE/[VX1_1-] LCK/[VX1_1+]

R_ODD[7]/LVB0N/[VX1_2-] R_ODD[6]/LVB0P/[VX1_2+] R_ODD[5]/LVB1N/[VX1_3-] R_ODD[4]/LVB1P/[VX1_3+] R_ODD[3]/LVB2N/[VX1_4-]

R_ODD[2]/LVB2P/[VX1_4+] R_ODD[1]/LVBCLKN/[VX1_5-] R_ODD[0]/LVBCLKP/[VX1_5+]

G_ODD[7]/LVB3N/[VX1_6-]

G_ODD[6]/LVB3P/[VX1_6+]

G_ODD[5]/LVB4N/[VX1_7-]

G_ODD[4]/LVB4P/[VX1_7+]

G_ODD[3]/LVA0N/[OSD_0-]

G_ODD[2]/LVA0P/[OSD_0+]

G_ODD[0]/LVA1P/[OSD_1+]

G_ODD[1]/LVA1N/[OSD_1-]

B_ODD[7]/LVA2N/[OSD_2-]

B_ODD[6]/LVA2P/[OSD_2+] B_ODD[5]/LVACLKN/[OSD_3-] B_ODD[4]/LVACLKP/[OSD_3+]

B_ODD[3]/LVA3N/[LOCKN]

B_ODD[2]/LVA3P/[HTPDN] B_ODD[1]/LVA4N/[OSD_LOCKN] B_ODD[0]/LVA4P/[OSD_HTPDN]

GPIO_PM[0]/GPIO10

GPIO_PM[3]/GPIO13 GPIO_PM[4]/GPIO14 GPIO_PM[7]/GPIO17 GPIO_PM[8]/GPIO18 GPIO_PM[9]/GPIO19

GPIO_PM[13]/GPIO23

GPIO_PM[1]/PM_UART1/GPIO11 GPIO_PM[5]/PM_UART1/GPIO15

GPIO_PM[11]/PM_UART0/GPIO21 GPIO_PM[12]/PM_UART0/GPIO22

SPI1_DI/GPIO107 SPI1_CK/GPIO106 SPI2_DI/GPIO109 SPI2_CK/GPIO108

VSYNC_LIKE/GPIO105

DIM0/GPIO110 DIM1/GPIO111

T-con I2C

BIT8

Protocol

BIT9

Division

Interface

BIT10

BIT11

/SPI_CS

TXOSD_3P TXOSD_3N TXOSD_2P TXOSD_2N TXOSD_1P TXOSD_1N TXOSD_0P TXOSD_0N

V-BY-ONE

AF32 AF31 AG32 AG31

AH31 AH30 AJ31 AJ32 AK32 AK31 AL32 AL31 AK30 AL30 AK29 AL29

AK28 AM28 AL28 AK27 AK26 AL26 AM26 AK25 AL25 AK24 AL24 AK23

AE2

U6 P4 U5 AE5 AJ5 AG6

P5 P6 AJ4 AH4

G7

TESTPIN

E13 D12 F11 D11 E12 D14 E14

Low

16Kbit

NON_Division

EPI

WebOS Lite WebOS

LM14A+URSA9

FRC_FLASH_SEL_SOC

FRC_FLASH_WP

LOCKAn_OSD URSA9_CONNECT Data_Format_1

Data_Format_0

URSA_RESET_SoC L/D_VSYNC_SOC

L/D_CLK_SOC

L/D_DI_SOC

TXVBY1_0N TXVBY1_0P TXVBY1_1N TXVBY1_1P

TXVBY1_2N TXVBY1_2P TXVBY1_3N TXVBY1_3P TXVBY1_4N TXVBY1_4P TXVBY1_5N TXVBY1_5P TXVBY1_6N TXVBY1_6P TXVBY1_7N TXVBY1_7P

TXOSD_0N TXOSD_0P TXOSD_1N TXOSD_1P TXOSD_2N TXOSD_2P TXOSD_3N TXOSD_3P

COMP1_DET

DDTS_RX

PCM_5V_CTL

PMIC_RESET

COMPENSATION_DONE

URSA9_CONNECT

/USB_OCD1 USB_CTL1

DATA_FORMAT_0_SOC DATA_FORMAT_1_SOC

HP_DET

RF_SWITCH_CTL

L/D_DI_SOC

L/D_CLK_SOC L/D_VSYNC_SOC SC_DET AV1_CVBS_DET

High

32Kbit

4_Division

Vx1

LOCKAn_Video HTPDAn_Video LOCKAn_OSD HTPDAn_OSD

R175 22

COMPENSATION_DONE

DATA_FORMAT_1_SOC

DATA_FORMAT_0_SOC

HTPDAn_OSD

HTPDAn_Video

EB_DATA[0-7]

EB_ADDR[0-14]

SM_Vsel

SM_CLK

SM_RST

SM_IO

SM_VCC

SM_CD

1K

R176

TCON_I2C_EN

EMMC_DATA[0-7]

FAN_ON

CAM_IREQ_N

EB_OE_N EB_BE_N1 /PCM_CE1

EB_WE_N

CAM_CD1_N PCM_RESET CAM_REG_N

EB_BE_N0

CAM_WAIT_N

EMMC_CMD

EMMC_CLK

EMMC_RST

EMMC_STRB

BIT0 BIT1

BIT2

BIT3

BIT4

EB_DATA[0] EB_DATA[1] EB_DATA[2] EB_DATA[3] EB_DATA[4] EB_DATA[5] EB_DATA[6] EB_DATA[7]

EB_ADDR[0] EB_ADDR[1] EB_ADDR[2] EB_ADDR[3] EB_ADDR[4] EB_ADDR[5] EB_ADDR[6] EB_ADDR[7] EB_ADDR[8] EB_ADDR[9] EB_ADDR[10] EB_ADDR[11] EB_ADDR[12] EB_ADDR[13] EB_ADDR[14]

BIT5

EMMC_DATA[6] EMMC_DATA[7] EMMC_DATA[2] EMMC_DATA[1] EMMC_DATA[0] EMMC_DATA[3] EMMC_DATA[4] EMMC_DATA[5]

OLED

LM14A_ONLY

AH14

PCM_D[0]/GPIO147

AG13

PCM_D[1]/GPIO148

AG12

PCM_D[2]/GPIO149

AK22

PCM_D[3]/GPIO119

AK21

PCM_D[4]/GPIO120

AL21

PCM_D[5]/GPIO121

AM23

PCM_D[6]/GPIO122

AH20

PCM_D[7]/GPIO123

AG14

PCM_A[0]/GPIO146

AL20

PCM_A[1]/GPIO145

AG15

PCM_A[2]/GPIO143

AH15

PCM_A[3]/GPIO142

AM19

PCM_A[4]/GPIO141

AJ17

PCM_A[5]/GPIO139

AJ16

PCM_A[6]/GPIO138

AH17

PCM_A[7]/GPIO137

AM20

PCM_A[8]/GPIO131

AH19

PCM_A[9]/GPIO129

AJ20

PCM_A[10]/GPIO125

AK20

PCM_A[11]/GPIO127

AG17

PCM_A[12]/GPIO136

AJ19

PCM_A[13]/GPIO132

AG18

PCM_A[14]/GPIO133

AH18

PCM_IRQA_N/GPIO135

AM22

PCM_OE_N/GPIO126

AG20

PCM_IORD_N/GPIO128

AL22

PCM_CE_N/GPIO124

AK19

PCM_WE_N/GPIO134

AG21

PCM_CD_N/GPIO151

AH16

PCM_RESET/GPIO150

AJ14

PCM_REG_N/GPIO144

AG19

PCM_IOWR_N/GPIO130

AG16

PCM_WAIT_N/GPIO140

C7

EMMC_IO15/[GPIO]/GPIO189

C6

EMMC_IO17/[GPIO]/GPIO188

C8

EMMC_IO9/[EMMC_CMD]/GPIO183

B8

EMMC_IO14/[GPIO]/GPIO185

A9

EMMC_IO10/[EMMC_CLK]/GPIO186

B7

EMMC_IO16/[GPIO]/GPIO187

B9

EMMC_IO11/[EMMC_RSTN]/GPIO190

A8

EMMC_IO12/[GPIO]/GPIO184

C9

EMMC_IO8/[NAND-DQS]/GPIO191

B6

EMMC_IO13/[GPIO]/GPIO217

C10

EMMC_IO6/[EMMC_D6]/GPIO221

B11

EMMC_IO7/[EMMC_D7]/GPIO220

A11

EMMC_IO2/[EMMC_D2]/GPIO219

C11

EMMC_IO1/[EMMC_D1]/GPIO218

A12

EMMC_IO0/[EMMC_D0]/GPIO194

B12

EMMC_IO3/[EMMC_D3]/GPIO193

C12

EMMC_IO4/[EMMC_D4]/GPIO192

B13

EMMC_IO5/[EMMC_D5]/GPIO222

GST_A GCLK_A MCLK_A

EO_A

IC100

LGE5332(LM14A)

LM14A UF74

PMIC_RESET

LOCKOUT12

TS1_D0/GPIO182 TS1_D1/GPIO181 TS1_D2/GPIO180 TS1_D3/GPIO179 TS1_D4/GPIO178 TS1_D5/GPIO177 TS1_D6/GPIO176

TS1_D7/GPIO175 TS1_CLK/GPIO172 TS1_VLD/GPIO174

TS1_SYNC/GPIO173

TS0_D0/GPIO161

TS0_D1/GPIO162

TS0_D2/GPIO163

TS0_D3 TS0_D4/GPIO165 TS0_D5/GPIO166 TS0_D6/GPIO167 TS0_D7/GPIO168

TS0_CLK/GPIO171 TS0_VLD/GPIO169

TS0_SYNC/GPIO170

TS3_D0/GPIO206 TS3_D1/GPIO207 TS3_D2/GPIO208 TS3_D3/GPIO209 TS3_D4/GPIO210 TS3_D5/GPIO211 TS3_D6/GPIO212 TS3_D7/GPIO213

TS3_CLK/GPIO216 TS3_VLD/GPIO214

TS3_SYNC/GPIO215

GPIO8/[TS4_D[0]]/GPIO63

GPIO5/[TS4_CLK]/GPIO60 GPIO7/[TS4_VLD]/GPIO62

GPIO6/[TS4_SYNC]/GPIO61

VIFP VIFM

SIFP SIFM

IFAGC

TGPIO0/GPIO157 TGPIO1/GPIO158

TGPIO2/SCK1/GPIO159 TGPIO3/SDA1/GPIO160

NC_1 NC_2 NC_3 NC_4

NC_5

GPIO34/GPIO89

NC_6

AH13 AG11 AG10 AJ11 AH10 AJ13 AG9 AH9 AH11 AJ10 AH12

AK17 AL18 AK18 AL15 AL16 AK15 AM16 AK16 AL19 AM17 AL17

AH23 AH27 AJ23 AG27 AH24 AH26 AJ25 AG26 AH25 AJ26 AG24

AJ28 AG28 AJ29 AG29

AL2 AM2

AK1 AK2

AK3

AJ1 AJ2 R4 R5

AM7 AL7 AM8 AK7

AL5

AM5 M7

FE_DEMOD1_TS_DATA[0] FE_DEMOD1_TS_DATA[1] FE_DEMOD1_TS_DATA[2] FE_DEMOD1_TS_DATA[3] FE_DEMOD1_TS_DATA[4] FE_DEMOD1_TS_DATA[5] FE_DEMOD1_TS_DATA[6] FE_DEMOD1_TS_DATA[7]

FE_DEMOD1_TS_CLK FE_DEMOD1_TS_VAL FE_DEMOD1_TS_SYNC

TPI_DATA[0] TPI_DATA[1] TPI_DATA[2] TPI_DATA[3] TPI_DATA[4] TPI_DATA[5] TPI_DATA[6] TPI_DATA[7]

TPI_CLK TPI_VAL TPI_SOP

POL

GST_A

GST

GCLK

GCLK_A

MCLK

MCLK_A

OPT_P

SOE

FB

EO_A

E/O

HCONV

DPM

LOCKOUT12

LOCK

FE_DEMOD3_TS_DATA FE_DEMOD3_TS_CLK FE_DEMOD3_TS_VAL FE_DEMOD3_TS_SYNC

Close to MSTAR

/USB_OCD3 USB_CTL3

I2C_SCL7 I2C_SDA7

C101 0.1uF C102 0.1uF

ANALOG SIF Close to MSTAR

CORE_VID1

TXVBY1_0N TXVBY1_0P TXVBY1_1N TXVBY1_1P

R183 100

R184 100

R182 10K

5V_DET_HDMI_1 /USB_OCD3 USB_CTL3

EPI

C103 0.1uF

C104 0.1uF

R185 47

R186 47

PZ1608U121-2R0TF

R187

0

LM14A UF68/64

/TU_RESET2

WOL_WAKE_UP_SOC

FE_DEMOD1_TS_DATA[0-7]

TPI_DATA[0-7]

OPT C107

100pF

OPT C109 33pF

R188

C105

300

1000pF

OPT

+3.3V_NORMAL

L100

C106

0.1uF

C108

0.047uF 25V

DTV_IF

IF_P

IF_N

OPT C110 33pF

TU_SIF

IF_AGC

R100

1.8K

R101

1.8K

+3.3V_LNA_TU

+3.3V_NORMAL

R102

1.8K

R104

1.8K

R103

1.8K

I2C_SDA_MICOM I2C_SCL_MICOM

R107

1.8K

I2C PULL UP

R124

1.8K

R114

1.8K

R121

1.8K

AR100 33

R127

1.8K

R130

1.8K

I2C_SDA3 I2C_SCL3

R131

1.8K

R134

1.8K

R137

1.8K

+3.3V_TU

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

I2C_SDA7 I2C_SCL7

I2C_SDA6 I2C_SCL6 I2C_SDA1 I2C_SCL1 I2C_SDA3 I2C_SCL3

I2C_SDA4 I2C_SCL4

I2C_SDA5 I2C_SCL5

I2C_SDA2 I2C_SCL2

I2C for URSA9 (URSA9 Only)

I2C for LCD Module

I2C for NAVRAM

I2C for Micom

I2C for Main Amp / Woofer AMP

I2C for tuner

I2C for tuner&LNB

GPIO PULL UP

+3.3V_NORMAL

OPT

R152 10K

R154 10K

R164 10K

R156 10K

R157 10K

R161 10K

Mstar Debug

MSTAR_DEBUG_OLD

MSTAR_DEBUG_NEW

P100

12507WS-04L

OPT

R165 10K

R170 10K

R166 10K

R168 10K

/TU_RESET1

RF_SWITCH_CTL

AMP_RESET_N

TCON_I2C_EN

/USB_OCD3

USB_CTL3

/USB_OCD2

USB_CTL2

M_RFModule_RESET

PCM_5V_CTL

1

2

DDCA_CK

3

DDCA_DA

4

5

P101

12505WS-04A00

1

2

3

4

5

RS232C_Debug

UART_4PIN_WAFER

P102

12507WS-04L

5

+3.3V_NORMAL

1

2

3

4

OPT

DDTS_Debug

P103

12507WS-04L

R178 10K

SOC_RX

OPT

R179 10K

SOC_TX

5

+3.3V_NORMAL

1

2

3

4

OPT

R180 10K

DDTS_RX

OPT

R181 10K

DDTS_TX

BSD-15Y-LM14A-001_00-HD

2015-01-23LM14A

MAIN1_SYSTEM

01

AVDDL_MOD11

LGE Internal Use Only

AVDD15_MOD

C227 0.1uF

DVDD_DDR11

+1.1V_VDDC_CPU

DVDD_NODIE

5V_HDMI_1

C200

1uF 25V

R200

+1.1V_VDDC

DVDD_DDR11

AVDD5V_MHL

10

AD29 AD30

AA13 AF11

AA22 AA23 AA24 AA25 AB24 AB25

AE16 AF16

J9 J10 J11 J12 J13

K9 K10 K11 K12 K13

L9 L10 L11 L12 R11 R12 R13 T11 T12 T13 U11 U12 U13

W21 Y21

W20 Y20 U19 V19

U21 U22 U23 U24 U25 V23 V24 V25 W23 W24 W25 Y23 Y24 Y25

L13

K21 N21

M21 L21

VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23

AVDDL_PREDRV_1 AVDDL_PREDRV_2 AVDDL_PREDRV_3 AVDDL_MOD_1 AVDDL_MOD_2 AVDDL_MOD_3 AVDD15_MOD_1 AVDD15_MOD_2 AVDDL_USB3_1 AVDDL_USB3_2

VDDC_CPU_1 VDDC_CPU_2 VDDC_CPU_3 VDDC_CPU_4 VDDC_CPU_5 VDDC_CPU_6 VDDC_CPU_7 VDDC_CPU_8 VDDC_CPU_9 VDDC_CPU_10 VDDC_CPU_11 VDDC_CPU_12 VDDC_CPU_13 VDDC_CPU_14 VDDC_CPU_15 VDDC_CPU_16 VDDC_CPU_17 VDDC_CPU_18 VDDC_CPU_19 VDDC_CPU_20

MCP_VDDC_1 MCP_VDDC_2

DVDD_NODIE

DVDD_DDR_1 DVDD_DDR_2

DVDD_DDR_3 DVDD_DDR_4

IC100

LGE5332(LM14A)

AVDD3P3_MHL3_1 AVDD3P3_MHL3_2

AVDD3P3_DADC_1 AVDD3P3_DADC_2

AVDD3P3_USB3_1 AVDD3P3_USB3_2

VDDP_3318_A/[3.3V/1.8V] VDDP_3318_C/[3.3V/1.8V]

AVDD_DDR_LDO_A AVDD_DDR_LDO_B

AVDD_HDMI_5V_PA

AVDD_DDR_VBP_A_1 AVDD_DDR_VBP_A_2 AVDD_DDR_VBP_A_3 AVDD_DDR_VBP_A_4

AVDD_DDR_VBN_A_1 AVDD_DDR_VBN_A_2 AVDD_DDR_VBN_A_3 AVDD_DDR_VBN_A_4

AVDD_DDR_VBP_B_1 AVDD_DDR_VBP_B_2 AVDD_DDR_VBP_B_3 AVDD_DDR_VBP_B_4

AVDD_DDR_VBN_B_1 AVDD_DDR_VBN_B_2 AVDD_DDR_VBN_B_3 AVDD_DDR_VBN_B_4

VDDC_24 VDDC_25 VDDC_26 VDDC_27 VDDC_28 VDDC_29 VDDC_30 VDDC_31 VDDC_32 VDDC_33 VDDC_34 VDDC_35 VDDC_36 VDDC_37 VDDC_38 VDDC_39

VDD_SRAM_1 VDD_SRAM_2 VDD_SRAM_3

CTRL_SRAMLDO

EMMC_CTRL

AVDD_NODIE

AVDDL_MHL3_1 AVDDL_MHL3_2

AVDD3P3_ETH

AVDD3P3_ADC_1 AVDD3P3_ADC_2 AVDD3P3_USB_1 AVDD3P3_USB_2

AVDD_AU33

AVDD_EAR33

AVDD3P3_DMPLL

VDDP_1 VDDP_2

AVDD_MOD_1

AVDD_MOD_2 AVDD_LPLL_1 AVDD_LPLL_2

AVDD_PLL_A

AVDD_PLL_B

AVDD_DDR_A_1 AVDD_DDR_A_2 AVDD_DDR_A_3 AVDD_DDR_A_4 AVDD_DDR_A_5 AVDD_DDR_A_6 AVDD_DDR_A_7 AVDD_DDR_B_1 AVDD_DDR_B_2 AVDD_DDR_B_3 AVDD_DDR_B_4 AVDD_DDR_B_5 AVDD_DDR_B_6 AVDD_DDR_B_7

GND_EFUSE

AC17 AC18 AC19 AC20 AC21 AC22 AD17 AD18 AD19 AD20 AD21 AD22 AE19 AE20 AE21 AE22

AE31 AC24 AD23

AE30

A6

V7

L7 N12 R7 T7

AVDD_DMPLL

Y7 AB7 AB8 AA7 AA8 G9 G10 AB15 AF13 AD7 AE7 AF8 AE15 AF15

V17 V18 W19 Y19

N15 N16

H16 K16

J21 K17 K18 K19 L17 L19 L20 J23 K22 K23 M22 N22 N23 P23

L18 L22

H7

G8

C14 B14 J17 J18

B15 C15 J19 J20

AC30 AC31 K24 L24

AD31 AD32 L23 M24

+1.1V_VDDC

DVDD_DDR11

AVDD33_ADC

R201

0

AVDD_DMPLL

VDDP_NAND_A

AVDD_DDR

AVDDP3P3_MHL

AVDD_DMPLL

AVDD_AU33

AVDD5V_MHL

C2100.47uF

C2110.47uF

C2120.47uF

C2130.47uF

C2140.47uF

C2150.47uF

C216

0.47uF

C220

AVDDP3P3

VDDP_NAND_C

0.1uF C229

C219

C221

AVDD_DDR

0.1uF

GND JIG POINT

+3.3V_NORMAL

+1.8V

JP204

JP202

JP203

L208

PZ1608U121-2R0TF

2A

L209

PZ1608U121-2R0TF

2A

+1.1V_VDDC_CPU

+1.1V_VDDC

JP205

VDDP_NAND_C

VDDP_NAND_A

C260 10uF 10V

C236 10uF 10V

C263 10uF 10V

C205 10uF 10V

1st layer

0.1uF

C276

C278

Close to chip side

1st layer

0.1uF

C230

C234

Close to chip side

C266

0.1uF

C239

0.1uF

C299

0.1uF

C235

0.1uF

+1.5V_DDR

PZ1608U121-2R0TF

+3.3V_NORMAL

C268 10uF 10V

+1.5V_Bypass Cap

AVDD_DDR

L227

L200

C207

4A

10uF 10V

C209 0.1uF

L213

PZ1608U121-2R0TF

2A

L221

PZ1608U121-2R0TF

2A

L219

PZ1608U121-2R0TF

2A

C208 10uF 10V

Close to chip side

1st layer

C201 10uF 10V

C224 0.1uF

Close to chip side

4th layer

AVDD_DMPLL

0.1uF

C269

Close to chip side

4th layer

AVDD33_ADC

Close to chip side

4th layer

AVDD_AU33

C322

C250

C225 0.1uF

C293

0.47uF

6.3V

C292

0.47uF

6.3V

4th layer

10uF

4th layer

10uF

C226 0.1uF

C294 1uF 10V

C295 1uF 10V

C323

0.1uF 16V

C261

0.1uF 16V

C203 0.1uF

C204 0.1uF

C251

0.47uF

6.3V

C287 0.1uF

C247

0.47uF

6.3V

C252

0.47uF

6.3V

+3.3V_NORMAL

+1.1V_Bypass Cap(CLOSE TO CHIP SIDE)

+1.1V_VDDC

4th layer

C223

C316

0.47uF 10uF

10uF

10V

C314

Close to chip side

+3.3V_Bypass Cap

C222 10uF 10V

+5V_NORMAL

R206 10K

G

S

D

RUE003N02

Q200

OPT

C248

C249

0.47uF

6.3V

L215

PZ1608U121-2R0TF

2A

0

R207

OPT

L202

PZ1608U121-2R0TF

2A

AVDD_DDR

PZ1608U121-2R0TF

AVDDP3P3

1st layer

C256 10uF 10V

Close to chip side

L226

PZ1608U121-2R0TF

2A

AVDD15_MOD

2A

L224

0.1uF

C274

L201

PZ1608U121-2R0TF

Close to chip side

AVDDL_MOD11

C307 0.1uF

C308 0.1uF

Close to chip side

4th layer

AVDDP3P3_MHL

C240

0.1uF

DVDD_DDR11

4th layer

0.47uF

C311

C241

0.47uF

6.3V

4th layer

C324

0.47uF

6.3V

Close to chip side

4th layer

C238

0.47uF

6.3V

Close to chip side

0.1uF

C253

C217 10uF 10V

C257

0.47uF

6.3V

C320

0.47uF

6.3V

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

Close to chip side

LM14A

MAIN2_POWER

2014-11-06

2

M0_DDR_A0

LGE Internal Use Only

M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14 M0_DDR_A15

M0_DDR_BA0 M0_DDR_BA1

M0_DDR_BA2 M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN M0_DDR_ODT M0_DDR_CKE

M0_DDR_RESET_N

M0_D_CLK

M0_D_CLKN

M0_DDR_CS1 M0_DDR_CS2

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ2 M0_DDR_DQ3 M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7 M0_DDR_DM0

M0_DDR_DQS0

M0_DDR_DQS_N0

M0_DDR_DQ8

M0_DDR_DQ9 M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

M0_DDR_DM1 M0_DDR_DQS1

M0_DDR_DQS_N1

M0_DDR_DQ16 M0_DDR_DQ17 M0_DDR_DQ18 M0_DDR_DQ19 M0_DDR_DQ20 M0_DDR_DQ21 M0_DDR_DQ22 M0_DDR_DQ23

M0_DDR_DM2 M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQ24 M0_DDR_DQ25 M0_DDR_DQ26 M0_DDR_DQ27 M0_DDR_DQ28 M0_DDR_DQ29 M0_DDR_DQ30 M0_DDR_DQ31

M0_DDR_DM3 M0_DDR_DQS3

M0_DDR_DQS_N3

F17

IO[3]/A-A0[AB-A0]/A-A6

C17

IO[2]/A-A1[AB-A1]/A-A5

E17

IO[8]/A-A2[AB-A2]/A-A8

F18

IO[12]/A-A3[AB-A3]/A-A4

B18

IO[11]/A-A4[AB-A4]/A-BA1

E18

IO[14]/A-A5[AB-A5]/A-A0

A17

IO[10]/A-A6[AB-A6]/A-A1

D17

IO[13]/A-A7[AB-A7]/A-A2

C16

IO[0]/A-A8[AB-A8]/A-A9

E16

IO[5]/A-A9[AB-A9]/A-A11

B19

IO[9]/A-A10[AB-A10]/A-RASZ

B17

IO[6]/A-A11[AB-A11]/A-A7

D20

IO[26]/A-A12[AB-A12]/A-BG0

F16

IO[4]/A-A13[AB-A13]/A-PARITY

B16

IO[7]/A-A14[AB-A14]/A-A13

E20

IO[19]/A-A15[AB-A15]/A-A3

E19

IO[24]/A-BA0[AB-BA0]/A-A10

C18

IO[20]/A-BA1[AB-BA1]/A-CASZ

F19

IO[21]/A-BA2[AB-BA2]/A-BA0

G22

IO[15]/A-RASZ[AB-RASZ]/A-ODT

F21

IO[17]/A-CASZ[AB-CASZ]/A-WEZ

E21

IO[16]/A-WEZ[AB-WEZ]/A-A12

F20

IO[25]/A-ODT[AB-ODT]/A-ACTZ

C19

IO[18]/A-CKE[AB-CKE]/A-CKE

F15

IO[1]/A-RST[AB-RST]/A-RST

A20

IO[28]/A-MCLK[AB-MCLK]/A-MCLKZ

B20

IO[27]/A-MCLKZ[AB-MCLKZ]/A-MCLK

E15

IO[23]/A-CSB1[AB-CSB1]/A-CSB1

D15

IO[22]/A-CSB2[AB-CSB2]/A-CSB2

C23

IO[47]/A-DQ[0][A-DQL0]/A-DQ[0]

B22

IO[31]/A-DQ[1][A-DQL1]/A-DQ[1]

B24

IO[48]/A-DQ[2][A-DQL2]/A-DQ[2]

C21

IO[29]/A-DQ[3][A-DQL3]/A-DQ[3]

B25

IO[50]/A-DQ[4][A-DQL4]/A-DQ[6]

C20

IO[30]/A-DQ[5][A-DQL5]/A-DQ[7]

C24

IO[49]/A-DQ[6][A-DQL6]/A-DQ[4]

B21

IO[32]/A-DQ[7][A-DQL7]/A-DQ[5]

C22

IO[33]/A-DQM[0][A-DML]/A-DQM[0]

A23

IO[42]/A-DQS[0][A-DQSL]/A-DQS[0]

B23

IO[41]/A-DQSB[0][A-DQSLB]/A-DQSB[0]

D23

IO[35]/A-DQ[8][A-DQU0]/A-DQ[15]

D26

IO[45]/A-DQ[9][A-DQU1]/A-DQ[10]

E22

IO[38]/A-DQ[10][A-DQU2]/A-DQ[13]

D27

IO[46]/A-DQ[11][A-DQU3]/A-DQM[1]

F23

IO[36]/A-DQ[12][A-DQU4]/A-DQ[9]

E26

IO[43]/A-DQ[13][A-DQU5]/A-DQ[12]

D22

IO[34]/A-DQ[14][A-DQU6]/A-DQ[11]

E25

IO[44]/A-DQ[15][A-DQU7]/A-DQ[8]

E24

IO[37]/A-DQM[1][A-DMU]/A-DQ[14]

D24

IO[40]/A-DQS[1][A-DQSU]/A-DQS[1]

E23

IO[39]/A-DQSB[1][A-DQSUB]/A-DQSB[1]

C28

IO[69]/A-DQ[16][B-DQL0]/A-DQ[16]

C26

IO[53]/A-DQ[17][B-DQL1]/A-DQ[17]

B29

IO[70]/A-DQ[18][B-DQL2]/A-DQ[18]

A26

IO[54]/A-DQ[19][B-DQL3]/A-DQ[19]

C29

IO[72]/A-DQ[20][B-DQL4]/A-DQ[22]

C25

IO[52]/A-DQ[21][B-DQL5]/A-DQ[23]

A29

IO[71]/A-DQ[22][B-DQL6]/A-DQ[20]

B26

IO[51]/A-DQ[23][B-DQL7]/A-DQ[21]

B27

IO[55]/A-DQM[2][B-DML]/A-DQM[2]

B28

IO[64]/A-DQS[2][B-DQSL]/A-DQS[2]

C27

IO[63]/A-DQSB[2]/[B-DQSLB]/A-DQSB[2]

E29

IO[58]/A-DQ[24][B-DQU0]/A-DQ[31]

C31

IO[67]/A-DQ[25][B-DQU1]/A-DQ[26]

E27

IO[56]/A-DQ[26][B-DQU2]/A-DQ[29]

D31

IO[66]/A-DQ[27][B-DQU3]/A-DQM[3]

D29

IO[59]/A-DQ[28][B-DQU4]/A-DQ[25]

D30

IO[65]/A-DQ[29][B-DQU5]/A-DQ[28]

E28

IO[57]/A-DQ[30][B-DQU6]/A-DQ[27]

C30

IO[60]/A-DQ[31][B-DQU7]/A-DQ[24]

B31

IO[68]/A-DQM[3][B-DMU]/A-DQ[30]

A31

IO[62]/A-DQS[3][B-DQSU]/A-DQS[3]

B30

IO[61]/A-DQSB[3][B-DQSUB]/A-DQSB[3]

IC100

LGE5332(LM14A)

IO[75]/B-A0[CD-A0]/B-A6 IO[80]/B-A1[CD-A1]/B-A5 IO[83]/B-A2[CD-A2]/B-A8 IO[79]/B-A3[CD-A3]/B-A4

IO[87]/B-A4[CD-A4]/B-BA1

IO[86]/B-A5[CD-A5]/B-A0 IO[90]/B-A6[CD-A6]/B-A1 IO[78]/B-A7[CD-A7]/B-A2 IO[77]/B-A8[CD-A8]/B-A9

IO[73]/B-A9[CD-A9]/B-A11

IO[93]/B-A10[CD-A10]/B-RASZ

IO[84]/B-A11[CD-A11]/B-A7

IO[85]/B-A12[CD-A12]/B-BG0

IO[74]/B-A13[CD-A13]/B-PARITY

IO[81]/B-A14[CD-A14]/B-A13

IO[96]/B-A15[CD-A15]/B-A3

IO[88]/B-BA0[CD-BA0]/B-A10

IO[92]/B-BA1[CD-BA1]/B-CASZ

IO[82]/B-BA2[CD-BA2]/B-BA0 IO[97]/B-RASZ[CD-RASZ]/B-ODT IO[94]/B-CASZ[CD-CASZ]/B-WEZ

IO[89]/B-WEZ[CD-WEZ]/B-A12

IO[95]/B-ODT[CD-ODT]/B-ACTZ

IO[91]/B-CKE[CD-CKE]/B-CKE

IO[76]/B-RST[CD-RST]/B-RST

IO[101]/B-MCLK[CD-MCLK]/B-MCLKZ

IO[100]/B-MCLKZ[CD-MCLKZ]/B-MCLK

IO[99]/B-CSB1[CD-CSB1]/B-CSB1 IO[98]/B-CSB2[CD-CSB2]/B-CSB2

IO[120]/B-DQ[0][C-DQL0]/B-DQ[0] IO[104]/B-DQ[1][C-DQL1]/B-DQ[1] IO[121]/B-DQ[2][C-DQL2]/B-DQ[2] IO[102]/B-DQ[3][C-DQL3]/B-DQ[3] IO[123]/B-DQ[4][C-DQL4]/B-DQ[6] IO[105]/B-DQ[5][C-DQL5]/B-DQ[7] IO[122]/B-DQ[6][C-DQL6]/B-DQ[4] IO[103]/B-DQ[7][C-DQL7]/B-DQ[5]

IO[106]/B-DQM[0][C-DML]/B-DQM[0]

IO[115]/B-DQS[0][C-DQSL]/B-DQS[0]

IO[114]/B-DQSB[0][C-DQSLB]/B-DQSB[0]

IO[109]/B-DQ[8][C-DQU0]/B-DQ[15]

IO[116]/B-DQ[9][C-DQU1]/B-DQ[10] IO[107]/B-DQ[10][C-DQU2]/B-DQ[13] IO[119]/B-DQ[11][C-DQU3]/B-DQM[1]

IO[111]/B-DQ[12][C-DQU4]/B-DQ[9] IO[117]/B-DQ[13][C-DQU5]/B-DQ[12] IO[108]/B-DQ[14][C-DQU6]/B-DQ[11]

IO[118]/B-DQ[15][C-DQU7]/B-DQ[8]

IO[110]/B-DQM[1][C-DMU]/B-DQ[14] IO[113]/B-DQS[1][C-DQSU]/B-DQS[1]

IO[112]/B-DQSB[1][C-DQSUB]/B-DQSB[1]

IO[145]/B-DQ[16][D-DQL0]/B-DQ[16] IO[126]/B-DQ[17][D-DQL1]/B-DQ[17] IO[143]/B-DQ[18][D-DQL2]/B-DQ[18] IO[127]/B-DQ[19][D-DQL3]/B-DQ[19] IO[142]/B-DQ[20][D-DQL4]/B-DQ[22] IO[124]/B-DQ[21][D-DQL5]/B-DQ[23] IO[144]/B-DQ[22][D-DQL6]/B-DQ[20] IO[125]/B-DQ[23][D-DQL7]/B-DQ[21]

IO[128]/B-DQM[2][D-DML]/B-DQM[2] IO[137]/B-DQS[2][D-DQSL]/B-DQS[2]

IO[136]/B-DQSB[2][D-DQSLB]/B-DQSB[2]

IO[131]/B-DQ[24][D-DQU0]/B-DQ[31] IO[141]/B-DQ[25][D-DQU1]/B-DQ[26]

IO[130]_/B-DQ[26][D-DQU2]/B-DQ[29]

IO[140]/B-DQ[27][D-DQU3]/B-DQM[3] IO[129]/B-DQ[28][D-DQU4]/B-DQ[25] IO[139]/B-DQ[29][D-DQU5]/B-DQ[28] IO[132]/B-DQ[30][D-DQU6]/B-DQ[27] IO[138]/B-DQ[31][D-DQU7]/B-DQ[24]

IO[133]/B-DQM[3][D-DMU]/B-DQ[30] IO[135]/B-DQS[3][D-DQSU]/B-DQS[3]

IO[134]/B-DQSB[3][D-DQSUB]/B-DQSB[3]

DDR_VTT

AR400

M0_DDR_A14

M0_DDR_A8

M0_DDR_A11

M0_DDR_A6

M0_DDR_A1

M0_DDR_A4 M0_DDR_A12 M0_DDR_BA1

M0_DDR_A13

M0_DDR_A9

M0_DDR_A7

M0_DDR_A2

M0_DDR_A5

M0_DDR_A3

M0_DDR_A0

M0_DDR_BA0 M0_DDR_BA2 M0_DDR_A15 M0_DDR_A10

M0_DDR_WEN

M0_DDR_CASN

M0_DDR_ODT

M0_DDR_RASN

M0_DDR_CKE

M0_D_CLKN

M0_D_CLK

AVDD_DDR

R410

R411

AVDD_DDR

R408

R409

56 1/16W

AR401 56 1/16W

AR402 56 1/16W

AR403 56 1/16W

AR404 56 1/16W

AR405 56 1/16W

AR406 56 1/16W

1K 1%

M0_DDR_VREFDQ

C472

0.1uF C474 1000pF 50V

M1_DDR_VREFDQ

C516

0.1uF C517 1000pF 50V

DDR_VTT

AVDD_DDR

C414 10uF 10V

CIS2 1J121

C424 0.1uF

C425 0.1uF

C426 0.1uF

C427 0.1uF

C428 0.1uF

C429 0.1uF

C430 0.1uF

C431 0.1uF

C432 0.1uF

C433 0.1uF

C434 0.1uF

C435 0.1uF

C436 0.1uF

C437 0.1uF

* DDR_VTT

R443 10K

1/16W 1%

L400

C417 10uF 10V

C535 10uF 10V

AVDD_DDR

R416

R417

1%

1/16W

1K 1%

AVDD_DDR

R414

R415

C421 10uF 10V

10K

R444

M0_1_DDR_VREFDQ

C479

0.1uF

M1_1_DDR_VREFDQ

1K 1%

C518

0.1uF

1K 1%

AP2303MPTR-G1

VIN

GND

VREFEN

VOUT

C543

0.1uF 16V

C483 1000pF 50V

1

2

3

4

C519 1000pF 50V

IC402

THERMAL

9

M1_DDR_A14

M1_DDR_A8

M1_DDR_A11

M1_DDR_A6

M1_DDR_A1

M1_DDR_A4 M1_DDR_A12 M1_DDR_BA1

M1_DDR_A13

M1_DDR_A9

M1_DDR_A7

M1_DDR_A2

M1_DDR_A5

M1_DDR_A3

M1_DDR_A0

M1_DDR_BA0 M1_DDR_BA2 M1_DDR_A15 M1_DDR_A10

M1_DDR_WEN

M1_DDR_CASN

M1_DDR_ODT

M1_DDR_RASN

M1_DDR_CKE

M1_D_CLKN

M1_D_CLK

AVDD_DDR

[EP]

NC_3

8

NC_2

7

VCNTL

6

NC_1

5

AVDD_DDR

R446

10K

1K

1% 10K

R445

1K

M8

H1

L8

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1 J9 L1 L9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

AVDD_DDR

C410 C411

M1_DDR_VREFDQ

R404

C468

0.1uF

C469

0.1uF

SS_DDR3_4Gb_25n

IC403-*1

K4B4G1646D-BCMA

EAN63391401

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M0_DDR_VREFDQ

R400

240

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

IC400-*1

IC400-*2

K4B4G1646D-BCMA

H5TQ4G63CFR_RDC

EAN63391401

EAN63053202

N3

M8

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

VREFCA

A0

VREFCA

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

N7

K2

A12/BC

VDD_4

T3

K8

A13

VDD_5

T7

N1

A14

VDD_6

N9

M7

N9

VDD_7

NC_5

VDD_7

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

C1

VDDQ_3

CK

C9

K9

C9

VDDQ_4

CKE

VDDQ_4

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

Hynix_DDR3_2Gb

SS_DDR3_2Gb

IC400-*4

IC400-*3

H5TQ2G63FFR-RDC

K4B2G1646Q-BCMA

EAN63648701

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

240

DDR3 1.5V bypass Cap - Place these caps near Memory

Hynix_DDR3_4Gb_25n

SS_DDR3_2Gb

IC403-*2

IC403-*3

H5TQ4G63CFR_RDC

K4B2G1646Q-BCMA

EAN63053202

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

L8

R8

L8

ZQ

A6

ZQ

R2

A7

T8

A8

B2

R3

B2

VDD_1

A9

VDD_1

D9

L7

D9

VDD_2

A10/AP

VDD_2

G7

R7

G7

VDD_3

A11

VDD_3

K2

N7

VDD_4

A12/BC

VDD_4

K8

T3

VDD_5

A13

N1

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

VREFCA

VREFDQ

ZQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

NC_1 NC_2 NC_3 NC_4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

Hynix_DDR3_2Gb

IC403-*4

H5TQ2G63FFR-RDC

EAN63648701

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14 M0_DDR_A15

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_D_CLK

M0_D_CLKN M0_DDR_CKE

M0_DDR_CS2 M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS2

M0_DDR_DQS_N2

M0_DDR_DQS3

M0_DDR_DQS_N3

M0_DDR_DM2 M0_DDR_DM3

M0_DDR_DQ16 M0_DDR_DQ17 M0_DDR_DQ18 M0_DDR_DQ19 M0_DDR_DQ20 M0_DDR_DQ21 M0_DDR_DQ22 M0_DDR_DQ23

M0_DDR_DQ24 M0_DDR_DQ25 M0_DDR_DQ26 M0_DDR_DQ27 M0_DDR_DQ28 M0_DDR_DQ29 M0_DDR_DQ30 M0_DDR_DQ31

M8

H1

L8

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1 J9 L1 L9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13

M1_DDR_A14

M1_DDR_A15

M1_DDR_BA0 M1_DDR_BA1

M1_DDR_BA2

M1_DDR_CKE

M1_DDR_CS2

M1_DDR_ODT M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_RESET_N

M1_DDR_DQS2

M1_DDR_DQS_N2

M8

VREFCA

H1

VREFDQ

M1_DDR_DQS3

L8

ZQ

M1_DDR_DQS_N3

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

M1_DDR_DM2

VDD_7

R1

VDD_8

R9

VDD_9

M1_DDR_DM3

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

M1_DDR_DQ16

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

M1_DDR_DQ17

J1

NC_1

J9

NC_2

L1

M1_DDR_DQ18

NC_3

L9

NC_4

M1_DDR_DQ19

A9

VSS_1

B3

VSS_2

M1_DDR_DQ20

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

M1_DDR_DQ21

VSS_6

M1

VSS_7

M9

VSS_8

P1

M1_DDR_DQ22

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

M1_DDR_DQ23

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

M1_DDR_DQ24

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

M1_DDR_DQ25

G9

VSSQ_9

M1_DDR_DQ26 M1_DDR_DQ27 M1_DDR_DQ28 M1_DDR_DQ29 M1_DDR_DQ30 M1_DDR_DQ31

Hynix_DDR3_4Gb_29n

IC400

H5TQ4G63AFR-RDC

EAN63053201

N3

M0_DDR_A0 M0_DDR_A1 M0_DDR_A2 M0_DDR_A3 M0_DDR_A4 M0_DDR_A5 M0_DDR_A6 M0_DDR_A7 M0_DDR_A8

M0_DDR_A9 M0_DDR_A10 M0_DDR_A11 M0_DDR_A12 M0_DDR_A13 M0_DDR_A14 M0_DDR_A15

M0_DDR_BA0 M0_DDR_BA1 M0_DDR_BA2

M0_D_CLK

M0_D_CLKN M0_DDR_CKE

M0_DDR_CS1 M0_DDR_ODT

M0_DDR_RASN M0_DDR_CASN

M0_DDR_WEN

M0_DDR_RESET_N

M0_DDR_DQS0

H28 K31 J29 K27 K30 J28 K32 H31 J32 G30 L30 J30 L29 G31 J31 M28 L28 L31 K28 N28 N27 L27 M27 M31 G32 N32 M30 G29 F32

T31 P30 T30 P31 U30 N31 U31 N30 R31 T32 R30

P27 U29 P28 U27 R28 V28 P29 U28 T28 T27 R27

AA31 W31 AA30 W32 AB31 V31 AB32 V30 W30 Y30 Y31

Y28 AB27 V27 AB29 W28 AB28 W27 AA27 Y27 AA28 Y29

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8 M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14 M1_DDR_A15 M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2 M1_DDR_RASN M1_DDR_CASN M1_DDR_WEN M1_DDR_ODT M1_DDR_CKE M1_DDR_RESET_N M1_D_CLK M1_D_CLKN M1_DDR_CS1 M1_DDR_CS2

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7 M1_DDR_DM0 M1_DDR_DQS0 M1_DDR_DQS_N0

M1_DDR_DQ8 M1_DDR_DQ9 M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15 M1_DDR_DM1 M1_DDR_DQS1 M1_DDR_DQS_N1

M1_DDR_DQ16 M1_DDR_DQ17 M1_DDR_DQ18 M1_DDR_DQ19 M1_DDR_DQ20 M1_DDR_DQ21 M1_DDR_DQ22 M1_DDR_DQ23 M1_DDR_DM2 M1_DDR_DQS2 M1_DDR_DQS_N2

M1_DDR_DQ24 M1_DDR_DQ25 M1_DDR_DQ26 M1_DDR_DQ27 M1_DDR_DQ28 M1_DDR_DQ29 M1_DDR_DQ30 M1_DDR_DQ31 M1_DDR_DM3 M1_DDR_DQS3 M1_DDR_DQS_N3

M0_DDR_DQS_N0

M0_DDR_DQS_N1

M1_DDR_RESET_N

M1_DDR_DQS0

M1_DDR_DQS_N0

M1_DDR_DQS1

M1_DDR_DQS_N1

M1_DDR_DM0 M1_DDR_DM1

M0_DDR_DQS1

M0_DDR_DM0 M0_DDR_DM1

M0_DDR_DQ0 M0_DDR_DQ1 M0_DDR_DQ2 M0_DDR_DQ3 M0_DDR_DQ4 M0_DDR_DQ5 M0_DDR_DQ6 M0_DDR_DQ7

M0_DDR_DQ8 M0_DDR_DQ9

M0_DDR_DQ10 M0_DDR_DQ11 M0_DDR_DQ12 M0_DDR_DQ13 M0_DDR_DQ14 M0_DDR_DQ15

+1.5V_Bypass Cap Close to DDR Power Pin

AVDD_DDR

C400 0.1uF

C401 0.1uF

Hynix_DDR3_4Gb_29n

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8

M1_DDR_A9 M1_DDR_A10 M1_DDR_A11 M1_DDR_A12 M1_DDR_A13 M1_DDR_A14 M1_DDR_A15

M1_DDR_BA0 M1_DDR_BA1 M1_DDR_BA2

M1_D_CLK

M1_D_CLKN M1_DDR_CKE

M1_DDR_CS1 M1_DDR_ODT

M1_DDR_RASN M1_DDR_CASN

M1_DDR_WEN

M1_DDR_DQ0 M1_DDR_DQ1 M1_DDR_DQ2 M1_DDR_DQ3 M1_DDR_DQ4 M1_DDR_DQ5 M1_DDR_DQ6 M1_DDR_DQ7

M1_DDR_DQ8 M1_DDR_DQ9

M1_DDR_DQ10 M1_DDR_DQ11 M1_DDR_DQ12 M1_DDR_DQ13 M1_DDR_DQ14 M1_DDR_DQ15

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

C402 0.1uF

IC403

H5TQ4G63AFR-RDC

EAN63053201

DDR3

A0

4Gbit

A1

(x16)

A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

VREFCA

VREFDQ

ZQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

NC_1 NC_2 NC_3 NC_4

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

M8

H1

L8

ZQ

B2

D9

G7

K2

K8

N1

N9

R1

R9

A1

A8

C1

C9

D2

E9

F1

H2

H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9

B3

E1

G8

J2

J8

M1

M9

P1

P9

T1

T9

B1

B9

D1

D8

E2

E8

F9

G1

G9

Hynix_DDR3_4Gb_29n

IC401

H5TQ4G63AFR-RDC

EAN63053201

N3

DDR3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

+1.5V_Bypass Cap Close to DDR Power Pin

4Gbit (x16)

VREFCA

VREFDQ

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

AVDD_DDR

C403 0.1uF

C404 0.1uF

C405 0.1uF

Hynix_DDR3_4Gb_29n

IC404

H5TQ4G63AFR-RDC

EAN63053201

N3

M1_DDR_A0 M1_DDR_A1 M1_DDR_A2 M1_DDR_A3 M1_DDR_A4 M1_DDR_A5 M1_DDR_A6 M1_DDR_A7 M1_DDR_A8 M1_DDR_A9

M1_D_CLK

M1_D_CLKN

DDR3

A0

P7

4Gbit

A1

P3

(x16)

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

T7

A14

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M0_1_DDR_VREFDQ

M8

H1

L8

R403

ZQ

AVDD_DDR B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

240

C440

0.1uF

C441

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

SS_DDR3_4Gb_25n

Hynix_DDR3_4Gb_25n

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3

M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

IC401-*1

K4B4G1646D-BCMA

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13

NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

IC401-*2

H5TQ4G63CFR_RDC

EAN63391401

EAN63053202

M8

VREFCA

N3

M8

A0

VREFCA

P7

A1

P3

H1

A2

VREFDQ

N2

H1

A3

VREFDQ

P8

A4

P2

L8

A5

ZQ

R8

L8

A6

ZQ

R2

A7

T8

B2

A8

VDD_1

R3

B2

D9

A9

VDD_1

VDD_2

L7

D9

G7

A10/AP

VDD_2

VDD_3

R7

G7

K2

A11

VDD_3

VDD_4

N7

K2

K8

A12/BC

VDD_4

VDD_5

T3

K8

N1

A13

VDD_5

VDD_6

T7

N1

N9

A14

VDD_6

VDD_7

M7

N9

R1

NC_5

VDD_7

VDD_8

R1

R9

VDD_8

VDD_9

R9

M2

VDD_9

BA0

N8

BA1

M3

A1

BA2

VDDQ_1

A1

A8

VDDQ_1

VDDQ_2

A8

J7

C1

VDDQ_2

CK

VDDQ_3

K7

C1

C9

VDDQ_3

CK

VDDQ_4

K9

C9

D2

CKE

VDDQ_4

VDDQ_5

D2

E9

VDDQ_5

VDDQ_6

E9

L2

F1

VDDQ_6

CS

VDDQ_7

F1

K1

H2

VDDQ_7

ODT

VDDQ_8

H2

J3

H9

VDDQ_8

RAS

VDDQ_9

H9

K3

VDDQ_9

CAS

L3

J1

WE

NC_1

J1

J9

NC_1

NC_2

J9

T2

L1

NC_2

RESET

NC_3

L1

L9

NC_3

NC_4

L9

T7

NC_4

NC_6

F3

DQSL

G3

DQSL

A9

VSS_1

A9

C7

B3

VSS_1

DQSU

VSS_2

B3

B7

E1

VSS_2

DQSU

VSS_3

E1

G8

VSS_3

VSS_4

G8

E7

J2

VSS_4

DML

VSS_5

J2

D3

J8

VSS_5

DMU

VSS_6

J8

M1

VSS_6

VSS_7

M1

E3

M9

VSS_7

DQL0

VSS_8

M9

F7

P1

VSS_8

DQL1

VSS_9

P1

F2

P9

VSS_9

DQL2

VSS_10

P9

F8

T1

VSS_10

DQL3

VSS_11

T1

H3

T9

VSS_11

DQL4

VSS_12

T9

H8

VSS_12

DQL5

G2

DQL6

H7

B1

DQL7

VSSQ_1

B1

B9

VSSQ_1

VSSQ_2

B9

D7

D1

VSSQ_2

DQU0

VSSQ_3

D1

C3

D8

VSSQ_3

DQU1

VSSQ_4

D8

C8

E2

VSSQ_4

DQU2

VSSQ_5

E2

C2

E8

VSSQ_5

DQU3

VSSQ_6

E8

A7

F9

VSSQ_6

DQU4

VSSQ_7

F9

A2

G1

VSSQ_7

DQU5

VSSQ_8

G1

B8

G9

VSSQ_8

DQU6

VSSQ_9

G9

A3

VSSQ_9

DQU7

N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3

M7

M2 N8 M3

J7 K7 K9

L2 K1 J3 K3 L3

T2

F3 G3

C7 B7

E7 D3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

SS_DDR3_2Gb

K4B2G1646Q-BCMA

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13

NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

Hynix_DDR3_2Gb

IC401-*4

IC401-*3

H5TQ2G63FFR-RDC

EAN63648701

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

N2

H1

A3

VREFDQ

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

M1_1_DDR_VREFDQ

M8

VREFCA

H1

VREFDQ

L8

R419

240

C490

0.1uF

C491

0.1uF

DDR3 1.5V bypass Cap - Place these caps near Memory

Hynix_DDR3_4Gb_25n

SS_DDR3_4Gb_25n

IC404-*2

IC404-*1

H5TQ4G63CFR_RDC

K4B4G1646D-BCMA

EAN63053202

EAN63391401

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12/BC

T3

A13

M7

NC_5

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE

L2

CS

K1

ODT

J3

RAS

K3

CAS

L3

WE

T2

RESET

F3

DQSL

G3

DQSL

C7

DQSU

B7

DQSU

E7

DML

D3

DMU

E3

DQL0

F7

DQL1

F2

DQL2

F8

DQL3

H3

DQL4

H8

DQL5

G2

DQL6

H7

DQL7

D7

DQU0

C3

DQU1

C8

DQU2

C2

DQU3

A7

DQU4

A2

DQU5

B8

DQU6

A3

DQU7

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

ZQ

B2

VDD_1

D9

VDD_2

G7

VDD_3

K2

VDD_4

K8

VDD_5

N1

VDD_6

N9

VDD_7

R1

VDD_8

R9

VDD_9

A1

VDDQ_1

A8

VDDQ_2

C1

VDDQ_3

C9

VDDQ_4

D2

VDDQ_5

E9

VDDQ_6

F1

VDDQ_7

H2

VDDQ_8

H9

VDDQ_9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

T7

NC_6

A9

VSS_1

B3

VSS_2

E1

VSS_3

G8

VSS_4

J2

VSS_5

J8

VSS_6

M1

VSS_7

M9

VSS_8

P1

VSS_9

P9

VSS_10

T1

VSS_11

T9

VSS_12

B1

VSSQ_1

B9

VSSQ_2

D1

VSSQ_3

D8

VSSQ_4

E2

VSSQ_5

E8

VSSQ_6

F9

VSSQ_7

G1

VSSQ_8

G9

VSSQ_9

R8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

F3

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

SS_DDR3_2Gb

K4B2G1646Q-BCMA

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13

NC_5

BA0 BA1 BA2

CK CK CKE

CS ODT RAS CAS WE

RESET

DQSL DQSL

DQSU DQSU

DML DMU

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

Hynix_DDR3_2Gb

IC404-*4

IC404-*3

H5TQ2G63FFR-RDC

EAN63648701

EAN63667401

M8

N3

VREFCA

A0

P7

A1

P3

A2

H1

N2

VREFDQ

A3

P8

A4

P2

A5

R8

L8

A6

ZQ

R2

A7

T8

A8

R3

B2

A9

VDD_1

L7

D9

A10/AP

VDD_2

R7

G7

A11

VDD_3

K2

N7

A12/BC

VDD_4

K8

T3

VDD_5

A13

T7

N1

A14

VDD_6

N9

M7

VDD_7

NC_5

R1

VDD_8

R9

M2

VDD_9

BA0

N8

BA1

M3

BA2

A1

VDDQ_1

A8

J7

VDDQ_2

CK

C1

K7

VDDQ_3

CK

C9

K9

VDDQ_4

CKE

D2

VDDQ_5

E9

L2

VDDQ_6

CS

F1

K1

VDDQ_7

ODT

H2

J3

VDDQ_8

RAS

H9

K3

VDDQ_9

CAS

L3

WE

J1

NC_1

J9

T2

NC_2

RESET

L1

NC_3

L9

NC_4

T7

F3

NC_6

DQSL

G3

DQSL

A9

C7

VSS_1

DQSU

B3

B7

VSS_2

DQSU

E1

VSS_3

G8

E7

VSS_4

DML

J2

D3

VSS_5

DMU

J8

VSS_6

M1

E3

VSS_7

DQL0

M9

F7

VSS_8

DQL1

P1

F2

VSS_9

DQL2

P9

F8

VSS_10

DQL3

T1

H3

VSS_11

DQL4

T9

H8

VSS_12

DQL5

G2

DQL6

H7

DQL7

B1

VSSQ_1

B9

D7

VSSQ_2

DQU0

D1

C3

VSSQ_3

DQU1

D8

C8

VSSQ_4

DQU2

E2

C2

VSSQ_5

DQU3

E8

A7

VSSQ_6

DQU4

F9

A2

VSSQ_7

DQU5

G1

B8

VSSQ_8

DQU6

G9

A3

VSSQ_9

DQU7

VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9

VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9

VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8

VSS_9 VSS_10 VSS_11 VSS_12

VSSQ_1 VSSQ_2 VSSQ_3 VSSQ_4 VSSQ_5 VSSQ_6 VSSQ_7 VSSQ_8 VSSQ_9

ZQ

AVDD_DDR B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

J1

NC_1

J9

NC_2

L1

NC_3

L9

NC_4

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

AR407 56 1/16W

AR408 56 1/16W

AR409 56 1/16W

AR410 56 1/16W

AR411 56 1/16W

AR412 56 1/16W

AR413 56 1/16W

OPT

R405

M0_DDR_RESET_N

OPT

R422

1%

+3.3V_NORMAL

M1_DDR_RESET_N

CIS2 1J121

DDR_VTT

M0_DDR_CKE

M1_DDR_CKE

C544 10uF

L401

10V

C453 0.1uF

C454 0.1uF

C455 0.1uF

C456 0.1uF

C457 0.1uF

C458 0.1uF

C459 0.1uF

C460 0.1uF

C461 0.1uF

C462 0.1uF

C463 0.1uF

C464 0.1uF

C465 0.1uF

C466 0.1uF

R412 56 1%

R413 56 1%

R427 56 1%

R428 56 1%

C477

0.01uF 50V

1K

M0_D_CLK

M0_D_CLKN

1K

C497

0.01uF 50V

M1_D_CLKN

R418

R433

M1_D_CLK

THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION. FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.

+1.5V_Bypass Cap Close to DDR Power Pin

AVDD_DDR

C446 0.1uF

C444 0.1uF

C445 0.1uF

+1.5V_Bypass Cap Close to DDR Power Pin

AVDD_DDR

C475 0.1uF

C480 0.1uF

C476 0.1uF

LM14A

LM14A DDR

BSD-15Y-LM14A-004_00-HD

2014-12-30

04