Lenovo Thinkpad S5 E560P Schematic

Compal

Model Name : CIMS1

A A

File Name : LA-D214P

B B

Confidentia

Intel Kaby Lake-H Processor + PCH with DDR4

+ NVIDA N17P-G1 GPU

C C

Rev. 1.0

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Cover Sheet

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet of

1 66Monday, November 28, 2016

1.0

HDMI level shif t er

NV N17P-G1 50W

PEG x8

29mm * 29mm

1 1

GDDR5 * 4 VRAM 128M*32

Intel

Kaby Lake H

45W

eDP Connector (FHD/UHD)

HDMI Connector

2 2

Card Reader

BayHub OZ777

2.97G PS8407

SPI ROM

eDP *4 Lane

HDMI *4 Lane

PCI-E

BGA

DMI

SPI

Memory Bus

DDR4 2400MHz\2133MHz

Memory Bus

DDR4 2400MHz\2133MHz

HD Audio

Audio Codec

Conexant CX11771

A-ch DDR4-SO-DIMM X1

B-ch DDR4-SO-DIMM X1

2Channel Speaker

Digital MIC

Audio combo Jack

LAN

Realtek RTL8111GUL

KBL PCH-H

USB 3.0

USB PORT 3.0 (AOU)

USB 2.0

SATA

USB PORT 3.0

3 3

ENE KBC9022

Int.KBD

with BKLIT

Click Pad

Track Point

4 4

LID switch

G-Sensor

ST LIS3DSH

Thermal Sensor

Fintek F75303M

CPU & RAM

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

PCI-E

SATA

SATA/PCIEx4

Deciphered Date

CMOS Camera

M.2 WLAN / BT

SATA 3.0 HDD CONN

M.2 SSD (2280)

Compal Electronics, Inc.

Title

Block Diagram

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet of

1.0

2 66Monday, November 28, 2016

1.0

BOARD ID Table

Voltage Rails

+1.8VS +5VS

+3VS

power plane

A A

State

S5 S4/AC

S5 S4/ Battery only

B B

S5 S4/AC & Battery don't exist

EC SM Bus1 address

Device

Smart Battery Charger

+5VALW +3VALW

+1VALW

O O O

X X

+1.2V_VDDQ +2.5V +1.0V_VCCST

O O O

X X X

CPU

Address

16H 12H

UC1

E S

KBL-H ES 2.7G QL2X

CPU1@ SA0000A1310

+CPU_CORE +VCCGT +VCCIO +VCC_SA +0.6VS_VTT +1.0VS_VCCSTG +NVVDD +NVVDDS +1.8VAON_VGA +1.8VS_VGA +1.0VS_VGA +1.5VS_VGA

UC1

E S

KBL-H ES 2.4GQL3X

CPU2@ SA0000A1510

UC1

Q S Q S

KBL-H i5-7300HQ QLM7

CPU3@ SA0000AD800

STATE

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

USB 2.0 Port Table

Port

1 2 3 4 5 6 7 8 9 10 11 12 13 14

UC1

KBL-H ii7-7700HQ QLM5

CPU4@ SA0000AD700

PCH

E S

H y n i x

Q S

KBL-H QLF9

PCH2@ SA0000ADB00

U30

Q S

N17P-G1

GPU2@ SA0000A0620

ZZZ

S a m s u n g

Samsung_2GB

X76S2G@ X7664939L22

R 3

KBL-H QLF9

PCH3@ SA0000ADB20

U30

P S

N17P-G1

GPU3@ SA0000A0630

U30

N17P-G1

GPU4@ SA0000A0640

ZZZ

H y n i x

Hynix_4GB

X76H4G@ X7664939L23

R 3

VRAM

LAN

ZZZ

S a m s u n g

Samsung_4GB

X76S4G@ X7664939L24

BOM Structure Table

EC SM Bus2 address

Device

Thermal Sensor Fintek F75303M

C C

Thermal Sensor ON-semi ADM1032

Nvidia N16P-GT

APS ST LIS3DHTR CPU Intel SKL-H

Address(7bit)

0x9A

4CH

96H 30h/31h

KBL-H QJGE

PCH1@ SA00008RM60

dGPU

U30

PCH SM Bus address

N17P-G1

Device

DDR DIMM1 DDR DIMM2

Synaptics Inter Touch Click Pad

PCB

ZZZ

LA-D214P

PCB

DAZ1X500100

D D

Address(7bit)

A0H A2H

2CH

GPU1@ SA0000A0600

VRAM

ZZZ

Hynix_2GB

X76H2G@ X7664939L21

ZZZ

F o r E M I B O M

X4E@ X4EA5839L01

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

HIGH HIGH HIGH

LOW

HIGH

LOWLOW

3 External USB Port

USB 3.0 Port (SB-Right) USB 3.0 Port (SB-Right)

USB 3.0 AOU Port (MB-Left)

2D Camera

M.2 BT

UC1

i 5 - R 3 i 7 - R 3

KBL-H i5-7300HQ QLM7

CPU5@ SA0000AD840

BTO Item

UC1

KBL-H ii7-7700HQ QLM5

CPU6@ SA0000AD740

BOM Structure

Connector ME@ Unpop

@ DIS@Nviida GPU

UMA@Intel UMA

EMI Un-Mount @EMI@ EMI Mount Hynix 2G VRAM Samsung 2G VRAM

EMI@

X76H2G@

X76S2G@

Trick Point TP@ LAN Switching mode SWR@

TPM (LNV UMA Only) N17P-G1 For EMI BOM For DGPU HDMI

Nviida GPU discharge @DIS@

TPM@ GPU1@ X4E@

@HDMI@

ESD requirement @ESD@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORM ATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR W RITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HIGH

OC# Mapping

OC0#

OC2#

ON ON ON

OFF

OFFLOW LOW LOW

OFF

USB 3.0 Port Table

Port

USB 3.0 Port (SB-Right)

3 4 5

USB 3.0 Port (MB-Left)

6 7 8 9 10

SATA Port Table

Port

M.2 SSD

0 1 2

HDD

3 4 5

FVT

SDV

V V

V V V V V V V V V

SIT

SVT

Compal Secret Data

Deciphered Date

2016/05/13 2017/12/31

Deciphered Date

Board ID

0 1 2 3 4 5 6 7

PCIE Port Table

Port

Lane

1 2 3 4 5 6 7 8

13 14 15 16 17 18 19 20

M.2 WLAN LAN

0 1

M.2 PCIEx4

2 3

Card Reader

Title

Size Document Number Re v

Custom

Date: Sheet of

PCB Revision

0.1

0.2

0.3

0.4

1.0

Compal Electronics, Inc.

Compal Electronics, Inc. Notes List

Notes List

Notes List Merlyn2 LA-D214P

Merlyn2 LA-D214P

1.0

3 66Monday, November 28, 2016

1.0

H_4P0

H_3P3

H_2P3

H_2P5

H_4P0

H10

H_2P3

H14

H15

H_2P5

H20

H19

H_1P2

H25

H_2P1N

+RTCBATT

RTCRST#

B+

+3VLP

EN_3V (PIN112) EN_5V (PIN107)

+5VALW /+3VALW +3VALW_DSW

SUSACK#

+1.0VALW +1.0VALW_ PRIM

DSW_PWR OK

EC_RSMRST#

AC_PRESENT

ON/OFF

H7 H_4P0

H_4P0

H_2P7X2P5

H17 H_2P5

H_2P5

H23 H_2P3

H_2P3

H28 H_2P3

H_2P3

H21 H_2P9X2P5N

H_2P9X2P5N

H12

H3 H_4P0

H_4P0

H_2P7X2P5

H18 H_3P3

H_3P3

H24 H_3P3

H_3P3

H29 H_3P3

H_3P3

H_2P9X2P5N

BARCODE_12X4

H13

H_2P7X2P5

H_4P0

H11

H_4P0

H16

H_2P3

A A

H22

H_2P3N

H_2P3

H27

H_2P5

H26

H_2P5N

BARCODE_8X8

PBTN_OUT# (PIN106)

BARCODE_20X4

FD1

B B

FIDUCIAL_C40M80

FD3

FIDUCIAL_C40M80

BARCODE_10X10

FD2

FIDUCIAL_C40M80

FD4

FIDUCIAL_C40M80

PM_SLP_S5#

PM_SLP_S4#

SYSON (PIN95)

+1.0V_VCCST

+2.5V

+1.2V_VDDQ

PM_SLP_S3#

SUSP# (PIN116)

+1.0VS_VCCSTG

+VCCIO

+5VS/+3VS/+1.8VS

EC_VCCST_PG (PIN18)

VR_ON (PIN120)

C C

SM_PG_CTRL

+0.6VS_VT T

+VCCSA

tPCH01_Min : 9 ms

tPCH06_Min : 200 us

G3->S0

tPCH04_Min : 9 ms

tPCH34_Max : 20 ms

tPCH02_Min : 10 ms

tPCH03_Min : 10 ms (VccPrimary stable to RSMRST# high)

tPLT02_Min : 0 ms Max : 90 ms

tPCH43_Min : 95 ms

Minimum duration of PWRBTN# assertion = 16mS. PWRBTN# can assert before or after RSMRST#

T = 30msec

T = 40msec

tCPU04 Min : 100 ns

tCPU10 Min : 1 ms

T <=10msec

T = 20msec

tCPU19 Max : 100 ns

tCPU18 Max : 35 us

tCPU09 Min : 1 ms

+VCCCORE

+VCCGT

VGATE

PCH_PWROK (PIN32)

H_CPUPWRGD

SYS_PWROK (PIN121)

T = 100msec

SUS_STAT#

PLTRST#

D D

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRI ETARY PROPERTY OF COMPAL ELECTRONICS, I NC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D

AND TRADE SECRET I NFORMATION. THIS SHEET MAY NOT BE TRANSFERED FRO M THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIO R WRITTEN CONSENT OF COMPAL ELECT RONICS, INC.

Compal Secret Data

Deciphered Date

2016/05/13 2017/12/31

Deciphered Date

Compal Electronics, Inc.

Title

Screw Hole

Size

Document Number Rev

Custom

Merlyn2 LA-D214P

Date: Sheet of

4 66Monday, November 28, 2016

1.0

1 1

2 2

HDMI

SKYLAKE_HALO

UC1D

CPU_DP1_P0[39] CPU_DP1_N0[39] CPU_DP1_P1[39] CPU_DP1_N1[39] CPU_DP1_P2[39] CPU_DP1_N2[39] CPU_DP1_P3[39] CPU_DP1_N3[39]

K36 K37

J35

J34 H37 H36

J37

J38 D27

E27 H34

H33 F37 G38 F34 F35 E37 E36

F26 E26

C34 D34 B36 B34 F33 E33 C33 B33

A27 B27

DDI1_TXP[0] DDI1_TXN[0] DDI1_TXP[1] DDI1_TXN[1] DDI1_TXP[2] DDI1_TXN[2] DDI1_TXP[3] DDI1_TXN[3]

DDI1_AUXP DDI1_AUXN

DDI2_TXP[0] DDI2_TXN[0] DDI2_TXP[1] DDI2_TXN[1] DDI2_TXP[2] DDI2_TXN[2] DDI2_TXP[3] DDI2_TXN[3]

DDI2_AUXP DDI2_AUXN

DDI3_TXP[0] DDI3_TXN[0] DDI3_TXP[1] DDI3_TXN[1] DDI3_TXP[2] DDI3_TXN[2] DDI3_TXP[3] DDI3_TXN[3]

DDI3_AUXP DDI3_AUXN

SKL-H_BGA1440

BGA1440

4 OF 14

REV = 1

EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3]

EDP_AUXP EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK PROC_AUDIO_SDI

PROC_AUDIO_SDO

D29 E29 F28 E28 B29 A29 B28 C28

C26 B26

A33

EDP_COMP

D37

G27 G25

CPU_DISPA_SDI

G29

EDP_TXP0 [34] EDP_TXN0 [34] EDP_TXP1 [34] EDP_TXN1 [34] EDP_TXN2 [34] EDP_TXP2 [34] EDP_TXN3 [34] EDP_TXP3 [34]

EDP_AUXP [34]

EDP_AUXN [34]

CAD note: Trace width=20 mils,Spacing=25mil,Max length=100mils

R2 20_0402_1%

eDP

+VCCIO

R124.9_0402_1%

CPU_DISPA_BCLK_R [18] CPU_DISPA_SDO_R [18]

CPU_DISPA_SDI_R [18]

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Date: Sheet o f

Compal Electronics, Inc.

KBL-H(1/8)DDI,EDP

Custom

Merlyn2 LA-D214P

1.0

5 66Monday, November 28, 2016

1.0

Interleaved Memory

1 1

REV = 1

SKYLAKE _HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]

DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1]

DDR0_CKP[1] DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3] DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3] DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0] DDR0_DQSN[1]

DDR0_DQSP[0] DDR0_DQSP[1]

DDR0_DQSP[8] DDR0_DQSN[8]

AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1

AT1 AT2 AT3 AT5

AD5 AE2 AD2 AE5

AD3 AE4 AE1 AD4

AH5 AH1 AU1

AH4 AG4 AD1

AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3

AG3 AU5

BR5 BL3 BG3 BD3 AB3 V3 R3 M3

BP5 BK3 BF3 BC3 AA3 U3 P3 L3

AY3 BA3

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK#1 DDR_A_CLK1

DDR_A_CKE0 DDR_A_CKE1

DDR_A_CS#0 DDR_A_CS#1

DDR_A_ODT0 DDR_A_ODT1

DDR_A_BA0 DDR_A_BA1 DDR_A_BG0

DDR_A_RAS# DDR_A_WE# DDR_A_CAS#

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT#

DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7

DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7

DDR_A_CLK0 [13] DDR_A_CLK#0 [13] DDR_A_CLK#1 [13] DDR_A_CLK1 [13]

DDR_A_CKE0 [13] DDR_A_CKE1 [13]

DDR_A_CS#0 [13] DDR_A_CS#1 [13]

DDR_A_ODT0 [13] DDR_A_ODT1 [13]

DDR_A_BA0 [13] DDR_A_BA1 [13] DDR_A_BG0 [13]

DDR_A_RAS# [13] DDR_A_WE# [13] DDR_A_CAS# [13]

DDR_A_MA0 [13] DDR_A_MA1 [13] DDR_A_MA2 [13] DDR_A_MA3 [13] DDR_A_MA4 [13] DDR_A_MA5 [13] DDR_A_MA6 [13] DDR_A_MA7 [13] DDR_A_MA8 [13] DDR_A_MA9 [13] DDR_A_MA10 [13] DDR_A_MA11 [13] DDR_A_MA12 [13] DDR_A_MA13 [13] DDR_A_BG1 [13] DDR_A_ACT# [13]

DDR_A_PAR [13] DDR_A_ALERT# [13]

DDR_A_DQS#0 [13] DDR_A_DQS#1 [13] DDR_A_DQS#2 [13] DDR_A_DQS#3 [13] DDR_A_DQS4 [13] DDR_A_DQS5 [13] DDR_A_DQS6 [13] DDR_A_DQS7 [13]

DDR_A_DQS0 [13] DDR_A_DQS1 [13] DDR_A_DQS2 [13] DDR_A_DQS3 [13] DDR_A_DQS#4 [13] DDR_A_DQS#5 [13] DDR_A_DQS#6 [13] DDR_A_DQS#7 [13]

DDR_B_D[0..15][14]

DDR_B_D[16..31][14]

DDR_B_D[32..47][14]

DDR_B_D[48..63][14]

12 12 12

R28121_0402_1% R2975_0402_1% R30100_0402_1%

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

DDR1_DQ[40]/DDR1_DQ[24]

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

DDR1_DQ[46]/DDR1_DQ[30]

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

DDR1_DQ[50]

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

DDR1_DQ[54]

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

DDR1_DQ[58]

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

DDR1_DQ[62]

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

DDR_RCOMP[0]

DDR_RCOMP[1]

DDR_RCOMP[2]

SKL-H_BGA1440

DDR_A_D[0..15][13]

DDR_A_D[16..31][13]

DDR_A_D[32..47][13]

2 2

DDR_A_D[48..63][13]

3 3

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

UC1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

DDR0_DQ[40]/DDR1_DQ[8]

DDR0_DQ[41]/DDR1_DQ[9]

DDR0_DQ[42]/DDR1_DQ[10]

DDR0_DQ[43]/DDR1_DQ[11]

DDR0_DQ[44]/DDR1_DQ[12]

DDR0_DQ[45]/DDR1_DQ[13]

DDR0_DQ[46]/DDR1_DQ[14]

DDR0_DQ[47]/DDR1_DQ[15]

DDR0_DQ[48]/DDR1_DQ[32]

DDR0_DQ[49]/DDR1_DQ[33]

DDR0_DQ[50]/DDR1_DQ[34]

DDR0_DQ[51]/DDR1_DQ[35]

DDR0_DQ[52]/DDR1_DQ[36]

DDR0_DQ[53]/DDR1_DQ[37]

DDR0_DQ[54]/DDR1_DQ[38]

DDR0_DQ[55]/DDR1_DQ[39]

DDR0_DQ[56]/DDR1_DQ[40]

DDR0_DQ[57]/DDR1_DQ[41]

DDR0_DQ[58]/DDR1_DQ[42]

DDR0_DQ[59]/DDR1_DQ[43]

DDR0_DQ[60]/DDR1_DQ[44]

DDR0_DQ[61]/DDR1_DQ[45]

DDR0_DQ[62]/DDR1_DQ[46]

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKL-H_BGA1440

SKYLAKE _HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3]

DDR CHANNEL B

2 OF 14

REV = 1 ?

DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1]

DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3]

DDR1_CKE[0]

DDR1_CKE[1]

DDR1_CKE[2]

DDR1_CKE[3]

DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3]

DDR1_ODT[0]

DDR1_ODT[1]

DDR1_ODT[2]

DDR1_ODT[3]

DDR1_MA[3] DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6] DDR1_DQSN[7]

DDR1_DQSP[6] DDR1_DQSP[7]

DDR1_DQSP[8] DDR1_DQSN[8]

DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ

DDR_B_CLK0

AM9

DDR_B_CLK#0

AN9

DDR_B_CLK#1

AM8

DDR_B_CLK1

AM7 AM11 AM10 AJ10 AJ11

DDR_B_CKE0

AT8

DDR_B_CKE1

AT10 AT7 AT11

DDR_B_CS#0

AF11

DDR_B_CS#1

AE7 AF10 AE10

DDR_B_ODT0

AF7

DDR_B_ODT1

AE8 AE9 AE11

DDR_B_RAS#

AH10

DDR_B_WE#

AH11

DDR_B_CAS#

AF8

DDR_B_BA0

AH8

DDR_B_BA1

AH9

DDR_B_BG0

AR9

DDR_B_MA0

AJ9

DDR_B_MA1

AK6

DDR_B_MA2

AK5

DDR_B_MA3

AL5

DDR_B_MA4

AL6

DDR_B_MA5

AM6

DDR_B_MA6

AN7

DDR_B_MA7

AN10

DDR_B_MA8

AN8

DDR_B_MA9

AR11

DDR_B_MA10

AH7

DDR_B_MA11

AN11

DDR_B_MA12

AR10

DDR_B_MA13

AF9

DDR_B_BG1

AR7

DDR_B_ACT#

AT9 AJ7

AR8

DDR_B_DQS#0

BP9

DDR_B_DQS#1

BL9

DDR_B_DQS#2

BG9

DDR_B_DQS#3

BC9

DDR_B_DQS#4

AC9

DDR_B_DQS#5

DDR_B_DQS#6

DDR_B_DQS#7

DDR_B_DQS0

BR9

DDR_B_DQS1

BJ9

DDR_B_DQS2

BF9

DDR_B_DQS3

BB9

DDR_B_DQS4

AA9

DDR_B_DQS5

DDR_B_DQS6

DDR_B_DQS7

L9 AW9

AY9

BN13 BP13 BR13

Trace width/Spacing >= 20mils

+0.6V_VREFCA +0.6V_A_VREFDQ +0.6V_B_VREFDQ

DDR_B_CLK0 [14] DDR_B_CLK#0 [14] DDR_B_CLK#1 [14] DDR_B_CLK1 [14]

DDR_B_CKE0 [14] DDR_B_CKE1 [14]

DDR_B_CS#0 [14] DDR_B_CS#1 [14]

DDR_B_ODT0 [14] DDR_B_ODT1 [14]

DDR_B_RAS# [14] DDR_B_WE# [14] DDR_B_CAS# [14]

DDR_B_BA0 [14] DDR_B_BA1 [14] DDR_B_BG0 [14]

DDR_B_MA0 [14] DDR_B_MA1 [14] DDR_B_MA2 [14] DDR_B_MA3 [14] DDR_B_MA4 [14] DDR_B_MA5 [14] DDR_B_MA6 [14] DDR_B_MA7 [14] DDR_B_MA8 [14] DDR_B_MA9 [14] DDR_B_MA10 [14] DDR_B_MA11 [14] DDR_B_MA12 [14] DDR_B_MA13 [14] DDR_B_BG1 [14] DDR_B_ACT# [14]

DDR_B_PAR [14] DDR_B_ALERT# [14]

DDR_B_DQS#0 [14] DDR_B_DQS#1 [14] DDR_B_DQS#2 [14] DDR_B_DQS#3 [14] DDR_B_DQS#4 [14] DDR_B_DQS#5 [14] DDR_B_DQS#6 [14] DDR_B_DQS#7 [14]

DDR_B_DQS0 [14] DDR_B_DQS1 [14] DDR_B_DQS2 [14] DDR_B_DQS3 [14] DDR_B_DQS4 [14] DDR_B_DQS5 [14] DDR_B_DQS6 [14] DDR_B_DQS7 [14]

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE S ECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL E LECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

KBL-H(2/8)DDR4

Size

Document Number Re v

Merlyn2 LA-D214P

Date: Sheet of

Monday, November 28, 2016

Date: Sheet of

Monday, November 28, 2016

Date: Sheet of

Monday, November 28, 2016

1.0

1 1

PCIE_CRX_GTX_P7[23] PCIE_CRX_GTX_N7[23]

PCIE_CRX_GTX_P6[23] PCIE_CRX_GTX_N6[23]

PCIE_CRX_GTX_P5[23] PCIE_CRX_GTX_N5[23]

PCIE_CRX_GTX_P4[23] PCIE_CRX_GTX_N4[23]

PCIE_CRX_GTX_P3[23] PCIE_CRX_GTX_N3[23]

PCIE_CRX_GTX_P2[23] PCIE_CRX_GTX_N2[23]

PCIE_CRX_GTX_P1[23] PCIE_CRX_GTX_N1[23]

PCIE_CRX_GTX_P0[23]

2 2

3 3

PCIE_CRX_GTX_N0[23]

1 2

R31 24.9_0402_1%

DMI_CRX_PTX_P0[15] DMI_CRX_PTX_N0[15]

DMI_CRX_PTX_P1[15] DMI_CRX_PTX_N1[15]

DMI_CRX_PTX_P2[15] DMI_CRX_PTX_N2[15]

DMI_CRX_PTX_P3[15] DMI_CRX_PTX_N3[15]

+VCCIO

CAD note: Trace width=12 mils,Spacing=15mil,Max length=400mils

PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7

PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6

PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5

PCIE_CRX_GTX_P4 PCIE_CRX_GTX_N4

PCIE_CRX_GTX_P3 PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P2 PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P0 PCIE_CRX_GTX_N0

PEG_RCOMP

DMI_CRX_PTX_P0 DMI_CRX_PTX_N0

DMI_CRX_PTX_P1 DMI_CRX_PTX_N1

DMI_CRX_PTX_P2 DMI_CRX_PTX_N2

DMI_CRX_PTX_P3 DMI_CRX_PTX_N3

D25

D23

D21

D19

D17

D15

D13

D11

E25

E24 F24

E23

E22 F22

E21

E20 F20

E19

E18 F18

E17 F16

E16

E15 F14

E14

E13 F12

E12

E11 F10

E10

D8 E8

E6 F6

D5 E5

J8 J9

UC1C

PEG_RXP[0] PEG_RXN[0]

PEG_RXP[1] PEG_RXN[1]

PEG_RXP[2] PEG_RXN[2]

PEG_RXP[3] PEG_RXN[3]

PEG_RXP[4] PEG_RXN[4]

PEG_RXP[5] PEG_RXN[5]

PEG_RXP[6] PEG_RXN[6]

PEG_RXP[7] PEG_RXN[7]

PEG_RXP[8] PEG_RXN[8]

PEG_RXP[9] PEG_RXN[9]

PEG_RXP[10] PEG_RXN[10]

PEG_RXP[11] PEG_RXN[11]

PEG_RXP[12] PEG_RXN[12]

PEG_RXP[13] PEG_RXN[13]

PEG_RXP[14] PEG_RXN[14]

PEG_RXP[15] PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0] DMI_RXN[0]

DMI_RXP[1] DMI_RXN[1]

DMI_RXP[2] DMI_RXN[2]

DMI_RXP[3] DMI_RXN[3]

SKL-H_BGA1440

SKYLAKE_HALO

BGA1440

3 OF 14

PEG_TXP[0]

PEG_TXN[0]

PEG_TXP[1]

PEG_TXN[1]

PEG_TXP[2]

PEG_TXN[2]

PEG_TXP[3]

PEG_TXN[3]

PEG_TXP[4]

PEG_TXN[4]

PEG_TXP[5]

PEG_TXN[5]

PEG_TXP[6]

PEG_TXN[6]

PEG_TXP[7]

PEG_TXN[7]

PEG_TXP[8]

PEG_TXN[8]

PEG_TXP[9]

PEG_TXN[9]

PEG_TXP[10] PEG_TXN[10]

PEG_TXP[11] PEG_TXN[11]

PEG_TXP[12] PEG_TXN[12]

PEG_TXP[13] PEG_TXN[13]

PEG_TXP[14] PEG_TXN[14]

PEG_TXP[15] PEG_TXN[15]

DMI_TXP[0] DMI_TXN[0]

DMI_TXP[1] DMI_TXN[1]

DMI_TXP[2] DMI_TXN[2]

DMI_TXP[3] DMI_TXN[3]

B25 A25

B24 C24

B23 A23

B22 C22

B21 A21

B20 C20

B19 A19

B18 C18

A17 B17

C16 B16

A15 B15

C14 B14

A13 B13

C12 B12

A11 B11

C10 B10

B8 A8

C6 B6

B5 A5

D4 B4

?REV = 1

PCIE_CTX_GRX_P7 PCIE_CTX_GRX_N7

PCIE_CTX_GRX_P6 PCIE_CTX_GRX_N6

PCIE_CTX_GRX_P5 PCIE_CTX_GRX_N5

PCIE_CTX_GRX_P4 PCIE_CTX_GRX_N4

PCIE_CTX_GRX_P3 PCIE_CTX_GRX_N3

PCIE_CTX_GRX_P2 PCIE_CTX_GRX_N2

PCIE_CTX_GRX_P1 PCIE_CTX_GRX_N1

PCIE_CTX_GRX_P0 PCIE_CTX_GRX_N0

DMI_CTX_PRX_P0 DMI_CTX_PRX_N0

DMI_CTX_PRX_P1 DMI_CTX_PRX_N1

DMI_CTX_PRX_P2 DMI_CTX_PRX_N2

DMI_CTX_PRX_P3 DMI_CTX_PRX_N3

12 12

DMI_CTX_PRX_P0 [15] DMI_CTX_PRX_N0 [15]

DMI_CTX_PRX_P1 [15] DMI_CTX_PRX_N1 [15]

DMI_CTX_PRX_P2 [15] DMI_CTX_PRX_N2 [15]

DMI_CTX_PRX_P3 [15] DMI_CTX_PRX_N3 [15]

C40.22U_0201_6.3V6M DIS@ C50.22U_0201_6.3V6M DIS@

C60.22U_0201_6.3V6M DIS@ C70.22U_0201_6.3V6M DIS@

C80.22U_0201_6.3V6M DIS@ C90.22U_0201_6.3V6M DIS@

C100.22U_0201_6.3V6M DIS@ C110.22U_0201_6.3V6M DIS@

C120.22U_0201_6.3V6M DIS@ C130.22U_0201_6.3V6M DIS@

C140.22U_0201_6.3V6M DIS@ C150.22U_0201_6.3V6M DIS@

C160.22U_0201_6.3V6M DIS@ C170.22U_0201_6.3V6M DIS@

C180.22U_0201_6.3V6M DIS@ C190.22U_0201_6.3V6M DIS@

PCIE_CTX_C_GRX_P7 [23]

PCIE_CTX_C_GRX_N7 [23]

PCIE_CTX_C_GRX_P6 [23]

PCIE_CTX_C_GRX_N6 [23]

PCIE_CTX_C_GRX_P5 [23]

PCIE_CTX_C_GRX_N5 [23]

PCIE_CTX_C_GRX_P4 [23]

PCIE_CTX_C_GRX_N4 [23]

PCIE_CTX_C_GRX_P3 [23]

PCIE_CTX_C_GRX_N3 [23]

PCIE_CTX_C_GRX_P2 [23]

PCIE_CTX_C_GRX_N2 [23]

PCIE_CTX_C_GRX_P1 [23]

PCIE_CTX_C_GRX_N1 [23]

PCIE_CTX_C_GRX_P0 [23]

PCIE_CTX_C_GRX_N0 [23]

4 4

Security Classification

2016/05/13 2017/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

KBL-H(3/8) PEG,DMI

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet of

7 66Monday, November 28, 2016

1.0

SKYLAKE_HALO

BGA1440

PROC_TDO PROC_TMS

PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

CFG_RCOMP

5 OF 14

REV = 1

+1.0V_VCCST

1 2

R39 1K_0402_5%

From EC(open-drain)

H_PROCHOT#[49]

BN25

CFG[0]

BN27

CFG[1]

BN26

CFG[2]

BN28

CFG[3]

BR20

CFG[4]

BM20

CFG[5]

BT20

CFG[6]

BP20

CFG[7]

BR23

CFG[8]

BR22

CFG[9]

BT23

CFG[10]

BT22

CFG[11]

BM19

CFG[12]

BR19

CFG[13]

BP19

CFG[14]

BT19

CFG[15]

BN23

CFG[17]

BP23

CFG[16]

BP22

CFG[19]

BN22

CFG[18]

BR27

BPM#[0]

BT27

BPM#[1]

BM31

BPM#[2]

BT30

BPM#[3]

BT28 BL32

PROC_TDI

BP28 BR28

BP30 BL30 BP27

CFG_RCOMP

BT25

THERMTRIP#

+1.0VS_VCCSTG

R42 1K_0402_5%

1 2

R44 499_0402_1%

CFG0 CFG2

CFG3 CFG4 CFG5 CFG6 CFG7

PROC_TDO PROC_TDI PROC_TMS PROC_TCK

PROC_TRST# PROC_PREQ# PROC_PRDY#

PAD

PAD PAD

PAD PAD PAD PAD

PAD

1 2

R35 49.9_0402_1%

T29

T49

T30

T31

Intel DCI debug

DCI R3 DCI R2 DCI R1

@ @ @ @

PAD

@ @

PAD

H_PROCHOT#_R

PROC_PREQ#

PROC_TDO

PROC_TCK

T32 T33 T34 T35

T36 T47

1121

T48

+1.0VS_VCCSTG

1 2

R9490 51_0402_1%

1 2

R9488 51_0402_1%

1 2

R9489 51_0402_1%

CFG4

CFG5

CFG2

ESD Reserve ,pleace close to cpu. 12/30

H_CPUPW RGD

H_PROCHOT#_R

THERMTRIP#

1 2

R34 1K_0402_1%

1 2

R36 1K_0402_1%

1 2

R37 1K_0402_1%

1 2

@EMI@

C36 .1U_0402_16V7K

C37 .1U_0402_16V7K

C38 .1U_0402_16V7K

B31 A32

D35 C36

E31

D31

BH31 BH32 BH29 BR30

BT13

H13

BT31 BP35

BM34

BP31 BT34

BR33

BN1

BM30

J31

UC1E

BCLKP BCLKN

PCI_BCLKP PCI_BCLKN

CLK24P CLK24N

VIDALERT# VIDSCK VIDSOUT PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD PROCPWRGD

RESET# PM_SYNC PM_DOWN PECI THERMTRIP#

SKTOCC# PROC_SELECT#

CATERR#

SKL-H_BGA1440

CPU_SVID_ALERT# CPU_SVID_CLK CPU_SVID_DAT H_PROCHOT#_R

DDR_PG_CTRL

EC_VCCST_PG H_CPUPW RGD

PLTRST_CPU# H_PM_SYNC PM_DOW N H_PECI

THERMTRIP#

SKL_CNL_N

T1 PAD

EC_VCCST_PG

PM_DOW N

CPU_BCLK CPU_BCLK#

CPU_PCIBCLK CPU_PCIBCLK#

CPU_24M CPU_24M#

CPU_BCLK[19] CPU_BCLK#[19]

CPU_PCIBCLK[19] CPU_PCIBCLK#[19]

CPU_24M[19]

1 1

H_SKTOCC#[18]

2 2

From EC OD output

EC_VCCST_PG_R[49]

3 3

PM_DOW N_R[16]

H_SKTOCC# H_SKTOCC#_R

1 2

R43 1K_0402_5%

CPU_24M#[19]

CPU_SVID_CLK[58]

H_CPUPW RGD[18] PLTRST_CPU#[16] H_PM_SYNC[16]

H_PECI[16,49]

THERMTRIP#[16]

1 2

R32 0_0402_5%@

1 2

R33 0_0402_5%

FLOAT FOR SKL GND FOR CNL

+1.0V_VCCST

R38 1K_0402_5%

1 2

R40 60.4_0402_1%

R41 20_0402_1%

Reference SKL EDS 0.85 Table 6-8 CFG signals internal PH default value = 1

Description

Stall reset sequence after PCU PLL lock until de-asserted — 1 = (Default) Normal Operation;

No stall. — 0 = Stall.

Enable eDP — 1 = Disabled. — 0 = Enabled.

PEG Training: — 1 = (default) PEG Train immediately

following RESET# de assertion. — 0 = PEG Wait for BIOS for training

Reserved configuration lane.

PCIE pore assign

1 x 16 1 x 16

reverse 2 x 8

2 x 8 reverse 1 x 8 + 2 x 4 1x8+2x4 reverse

Config. Signals

1 1 1 1 1 1 1

0 0 0

1121

CFG[0]

CFG[4]

CFG[7]

CFG[1] CFG[3]

CFG[8:19]

CFG[2]CFG[5]CFG[6]

0 0 0 00

DDR_VTT_CNTL to DDR VTT supplied ramped

SVID ALERT

+1.0V_VCCST

CPU_SVID_ALERT#

4 4

SVID DATA

+1.0V_VCCST

CPU_SVID_DAT

1 2

R45 56_0402_5%

1 2

R47 220_0402_5%

1 2

R49 100_0402_1%

Place the PU resistors close to CPU

CPU_SVID_ALERT#_R [58]

Place the PU resistors close to CPU

CPU_SVID_DAT [58]

Follow PDG1.0 Table 12-16

(To VR)

<35uS (tCPU18)

U29

DDR_PG_CTRL

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NC1VCC

GND

SN74AUP1G07DCKR SC70

2016/05/13 2017/12/31

+1.2V_VDDQ

+3VS

C39.1U_0402_16V7K

Compal Secret Data

Deciphered Date

R46 220K_0402_5%

R48 2M_0402_5%@

1 2

CRB 330K

SM_PG_CTRL [55]

Compal Electronics, Inc.

Title

KBL-H(4/8)CLK,GPIO

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet of

8 66Monday, November 28, 2016

1.0

1 1

VCC 27A (U 15W Dual Core GT2)

+VCCCORE +VCCCORE

2 2

3 3

AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38

K13 K14

L13 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13

SKYLAKE_HALO

UC1G

BGA1440

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

SKL-H_BGA1440

REV = 1 ?

7 OF 14

VCC_SENSE VSS_SENSE

V32

VCC

V33

VCC

V34

VCC

V35

VCC

V36

VCC

V37

VCC

V38

VCC

W13

VCC

W14

VCC

W29

VCC

W30

VCC

W31

VCC

W32

VCC

W35

VCC

W36

VCC

W37

VCC

W38

VCC

Y29

VCC

Y30

VCC

Y31

VCC

Y32

VCC

Y33

VCC

Y34

VCC

Y35

VCC

Y36

VCC

L14

VCC

P29

VCC

P30

VCC

P31

VCC

P32

VCC

P33

VCC

P34

VCC

P35

VCC

P36

VCC

R13

VCC

R31

VCC

R32

VCC

R33

VCC

R34

VCC

R35

VCC

R36

VCC

R37

VCC

R38

VCC

T29

VCC

T30

VCC

T31

VCC

T32

VCC

T35

VCC

T36

VCC

T37

VCC

T38

VCC

U29

VCC

U30

VCC

U31

VCC

U32

VCC

U33

VCC

U34

VCC

U35

VCC

U36

VCC

V13

VCC

V14

VCC

V31

VCC

P14

VCC

AG37 AG38

PH/PL o n pwr side 10/07 Da n

Trace Length < 25 mils

VCCSENSE [58]

VSSSENSE [58]

VCCGT / VCCGTX(2+3e only) 40A(n eed confirm)

+VCCGT +VCCGT

BG34 BG35 BG36 BH33 BH34 BH35 BH36 BH37 BH38

BM36 BM37 BN36 BN37 BN38 BP37 BP38 BR37 BT37 BE38 BF13 BF14 BF29 BF30 BF31 BF32 BF35 BF36 BF37 BF38 BG29 BG30 BG31 BG32 BG33 BC36 BC37 BC38 BD13 BD14 BD29 BD30 BD31 BD32 BD33 BD34 BD35 BD36 BE31 BE32 BE37

SKYLAKE_HALO

UC1H

BGA1440

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

BJ37

VCCGT

BJ38

VCCGT

BL36

VCCGT

BL37

VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT VCCGT

8 OF 14

SKL-H_BGA1440

REV = 1

Rev_0.53

AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AW14 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AY29 AY30 AY31 AY32 AY35 AY36 AY37 AY38 BA13 BA14 BA29 BA30 BA31 BA32 BA33 BA34 BA35 BA36 BB13 BB14 BB31 BB32 BB33 BB34 BB35 BB36 BB37 BB38 BC29 BC30 BC31 BC32 BC35 BE33 BE34 BE35 BE36

+VCCGT

UC1N

AJ29

VCCGT

AJ30

VCCGT

AJ31

VCCGT

AJ32

VCCGT

AJ33

VCCGT

AJ34

VCCGT

AJ35

VCCGT

AJ36

VCCGT

AK31

VCCGT

AK32

VCCGT

AK33

VCCGT

AK34

VCCGT

AK35

VCCGT

AK36

VCCGT

AK37

VCCGT

AK38

VCCGT

AL13

VCCGT

AL29

VCCGT

AL30

VCCGT

AL31

VCCGT

AL32

VCCGT

AL35

VCCGT

AL36

VCCGT

AL37

VCCGT

AL38

VCCGT

AM13

VCCGT

AM14

VCCGT

AM29

VCCGT

AM30

VCCGT

AM31

VCCGT

AM32

VCCGT

AM33

VCCGT

AM34

VCCGT

AM35

VCCGT

AM36

VCCGT

AN13

VCCGT

AN14

VCCGT

AN31

VCCGT

AN32

VCCGT

AN33

VCCGT

AN34

VCCGT

AN35

VCCGT

AN36

VCCGT

AN37

VCCGT

AN38

VCCGT

AP13

VCCGT

AP14

VCCGT

AP29

VCCGT

AP30

VCCGT

AP31

VCCGT

AP32

VCCGT

AP35

VCCGT

AP36

VCCGT

AP37

VCCGT

AP38

VCCGT

AR29

VCCGT

AR30

VCCGT

AR31

VCCGT

AR32

VCCGT

AR33

VCCGT

AR34

VCCGT

AR35

VCCGT

AR36

VCCGT

AT14

VCCGT

AT31

VCCGT

AT32

VCCGT

AT33

VCCGT

AT34

VCCGT

AT35

VCCGT

AT36

VCCGT

AT37

VCCGT

AT38

VCCGT

AU14

VCCGT

AU29

VCCGT

AU30

VCCGT

AU31

VCCGT

AU32

VCCGT

AU35

VCCGT

AU36

VCCGT

AU37

VCCGT

AU38

VCCGT

SKL-H_BGA1440

REV = 1

Change to 14/14 Loss 13 of 14

SKYLAKE_HALO

BGA1440

14 OF 14

VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AF29 AF30 AF31 AF32 AF33 AF34 AG13 AG14

EDS:Rail is uncon nected for Processor s without GT3/4.

AG31 AG32 AG33 AG34 AG35 AG36 AH13 AH14 AH29 AH30 AH31 AH32 AJ13 AJ14

VCCGT_SENSE

AH38 AH35 AH37 AH36

VSSGT_SENSE

VCCGT_SENSE

VSSGT_SENSE

Trace Length < 25 mils

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENT IAL AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS S HEET MAY NOT BE TRANSFERED FROM T HE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECT RONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

KBL-H(5/8)Power,SVID

Size

Document Number Re v

Custom

Merlyn2 LA-D214P

Date : Sheet o f

9 66Monday, November 28, 2016

1.0

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

+1.2V_VDDQ_CPU

AA6 AE12 AF5 AF6 AG5 AG9 AJ12 AL11 AP6 AP7 AR12 AR6 AT12 AW6 AY6 J5 J6 K12 K6 L12 L6 R6 T6 W6

Y12 BH13

G11

H30 H29 G30 H28

J28

M38 M37

H14 J14

?REV = 1

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE VSSIO_SENSE

For Power consumption Measurement

JP1

JUMP_43X118

+VDDQ_CLK

+VCCSFR_OC_1 +VCCSFR_OC_2

+1.0V_VCCST +1.0VS_VCCSTG

+1.0V_VCCST

JP2

VCCSA_SENSE [58] VSSSA_SENSE [58]

VCCIO_SENSE [57] VSSIO_SENSE [57]

+1.2V_VDDQ

+1.0V_VCCST

1 2

C40 1U_0402_6.3V6K

1 1

+1.0VS_VCCSTG

1U_0402_6.3V6K

C42

(1.0VS)

1U_0402_6.3V6K

C41

+1.0V_VCCST

C43 1U_0402_6.3V6K

Place at Back Side

(1.35V)

+VDDQ_CLK

BSC Side

10U_0603_6.3V6M

C44

+VCCSFR_OC_1

1U_0402_6.3V6K

C45

+VCCSFR_OC_2

1U_0402_6.3V6K

C46

2 2

+1.2V_VDDQ_CPU

1 2

R51 0_0603_5%

Place at Back Side

+1.2V_VDDQ

1 2

R52 0_0402_5%

1 2

R53 0_0402_5%

NOTE: VCCPLL_OC is allowed to be turned off during S3 & DS3 if it is not powered

3 3

directly from VDDQ

RVP11 47u*1,10u*7,1u*3 CAP place on PWR side.

RVP11 PWR NEED PROVIDE

0.95V FOR VCCIO

+VCCSA

+VCCIO

K29 K30 K31 K32 K33 K34 K35 L31 L32 L35 L36 L37

L38 M29 M30 M31 M32 M33 M34 M35 M36

AG12

G15 G17 G19 G21

H15

H16

H17

H19

H20

H21

H26

H27

J30

J15 J16 J17 J19 J20 J21 J26 J27

UC1I

VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA VCCSA

VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO

SKL-H_BGA1440

SKYLAKE_HALO

BGA1440

9 OF 14

VDDQC

VCCPLL_OC VCCPLL_OC

VCCST VCCSTG VCCSTG

VCCPLL VCCPLL

VCCSA_SENSE VSSSA_SENSE

VCCIO_SENSE VSSIO_SENSE

Place at Back Side

+1.2V_VDDQ_CPU

10U_0603_6.3V6M

C47

22U_0603_6.3V6M

10U_0603_6.3V6M

C48

C49

10U_0603_6.3V6M

C50

10U_0603_6.3V6M

C51

C52

10U_0603_6.3V6M

C53

10U_0603_6.3V6M

C54

10U_0603_6.3V6M

C55

C56

22U_0603_6.3V6M

C58

C57

22U_0603_6.3V6M

C59

C60

+VCCIO

22U_0603_6.3V6M

10U_0603_6.3V6M

C61

10U_0603_6.3V6M

C62

C63

22U_0603_6.3V6M

C260

C228

22U_0603_6.3V6M

C261

C229

Place at Back SidePlace at Back Side

+1.2V_VDDQ_CPU : 10UF/6.3V/0603 *10 22UF/6.3V/0603 * 4

4 4

update CRB cap QTY

CPU_CORE/VCCGT/VCCSA decoupling capacitor place to PWR side

Security Classification

2016/05/13 2017/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

Compal Electronics, Inc.

KBL-H(6/8)POWER

Merlyn2 LA-D214P

10 66Monday, November 28, 2016

1.0

C17 C13

BT9 BT5

BR7

BP7

BN9 BN7 BN4 BN2

BM9 BM6 BM2

BH9 BH8 BH5 BH4 BH1

BE6 BD9

UC1L

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

SKL-H_BGA1440

REV = 1

SKYLAKE_HALO

BGA1440

12 OF 14

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

SKYLAKE_HALO

BJ17 BJ19 BJ20 BK17 BK19 BK20 BL16 BL17 BL18 BL19 BL20 BL21

BM17

BN17 BJ23

BJ26 BJ27 BK23 BK26 BK27 BL23 BL24 BL25 BL26 BL27 BL28

BM24

BL15

BM16

BL22

BM22

BP15 BR15 BT15

BP16 BR16 BT16

BN15

BM15

BP17 BN16

BM14

BL14 BJ35

BJ36

AT13

AW13

AU13 AY13

BT29 BR25 BP25

UC1J

BGA1440

VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

VCCOPC_SENSE VSSOPC_SENSE

RSVD RSVD

VCCEOPIO VCCEOPIO VCCEOPIO

RSVD RSVD RSVD

VCCEOPIO_SENSE VSSEOPIO_SENSE

RSVD RSVD

VCC_OPC_1P8 VCC_OPC_1P8

RSVD RSVD

ZVM# MSM#

ZVM2# MSM2#

OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2

SKL-H_BGA1440

REV = 1

10 OF 14

C25 C23 C21 C19 C15 C11 C8 C5 BM29 BM25 BM18 BM11 BM8 BM7 BM5 BM3 BL38 BL35 BL13 BL6 BK25 BK22 BK13 BK6 BJ30 BJ29 BJ15 BJ12 BH11 BH10 BH7 BH6 BH3 BH2 BG37 BG14 BG6 BF34 BF6 BE30 BE5 BE4 BE3 BE2 BE1 BD38 BD37 BD12 BD11 BD10 BD8 BD7 BD6 BC33 BC14 BC13 BC6 BB30 BB29 BB6 BB5

C2 BT36 BT35 BT4 BT3 BR38

EDRAM

CRB EDRAM

SKYLAKE_HALO

UC1F

Y9 Y8 Y7

W5 W4 W3 W2 W1

T9 T8 T7

T5 T4 T3 T2 T1

N9 N8 N7 N6 N5 N4 N3 N2 N1

K9 K8 K7 K5 K4 K3 K2

SKL-H_BGA1440

REV = 1

BGA1440

6 OF 14

NCTFVSS

K1 J36 J33 J32 J25 J22 J18 J10 J7 J4 H35 H32 H25 H22 H18 H12 H11 G28 G26 G24 G23 G22 G20 G18 G16 G14 G12 G10 G9 G8 G6 G5 G4 F36 F31 F29 F27 F25 F23 F21 F19 F17 F15 F13 F11 F9 F8 F5 F4 F3 F2 E38 E35 E34 E9 E4 D33 D30 D28 D26 D24 D22 D20 D18 D16 D14 D12 D10 D9 D6 D3 C37 C31 C29 C27

D38

BA38 BA37 BA12 BA11 BA10

AY34 AY33 AY14

AY12 AW30 AW29 AW12

AW5 AW4 AW3 AW2

AW1 AV38 AV37 AU34 AU33 AU12 AU11 AU10

AT30

AT29 AR38

AR37 AR14 AR13

AP34 AP33 AP12 AP11 AP10

AN30 AN29 AN12

AM38 AM37 AM12

AM5 AM4 AM3 AM2

AM1 AL34 AL33 AL14 AL12 AL10

Y38 Y37 Y14 Y13

1 1

2 2

3 3

4 4

Y11 Y10

W34 W33 W12

V30 V29 V12

U38 U37

T34 T33 T14 T13 T12 T11 T10

R30 R29 R12 P38 P37 P12

N34 N33 N12 N11 N10

M14 M13 M12

L34 L33 L30 L29 K38 K11 K10

BB4 BB3 BB2 BB1

BA9 BA8 BA7 BA6

AU9 AU8 AU7 AU6

AT6

AR5 AR4 AR3 AR2 AR1

AP9 AP8

AN6 AN5

AL9 AL8 AL7 AL4

UC1M

SKL-H_BGA1440

REV = 1

SKYLAKE_HALO

BGA1440

13 OF 14

NCTFVSS NCTFVSS NCTFVSS NCTFVSS NCTFVSS

AK30 AK29 AK4 AJ38 AJ37 AJ6 AJ5 AJ4 AJ3 AJ2 AJ1 AH34 AH33 AH12 AH6 AG30 AG29 AG11 AG10 AG8 AG7 AG6 AF14 AF13 AF12 AF4 AF3 AF2 AF1 AE34 AE33 AE6 AD30 AD29 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AC38 AC37 AC12 AC6 AC5 AC4 AC3 AC2 AC1 AB34 AB33 AB6 AA30 AA29 AA12 A30 A28 A26 A24 A22 A20 A18 A16 A14 A12 A10 A9 A6

B37 B3 A34 A4 A3

BT32 BT26 BT24 BT21 BT18 BT14 BT12

BR36 BR34 BR29 BR26 BR24 BR21 BR18 BR14 BR12

BP34 BP33 BP29 BP26 BP24 BP21 BP18 BP14 BP12

BN34 BN31 BN30 BN29 BN24 BN21 BN20 BN19 BN18 BN14 BN12

BM38 BM35 BM28 BM27 BM26 BM23 BM21 BM13 BM12

BL29 BK29 BK15 BK14

BJ32

BJ31

BJ25

BJ22 BH14 BH12

BG38 BG13 BG12

BF33

BF12 BE29

BC34 BC12 BB12

Security Classification

2016/05/13 2017/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

KBL-H(7/8)GND

Merlyn2 LA-D214P

1.0

11 66Monday, November 28, 2016

1 1

UC1K

RSVD_TP

BR1

RSVD_TP

BT2

RSVD_TP

BN35

RSVD

J24

RSVD

H24

RSVD

BN33

RSVD

BL34

RSVD

N29

RSVD

R14

RSVD

AE29

RSVD

2 2

PROC_TRIGIN_R[22]

PROC_TRIGOUT_R[22]

3 3

1 2

R55 30_0402_1%

PROC_TRIGIN_R PROC_TRIGOUT

AA14

A36 A37

H23

F30 E30

B30 C30

BR35 BR31 BH30

J23

RSVD RSVD

RSVD PROC_TRIGIN

PROC_TRIGOUT RSVD

RSVD RSVD

RSVD

RSVD RSVD RSVD

SKL-H_BGA1440

SKYLAKE_HALO

BGA1440

11 OF 14

Rev_0 .53

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD

VSS

RSVD_TP RSVD_TP

RSVD RSVD RSVD

NCTF NCTF NCTF NCTF NCTF NCTF

+5VALW

+1.0VALW

C64

EN_1.0V_VCCSTU

1U_0402_6.3V6K

C70

C72

1U_0402_6.3V6K

+1.0VALW TO +1.0V_VCCST

U25

VIN

1U_0402_6.3V6K

C68

VBIAS

TPS22967DSGR_SON8_2X2

VOUT VOUT

GND GND

7 8

5 9

+1.0V_VCCST_L

1 2

C66

1000P_0402_50V7K

+1.0VALW TO +1.0VS_VCCSTG

U34

VIN1

VIN2

VIN thermal

VBIAS

1U_0402_6.3V6K

TPS22961DNYR_WSON8

VCCSTG and VCCIO SLEW RATE <=65us

+1.0VS_VCCSTG_IO

VOUT

GND

JP3

112

JUMP_43X39

JP@

JP4

112

JUMP_43X39

JP@

+1.0V_VCCST

+1.0VS_VCCSTG

C67 .1U_0402_16V7K

C71

.1U_0402_16V7K

BM33 BL33

BJ14 BJ13

BK28 BJ28

BJ18 BJ16

BK16

BK24 BJ24

BK21 BJ21

BT17 BR17

BK18 BJ34

BJ33

G13 AJ8 BL31

B2 B38 BP1 BR2 C1 C38

?REV = 1

SYSON[49,55]

+1.0V_VCCST: 60mA R ON = 22mΩ VDROP= 1.32mV Delay time: 270us

C65 1U_0402_6.3V6K

.1U_0402_16V7K

SUSP#[49,50,55,57,65]

1 2

R54 0_0402_5%@

C69

SUSP#

+5VALW

1 2

R57 0_0402_5%

+1.0VS_VCCSTG: 60mA R ON = 4.4mΩ VDROP= 11mV Delay time: 9.3us

4 4

Security Classification

2016/05/13 2017/12/31

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Re v

Custom

Date: Sheet of

KBL-H(8/8)RSVD

Merlyn2 LA-D214P

1.0

12 66Monday, November 28, 2016

CHANNEL-A

D D

Layout Note: Place near JDIMM1

C C

+1.2V_VDDQ +1.2V_VDDQ

10U_0603_6.3V6M

CD2

Layout Note: Place near JDIMM1

+2.5V

10U_0603_6.3V6M

CD35

B B

Layout Note: Place near JDIMM1

+0.6VS_VTT

Layout Note: PLACE THE CAP WITHIN 200 MILS FROM THE JDIMM1

A A

+0.6V_DDR_VREFCA

CD56

0.1U_0201_10V6K

CD3

10U_0603_6.3V6M

CD47

10U_0603_6.3V6M

CD4

CD36

10U_0603_6.3V6M

PDG:10uF *16/1uF *16/330u Fx1 ORB:10uF *8/1uF* 8/330uF* 1

10U_0603_6.3V6M

CD5

10uF*2 1uF*2

1U_0402_6.3V6K

CD37

CD38

10uF*2 1uF*1

1U_0402_6.3V6K

CD49

CD48

2.2uF*1

0.1uF*1

CD57

2.2U_0402_6.3V6M

CD6

+3VS +3VS +3VS

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL A : WRITE ADDRESS: 0XA0 READ ADDRESS: 0XA1 SA0 = 0; SA1 = 0; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S STRETCH GOAL IS 2133 MT/S

10U_0603_6.3V6M

CD1

CD7

CD8

Interleaved Memory

Non-ECC DIMM

RD2

0_0402_5%

SA2_CHA_DIM1

RD4 0_0402_5%

+1.2V_VDDQ

1U_0402_6.3V6K

+1.2V_VDDQ

CD10

1U_0402_6.3V6K

CD11

CD271

2.2U_0402_6.3V6M

SIV for RF request 150420

RD9 0_0402_5%

SA1_CHA_DIM1 SA0_CHA_DIM1

RD8 0_0402_5%

1U_0402_6.3V6K

CD12

@EMI@

RD10

0_0402_5%

RD12 0_0402_5%

1U_0402_6.3V6K

CD15

CD13

CD14

CD272

@EMI@

6.8P_0402_50V8C

1U_0402_6.3V6K

CD16

CD17 330U 2.0V Y ESR9M D1 H1.9

CD9

SGA00009S00

+1.2V_VDDQ_CPU

RH47 470_0402_5%

1 2

CH268

RH51 0_0402_5%@

Place near SODIMM side,

DDR_DRAMRST#[18] DDR_DRAMRST#_R [14 ]

@EMI@

100P_0402_50V8J

20141230, ESD require 20150424, ESD stuff

DDR_DRAMRST#_RDDR_DRAMRST#

0.1U_0201_10V6K CH16

1U_0402_6.3V6K

+1.2V_VDDQ

DIMM1 Side

RD15 1K_0402_1%

CD53

0.1U_0201_10V6K

1 2

RD17 1K_0402_1%

+0.6V_DDR_VREFCA

CD54

0.1U_0201_10V6K

RD16

1 2

2_0402_1%

+0.6V_VREFCA

CD55

0.022U_0402_25V7 K

RD18

24.9_0402_1%

1 2

CPU Side

+1.2V_VDDQ

+1.2V_VDDQ +1.2V_VDDQ

+1.2V_VDDQ

+3VS

0.1U_0201_10V6K

2.2U_0402_6.3V6M

CD45

CD46

PLACE NEAR TO PIN

JDIMM1

VSS1VSS DQ53DQ4 VSS5VSS DQ17DQ0

DDR_A_DQS#0[6] DDR_A_DQS0[6]

DDR_A_D7[6]

DDR_A_D3[6] DDR_A_D9[6] DDR_A_D8[6]

+1.2V_VDDQ

DDR_A_D14[6] DDR_A_D10 [6]

DDR_A_DQS#2[6] DDR_A_DQS2[6]

DDR_A_D19[6] DDR_A_D18[6] DDR_A_D25[6] DDR_A_D24[6]

+1.2V_VDDQ

DDR_A_D26[6] DDR_A_D31 [6] DDR_A_D30[6] DDR_A_D27 [6]

DDR_A_CKE0[6] DDR_A_CKE1 [6]

DDR_A_BG1[6] DDR_A_BG0[6]

DDR_A_MA9[6] DDR_A_MA8[6]

DDR_A_MA6[6]

DDR_A_MA1[6]

DDR_A_CLK0[6] DDR_A_CLK#0[6]

DDR_A_PAR[6]

DDR_A_BA1[6]

DDR_A_CS#0[6]

DDR_A_WE#[6]

DDR_A_ODT0[6] DDR_A_CS#1[6]

DDR_A_ODT1[6]

DDR_A_DQS#4[6] DDR_A_DQS4[6]

DDR_A_D34[6] DDR_A_D35[6] DDR_A_D40[6] DDR_A_D45[6]

DDR_A_D47[6] DDR_A_D42 [6] DDR_A_D48[6] DDR_A_D50 [6] DDR_A_D49[6]

DDR_A_DQS#6[6] DDR_A_DQS6[6]

DDR_A_D55[6] DDR_A_D51[6] DDR_A_D61[6] DDR_A_D56[6]

DDR_A_D59[6] DDR_A_D63[6]

+2.5V

VSS9VSS DQS0_C11DM0*/DBI0* DQS0_T13VSS VSS15DQ6 DQ717VSS VSS19DQ2 DQ321VSS VSS23DQ12 DQ1325VSS VSS27DQ8 DQ929VSS VSS31DQS1_C DM1*/DBI1*33DQS1_T VSS35VSS DQ1537DQ14 VSS39VSS DQ1041DQ11 VSS43VSS DQ2145DQ20 VSS47VSS DQ1749DQ16 VSS51VSS DQS2_C53DM2*/DBI2* DQS2_T55VSS VSS57DQ22 DQ2359VSS VSS61DQ18 DQ1963VSS VSS65DQ28 DQ2967VSS VSS69DQ24 DQ2571VSS VSS73DQS3_C DM3*/DBI3*75DQS3_T VSS77VSS DQ3079DQ31 VSS81VSS DQ2683DQ27 VSS85VSS CB5_NC87CB4_NC VSS89VSS CB1_NC91CB0_NC VSS93VSS DQS8_C95DM8*/DBI8* DQS8_T97VSS VSS99CB6_NC

101

CB2_NC

103

VSS

105

CB3_NC

107

VSS

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

123

VDD5

125

127

129

VDD7

131

133

135

VDD9

137

CK0_T

139

CK0_C

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

S0*

151

A14_WE*

153

VDD15

155

ODT0

157

S1*

159

VDD17

161

ODT1

163

VDD19

165

S3*/C1

167

VSS

169

DQ37

171

VSS

173

DQ33

175

VSS

177

DQS4_C

179

DQS4_T

181

VSS

183

DQ38

185

VSS

187

DQ34

189

VSS

191

DQ44

193

VSS

195

DQ40

197

VSS

199

DM5*/DBI5*

201

VSS

203

DQ46

205

VSS

207

DQ42

209

VSS

211

DQ52

213

VSS

215

DQ49

217

VSS

219

DQS6_C

221

DQS6_T

223

VSS

225

DQ55

227

VSS

229

DQ51

231

VSS

233

DQ61

235

VSS

237

DQ56

239

VSS

241

DM7*/DBI7*

243

VSS

245

DQ62

247

VSS

249

DQ58

251

VSS

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

LOTES_ADDR0107-P00 5A_260P-T

ME@

CB7_NC

RESET*

ALERT*

EVENT*

VDD10 CK1_T CK1_C VDD12

A10_AP

VDD14

A16_RAS*

VDD16

A15_CAS*

VDD18 S2*/C0

VREFCA

DM4*/DBI4*

DQS5_C DQS5_T

DM6*/DBI6*

DQS7_C DQS7_T

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102

VSS

104 106

VSS

108 110

CKE1

112

VDD2

114

ACT*

116 118

VDD4

120

A11

122

124

VDD6

126

128

130

VDD8

132

134 136 138 140 142 144

146 148 150

BA0

152 154 156 158

A13

160 162 164 166

SA2

168

VSS

170

DQ36

172

VSS

174

DQ32

176

VSS

178 180

VSS

182

DQ39

184

VSS

186

DQ35

188

VSS

190

DQ45

192

VSS

194

DQ41

196

VSS

198 200 202

VSS

204

DQ47

206

VSS

208

DQ43

210

VSS

212

DQ53

214

VSS

216

DQ48

218

VSS

220 222

VSS

224

DQ54

226

VSS

228

DQ50

230

VSS

232

DQ60

234

VSS

236

DQ57

238

VSS

240 242 244

VSS

246

DQ63

248

VSS

250

DQ59

252

VSS

254

SDA

256

SA0

258

VTT

260

SA1

261

GND

262

GND

DIMM1_CHA_EVENT#

SA2_CHA_DIM1

SA0_CHA_DIM1 SA1_CHA_DIM1

+1.2V_VDDQ

+0.6VS_VTT

DDR_A_D0 [6]DDR_A_D4[6] DDR_A_D5 [6]DDR_A_D1[6]

DDR_A_D2 [6] DDR_A_D6 [6] DDR_A_D12 [6] DDR_A_D13 [6] DDR_A_DQS#1 [6]

DDR_A_DQS1 [6] DDR_A_D11 [6]DDR_A_D15[6]

DDR_A_D21 [6]DDR_A_D17[6] DDR_A_D20 [6]DDR_A_D16[6]

DDR_A_D22 [6] DDR_A_D23 [6] DDR_A_D28 [6] DDR_A_D29 [6] DDR_A_DQS#3 [6]

DDR_A_DQS3 [6]

DDR_A_ACT# [6]

DDR_A_ALERT# [6]

DDR_A_MA11 [6]DDR_A_MA12[6]

DDR_A_MA7 [6] DDR_A_MA5 [6]

DDR_A_MA4 [6] DDR_A_MA2 [6]DDR_A_MA3[6]

DDR_A_CLK1 [6] DDR_A_CLK#1 [6]

DDR_A_MA0 [6]

DDR_A_MA10 [6]

DDR_A_BA0 [6]

DDR_A_RAS# [6] DDR_A_CAS# [6]

DDR_A_MA13 [6]

DDR_A_D36 [6]DDR_A_D37[6] DDR_A_D32 [6]DDR_A_D33[6]

DDR_A_D38 [6] DDR_A_D39 [6] DDR_A_D41 [6] DDR_A_D44 [6] DDR_A_DQS#5 [6]

DDR_A_DQS5 [6] DDR_A_D46 [6]DDR_A_D43[6]

DDR_A_D52 [6]

DDR_A_D54 [6] DDR_A_D53 [6] DDR_A_D60 [6] DDR_A_D57 [6] DDR_A_DQS#7 [6]

DDR_A_DQS7 [6] DDR_A_D62 [6] DDR_A_D58 [6] PCH_SMBDATA_R [14,18,44,47]PCH_SMBCLK_R[14,18,44,47]

1 2

RD14

240_0402_1%

REVERSE

+1.2V_VDDQ

@ESD@

+1.2V_VDDQ

100P_0402_50V8J

+1.2V_VDDQ

20141230, ESD require

+1.2V_VDDQ +1.2V_VDDQ

+1.2V_VDDQ

+0.6V_DDR_VREFCA

+1.2V_VDDQ

DDR_DRAMRST#_R

CD269

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Size

Date: Sheet of

Compal Electronics, Inc.

Title

Custom

DDRIV DIMM1, DIMM2

Document Number Re v

Merlyn2 LA-D214P

13 66Monday, November 28, 2016

1.0

CHANNEL-B

D D

Layout Note: Place near JDIMM3

C C

10U_0603_6.3V6M

CD60

Layout Note: Place near JDIMM2

+2.5V

10U_0603_6.3V6M

CD94

B B

Layout Note: Place near JDIMM2

+0.6VS_VTT

Layout Note: PLACE THE CAP WITHIN 200 MILS FROM THE JDIMM2

+0.6V_DDRB_VREFCA

A A

CD116

0.1U_0201_10V6K

10U_0603_6.3V6M

CD61

10U_0603_6.3V6M

CD95

CD106

10U_0603_6.3V6M

CD62

1U_0402_6.3V6K

CD96

10U_0603_6.3V6M

CD107

PDG:10uF *16/1uF *16/330u Fx1 ORB:10uF *8/1uF* 8/330uF* 1

10U_0603_6.3V6M

CD63

10uF*2 1uF*2

1U_0402_6.3V6K

CD97

10uF*2 1uF*1

1U_0402_6.3V6K

CD108

2.2uF*1

0.1uF*1

CD117

2.2U_0402_6.3V6M

+3VS +3VS

PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM

SPD ADDRESS FOR CHANNEL B : WRITE ADDRESS: 0XA4 READ ADDRESS: 0XA3 SA0 = 0; SA1 = 1; SA2 = 0. DDR4 POR OPERATING SPEED: 1867 MT/S STRETCH GOAL IS 2133 MT/S

10U_0603_6.3V6M

CD64

10U_0603_6.3V6M

CD66

CD65

Interleaved Memory

Non-ECC DIMM

+3VS

RD21

0_0402_5%

SA2_CHB_DIM2 SA1_CHB_DIM2 SA0_CHB_DIM2

RD26 0_0402_5%

+1.2V_VDDQ+1.2V_VDDQ

1U_0402_6.3V6K

CD67

1U_0402_6.3V6K

CD68

CD69

RD22

0_0402_5%

RD27

0_0402_5%

1U_0402_6.3V6K

CD70

CD112

0.1U_0201_10V6K

CD113

0.1U_0201_10V6K

1U_0402_6.3V6K

CD71

+1.2V_VDDQ

1 2

RD23

0_0402_5%

RD28 0_0402_5%

1U_0402_6.3V6K

CD75

RD33 1K_0402_1%

RD35 1K_0402_1%

1U_0402_6.3V6K

CD72

+1.2V_VDDQ

1U_0402_6.3V6K

CD73

CD76

CD74

330U 2.0V Y ESR9M D1 H1.9

SGA00009S00

DIMM2 Side

+0.6V_DDRB_VREFCA +0.6V_B_VREFDQ

1 2

RD34

2_0402_1%

CD114

0.1U_0201_10V6K

CD115

0.022U_0402_25V7 K

RD36

24.9_0402_1%

1 2

CPU Side

+1.2V_VDDQ

+1.2V_VDDQ +1.2V_VDDQ

+1.2V_VDDQ

+3VS

0.1U_0201_10V6K

2.2U_0402_6.3V6M

CD104

CD105

PLACE NEAR TO PIN

JDIMM2

DDR_B_D5[6]

DDR_B_DQS#0[6] DDR_B_DQS0[6]

DDR_B_D3[6] DDR_B_D6[6] DDR_B_D14[6]

DDR_B_D10[6]

+1.2V_VDDQ

DDR_B_D11[6] DDR_B_D13 [6] DDR_B_D18[6] DDR_B_D17[6]

DDR_B_DQS#2[6] DDR_B_DQS2[6]

DDR_B_D23[6] DDR_B_D19[6] DDR_B_D30[6] DDR_B_D27[6]

+1.2V_VDDQ

DDR_B_D26[6] DDR_B_D29[6] DDR_B_D24 [6]

DDR_B_CKE0[6] DDR_B_CKE1 [6]

DDR_B_BG1[6] DDR_B_BG0[6]

DDR_B_MA8[6] DDR_B_MA6[6]

DDR_B_MA1[6]

DDR_B_CLK0[6] DDR_B_CLK1 [6] DDR_B_CLK#0[6]

DDR_B_PAR[6]

DDR_B_BA1[6]

DDR_B_CS#0[6]

DDR_B_WE#[6]

DDR_B_ODT0[6] DDR_B_CS#1[6]

DDR_B_ODT1[6]

DDR_B_D38[6] DDR_B_D39[6] DDR_B_D34 [6]

DDR_B_DQS#4[6] DDR_B_DQS4[6]

DDR_B_D33[6] DDR_B_D32[6] DDR_B_D40[6] DDR_B_D41[6]

DDR_B_D43[6] DDR_B_D47 [6] DDR_B_D42[6] DDR_B_D51[6] DDR_B_D52 [6]

DDR_B_DQS#6[6] DDR_B_DQS6[6]

DDR_B_D53[6] DDR_B_D49[6] DDR_B_D59[6] DDR_B_D62[6]

DDR_B_D63[6] DDR_B_D58[6]

+2.5V

VSS1VSS DQ53DQ4 VSS5VSS DQ17DQ0 VSS9VSS DQS0_C11DM0*/DBI0* DQS0_T13VSS VSS15DQ6 DQ717VSS VSS19DQ2 DQ321VSS VSS23DQ12 DQ1325VSS VSS27DQ8 DQ929VSS VSS31DQS1_C DM1*/DBI1*33DQS1_T VSS35VSS DQ1537DQ14 VSS39VSS DQ1041DQ11 VSS43VSS DQ2145DQ20 VSS47VSS DQ1749DQ16 VSS51VSS DQS2_C53DM2*/DBI2* DQS2_T55VSS VSS57DQ22 DQ2359VSS VSS61DQ18 DQ1963VSS VSS65DQ28 DQ2967VSS VSS69DQ24 DQ2571VSS VSS73DQS3_C DM3*/DBI3*75DQS3_T VSS77VSS DQ3079DQ31 VSS81VSS DQ2683DQ27 VSS85VSS CB5_NC87CB4_NC VSS89VSS CB1_NC91CB0_NC VSS93VSS DQS8_C95DM8*/DBI8* DQS8_T97VSS VSS99CB6_NC

101

CB2_NC

103

VSS

105

CB3_NC

107

VSS

109

CKE0

111

VDD1

113

BG1

115

BG0

117

VDD3

119

A12

121

123

VDD5

125

127

129

VDD7

131

133

135

VDD9

137

CK0_T

139

CK0_C

141

VDD11

143

PARITY

145

BA1

147

VDD13

149

S0*

151

A14_WE*

153

VDD15

155

ODT0

157

S1*

159

VDD17

161

ODT1

163

VDD19

165

S3*/C1

167

VSS

169

DQ37

171

VSS

173

DQ33

175

VSS

177

DQS4_C

179

DQS4_T

181

VSS

183

DQ38

185

VSS

187

DQ34

189

VSS

191

DQ44

193

VSS

195

DQ40

197

VSS

199

DM5*/DBI5*

201

VSS

203

DQ46

205

VSS

207

DQ42

209

VSS

211

DQ52

213

VSS

215

DQ49

217

VSS

219

DQS6_C

221

DQS6_T

223

VSS

225

DQ55

227

VSS

229

DQ51

231

VSS

233

DQ61

235

VSS

237

DQ56

239

VSS

241

DM7*/DBI7*

243

VSS

245

DQ62

247

VSS

249

DQ58

251

VSS

253

SCL

255

VDDSPD

257

VPP1

259

VPP2

LOTES_ADDR0106-P00 5A_260P-T

ME@

CB7_NC

RESET*

ALERT*

EVENT*

VDD10

CK1_T CK1_C VDD12

A10_AP

VDD14

A16_RAS*

VDD16

A15_CAS*

VDD18

S2*/C0

VREFCA

DM4*/DBI4*

DQS5_C DQS5_T

DM6*/DBI6*

DQS7_C DQS7_T

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102

VSS

104 106

VSS

108 110

CKE1

112

VDD2

114

ACT*

116 118

VDD4

120

A11

122

124

VDD6

126

128

130

VDD8

132

134 136 138 140 142 144

146 148 150

BA0

152 154 156 158

A13

160 162 164

SA2_CHB_DIM2

166

SA2

168

VSS

170

DQ36

172

VSS

174

DQ32

176

VSS

178 180

VSS

182

DQ39

184

VSS

186

DQ35

188

VSS

190

DQ45

192

VSS

194

DQ41

196

VSS

198 200 202

VSS

204

DQ47

206

VSS

208

DQ43

210

VSS

212

DQ53

214

VSS

216

DQ48

218

VSS

220 222

VSS

224

DQ54

226

VSS

228

DQ50

230

VSS

232

DQ60

234

VSS

236

DQ57

238

VSS

240 242 244

VSS

246

DQ63

248

VSS

250

DQ59

252

VSS

254

SA0_CHB_DIM2

SDA

256

SA0

258

SA1_CHB_DIM2

VTT

260

SA1

261

GND

262

GND

DIMM2_CHB_EVENT#

DDR_B_D4 [6] DDR_B_D0 [6]DDR_B_D1[6]

+1.2V_VDDQ

DDR_B_D7 [6] DDR_B_D2 [6] DDR_B_D8 [6] DDR_B_D9 [6] DDR_B_DQS#1 [6]

DDR_B_DQS1 [6] DDR_B_D12 [6]DDR_B_D15[6]

DDR_B_D22 [6] DDR_B_D16 [6]

+1.2V_VDDQ

DDR_B_D21 [6] DDR_B_D20 [6] DDR_B_D28 [6] DDR_B_D25 [6] DDR_B_DQS#3 [6]

DDR_B_DQS3 [6] DDR_B_D31 [6]

+1.2V_VDDQ

DDR_B_ACT# [6]

DDR_B_ALERT# [6] DDR_B_MA11 [6]DDR_B_MA12[6]

DDR_B_MA7 [6]DDR_B_MA9[6] DDR_B_MA5 [6]

DDR_B_MA4 [6] DDR_B_MA2 [6]DDR_B_MA3[6]

DDR_B_CLK#1 [6] DDR_B_MA0 [6]

DDR_B_MA10 [6]

DDR_B_BA0 [6]

DDR_B_RAS# [6] DDR_B_CAS# [6]

DDR_B_MA13 [6]

DDR_B_D35 [6]

DDR_B_D37 [6] DDR_B_D36 [6] DDR_B_D45 [6] DDR_B_D44 [6] DDR_B_DQS#5 [6]

DDR_B_DQS5 [6]

DDR_B_D46 [6]

DDR_B_D48 [6]DDR_B_D54[6]

+1.2V_VDDQ

DDR_B_D55 [6] DDR_B_D50 [6] DDR_B_D61 [6] DDR_B_D57 [6] DDR_B_DQS#7 [6]

DDR_B_DQS7 [6] DDR_B_D60 [6] DDR_B_D56 [6] PCH_SMBDATA_R [13,18,44,47]PCH_SMBCLK_R[13,18,44,47]

+0.6VS_VTT

1 2

RD20

240_0402_1%

+1.2V_VDDQ

+1.2V_VDDQ +1.2V_VDDQ

+1.2V_VDDQ

+0.6V_DDRB_VREFCA

+1.2V_VDDQ

STANDARD

DDR_DRAMRST#_R[13]

CD270

@ESD@

100P_0402_50V8J

20141230, ESD require

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, I NC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Size

Date: Sheet of

Compal Electronics, Inc.

Title

Custom

DDRIV DIMM1, DIMM2

Document Number Re v

Merlyn2 LA-D214P

14 66Monday, November 28, 2016

1.0

REV = 1.3

USB

SPT-H_PCH

LPC/eSPI

GPP_A14/SUS_STAT#/ESPI_RESET#

SATA

6 OF 12

SPT-H_PCH

DMI

PCIe/USB 3

2 OF 12

GPP_A1/LAD0/ESPI_IO0 GPP_A2/LAD1/ESPI_IO1 GPP_A3/LAD2/ESPI_IO2 GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI# GPP_G18/NMI#

GPP_E6/DEVSLP2 GPP_E5/DEVSLP1 GPP_E4/DEVSLP0 GPP_F9/DEVSLP7 GPP_F8/DEVSLP6 GPP_F7/DEVSLP5 GPP_F6/DEVSLP4 GPP_F5/DEVSLP3

USB2N_1 USB2P_1 USB2N_2 USB2P_2 USB2N_3 USB2P_3 USB2N_4 USB2P_4 USB2N_5 USB2P_5 USB2N_6 USB2P_6

USB 2.0

USB2N_7 USB2P_7 USB2N_8 USB2P_8 USB2N_9 USB2P_9

USB2N_10

USB2P_10

USB2N_11

USB2P_11

USB2N_12

USB2P_12

USB2N_13

USB2P_13

USB2N_14

USB2P_14

GPP_E9/USB2_OC0# GPP_E10/USB2_OC1# GPP_E11/USB2_OC2# GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4 GPP_F16/USB2_OCB_5 GPP_F17/USB2_OCB_6 GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

LPC_AD0

AT22

LPC_AD1

AV22

LPC_AD2

AT19

LPC_AD3

BD16

LPC_FRAME#

BE16 BA17

SERIRQ TPM_IRQ#

AW17

KB_RST#

AT17 BC18

CLKOUT_LPC0

BC17

CLKOUT_LPC1

AV19 M45

N43

AE45 AG43 AG42 AB39 AB36 AB43 AB42 AB41

USB20_N1

AF5

USB20_P1

AG7

USB20_N2

AD5

USB20_P2

AD7 AG8 AG10 AE1 AE2

USB20_N5

AC2

USB20_P5

AC3 AF2 AF3 AB3 AB2

USB20_N8

AL8

USB20_P8

AL7 AA1 AA2 AJ8 AJ7 W2 W3 AD3 AD2 V2 V1

USB20_N14

AJ11

USB20_P14

AJ13

USB_OC0#

AD43

USB_OC1#

AD42 AD39

USB_OC3#

AC44

USB_OC4

Y43

USB_OC5

Y41

USB_OC6

W44

USB_OC7

W43

USB2_COMP

AG3 AD10 AB13 AG2

BD14

LPC_AD0 [49] LPC_AD1 [49] LPC_AD2 [49] LPC_AD3 [49]

LPC_FRAME# [49] SERIRQ [49] TPM_IRQ# [46]

KB_RST# [49]

PAD

R76 22_0402_5% R180 22_0402_5%@

R79 113_0402_1% R279 1K_0402_5%

R330 1K_0402_5%

USB20_N1 [42] USB20_P1 [42] USB20_N2 [42] USB20_P2 [42]

USB20_N5 [43] USB20_P5 [43]

USB20_N8 [35] USB20_P8 [35]

USB20_N14 [44] USB20_P14 [44]

1 2 1 2

1 2

12 12

USB_OC0# [42] USB_OC2# [43]

LPC Bus

LPC : +3.3V

To TPM

LPC_CLK_R [49]

T42

PAD

HDD_DEVSLP2 MSATA_DEVSLP0 [44]

USB3 SB USB3 SB

USB3 MB

Camera

To EC

SERIRQ

DG requierment 8.2k PH +3VS CRB 10K PH +3vs

KB_RST#

check EC design needed pop R75 or not

TPM_IRQ#

1 2

R74 10K_0402_5%

1 2

R75 10K_0402_5%

R77 10K_0402_5%

CLKOUT_LPC0

reference PDG1.0 50-30

USB_OC0# USB_OC1# USB_OC3# USB_OC2#USB_OC2#

USB_OC5 USB_OC4 USB_OC6 USB_OC7

RP5

10K_0804_8P4R_5%

RP6

10K_0804_8P4R_5%

C8767

0.1U_0402_10V6K@EMI@

18 27 36 45

+3VS

+3VALW_PCH_PRIM

U2F

1 1

USB3 SB

USB3 MB

2 2

#543016 P.239 PCIE_RCOMPN/PCIE_RCOMPP BO=4 W=12 S=12 R=100ohm

3 3

NGFF WL+BT(KEY E)

GLAN

PCIE_PRX_DTX_N3[44]

PCIE_PRX_DTX_P3[44] PCIE_PTX_C_DRX_N3[44] PCIE_PTX_C_DRX_P3[44]

PCIE_PRX_DTX_N4[40]

PCIE_PRX_DTX_P4[40]

PCIE_PTX_C_DRX_N4[40] PCIE_PTX_C_DRX_P4[40]

USB3_PTX_DRX_N1[42] USB3_PTX_DRX_P1[42] USB3_PRX_DTX_N1[42] USB3_PRX_DTX_P1[42] USB3_PTX_DRX_N2[42] USB3_PTX_DRX_P2[42] USB3_PRX_DTX_N2[42] USB3_PRX_DTX_P2[42]

USB3_PTX_DRX_N5[43] USB3_PTX_DRX_P5[43] USB3_PRX_DTX_N5[43] USB3_PRX_DTX_P5[43]

DMI_CTX_PRX_N0[7] DMI_CTX_PRX_P0[7] DMI_CRX_PTX_N0[7] DMI_CRX_PTX_P0[7] DMI_CTX_PRX_N1[7] DMI_CTX_PRX_P1[7] DMI_CRX_PTX_N1[7] DMI_CRX_PTX_P1[7] DMI_CTX_PRX_N2[7] DMI_CTX_PRX_P2[7] DMI_CRX_PTX_N2[7] DMI_CRX_PTX_P2[7] DMI_CTX_PRX_N3[7] DMI_CTX_PRX_P3[7] DMI_CRX_PTX_N3[7] DMI_CRX_PTX_P3[7]

R78 100_0402_1%

1 2

C122 .1U_0402_16V7K C123 .1U_0402_16V7K

C124 .1U_0402_16V7K

12 12

C125 .1U_0402_16V7K

DMI_CTX_PRX_N0 DMI_CTX_PRX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P0 DMI_CTX_PRX_N1 DMI_CTX_PRX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P1 DMI_CTX_PRX_N2 DMI_CTX_PRX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P3

PCIE_RCOMPN PCIE_RCOMPP

PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4

C11

USB3_1_TXN

B11

USB3_1_TXP

USB3_1_RXN

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

USB3_2_RXN/SSIC_1_RXN

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKL-H-PCH_BGA837

U2B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKL-H-PCH_BGA837

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH (1/8) DMI,PCIE,USB

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet o f

15 66Monday, November 28, 2016

1.0

1 1

+3VALW_PCH_PRIM

R81

UMA@

10K_0402_5%

DGPU_PRSNT#

R82

DIS@

10K_0402_5%

GPP_F13

DGPU_PRSNT#

DIS,Optimus10

2 2

3 3

UMA

Card Reader

M.2 PCIe x4 L3

PCIE_PTX_C_DRX_N13[42] PCIE_PTX_C_DRX_P13[42]

PCIE_PRX_DTX_N13[42] PCIE_PRX_DTX_P13[42]

PCIE4_L3_TXP[44] PCIE4_L3_TXN[44] PCIE4_L3_RXP[44] PCIE4_L3_RXN[44]

M.2 PCIe x4 L2

C126 .1U_0402_16V7K C127 .1U_0402_16V7K

+3VS

EC_SCI#_SMI#

R8010K_0402_5%

U2C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

R9469

0_0402_5%

EC_SCI#_SMI#_G3EC_SCI#_SMI#

DGPU_PRSNT#

PCIE_PTX_DRX_N13 PCIE_PTX_DRX_P13

PCIE_PRX_DTX_N13 PCIE_PRX_DTX_P13

1 2

PCIE4_L2_TXP[44] PCIE4_L2_TXN[44] PCIE4_L2_RXP[44] PCIE4_L2_RXN[44]

12 12

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

EC_SCI#_SMI# [20,49]

SPT-H_PCH

CLINK

FAN

3 OF 12

PCIE9_RXN/SATA0A_RXN PCIE9_RXP/SATA0A_RXP

PCIE9_TXN/SATA0A_TXN PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN

PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN

PCIE15_RXP/SATA2_RXP PCIE15_TXN/SATA2_TXN

PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN

PCIE16_RXP/SATA3_RXP PCIE16_TXN/SATA3_TXN

PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN

PCIE17_RXP/SATA4_RXP PCIE17_TXN/SATA4_TXN

PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN

PCIE18_RXP/SATA5_RXP PCIE18_TXN/SATA5_TXN

PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED# GPP_E0/SATAXPCIE0/SATAGP0 GPP_E1/SATAXPCIE1/SATAGP1 GPP_E2/SATAXPCIE2/SATAGP2 GPP_F0/SATAXPCIE3/SATAGP3 GPP_F1/SATAXPCIE4/SATAGP4 GPP_F2/SATAXPCIE5/SATAGP5 GPP_F3/SATAXPCIE6/SATAGP6 GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

HOST

PLTRST_PROC#

THERMTRIP#

PECI

PM_SYNC

PM_DOWN

REV = 1.3

G31 H31 C31 B31

G29 E29 C32 B32

F41 E41 B39 A39

D43 E42 A41 A40

H42 H40 E45 F45

K37 G37 G45 G44

AD44 AG36 AG35 AG39 AD35 AD31 AD38 AC43 AB44

FOR SERVER & WS ONLY

PCH_BKL_PWM

W36 W35

ENBKL PCH_ENVDD

W42

PCH_THERMTRIP#

AJ3

PCH_PECI

AL3

H_PM_SYNC_R

AJ4

PLTRST_CPU#

AK2

PM_DOWN_R

AH2

PCH_PECI

+3VS

10K_0402_5% R83

SATA_GP0 [44]

PCH_BKL_PWM [34] ENBKL [49] PCH_ENVDD [34]

R89 620_0402_5%

1 2 1 2

R90 12.1_0402_1% R91 30_0402_1%

PLTRST_CPU# [8]

PM_DOWN_R [8]

1 2

R94 10K_0402_5%@

PCIE4_L0_SATA1_RXN [44] PCIE4_L0_SATA1_RXP [44] PCIE4_L0_SATA1_TXN [44] PCIE4_L0_SATA1_TXP [44]

PCIE4_L1_RXN [44] PCIE4_L1_RXP [44] PCIE4_L1_TXN [44]

PCIE4_L1_TXP [44]

SATA_PRX_DTX_N2 [45] SATA_PRX_DTX_P2 [45] SATA_PTX_DRX_N2 [45] SATA_PTX_DRX_P2 [45]

M.2 SSD PCIe x4 L0

M.2 SSD PCIe x4 L1

HDD

THERMTRIP# [8]

H_PECI [8,49]

H_PM_SYNC [8]

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(2/8)SATA,PCIE

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet o f

16 66Monday, November 28, 2016

1.0

1 1

ROM side

SPT-H_PCH

GPP_B13/PLTRST# GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

INTRUDER#

REV = 1.31 OF 12

non vPro : 8 M

PCH_SPI_CS#0 PCH_SPI_MISO_R0 PCH_SPI_WP#_R0

PLT_RST#

BB27 P43

R39 R36 R42 R41

AF41 AE44 BC23 BD24

BC36 BE34 BD39 BB36

for server and W S use

BA35 BC35 BD35 AW35 BD34

SM_INTRUDER#

BE11

SPI ROM ( 8MByte )

U27

/CS

DO(IO1)

/WP(IO2)

GND

W25Q64FVSSIQ_SO8

PAD

1 2

R98 1M_0402_5%

/HOLD(IO3)

DI(IO0)

VCC

CLK

8 7 6 5

PCH_SPI_HOLD#_R0 PCH_SPI_CLK_R0 PCH_SPI_MOSI_R0

+RTCBATT

+3VALW_SPI

C129

0.1U_0402_10V6K

PCH PLTRST Buf f er

PLT_RST#

C5405

100P_0402_50V8J

EMI@

SN74AHC1G08DCKR_SC70-5

U2A

RP7

EC_PME#_R

PCH_SPI_SI PCH_SPI_SO PCH_SPI_CS#0 PCH_SPI_CLK PCH_SPI_CS#1 PCH_SPI_IO2 PCH_SPI_IO3 PCH_SPI_CS#2

PCH_SPI_HOLD#_R0

PCH_SPI_WP#_R0

PCH_SPI_MISO_R0

PCH_SPI_MOSI_R0

BD17 AG15

AG14 AF17 AE17

AR19 AN17

BB29 BE30 BD31 BC31

AW31

BC29 BD30 AT31

AN36

AL39 AN41 AN38 AH43 AG44

GPP_A11/PME# RSVD

RSVD RSVD RSVD

TP2 TP1

SPI0_MOSI SPI0_MISO SPI0_CS0# SPI0_CLK SPI0_CS1# SPI0_IO2 SPI0_IO3 SPI0_CS2#

GPP_D1/SPI1_CLK GPP_D0/SPI1_CS# GPP_D3/SPI1_MOSI GPP_D2/SPI1_MISO GPP_D22/SPI1_IO3 GPP_D21/SPI1_IO2

SKL-H-PCH_BGA837

EC_PME#[49]

SPI ROM

2 2

PCH_SPI_CLK PCH_SPI_CLK_R0

SPI Signals

PCH side

3 3

PCH_SPI_IO3 PCH_SPI_IO2 PCH_SPI_SO PCH_SPI_SI

R100 33_0402_5%

R97 0_0402_5%

PCH_SPI_SI[46] PCH_SPI_SO

PCH_SPI_CLK[46]

PCH_SPI_CS#2[46]

1 2

33_0804_8P4R_5%

1 2

Functional Strap Definitions

SPI0_MOSI int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_MISO int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_IO2 int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

SPI0_IO3 int. PH This strap should sample HIGH. There should NOT be any on-board device driving it to opposite direction during strap sampling.

GPP_H12 int. PD This strap should sample LOW.

1 2

R99 0_0402_5%

+3VALW

C128

.1U_0402_16V7K

1 2

IN1

IN2

PLT_RST_BUF#

R102 100K_0402_5%

PLT_RST_BUF# [26,40,42,44,46,49]

PCH_SPI_CS#0

PCH_SPI_IO2

SPI ROM

1st

2nd

4 4

Vendor

Winbond

Micron

8MB16MB

4MB

SA00005VV10 SA000039A30 SA00003K820

SA000099300

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

PCH_SPI_IO3

Follow MOW WW36 pull down with pre-ES1/ES1 samples

1 2

R103 4.7K_0402_5%

1 2

R104 1K_0402_1%@

1 2

R105 1K_0402_1%@

1 2

R106 1K_0402_1%@

1 2

R107 1K_0402_1%@

Title

Size Document Number Rev

Custom

Date: Sheet of

+3VALW_SPI

Compal Electronics, Inc.

PCH(3/8)SPI,XDP

Merlyn2 LA-D214P

17 66Monday, November 28, 2016

1.0

HDA for AUDIO

ME_FLASH[49]

HDA_SDOUT_R[36] HDA_RST#_R[36] HDA_SYNC_R[36] HDA_BIT_CLK_R[36]

1 1

+3VALW_DSW

HDA_SDIN0[36]

+3VALW_PCH_PRIM

RP10

10K_0804_8P4R_5%

18 27 36 45

Follow 543016_SKL_U_Y_PDG_0_9

+3VALW_DSW

1 2

R111 10K_0402_5%

1 2

R112 1K_0402_5%

EC_RSMRST#

2 2

R114 0_0402_5%

R118 0_0402_5%

+RTCBATT

PCH_DPWROK

PCH_PWROKSYS_PWROK

1 2

R121 20K_0402_5%

1 2

C131 1U_0402_6.3V6K

1 2

JME1 SHORT PADS

1 2

R124 20K_0402_5%

1 2

C133 1U_0402_6.3V6K

1 2

JME2 SHORT PADS

Place at RAM DOOR

3 3

Functional Strap Definitions

SMBALERT# / GPP_C2 int. PD 0 = Disable Intel ME (TLS) (Default) 1 = Enable Intel ME (TLS)

SML0ALERT# / GPP_C5 int. PD 0 = LPC Is selected for EC. (Default) 1 = eSPI Is selected for EC.

SML1ALERT# / PCHHOT# / GPP_B23 int. PD

SPKR / GPP_B14 int. PD 0 = Disable “ Top S wap” mode. ( Def ault ) 1 = Enable “ Top Swap” mode.

HDA_SDO

4 4

int. PD 0 = Enable security measures defined in the Flash Descriptor. (Default) 1 = Disable Flash Descriptor Security (override).

DDPB_CTRLDATA / GPP_I6 int. PD 0 = Port B is not detected. 1 = Port B is detected. (Default)

1 2

R108 0_0402_5%

RP9

1 8 2 7 3 6 4 5

33_0804_8P4R_5%

SYS_RESET#

PM_BATLOW# LAN_WAKE# EC_RSMRST#

AC_PRESENT_R

WAKE#

PCH_SRTCRST#

PCH_RTCRST#

HDA_SDOUT HDA_RST# HDA_SYNC HDA_BIT_CLK

HDA_SDIN0

WAKE# (DSX wake event) 10 KΩ pull - up t o VccDS W3_3. The pull-up is required even if PCIe* interface is not used on the plat f or m.

CLR CMOS

HDM I

CPU_DISPA_SDO_R[5]

CPU_DISPA_SDI_R[5]

CPU_DISPA_BCLK_R[5]

EC_WAKE#[49]

(SO-DIMM, XDP,WLAN, CP)

(VGA, EC, Thermal, G-sensor)

+3VALW_PCH_PRIM

+3VS

DDPC_CTRLDATA / GPP_I8 int. PD 0 = Port C is not detected. 1 = Port C is detected. (Default)

DDPD_CTRLDATA / GPP_I10 int. PD 0 = Port D is not detected. (Default) 1 = Port D is detected.

PCH_DP1_HPD

PCH_EDP_HPD[34]

R117 R119

PCH_PWROK[49,57] EC_RSMRST#[49]

T12

T13

T14

1 2

R125 4.7K_0402_5%

1 2

R126 499_0402_1%

1 2

R127 499_0402_1%

PCH_SMBALERT#

PCH_SML0CLK PCH_SML0DATA

1 2

30_0402_1%

1 2

30_0402_1%

PAD@

PAD

PCH_DP1_HPD

EC_SCI#_I3

PCH_EDP_HPD

HDA_BIT_CLK HDA_RST# HDA_SDIN0

HDA_SDOUT HDA_SYNC

CPU_DISPA_SDO CPU_DISPA_SDI_R CPU_DISPA_BCLK

EC_WAKE#

PCH_RTCRST# PCH_SRTCRST#

PCH_PWROK EC_RSMRST#

PCH_DPWROK PCH_SMBALERT# PCH_SMBCLK PCH_SMBDATA PCH_SML0ALERT# PCH_SML0CLK PCH_SML0DATA PCH_SML1ALERT# PCH_SML1CLK PCH_SML1DATA

U2E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKL-H-PCH_BGA837

U2D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837

REV = 1.3

SPT-H_PCH

5 OF 12

AUDIO

+3VALW_PCH_PRIM

+3VS

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

SPT-H_PCH

SMBUS

1K_0804_8P4R_5%

GPP_F14 GPP_F23 GPP_F22 GPP_G23 GPP_G22 GPP_G21 GPP_G20 GPP_H23

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_G17/ADR_COMPLETE

GPP_A13/SUSWARN#/SUSPWRDNACK

JTAG

4 OF 12

RP11

PCH_SML1CLK

PCH_SML1DATA

PCH_SMBCLK

PCH_SMBDATA

RP12

18 27

PCH_SMBCLK_R

PCH_SMBDATA_R

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

BB3 BD6

PCH_DP1_CTRL_CLK

BA5

PCH_DP1_CTRL_DATA

BC4 BE5 BE6

Y44 V44 W39 L43 L44 U35 R35 BD36

GPP_A8/CLKRUN# GPD11/LANPHYPC GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_B12/SLP_S0#

GPD4/SLP_S3# GPD5/SLP_S4#

GPD10/SLP_S5#

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE# GPD1/ACPRESENT

GPD3/PWRBTN#

GPP_B14/SPKR

PCH_DP1_CTRL_CLK [39] PCH_DP1_CTRL_DATA [39]

PAD

H_SKTOCC# [8]

BB17

PM_CLKRUN#

GPP_B1 GPP_B0

GPP_B11

SYS_PWROK

WAKE#

GPD6/SLP_A#

SLP_LAN#

GPD8/SUSCLK

SLP_SUS#

SYS_RESET#

PROCPWRGD

ITP_PMODE

JTAGX JTAG_TMS JTAG_TDO

JTAG_TDI

JTAG_TCK

AW22 AR15 AV13

DDR_DRAMRST#

BC14

PCH_VRALERT#

BD23 AL27 AR27 N44 AN24

SYS_PWROK

AY1 BC13

WAKE# PM_SLP_A#

BC15

PM_SLP_LAN#

AV15

PM_SLP_S0#

BC26

PM_SLP_S3#

AW15

PM_SLP_S4#

BD15

PM_SLP_S5#

BA13 AN15

SUSCLK PM_BATLOW#

BD13 BB19 BD19

SUSPWRDNACK

LAN_WAKE#

BD11

AC_PRESENT_R

BB15

PM_SLP_SUS#

BB13

PBTN_OUT#_R

AT13

SYS_RESET#

AW1

PCH_SPKR

BD26

H_CPUPWRGD

AM3

ITP_PMODE

AT2 AR3

JTAGX JTAG_TMS

AR2

JTAG_TDO

AP1

JTAG_TDI

AP2

JTAG_TCK

AN3

PAD PAD

PAD

R123 0_0402_5%@

1 2

PAD PAD

PAD PAD PAD PAD PAD PAD

PM_CLKRUN#

DDR_DRAMRST# [13]

SYS_PWROK [49]

T26

@ PM_SLP_S3# [49] PM_SLP_S4# [49,55] PM_SLP_S5# [49]

SUSCLK [44]

T25

T11

PCH_SPKR [36]

H_CPUPWRGD [8]

T37

T53

1121

T38

T39

T40

T41

EC (PH@EC)

DIMM/WLAN/CPXDP

Compal Secret Data

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

+3VS

1 2

PAD

CRB 8.2K

+3VALW_PCH_PRIM

+3VALW_DSW

PBTN_OUT# [49]

AC_PRESENT [49]

T10

PAD

EC_GPIO5D [40,49]

PM_CLKRUN#

PCH_VRALERT#

PBTN_OUT#_R

AC_PRESENT_R

PM_SLP_S3#

PM_SLP_S4#

SYS_PWROK

SYS_RESET#

R109 10K_0402_5%

R113 10K_0402_5%

R115 100K_0402_5%

1 2

R116 0_0402_5%

1 2

R120 0_0402_5%

1 2

R122 10K_0402_5%

C132 .1U_0402_16V7K

@EMI@

Intel DCI debug 1121

JTAG_TDO

EC_SMB_CK2[26,47,49]

EC_SMB_DA2[26,47,49]

EC_SMB_CK2 PCH_SML1CLK

EC_SMB_DA2 PCH_SML1DATA

1121

PCH_SMBCLK_R[13,14,44,47]

PCH_SMBDATA_R[13,14,44,47]

PCH_SMBCLK_R

Title

Size Document Number Re v

Custom

Date: Sheet o f

1 2

R9491 51_0402_1%

+3VS

Q1A

DMN66D0LDW-7_SOT363-6

Q1B DMN66D0LDW-7_SOT363-6

R9449

1 2

0_0201_5%@

R9450

1 2

0_0201_5%@

+3VS

Q2A

DMN66D0LDW-7_SOT363-6

Q2B DMN66D0LDW-7_SOT363-6

1121

R9451

1 2

0_0201_5%@

R9452

1 2

0_0201_5%@

Compal Electronics, Inc.

PCH(4/8)CGPIO,SMBUS

Merlyn2 LA-D214P

PAD

PCH_SMBCLK

PCH_SMBDATAPCH_SMBDATA_R

T54

PCH

1.0

18 66Monday, November 28, 2016

1.0

1 1

2 2

3 3

+3VS

RP19

10K_0804_8P4R_5%

1 2

RH2 10M_0402_5%

1 2

32.768KHZ 9PF 20PPM 9H03280012 8P2_0402_50V8J

CH3

18 27 36 45

RTCX1

RTCX2

LAN_CLKREQ# CR_CLKREQ# WLAN_CLKREQ# M2_CLKREQ#

8P2_0402_50V8J

CH4

RH3 1M_0402_5%

R9483 33_0201_5%

Y2 24MHZ_12PF_7V24000020

15P_0402_50V8J

CH1

1 2

GND

REV = 1.3

SPT-H_PCH

CLKOUT_CPUPCIBCLK_N CLKOUT_CPUPCIBCLK_P

7 OF 12

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

CLKOUT_PCIE_N4 CLKOUT_PCIE_P4

CLKOUT_PCIE_N5 CLKOUT_PCIE_P5

CLKOUT_PCIE_N6 CLKOUT_PCIE_P6

CLKOUT_PCIE_N7 CLKOUT_PCIE_P7

CLKOUT_PCIE_N8 CLKOUT_PCIE_P8

CLKOUT_PCIE_N9 CLKOUT_PCIE_P9

CLKOUT_PCIE_N10

CLKOUT_PCIE_P10

CLKOUT_PCIE_N11

CLKOUT_PCIE_P11

L1 L2 J1 J2

N7 N8

L7 L5

D3 F2

E5 G4

D5 E6

D8 D7

R8 R7

U5 U7

W10 W11

N3 N2

P3 P2

R3 R4

CLK_PEG_VGA#

CLK_PEG_VGA

CLK_PCIE_LAN#

CLK_PCIE_LAN

CLK_PCIE_WLAN#

CLK_PCIE_WLAN

CLK_PCIE_CR#

CLK_PCIE_CR

CLK_PCIE_M2#

CLK_PCIE_M2

CPU_PCIBCLK# [8] CPU_PCIBCLK [8]

CLK_PEG_VGA# [23]

CLK_PEG_VGA [23]

CLK_PCIE_LAN# [40] CLK_PCIE_LAN [40]

CLK_PCIE_WLAN# [44] CLK_PCIE_WLAN [44]

CLK_PCIE_CR# [42] CLK_PCIE_CR [42]

CLK_PCIE_M2# [44] CLK_PCIE_M2 [44]

dGPU

GLAN

NGFF WL+BT(KEY E)

Card Reader

M2 SSD

U2G

AR17

GPP_A16/CLKOUT_48

CPU_24M[8] CPU_24M#[8]

CPU_BCLK[8] CPU_BCLK#[8]

XTAL24_OUT XTAL24_IN

+1.0VALW_VCCCLK5

PH at DGPU side

XTAL24_OUT

XTAL24_IN

R9484 33_0201_5%

15P_0402_50V8J

CH2

FOLLOW RVP11

PEG_CLKREQ#[23] LAN_CLKREQ#[40] WLAN_CLKREQ#[44] CR_CLKREQ#[42] M2_CLKREQ#[44]

RH12.7K_0402_1%

XCLK_BIASREF

RTCX1 RTCX2

PEG_CLKREQ# LAN_CLKREQ# WLAN_CLKREQ# CR_CLKREQ# M2_CLKREQ#

CLKOUT_CPUNSSC_P

CLKOUT_CPUNSSC_N

CLKOUT_CPUBCLK_P

CLKOUT_CPUBCLK_N

XTAL24_OUT

XTAL24_IN

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

CLKOUT_PCIE_N14

CLKOUT_PCIE_P14

CLKOUT_PCIE_N13

CLKOUT_PCIE_P13

CLKOUT_PCIE_N12

CLKOUT_PCIE_P12

SKL-H-PCH_BGA837

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(5/8)CLK

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet o f

19 66Monday, November 28, 2016

1.0

Functional Strap Definitions

GSPI1_MOSI / GPP_B22 int. PD Boot BIOS Destination 0 = SPI (Default) 1 = LPC

GSPI0_MOSI / GPP_B18 int. PD

1 1

0 = Disable “ No Reboot” mode. ( Def ault) 1 = Enable “ No Reboot” mode ( PCH will di sable t he T CO Timer system reboot feature).

+3VS

UART_2_CRXD_DTXD

R128 49.9K_0402_1% R130 49.9K_0402_1%

2 2

+3VS

R181 10K_0402_5%

R133 10K_0402_5%

R134 10K_0402_5%

3 3

DIS@

UART_2_CTXD_DRXD

CMOS_DET#

DGPU_PWR_EN

DGPU_HOLD_RST#

EC_SCI#_SMI#[16,49]

GC6_FB_EN_R#[26]

CMOS_DET#[35] BT_OFF#

GPU_EVENT#_R[26]

DGPU_HOLD_RST#

DGPU_PWR_EN[33]

UART_2_CTXD_DRXD UART_2_CRXD_DTXD

1 2

1121

R9470

EC_SCI#_SMI#_B20

0_0402_5%

GC6_FB_EN_R#

CMOS_DET# BT_OFF# GPU_EVENT#_R

DGPU_HOLD_RST# DGPU_PWR_EN

UART_2_CCTS_DRTS UART_2_CRTS_DCTS UART_2_CTXD_DRXD UART_2_CRXD_DTXD

U2K

AT29

GPP_B22/GSPI1_MOSI

AR29

GPP_B21/GSPI1_MISO

AV29

GPP_B20/GSPI1_CLK

BC27

GPP_B19/GSPI1_CS#

BD28

GPP_B18/GSPI0_MOSI

BD27

GPP_B17/GSPI0_MISO

AW27

GPP_B16/GSPI0_CLK

AR24

GPP_B15/GSPI0_CS#

AV44

GPP_C9/UART0_TXD

BA41

GPP_C8/UART0_RXD

AU44

GPP_C11/UART0_CTS#

AV43

GPP_C10/UART0_RTS#

AU41

GPP_C15/UART1_CTS#/ISH_UART1_CTS#

AT44

GPP_C14/UART1_RTS#/ISH_UART1_RTS#

AT43

GPP_C13/UART1_TXD/ISH_UART1_TXD

AU43

GPP_C12/UART1_RXD/ISH_UART1_RXD

AN43

GPP_C23/UART2_CTS#

AN44

GPP_C22/UART2_RTS#

AR39

GPP_C21/UART2_TXD

AR45

GPP_C20/UART2_RXD

AR41

GPP_C19/I2C1_SCL

AR44

GPP_C18/I2C1_SDA

AR38

GPP_C17/I2C0_SCL

AT42

GPP_C16/I2C0_SDA

AM44

GPP_D4/ISH_I2C2_SDA/ISH_I2C3_SDA

AJ44

GPP_D23/ISH_I2C2_SCL/ISH_I2C3_SCL

SKL-H-PCH_BGA837

REV = 1.3

SPT-H_PCH

GPP_D9 GPP_D10 GPP_D11

GPP_D16/ISH_UART0_CTS#

GPP_D14/ISH_UART0_TXD/SML0BCLK/I2C2_SCL

GPP_D13/ISH_UART0_RXD/SML0BDATA/I2C2_SDA

GPP_D15/ISH_UART0_RTS#

11 OF 12

GPP_D12

GPP_H20/ISH_I2C0_SCL

GPP_H19/ISH_I2C0_SDA

GPP_H22/ISH_I2C1_SCL

GPP_H21/ISH_I2C1_SDA

GPP_A23/ISH_GP5 GPP_A22/ISH_GP4 GPP_A21/ISH_GP3 GPP_A20/ISH_GP2 GPP_A19/ISH_GP1 GPP_A18/ISH_GP0 GPP_A17/ISH_GP7

AL44 AL36 AL35 AJ39

AJ43 AL43 AK44 AK45

BC38 BB38

BD38 BE39

BC22 BD18 BE21 BD22 BD21 BB22 BC19

T15

PAD

T16

PAD

T17

PAD

T18

PAD

T19

PAD

T20

PAD

T21

PAD

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING D RAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2016/05/13 2017/12/31

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

PCH(6/8)UART,I2C,GPIO

Size Document Number Re v

Custom

Merlyn2 LA-D214P

Date: Sheet o f

20 66Monday, November 28, 2016

1.0

+ 46 hidden pages

Lenovo Thinkpad S5 E560P Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual