Lenovo thinkpad s3 s440 Schematics

1

2

3

4

5

Compal Confidential

Model Name : VIUV1

A A

File Name : LA-9761P
BOM P/N:

B B

Compal Confidential

M/B Schematics Document

Intel Haswell with DDR3L

AMD SUN GPU

C C

2012-09-20

REV:0.1

D D

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

1

http://sualaptop365.edu.vn

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

2011/07/12 2012/07/01

2011/07/12 2012/07/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Cover Sheet

Cover Sheet

Cover Sheet

LA-9761PR01

LA-9761PR01

LA-9761PR01

5

1 47Friday, November 02, 2012

1 47Friday, November 02, 2012

1 47Friday, November 02, 2012

0.1

0.1

0.1

A

B

C

D

E

Compal Confidential

Model Name : VIUV1

1 1

File Name : LA-9761P
BOM P/N:

EDP Connector

(Sub Board)

2 2

(Docking)

(Sub Board)

3 3

HDMI Connector

Display Port

Card Reader

Realtek RTS5227

LAN

Realtek RTL8111GS

RJ45 CONN

AMD Sun XT

23mm * 23mm

DDR3*4
VRAM 128M*16/256M*16

DDI2

DDI1

port 3

port 4

SPI ROM
BIOS 8M

SPI

PCI-E X4(Gen2) Memory Bus

port 5

DDR3L 1600MHz (1.35V)
~8GB

Intel
SharkBay
Consumer/
Coporate CPU

EDP (EDP1.3)

HDMI(HDMI1.4)

DP(DP1.2)

PCI-E(Gen2)

SMLink

ULT (15W)

BGA

EC

ENE KBC9012

Page 5~15

HD Audio

USB 3.0

USB 2.0

SATA(Gen3)

LPC

TPM (Labatt)

DDR3L-SO-DIMM X1

Audio Codec

Conexant CX20751

2Channel Speaker

Digital MIC

Audio combo Jack

port 2

USB PORT 3.0 [debug]

port 1

port 1

USB PORT 3.0

port 0

port 3

USB PORT 3.0

port 2

CMOS Camera

port 5

(Sub Board)

(Docking)

Finger Printer (Sub Board)

port 6

SATA 3.0 HDD CONN

port 0

NGFF card

port 1

mSATA

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

(Option)

LA-9761PR01

LA-9761PR01

LA-9761PR01

E

0.1

0.1

2 47Friday, November 02, 2012

2 47Friday, November 02, 2012

2 47Friday, November 02, 2012

0.1

PCI Express Mini card

WLAN / WiMAX / BT

PCIE (WLAN)

port 2

USB(BT)

port 3

Int.KBD

NFC

Click Pad
(6pin&12pin)

Touch panel

G-Sensor

LIS34ALTR

Thermal Sensor

Fintek F75303M
CPU & RAM & NGFF

(Option)

Thermal Sensor

4 4

UCPU2

ZZZ

ZZZ

LA9761P

DA_PCB

DA_PCB

DA8000XV000

DA8000XV000

UCPU2

CPU2@

CPU2@

QDJ6_B1_1.0G

QDJ6_B1_1.0G

SA00006FY00

SA00006FY00

UCPU3

UCPU3

CPU3@

CPU3@

QDJ7_B0_0.8G

QDJ7_B0_0.8G

SA000067H20

SA000067H20

A

UCPU4

UCPU4

CPU4@

CPU4@

QDJ9_B1_1.2G

QDJ9_B1_1.2G

SA00006G100

SA00006G100

UCPU5

UCPU5

UCPU6

UCPU6

w w w . c h i n a f i x . c o m

CPU5@

CPU5@

QDJB_B0_0.8G

QDJB_B0_0.8G

SA000067010

SA000067010

CPU6@

CPU6@

QDJC_B1_0.8G

QDJC_B1_0.8G

SA00006EY10

SA00006EY10

http://sualaptop365.edu.vn

B

On-semi ADM1032-1
GPU thermal (Reserved)

C

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Thermal Sensor

Nuvoton NCT7718
Panel

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

2011/07/12 2012/07/01

2011/07/12 2012/07/01

2011/07/12 2012/07/01

Deciphered Date

D

1

2

3

4

5

Voltage Rails

0
1
2
3
4
5
6
7

USB 2.0 Port

SIGNAL

SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

ON

ON

ON

ON

ON ON ON

ON

OFF

OFFLOW LOW LOW LOW

HIGH HIGH HIGH HIGH

LOW LOW

HIGH

LOWLOWLOW

HIGH

HIGH

PCB Revision

0.1

USB 3.0 Port Table

3 External

0
1
2
3
4
5
6
7

USB Port

USB 3.0 Port (I/O Board)
USB 3.0 Port (MB)
USB 3.0 Port (Docking)
Mini Card (WLAN/BT)
Touch Screen
Camera
FPR

Port

1
2
3
4

SATA Port Table

Port

0
1
2
3 3

OFF

OFF

OFF

OFF

OFF

OFF

USB 3.0 Port (I/O Board)
USB 3.0 Port (MB)
USB 3.0 Port (Docking)

HDD
NGFF SSD

STATE

+5VS

power
plane

A A

CHECK!

State

+5VALW

+B

+1.5V

+3VALW

+3VS

+1.5VS

+VCCP

+CPU_CORE

+VGA_CORE

+VCC_GFXCORE_AXG

+1.8VS

+0.75VS

+1.05VS

+3VM

+1.05VM

(SBA Only)

CHECK!

Full ON

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

BOARD ID Table

Board ID

S0

S3

S5 S4/AC

S5 S4/ Battery only

B B

S5 S4/AC & Battery
don't exist

EC SM Bus1 address

Device

Smart Battery

Address Address

PCH SM Bus address

Device Address

DDR DIMM0
WALN

C C

Touch Pad
Security ROM

O

O

O

O

O

O

X

X

X

X X X

OO

O

X

X X

X

EC SM Bus2 address

Device

Thermal Sensor Fintek F75303M
Panel Sensor AMD1032ARMZ
VGA Sensor AMD1032ARMZ
SharkBay ULT
AMD SUN XT

PCH SML0 Bus address

NFC

X

O

M3 Supported

O

M3 Supported

O

M3 Supported

AddressDevice

USB 2.0 Port Table

BOM Structure Table

BTO Item BOM Structure

Connector ME@
45 LEVEL 45@
Unpop

@
DIS@AMD SUN XT
VRAM@VRAM Option

UMA@INTEL UMA

CPU OPTION CPU@
Intel AOAC AOAC@/nonAOAC@
EMI PART EMI@
ESD PART
HDMI
NFC

ESD@

HDMI@

NFC@

LAN RTL8111G(S) LDO@/SWR@
Surge protection Surge@
TPM TPM@

PCIE Port Table

Port

Lane

1
2
3
4

5

6

0
1
2
3
0
1
2

LAN
WLAN
Cardreader

GPU

SMBUS Control Table

PANEL

HOST

VGA BATT KB9012 SODIMM

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2
SMBCLK
SMBDATA
SML0CLK

D D

SML0DATA
SML1CLK
SML1DATA

KB9012

+3VLP

KB9012

+3VS

CPU

+3VALW

CPU

+3VALW

KB9012

+3VS

1

X V

V

+3VS

X
X

+3VLP

X
X

X
X

X

X

X

X X

+3VS

http://sualaptop365.edu.vn

X
X

V

+3VS +3VALW

X

sensor

WLAN

ADM1032

X

X

V

X X

+3VSV+3VS

V

X
XX
XX V

X

w w w . c h i n a f i x . c o m

2

VGA

Thermal

sensor

sensor

ADM1032

F75303

X X X

X

V

+3VS

X X
X X
X X X

CPU
Sensor

X

V

+3VALW

X
X

V

+3VALW

Touch
Pad

X

+3VS

X

Security
ROM

VV

+3VS

X
X

NFC

X
X
X

V

+3VS

X

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2011/07/12 2012/07/01

2011/07/12 2012/07/01

2011/07/12 2012/07/01

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

4

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

Notes List

Notes List

Notes List

LA-9761PR01

LA-9761PR01

LA-9761PR01

5

3 47Friday, November 02, 2012

3 47Friday, November 02, 2012

3 47Friday, November 02, 2012

0.1

0.1

0.1

5

D D

4

U1A

U1A

HASWELL_MCP_E

HASWELL_MCP_E

3

2

1

EDP_TXN0
EDP_TXP0
EDP_TXN1
EDP_TXP1

EDP_TXN2
EDP_TXP2
EDP_TXN3
EDP_TXP3

EDP_AUXN
EDP_AUXP

Rev1p2

Rev1p2

PROC_TCK
PROC_TMS

PROC_TRST

PROC_TDI

PROC_TDO

PRDY
PREQ

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
BPM#6
BPM#7

Rev1p2

Rev1p2

C45
B46
A47
B47

C47
C46
A49
B49

A45
B45

D20
A43

J62
K62
E60
E61
E59
F63
F62

J60
H60
H61
H62
K59
H63
K60
J61

EDP_TXN0 <30>
EDP_TXP0 <30>
EDP_TXN1 <30>
EDP_TXP1 <30>

EDP_AUXN <30>
EDP_AUXP <30>

EDP_COMP
CPU_INV_PWM

1 2

R1 24.9_0402_1%R1 24.9_0402_1%

1 2

R31 0_0402_5%@R31 0_0402_5%@

EDP_COMP:
Trace width=20 mils,Spacing=25mil,Max length=100mils

XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO

XDP_BPM#0_R
XDP_BPM#1_R

T102@ T102@

T16@ T16@
T107@ T107@
T15@ T15@
T97@ T97@
T98@ T98@
T99@ T99@
T100@ T100@
T101@ T101@

R41

@R4 1

@

1 2

0_0402_5%

0_0402_5%

+VCCIOA_OUT

INVPWM <30,8>

PCH_JTAG_RST#

PCH_JTAG_RST# <6>

PU/PD for JTAG signals

H_PROCHOT#_R

H_CPUPWRGD

C54
C55
B58
C58
B55
A55
A57
B57

C51
C50
C53
B54
C49
B50
A53
B53

AU60

AU61

AV60

AV15
AV61

D61
K61
N62

K63

C61

DDI1_TXN0
DDI1_TXP0
DDI1_TXN1
DDI1_TXP1
DDI1_TXN2
DDI1_TXP2
DDI1_TXN3
DDI1_TXP3

DDI2_TXN0
DDI2_TXP0
DDI2_TXN1
DDI2_TXP1
DDI2_TXN2
DDI2_TXP2
DDI2_TXN3
DDI2_TXP3

@

@

U1B

U1B

PROC_DETECT
CATERR
PECI

PROCHOT

PROCPWRGD

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
SM_DRAMRST
SM_PG_CNTL1

DDI EDP

DDI EDP

1 OF 19

1 OF 19

HASWELL_MCP_E

HASWELL_MCP_E

MISC

MISC

JTAG

JTAG

THERMAL

THERMAL

PWR

PWR

DDR3

DDR3

2 OF 19

2 OF 19

EDP_RCOMP

EDP_DISP_UTIL

CPU_DP1_N0<31>
CPU_DP1_P0<31>
CPU_DP1_N1<31>

DP to Docking ( 2 lane )

HDMI (Sub Board)

C C

+1.05VS

H_PROCHOT#<26,35,36,37>

B B

DDR3 Compensation Signals:
20mils to comp signals
25mils to non-comp signals
500mil for Max trace length

CPU_DP1_P1<31>

CPU_DP2_N0<27>
CPU_DP2_P0<27>
CPU_DP2_N1<27>
CPU_DP2_P1<27>
CPU_DP2_N2<27>
CPU_DP2_P2<27>
CPU_DP2_N3<27>
CPU_DP2_P3<27>

H_PECI<26>

1 2

R2

R2

62_0402_5%

62_0402_5%

R6 10K_0402_5%R6 10K_0402_5%

DDR3 Compensation Signals

R9 200_0402_1%R9 200_0402_1%
R10 75_0402_1%R10 75_0402_1%
R11 100_0402_1%R11 100_0402_1%

Chklist 1.0
SM_RCOMP1 -->120 ohm 1%

1 2
1 2
1 2

DDR_PG_CTRL<15>

1 2

T111 @T111 @

R3

R3
56_0402_5%

56_0402_5%

1 2

T2 @T2 @

SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
DIMM_DRAMRST#
DDR_PG_CTRL

+1.05VS

+1.35V

12

R29

R29
470_0402_5%

470_0402_5%

DIMM_DRAMRST#

A A

DIMM_DRAMRST# <15>

ESD

H_CPUPWRGD

1

C2222
100P_0402_50V8J

100P_0402_50V8J

2

XDP_TMS

XDP_TDI

XDP_PREQ#

@C2222

@

XDP_TDO

XDP_TCK

XDP_TRST#

1 2

R15 51_0402_5%@R15 51_0402_5%@

1 2

R16 51_0402_5%@R16 51_0402_5%@

1 2

R17 51_0402_5%@R17 51_0402_5%@

1 2

R18 51_0402_5%@R18 51_0402_5%@

1 2

R25 51_0402_5%R25 51_0402_5%

1 2

R28 51_0402_5%@R28 51_0402_5%@

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

http://sualaptop365.edu.vn

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(1/11) DDI,MSIC,XDP

HSW MCP(1/11) DDI,MSIC,XDP

HSW MCP(1/11) DDI,MSIC,XDP

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

4 47Friday, November 02, 2012

4 47Friday, November 02, 2012

4 47Friday, November 02, 2012

0.1

0.1

0.1

5

D D

HASWELL_MCP_E

U1C

U1C

AH63

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

C C

B B

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

AH62
AK63
AK62
AH61
AH60
AK61
AK60
AM63
AM62
AP63
AP62
AM61
AM60
AP61
AP60
AP58
AR58
AM57
AK57

AL58
AK58
AR57
AN57
AP55
AR55
AM54
AK54

AL55
AK55
AR54
AN54
AY58

AW58

AY56

AW56

AV58
AU58
AV56
AU56
AY54

AW54

AY52

AW52

AV54
AU54
AV52
AU52
AK40
AK42

AM43
AM45

AK45
AK43

AM40
AM42
AM46

AK46

AM49

AK49

AM48

AK48

AM51

AK51

SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63

HASWELL_MCP_E

3 OF 19

3 OF 19

DDR CHANNEL A

DDR CHANNEL A

4

AU37

SA_CLK#0

AV37

SA_CLK0

AW36

SA_CLK#1

AY36

SA_CLK1

AU43

SA_CKE0

AW43

SA_CKE1

AY42

SA_CKE2

AY43

SA_CKE3

AP33

SA_CS#0

AR32

SA_CS#1

AP32

AY34
AW34
AU34

AU35
AV35
AY41

AU36
AY37
AR38
AP36
AU39
AR36
AV40
AW39
AY39
AU40
AP35
AW41
AU41
AR35
AV42
AU42

AJ61
AN62
AM58
AM55
AV57
AV53
AL43
AL48

AJ62
AN61
AN58
AN55
AW57
AW53
AL42
AL49

AP49
AR51
AP51

DDRA_ODT0

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SM_DIMM_VREFCA <15>
SA_DIMM_VREFDQ <15>

SA_ODT0

SA_RAS

SA_WE

SA_CAS

SA_BA0
SA_BA1
SA_BA2

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_MA14
SA_MA15

SA_DQSN0
SA_DQSN1
SA_DQSN2
SA_DQSN3
SA_DQSN4
SA_DQSN5
SA_DQSN6
SA_DQSN7

SA_DQSP0
SA_DQSP1
SA_DQSP2
SA_DQSP3
SA_DQSP4
SA_DQSP5
SA_DQSP6
SA_DQSP7

SM_VREF_CA
SM_VREF_DQ0
SM_VREF_DQ1

3

SA_CLK_DDR#0 <15>
SA_CLK_DDR0 <15>
SA_CLK_DDR#1 <15>
SA_CLK_DDR1 <15>

DDRA_CKE0_DIMMA <15 >
DDRA_CKE1_DIMMA <15 >

DDRA_CS0_DIMMA# <15>
DDRA_CS1_DIMMA# <15>

T4@ T4@

DDR_A_RAS# < 15>

DDR_A_WE# <15>

DDR_A_CAS# < 15>

DDR_A_BS0 <15>
DDR_A_BS1 <15>
DDR_A_BS2 <15>

DDR_A_D[0..63]<15>

DDR_A_MA[0..15]<15>

DDR_A_DQS#[0..7]<15>

DDR_A_DQS[0..7]<15>

AY31

AW31

AY29

AW29

AV31
AU31
AV29
AU29

AY27

AW27

AY25

AW25

AV27
AU27
AV25
AU25

AM29

AK29

AL28
AK28
AR29
AN29
AR28
AP28
AN26
AR26
AR25
AP25
AK26

AM26

AK25

AL25

AY23

AW23

AY21

AW21

AV23
AU23
AV21
AU21

AY19

AW19

AY17

AW17

AV19
AU19
AV17
AU17
AR21
AR22

AL21
AM22
AN22
AP21
AK21
AK22
AN20
AR20
AK18

AL18
AK20
AM20
AR18
AP18

U1D

U1D

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

2

HASWELL_MCP_E

HASWELL_MCP_E

DDR CHANNEL B

DDR CHANNEL B

4 OF 19

4 OF 19

SB_CK#0

SB_CK0

SB_CK#1

SB_CK1

SB_CKE0
SB_CKE1
SB_CKE2
SB_CKE3

SB_CS#0
SB_CS#1

SB_ODT0

SB_RAS

SB_WE

SB_CAS

SB_BA0
SB_BA1
SB_BA2

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14
SB_MA15

SB_DQSN0
SB_DQSN1
SB_DQSN2
SB_DQSN3
SB_DQSN4
SB_DQSN5
SB_DQSN6
SB_DQSN7

SB_DQSP0
SB_DQSP1
SB_DQSP2
SB_DQSP3
SB_DQSP4
SB_DQSP5
SB_DQSP6
SB_DQSP7

AM38
AN38
AK38
AL38

AY49
AU50
AW49
AV50

AM32
AK32

AL32

AM35
AK35
AM33

AL35
AM36
AU49

AP40
AR40
AP42
AR42
AR45
AP45
AW46
AY46
AY47
AU46
AK36
AV47
AU47
AK33
AR46
AP46

AW30
AV26
AN28
AN25
AW22
AV18
AN21
AN18

AV30
AW26
AM28
AM25
AV22
AW18
AM21
AM18

1

Rev1p2

Rev1p2

A A

Rev1p2

Rev1p2

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

http://sualaptop365.edu.vn

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet

Compal Electronics, Inc.

HSW MCP(2/11) DDRIII

HSW MCP(2/11) DDRIII

HSW MCP(2/11) DDRIII

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

0.1

0.1

0.1

of

5 47Friday, November 02, 2012

5 47Friday, November 02, 2012

5 47Friday, November 02, 2012

5

4

3

2

1

1

C4

C4
18P_0402_50V8J

18P_0402_50V8J

2

1 2

R39 330K_0402_5% R39 330K_0402_5%

1 2

R40 330K_0402_5%@R40 330K_0402_5%@

PCH_RTCX1

PCH_RTCX2

+RTCVCC

1 2

R33 10 M_0402_5%R33 10M_0402_ 5%

Y1

Y1

D D

C C

1 2

32.768KHZ_12.5PF_1TJF125DP1A000D

32.768KHZ_12.5PF_1TJF125DP1A000D

1

C3

C3
18P_0402_50V8J

18P_0402_50V8J

2

PCH_INTVRMEN

INTVRMEN (+1.05 VA)

H：Integrated VRM enable

*

L：Integrated VRM disable

RTC Battery

W=20mils W=20mils

+RTCVCC +RTCBATT

1 2

R107

R107

0_0402_5%

1

C179

C179
1U_0402_6.3V6K

1U_0402_6.3V6K

2

0_0402_5%

Safty suugestion remove EE side ,Keep PWR side

JME2 Short PAD placement to Bottom side.

ME CMOS

+RTCVCC

R36 20K_0402_1%R36 20K_0402_1%

R37 20K_0402_1%R37 20K_0402_1%

1U_0603_10V6K

1U_0603_10V6K

1 2
1 2

1U_0603_10V6K

1U_0603_10V6K

EMI

1

JME1

1 2

2

1

1 2

2

HDA_BIT_CLK

12

RA38
33_0402_5%

33_0402_5%

CA79
22P_0402_50V8J

22P_0402_50V8J

JME1
SHORT PADS

SHORT PADS

@

@

JME2

JME2
SHORT PADS

SHORT PADS

CMOS

@

@

@RA38

@

@CA79

@

C2

C2

C5

C5

HDA_SDIN0<24>

+RTCVCC

R35 1M_0402_5% R35 1M_0402_5%

PCH_JTAG_RST#<4>

1 2

T106@T106@

PCH_RTCX1
PCH_RTCX2
SM_INTRUDER#
PCH_INTVRMEN
PCH_SRTCRST#
PCH_RTCRST#

HDA_BIT_CLK
HDA_SYNC
HDA_RST#
HDA_SDIN0

HDA_SDOUT

PCH_JTAG_RST#
PCH_JTAG_TCK
PCH_JTAG_TDI
PCH_JTAG_TDO
PCH_JTAG_TMS

PCH_TCK_JTAGX

U1E

U1E

AW5

RTCX1

AY5

RTCX2

AU6

INTRUDER

AV7

INTVRMEN

AV6

SRTCRST

AU7

RTCRST

AW8

HDA_BCLK/I2S0_SCLK

AV11

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST/I2S_MCLK

AY10

HDA_SDI0/I2S0_RXD

AU12

HDA_SDI1/I2S1_RXD

AU11

HDA_SDO/I2S0_TXD

AW10

HDA_DOCK_EN/I2S1_TXD

AV10

HDA_DOCK_RST/I2S1_SFRM

AY8

I2S1_SCLK

AU62

PCH_TRST

AE62

PCH_TCK

AD61

PCH_TDI

AE61

PCH_TDO

AD62

PCH_TMS

AL11

RSVD

AC4

RSVD

AE63

JTAGX

AV2

RSVD

HASWELL_MCP_E

HASWELL_MCP_E

RTC

RTC

5 OF 19

5 OF 19

JTAG

JTAG

SATA_IREF

RSVD
RSVD

SATALED

Rev1p2

Rev1p2

J5
H5
B15
A15

J8
H8
A17
B17

J6
H6
B14
C15

F5
E5
C17
D17

V1
U1
V6
AC1

A12
L11
K10
C12
U3

EC_SMI#
PCH_GPIO35
PCH_GPIO36
PCH_GPIO37

SATA_IREF

SATA_RCOMP
PCH_SATALED#

SATA_RN0/PERN6_L3
SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3
SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2
SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2
SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1
SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATAAUDIO

SATAAUDIO

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0
SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0
SATA_TP3/PETP6_L0

SATA0GP/GPIO34
SATA1GP/GPIO35
SATA2GP/GPIO36
SATA3GP/GPIO37

SATA_RCOMP

SATA_PRX_DTX_N0 <28>
SATA_PRX_DTX_P0 <28>
SATA_PTX_DRX_N0 <28>
SATA_PTX_DRX_P0 <28>

SATA_PRX_DTX_N1 <28>
SATA_PRX_DTX_P1 <28>
SATA_PTX_DRX_N1 <28>
SATA_PTX_DRX_P1 <28>

EC_SMI# <26>
PCH_GPIO35 <9>
PCH_GPIO36 <9>
PCH_GPIO37 <9>

1 2

R42 0_0603_5%R42 0_0603_5%

within 500 mils

1 2

R43 3.01K_0402_1%R43 3.01K_0402_1%

PCH_SATALED# <32,9>

HDD

mSATA

+1.05VS_ASATA3PLL

+3VALW_PCH

B B

HDA_SDOUT

ME debug mode,t his signal has a weak interna l PD
* Low = Disable d (Default)
High = Enabled [Flash Descript or Security Ov eride]

A A

R1239 1K_0402_5%@R1239 1K_0402_5%@

12

R121
200_0402_5%

200_0402_5%

12

R126
100_0402_1%

100_0402_1%

1 2

@R121

@

@R126

@

HDA_SDOUT

+3VALW_PCH+3VALW_PCH +3VALW _PCH

12

R129

R129
200_0402_5%

200_0402_5%

PCH_JTAG_TMSPCH_JTAG_TDO PCH_JTAG_TDI

12

R130

R130
100_0402_1%

100_0402_1%

12

R124

R124
200_0402_5%

200_0402_5%

12

R131

R131
100_0402_1%

100_0402_1%

9/28

EMI

RP14

EMI@RP14

EMI@

1

2

R53 0_0402_5% R53 0_0 402_5%

1 8
2 7
3 6
4 5

33_8P4R_5%

33_8P4R_5%

1 2

HDA_SDOUT_AUDIO<24>

HDA_SYNC_AUDIO<24>
HDA_RST_AUDIO#<24>

HDA_BITCLK_AUDIO<24>

C5205

@C5205

@

68P_0402_50V8J

68P_0402_50V8J

RF

ME_FLASH<26>

HDA_SDOUT
HDA_SYNC
HDA_RST#
HDA_BIT_CLK

w w w . c h i n a f i x . c o m

R86 51_0402_5%@R86 51_0402_5%@

1 2

5

PCH_JTAG_TCK

9/28

http://sualaptop365.edu.vn

4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Compal Electronics, Inc.

HSW MCP(3/11) RTC,SATA,XDP

HSW MCP(3/11) RTC,SATA,XDP

HSW MCP(3/11) RTC,SATA,XDP

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

6 47Friday, November 02, 2012

6 47Friday, November 02, 2012

6 47Friday, November 02, 2012

0.1

0.1

0.1

5

4

3

2

1

HASWELL_MCP_E

HASWELL_MCP_E

HASWELL_MCP_E

LPC

LPC

SPI C-LINK

SPI C-LINK

RP4

RP4

1 8
2 7
3 6
4 5

15_8P4R_5%

15_8P4R_5%

+3VS

1

C91

C91

0.1U_0402_16V4Z

0.1U_0402_16V4Z

2

HASWELL_MCP_E

CLOCK

CLOCK

SIGNALS

SIGNALS

6 OF 19

6 OF 19

7 OF 19

7 OF 19

A25

XTAL24_IN

XTAL24_OUT

RSVD
RSVD

DIFFCLK_BIASREF

TESTLOW_C35
TESTLOW_C34
TESTLOW_AK8
TESTLOW_AL8

CLKOUT_LPC_0
CLKOUT_LPC_1

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

Rev1p2

Rev1p2

SMBALERT/GPIO11

SMBCLK

SMBDATA

SMBUS

SMBUS

SML0ALERT/GPIO60

SML0CLK

SML1ALERT/PCHHOT/GPIO73

PCH_SPI_MOSI
PCH_SPI_WP#
PCH_SPI_MISO
PCH_SPI_HOLD#

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

SML0DATA

SML1CLK/GPIO75

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST

Rev1p2

Rev1p2

SMBCLK
SMBDATA
SML1DATA
SML1CLK

SML0CLK
SML0DATA

3

XTAL24_IN

B25

XTAL24_OUT

K21
M21
C26

XCLK_BIASREF

C35
C34
AK8
AL8

AN15
AP15

B35
A35

AN2
AP2
AH1
AL2
AN1
AK1
AU4
AU3
AH3

AF2
AD2
AF4

CLKOUT_LPC0
CLKOUT_LPC1

CLK_BCLK_ITP#
CLK_BCLK_ITP

PCH_GPIO11
SMBCLK
SMBDATA
PCH_GPIO60
SML0CLK
SML0DATA
PCH_GPIO73
SML1CLK
SML1DATA

R92 10K_0402_5% R92 10K_0402_5%
R93 10K_0402_5% R93 10K_0402_5%
R94 10K_0402_5% R94 10K_0402_5%
R95 10K_0402_5% R95 10K_0402_5%

R96 22_0402_5% R96 22_0402_5%

T18@ T18@
T19@ T19@
T20@ T20@

EMI

RP13

RP13

1 8
2 7
3 6
4 5

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

1 2

R122 499_0402_1%NFC@R122 499_0402_1%NFC@

1 2

R123 499_0402_1%NFC@R123 499_0402_1%NFC@

Compal Secret Data

Compal Secret Data

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

1 2

R91 3.01K_0402_1%R91 3.01K_0402_1%

1 2
1 2
1 2
1 2

12

T21@ T21@
T26@ T26@

RF RF

PCH_GPIO11 <9>

PCH_GPIO60 <9>

PCH_GPIO73 <9>

PCH_SPI_CLK_R

12

RA39

@RA39

@

33_0402_5%

33_0402_5%

CA80

@CA80

@

22P_0402_50V8J

22P_0402_50V8J

+3VALW_PCH

Deciphered Date

Deciphered Date

Deciphered Date

1

2

2

+1.05VS_AXCK_LCPLL

R97 22_0402_5% R97 22_0402_5%

R99 22_0402_5%@R99 22_0402_5%@

C5207

@C 5207

@

68P_0402_50V8J

68P_0402_50V8J

SMBus :SPD/PCIe/Security/TP

FootPrint :DMN66D0LDW-7_SOT363-6

SMBDATA

SMBCLK

SML1 Bus :EC/Sensors

6 1

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6
Q3A

Q3A

Q3B 2N 7002KDWH_SOT363-6Q3B 2N 7002KDWH_SOT363-6

SMBDATA PCH_SMB_DATA

R157 0_0402_5%@R157 0_0402_5%@

SMBCLK PCH_SMB_CLK

R158 0_0402_5%@R158 0_0402_5%@

FootPrint :DMN66D0LDW-7_SOT363-6

SML1CLK

SML1DATA

SML0 Bus :NFC

FootPrint :DMN66D0LDW-7_SOT363-6

SML0CLK

SML0DATA

12

R871M_0402_5% R871M _0402_5%

Y2

Y2

24MHZ_12PF_7V24000020

24MHZ_12PF_7V24000020

1

1

GND

1

C6

2

18P_0402_50V8JC618P_0402_50V8J

12
12

1

C5210
68P_0402_50V8J

68P_0402_50V8J

2

+3VS

R132 2 .2K_0402_5%

R132 2 .2K_0402_5%

2

1 2

R133 2 .2K_0402_5%

R133 2 .2K_0402_5%

5

1 2

3 4

1 2

1 2

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6
Q2417A

Q2417A

SML1CLK

SML1DATA

SML0CLK

SML0DATA

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

+3VS

2

6 1

5

3 4

Q2417B 2N7002KDWH_SOT363-6Q2417B 2N7002KDWH_SOT363-6

1 2

R160 0_0402_5%@R160 0_0402_5%@

1 2

R161 0_0402_5%@R161 0_0402_5%@

+3VS

2

6 1

Q4A 2N7002KDWH_SOT363-6Q4A 2N7002KDW H_SOT363-6

3 4

Q4B 2N 7002KDWH_SOT363-6Q4B 2N 7002KDWH_SOT363-6

1 2

R152 0_0402_5%@R152 0_0402_5%@

1 2

R156 0_0402_5%@R156 0_0402_5%@

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Compal Electronics, Inc.

HSW MCP(4/11) CLK,SPI,SMBUS

HSW MCP(4/11) CLK,SPI,SMBUS

HSW MCP(4/11) CLK,SPI,SMBUS

LA-9761PR01

LA-9761PR01

LA-9761PR01

GND

2

4

CK_LPC_KBC <26>
CLK_PCI_TPM <30>
CLK_PCI_DB < 29>

@C 5210

@

+3VS

+3VS

PU 2.2K at EC s ide (+3VS)

EC_SMB_CK2

EC_SMB_DA2

5

SML0_SCL_NFC

SML0_SDA_NFC

1

U1F

U1F

C43

CLKOUT_PCIE_N0

C42

CLKOUT_PCIE_P0

PCH_GPIO18<9>

GLAN

D D

WLAN

Card Reader

dGPU

C C

RF

B B

CLK_PCIE_LAN#<25>
CLK_PCIE_LAN<25>
LAN_CLKREQ#<25>

CLK_PCIE_WLAN#<29>
CLK_PCIE_WLAN<29>
WLAN_CLKREQ#<29>

CLK_PCIE_CR#<30>
CLK_PCIE_CR<30>
CR_CLKREQ#<30>

CLK_PEG_VGA#<17>
CLK_PEG_VGA<17>
PEG_CLKREQ#<18>

PCH_GPIO23<9>

PCH_SPI_CLK_R

C5206
68P_0402_50V8J

68P_0402_50V8J

1

@C 5206

@

2

SPI1 ROM ( 8MByte )

U8

U8

PCH_SPI_CS0#
PCH_SPI_MISO_1
PCH_SPI_WP1#

1

CS#

2

DO

3

WP#

4

GND

W25Q32BVSSIG_SO8

W25Q32BVSSIG_SO8

SPI ROM 8MB
1ST: SA000039A20
2ND: SA000046400

PCH_GPIO18

CLK_PCIE_LAN#
CLK_PCIE_LAN

CLK_PCIE_WLAN#
CLK_PCIE_WLAN

CLK_PCIE_CR#
CLK_PCIE_CR

CLK_PEG_VGA#
CLK_PEG_VGA

PCH_GPIO23

+3VS

RP1

RP1

1 8
2 7
3 6
4 5

10K_8P4R_5%

10K_8P4R_5%

LPC_FRAME#<26,29,30>

EMI

+3VS

R106

1 2

1 2

R127 1K_0402_1%R127 1K_0402_1%

1 2

R128 1K_0402_1%R128 1K_0402_1%

8

VCC

7

HOLD#

6

CLK

5

DI

LPC_AD0<26,29,30>
LPC_AD1<26,29,30>
LPC_AD2<26,29,30>
LPC_AD3<26,29,30>

EMI@R106

EMI@

33_0402_5%

33_0402_5%

PCH_SPI_HOLD1#
PCH_SPI_CLK_R
PCH_SPI_MOSI_1

+3VS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#

PCH_SPI_CLK
PCH_SPI_CS0#

PCH_SPI_MOSI
PCH_SPI_MISO
PCH_SPI_WP#
PCH_SPI_HOLD#

C8

C8

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 2

U2

PCIECLKRQ0/GPIO18

B41

CLKOUT_PCIE_N1

A41

CLKOUT_PCIE_P1

Y5

PCIECLKRQ1/GPIO19

C41

CLKOUT_PCIE_N2

B42

CLKOUT_PCIE_P2

AD1

PCIECLKRQ2/GPIO20

B38

CLKOUT_PCIE_N3

C37

CLKOUT_PCIE_P3

N1

PCIECLKRQ3/GPIO21

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5/GPIO23

U1G

U1G

AU14

LAD0

AW12

LAD1

AY12

LAD2

AW11

LAD3

AV12

LFRAME

AA3

SPI_CLK

Y7

SPI_CS0

Y4

SPI_CS1

AC2

SPI_CS2

AA2

SPI_MOSI

AA4

SPI_MISO

Y6

SPI_IO2

AF1

SPI_IO3

PCH_SPI_MOSI_1
PCH_SPI_WP1#
PCH_SPI_MISO_1
PCH_SPI_HOLD1#

CHKLIST1.0
2 SPI Device = 33 ohm
1 SPI Device = 15 ohm

Sec. ROM

+3VS

A A

PLT_RST_BUF#<17,25,26,29,30,8>

5

12

R172

R172
10K_0402_5%

10K_0402_5%

@

@

PLT_RST_BUF#

http://sualaptop365.edu.vn

U11

U11

w w w . c h i n a f i x . c o m

1

NC

2

NC

3

PROT#

4

GND

PCA24S08D_SO8

PCA24S08D_SO8

EEPROM SA00004MK00
EEPROM SA00004ML00

VCC

SCL
SDA

WP

8
7
6

PCH_SMB_CLK

5

PCH_SMB_DATA

4

XTAL24_IN

XTAL24_OUT

3

3

1

C7

2

18P_0402_50V8JC718P_0402_50V8J

10/2

PCH_SMB_DATA <15,29,32>

PCH_SMB_CLK <15,29,32>

EC_SMB_CK2 <18,26,30,32>

EC_SMB_DA2 <18,26,30,32>

SML0_SCL_NFC <32>

SML0_SDA_NFC <32>

7 47Friday, November 02, 2012

7 47Friday, November 02, 2012

7 47Friday, November 02, 2012

0.1

0.1

0.1

5

D D

PCH_PWROK APWROK_R

ACIN<26,35,37>

C C

1 2

R146 0_0402_5%R146 0_0402_5%

+3VALW_PCH

12

R643

R643
200K_0402_5%

D2

D2

1 2

RB751V-40_SOD323-2

RB751V-40_SOD323-2

DGPU_PWR_EN<19,41,44,9>

DGPU_HOLD_RST#<17,9>

200K_0402_5%

DGPU_PWR_EN DGPU_PWR_I_EN

AC_PRESENT_R

R153 0_0402_5%@R153 0_0402_5%@
R151 0_0402_5%@R151 0_0402_5%@

R154 0_0402_5%DIS@R154 0_0402_5%DIS@

4

Note: SUSACK# a nd SUSWARN# can be tied toget her if
EC does not wan t to involve in the handshake mechanism
for the Deep Sl eep state entry and exit

CAN be NC ,if n ot support Deep Sx

1 2

PCH_GPIO30<9>
SYS_RESET#<9>
SYS_PWROK<26>
PCH_PWROK<26>

EC_RSMRST#<26>

PBTN_OUT#<26>

PCH_GPIO72<9>

PCH_GPIO29<9>

1 2
1 2

1 2

ESD

R135 0_0402_5%@R135 0_0402_5%@

@

@

12

C2223 100P_0402_50V8J

C2223 100P_0402_50V8J

1 2

R149 10K_0402_5%R149 10K_0402_5%

PCH_BATLOW# Nee d pull high to VCCDSW3_3
(If no deep Sx , connect to VC CSUS3_3)

INVPWM<30,4>
ENBKL<26>
PCH_ENVDD<30>

PCH_GPIO77<9>

PCH_GPIO80<9>

PCH_GPIO55<9>

TS_RST#<30>

PCH_GPIO51<9>
PCH_GPIO53<9>

PCH_GPIO77
DGPU_PWR_A_EN
DGPU_HOLD_A_RST#
PCH_GPIO80

PCH_GPIO55
TS_RST#

PCH_GPIO51
PCH_GPIO53

SYS_RESET#
SYS_PWROK
PCH_PWROK
APWROK_R
PLT_RST#

EC_RSMRST#
PCH_GPIO30
PBTN_OUT#
AC_PRESENT_R
PCH_GPIO72

PCH_GPIO29

T109@T109@

1 2

R150 0_0402_5%R 150 0_0402_5%

T27 @T27 @

EDP_BKCTL

3

U1H

U1H

AK2

SUSACK

AC3

SYS_RESET

AG2

SYS_PWROK

AY7

PCH_PWROK

AB5

APWROK

AG7

PLTRST

AW6

RSMRST

AV4

SUSWARN/SUSPW RDNACK/GPIO30

AL7

PWRBTN

AJ8

ACPRESENT/GPIO31

AN4

BATLOW/GPIO72

AF3

SLP_S0

AM5

SLP_WLAN/GPIO29

U1I

U1I

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA/GPIO77

P4

PIRQB/GPIO78

N4

PIRQC/GPIO79

N2

PIRQD/GPIO80

AD4

PME

U7

GPIO55

L1

GPIO52

L3

GPIO54

R5

GPIO51

L4

GPIO53

HASWELL_MCP_E

HASWELL_MCP_E

SYSTEM POWER MANAGEMENT

SYSTEM POWER MANAGEMENT

HASWELL_MCP_E

HASWELL_MCP_E

eDP SIDEBAND

eDP SIDEBAND

GPIO

GPIO

DPWROK: Tired t oghter with RSM RST#
that do not sup port Deep Sx

DSWVRMEN

DPWROK

WAKE

CLKRUN/GPIO32

SUS_STAT/GPIO61

SUSCLK/GPIO62

SLP_S5/GPIO63

SLP_S4
SLP_S3

SLP_A
SLP_SUS
SLP_LAN

Rev1p2

DDPB_CTRLCLK

DDPB_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_AUXN
DDPC_AUXN
DDPB_AUXP
DDPC_AUXP

DDPB_HPD
DDPC_HPD

EDP_HPD

Rev1p2

8 OF 19

8 OF 19

DISPLAY

DISPLAY

2

DSWODVREN - On Die DSW VR Enab le

H：Enable(DEFAULT)

*

L：Disable

1 2

R134 330K_0402_5%R134 330K_0402_5%

1 2

AW7

DSWODVRENSUSACK#_R

AV5

DPWROK

AJ5

PCH_PCIE_WAKE#

V5

PCH_GPIO32

AG4

LPCPD#

AE6

SUSCLK

AP5

PM_SLP_S5#

AJ6

PM_SLP_S4#

AT4

PM_SLP_S3#

AL5
AP4
AJ7

B9
C9
D9

DDI2_CTRL_CK

D11

DDI2_CTRL_DATA DDI2_CTRL_DATA

C5

DDI1_AUXN

B6
B5

DDI1_AUXP

A6

C8
A8
D6

R139 330K_0402_5%@R139 330K_0402_5%@

1 2

R148 0_0402_5%R148 0_0402_5%

T25@ T25@
T110@ T110@
T112@ T112@

DDI2_CTRL_CK <27>

DDI2_CTRL_DATA <27>

DDI1_AUXN <31>

DDI1_AUXP <31>

DDI1_DP_HPD <31>
DDI2_HDMI_HPD <27>
EDP_HPD <30>

+RTCVCC

EC_RSMRST#

PCH_PCIE_WAKE# <25,9>

PCH_GPIO32 <9>
LPCPD# <30>
SUSCLK <26>
PM_SLP_S5# <2 6>

PM_SLP_S4# <2 6>
PM_SLP_S3# <2 6>

DDI1_CTRL_DATADDI1_CTRL_DATA

DDI2_CTRL_CK

1

1 2

R310 2.2K_0402_5%R310 2.2K_040 2_5%

1 2

R311 2.2K_0402_5%R311 2.2K_040 2_5%

1 2

R312 2.2K_0402_5%R312 2.2K_040 2_5%

DDPB_CTRLDATA: Port B Detected
DDPC_CTRLDATA: Port C Detected

1: Port B or C is detected

*

0: Port B or C is not detected
(Have internal PD)

+3VS

9 OF 19

9 OF 19

B B

R155

R155

0_0402_5%

0_0402_5%

12

+3VS

5

U5

@U5

@

PLT_RST#

MC74VHC1G08DFT2G_SC70-5

MC74VHC1G08DFT2G_SC70-5

A A

2

P

B

4

Y

1

A

12

G

3

R159

R159

100K_0402_5%

100K_0402_5%

Rev1p2

Rev1p2

PLT_RST_BUF# <17,25,26,29,30,7>

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

http://sualaptop365.edu.vn

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(5/11) PM,GPIO,DDI

HSW MCP(5/11) PM,GPIO,DDI

HSW MCP(5/11) PM,GPIO,DDI

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

8 47Friday, November 02, 2012

8 47Friday, November 02, 2012

8 47Friday, November 02, 2012

0.1

0.1

0.1

5

+3VS

4

3

2

1

CHECK Power plane,for VGA thermtrip

1 8
2 7
3 6
4 5

1 8
2 7

D D

C C

3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

PCH_GPIO0
PCH_GPIO3
PCH_GPIO90
PCH_GPIO92

RP17 10K_8P4R_5%R P17 10K_8P4R _5%

PCH_GPIO64
PCH_GPIO65
PCH_GPIO68
PCH_GPIO70

RP16 10K_8P4R_5%R P16 10K_8P4R _5%

PCH_GPIO84
PCH_GPIO85
PCH_GPIO88
PCH_GPIO89

RP20 10K_8P4R_5%R P20 10K_8P4R _5%

PCH_GPIO39

PCH_GPIO83

RP21 10K_8P4R_5%R P21 10K_8P4R _5%

PCH_GPIO17

RP22 10K_8P4R_5%R P22 10K_8P4R _5%

PCH_GPIO4
PCH_GPIO5
PCH_GPIO69
PCH_GPIO1

RP18 10K_8P4R_5%R P18 10K_8P4R _5%

PCH_GPIO94
PCH_GPIO93
PCH_GPIO2
PCH_GPIO91

RP19 10K_8P4R_5%R P19 10K_8P4R _5%

PCH_GPIO51 <8>

PCH_GPIO32 <8>

PCH_GPIO80 <8>

PCH_GPIO23 <7>

+3VALW_PCH

+1.05VS

HASWELL_MCP_E

U1J

U1J

PCH_GPIO76
PCH_GPIO8

1 2

EC_WAKE#< 26>

mSATA_DETECT<28>

NFC_ON<32>

NFC_IRQ<32>

TS_INT#<30>

DGPU_HOLD_RST#<17,8>

R295 0_0402_5%@R295 0_0402_5%@

1 2

R302 0_0402_5%R302 0_0402_5%

1 2

R301 0_0402_5%NFC@R301 0_0402_5%NFC@

1 2

R296 0_0402_5%NFC@R296 0_0402_5%NFC@

WLBT_OFF_51#<29>

1 2

R299 0_0402_5%@R299 0_0402_5%@

1 2

R300 0_0402_5%

R300 0_0402_5%

DIS@

DIS@

WLBT_OFF_5#<29>

EC_SCI#<26>

DEVSLP1<28>

SPKR<24>

PCH_GPIO12
PCH_GPIO15
PCH_GPIO16
PCH_GPIO17
PCH_GPIO24
mSATA_DETECT_R
NFC_RESET#
NFC_IRQ_R

PCH_GPIO56
PCH_GPIO57
PCH_GPIO58
PCH_GPIO59
PCH_GPIO44
WLBT_OFF_51#
PCH_GPIO48
PCH_GPIO49
DGPU_HOLD_I_RST#
PCH_GPIO71PCH_GPIO76
PCH_GPIO13
PCH_GPIO14
PCH_GPIO25
WLBT_OFF_5#
PCH_GPIO46

PCH_GPIO9
EC_SCI#
PCH_GPIO33
PCH_GPIO70
DEVSLP1
PCH_GPIO39
SPKR

P1

BMBUSY/GPIO76

AU2

GPIO8

AM7

LAN_PHY_PWR_CTRL/GPIO12

AD6

GPIO15

Y1

GPIO16

T3

GPIO17

AD5

GPIO24

AN5

GPIO27

AD7

GPIO28

AN3

GPIO26

AG6

GPIO56

AP1

GPIO57

AL4

GPIO58

AT5

GPIO59

AK4

GPIO44

AB6

GPIO47

U4

GPIO48

Y3

GPIO49

P3

GPIO50

Y2

HSIOPC/GPIO71

AT3

GPIO13

AH4

GPIO14

AM4

GPIO25

AG5

GPIO45

AG3

GPIO46

AM3

GPIO9

AM2

GPIO10

P2

DEVSLP0/GPIO33

C4

SDIO_POWER_EN/GPIO70

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

HASWELL_MCP_E

GPIO

GPIO

10 OF 19

10 OF 19

CPU/

CPU/
MISC

MISC

LPIO

LPIO

1.8V rail

THERMTRIP

RCIN/GPIO82

SERIRQ

PCH_OPI_RCOMP

RSVD
RSVD

GSPI0_CS/GPIO83

GSPI0_CLK/GPIO84
GSPI0_MISO/GPIO85
GSPI0_MOSI/GPIO86

GSPI1_CS/GPIO87

GSPI1_CLK/GPIO88
GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90
UART0_RXD/GPIO91

UART0_TXD/GPIO92
UART0_RTS/GPIO93
UART0_CTS/GPIO94

UART1_RXD/GPIO0
UART1_TXD/GPIO1
UART1_RST/GPIO2
UART1_CTS/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66
SDIO_D1/GPIO67
SDIO_D2/GPIO68
SDIO_D3/GPIO69

Rev1p2

Rev1p2

D60

H_THERMTRIP#

V4
T4

SERIRQ

AW15

PCH_OPIRCOMP

AF20
AB21

R6

PCH_GPIO83

L6

PCH_GPIO84

N6

PCH_GPIO85

L8

PCH_GPIO86

R7

DGPU_A_PRSNT#

L5

PCH_GPIO88

N7

PCH_GPIO89

K2

PCH_GPIO90

J1

PCH_GPIO91

K3

PCH_GPIO92

J2

PCH_GPIO93

G1

PCH_GPIO94

K4

PCH_GPIO0

G2

PCH_GPIO1

J3

PCH_GPIO2

J4

PCH_GPIO3

F2

PCH_GPIO4

F3

PCH_GPIO5

G4

I2C1_SDA

F1

I2C1_SCL

E3

PCH_GPIO64

F4

PCH_GPIO65

D3

PCH_GPIO66

E4

DGPU_I_PRSNT#

C3

PCH_GPIO68

E2

PCH_GPIO69

12

R179

R179

1K_0402_1%

1K_0402_1%

R720 0_0402_5%@R7 20 0_0402_5%@

1 2

1 2

R185

R185

49.9_0402_1%

49.9_0402_1%

1 2

R729 0_0402_5%@R729 0_0402_5%@

1 2

R718 0_0402_5%@R718 0_0402_5%@

1 2

R719 0_0402_5%@R719 0_0402_5%@

1 2

R730 0_0402_5%

R730 0_0402_5%

DIS@

DIS@

RF

C5216

@C 5216

@

68P_0402_50V8J

68P_0402_50V8J

VGA_THRMTRIP# <18>
KB_RST# <26>

SERIRQ <26,30>

DGPU_PRSNT#

I2C1_SCL_TPNL

1

2

I2C1_SDA_TPNL <30>

I2C1_SCL_TPNL <30>

DGPU_PRSNT#

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

+3VALW_PCH

1 8
2 7
3 6
4 5

B B

PCH_GPIO71

RP23 10K_8P4R_5%R P23 10K_8P4R _5%

PCH_GPIO48
PCH_GPIO16
PCH_GPIO49

RP24 10K_8P4R_5%R P24 10K_8P4R _5%

RP25 10K_8P4R_5%R P25 10K_8P4R _5%

PCH_GPIO33

RP26 10K_8P4R_5%R P26 10K_8P4R _5%

KB_RST#

SERIRQ

PCH_GPIO53 <8>
PCH_GPIO36 <6>

PCH_GPIO35 <6>

PCH_GPIO18 <7>

PCH_GPIO55 <8>
PCH_GPIO77 <8>

DGPU_PWR_EN <19,41,44,8>

PCH_SATALED# <32,6>

+3VALW_PCH

+3VS

+3VS

R193 10K_0402_5%@R193 10K_0402_5%@

1 2

DEVSLP1

Check shuld be 1.8v plane or not. 9/15

+3VS

R114

R115

R197 100K_0402_5%NFC@R197 100K_0402_5%NFC@

@R114

@

@R115

@

1 2

1K_0402_5%

1K_0402_5%

1 2

1K_0402_5%

1K_0402_5%

1 2

I2C1_SDA

I2C1_SCL

NFC_IRQ_R

10/26
CRB 100K PD

PCH_GPIO86

R710 1K_0402_1%@R710 1K_0402_1%@
R711 1K_0402_1%@R711 1K_0402_1%@

GSPI0_MOSI / GPIO86 : Boot BIOS Strap

1: ENABLED (Have internal PU)

*

0: SPI ROM

PCH_GPIO66

1 2
1 2

1 2

R189 1K_0402_1%@R189 1K_0402_1%@

+3VS

SDIO_D0 / GPIO66 : Top-Block Swap Override

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

A A

1 8
2 7
3 6
4 5

5

PCH_GPIO59

RP29 10K_8P4R_5%R P29 10K_8P4R _5%

PCH_GPIO46
PCH_GPIO14

RP32 10K_8P4R_5%R P32 10K_8P4R _5%

PCH_GPIO57
PCH_GPIO13

PCH_GPIO8

RP27 10K_8P4R_5%R P27 10K_8P4R _5%

PCH_GPIO9

RP30 10K_8P4R_5%R P30 10K_8P4R _5%

PCH_GPIO30 <8>
PCH_GPIO43 <10>
PCH_GPIO73 <7> SYS_RESET# <8>

PCH_GPIO42 <10>

PCH_GPIO41 <10>

USB_OC0# <10,27,29>
PCH_GPIO60 <7>

PCH_GPIO11 <7>

w w w . c h i n a f i x . c o m

http://sualaptop365.edu.vn

1 8
2 7
3 6
4 5

RP33 10K_8P4R_5%R P33 10K_8P4R _5%

1 8
2 7
3 6
4 5

RP15 10K_8P4R_5%R P15 10K_8P4R _5%

1 8
2 7
3 6
4 5

RP31 10K_8P4R_5%R P31 10K_8P4R _5%

1 2

R194 10K_0402_5%R194 10K_0402_5%

1 2

R195 10K_0402_5%R195 10K_0402_5%

4

PCH_GPIO24

PCH_GPIO25
mSATA_DETECT_R
PCH_GPIO12

PCH_GPIO56
PCH_GPIO58
PCH_GPIO44

WLBT_OFF_51#

WLBT_OFF_5#

PCH_GPIO29 <8>
PCH_GPIO37 <6>

1 UMA

+3VS

0

PCH_GPIO72 <8>

DGPU_PRSNT#

PCH_PCIE_WAKE# <25,8>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

1 2

1 2

Deciphered Date

Deciphered Date

Deciphered Date

R707

R707
10K_0402_5%

10K_0402_5%

UMA@

UMA@

R708

R708
10K_0402_5%

10K_0402_5%

DIS@

DIS@

2

DIS

1: ENABLED

*

0: DISABLED

+3VALW_PCH

(Have internal PU)

1 2

R712

@R712

@

10K_0402_5%

10K_0402_5%

PCH_GPIO15

GPIO15 : TLS Confidentiality

1: Intel ME TLS with confidentiality

0: Intel ME TLS with no confidentiality

*

(Have internal PD)

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(6/11) GPIO,LPIO

HSW MCP(6/11) GPIO,LPIO

HSW MCP(6/11) GPIO,LPIO

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

9 47Friday, November 02, 2012

9 47Friday, November 02, 2012

9 47Friday, November 02, 2012

0.1

0.1

0.1

5

D D

PCIE_PRX_DTX_N5_L0< 17>
PCIE_PRX_DTX_P5_L0<17>

PCIE_PTX_C_DRX_N5_L0<17>
PCIE_PTX_C_DRX_P5_L0<17>

PCIE_PRX_DTX_N5_L1< 17>
PCIE_PRX_DTX_P5_L1<17>

dGPU

C C

WLAN

Card Reader

USB 2/3 (Docking)

LAN

B B

PCIE_PTX_C_DRX_N5_L1<17>
PCIE_PTX_C_DRX_P5_L1<17>

PCIE_PRX_DTX_N5_L2<17>
PCIE_PRX_DTX_P5_L2<17>

PCIE_PTX_C_DRX_N5_L2<17>
PCIE_PTX_C_DRX_P5_L2<17>

PCIE_PRX_DTX_N5_L3<17>
PCIE_PRX_DTX_P5_L3<17>

PCIE_PTX_C_DRX_N5_L3<17>
PCIE_PTX_C_DRX_P5_L3<17>

PCIE_PRX_DTX_N3<29>
PCIE_PRX_DTX_P3< 29>

PCIE_PTX_C_DRX_N3<29>
PCIE_PTX_C_DRX_P3<29>

PCIE_PRX_DTX_N4<30>
PCIE_PRX_DTX_P4<30>

PCIE_PTX_C_DRX_N4<30>
PCIE_PTX_C_DRX_P4<30>

USB3_RX3_N<31>
USB3_RX3_P<31>

USB3_TX3_N<31>
USB3_TX3_P<31>

PCIE_PRX_DTX_N2<25>
PCIE_PRX_DTX_P2<25>

PCIE_PTX_C_DRX_N2<25>
PCIE_PTX_C_DRX_P2<25>

+1.05VS_AUSB3PLL

R235 3.01K_0402_1%R235 3.01K_0402_1%
R236 0_0603_5%R236 0_0603_5%

4

0.1U_0402_16V7K

CC250
CC243 0.1U_0402_16V7KDIS@CC243 0.1U_0402_16V7KDIS@

CC245 0.1U_0402_16V7KDIS@CC245 0.1U_0402_16V7KDIS@
CC247 0.1U_0402_16V7KDIS@CC247 0.1U_0402_16V7KDIS@

CC249 0.1U_0402_16V7KDIS@CC249 0.1U_0402_16V7KDIS@
CC244

CC244

CC246

CC246
CC248

CC248

0.1U_0402_16V7K

DIS@CC250

DIS@1 2

1 2

1 2
1 2

1 2

0.1U_0402_16V7K

0.1U_0402_16V7K

DIS@

DIS@

1 2

0.1U_0402_16V7KDIS@

0.1U_0402_16V7KDIS@

1 2

0.1U_0402_16V7KDIS@

0.1U_0402_16V7KDIS@

1 2

1 2

C29 .1U_0402_16V 7KC29 .1U_04 02_16V7K

1 2

C30 .1U_0402_16V 7KC30 .1U_04 02_16V7K

1 2

C31 .1U_0402_16V 7KC31 .1U_04 02_16V7K

1 2

C32 .1U_0402_16V 7KC32 .1U_04 02_16V7K

1 2

C856 .1U_0402_16V7KC856 .1U_0402_16V7K

1 2

C857 .1U_0402_16V7KC857 .1U_0402_16V7K

1 2
1 2

PCIE_PRX_DTX_N5_L0
PCIE_PRX_DTX_P5_L0

PCIE_PTX_DRX_N5_L0

PCIE_PTX_DRX_P5_L0

PCIE_PRX_DTX_N5_L1
PCIE_PRX_DTX_P5_L1

PCIE_PTX_DRX_N5_L1
PCIE_PTX_DRX_P5_L1

PCIE_PRX_DTX_N5_L2
PCIE_PRX_DTX_P5_L2

PCIE_PTX_DRX_N5_L2
PCIE_PTX_DRX_P5_L2

PCIE_PRX_DTX_N5_L3
PCIE_PRX_DTX_P5_L3

PCIE_PTX_DRX_N5_L3
PCIE_PTX_DRX_P5_L3

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3

PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3

PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4

PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

USB3_RX3_N
USB3_RX3_P

USB3_TX3_N
USB3_TX3_P

PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2

PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P2

PCIE_RCOMP
PCIE_IREF

F10

E10

C23
C22

F8
E8

B23
A23

H10
G10

B21
C21

E6
F6

B22
A21

G11

F11

C29
B30

F13

G13

B29
A29

G17

F17

C30
C31

F15

G15

B31
A31

E15
E13
A27
B27

U1K

U1K

PERN5_L0
PERP5_L0

PETN5_L0
PETP5_L0

PERN5_L1
PERP5_L1

PETN5_L1
PETP5_L1

PERN5_L2
PERP5_L2

PETN5_L2
PETP5_L2

PERN5_L3
PERP5_L3

PETN5_L3
PETP5_L3

PERN3
PERP3

PETN3
PETP3

PERN4
PERP4

PETN4
PETP4

PERN1/USB3RN3
PERP1/USB3RP3

PETN1/USB3TN3
PETP1/USB3TP3

PERN2/USB3RN4
PERP2/USB3RP4

PETN2/USB3TN4
PETP2/USB3TP4

RSVD
RSVD
PCIE_RCOMP
PCIE_IREF

3

HASWELL_MCP_E

HASWELL_MCP_E

11 OF 19

11 OF 19

PCIe

PCIe

USB3.0 P3 / PCIE P1

USB3.0 P4 / PCIE P2

USB

USB

USB3.0 P1

USB3.0 P2

USB2N0
USB2P0

USB2N1
USB2P1

USB2N2
USB2P2

USB2N3
USB2P3

USB2N4
USB2P4

USB2N5
USB2P5

USB2N6
USB2P6

USB2N7
USB2P7

USB3RN1
USB3RP1

USB3TN1
USB3TP1

USB3RN2
USB3RP2

USB3TN2
USB3TP2

USBRBIAS
USBRBIAS

RSVD
RSVD

OC0/GPIO40
OC1/GPIO41
OC2/GPIO42
OC3/GPIO43

Rev1p2

Rev1p2

AN8
AM8

AR7
AT7

AR8
AP8

AR10
AT10

AM15
AL15

AM13
AN13

AP11
AN11

AR13
AP13

G20
H20

C33
B34

E18
F18

B33
A33

AJ10
AJ11
AN10
AM10

AL3
AT1
AH2
AV3

USBRBIAS

USB_OC0#
PCH_GPIO41
PCH_GPIO42
PCH_GPIO43

2

USB20_N0
USB20_P0

USB20_N1
USB20_P1

USB20_N2
USB20_P2

USB20_N3
USB20_P3

USB20_N4
USB20_P4

USB20_N5
USB20_P5

USB20_N6
USB20_P6

1 2

R233 22.6_0402_1%R233 22.6_0402_1%

USB20_N0 <27>
USB20_P0 <27>

USB20_N1 <29>
USB20_P1 <29>

USB20_N2 <31>
USB20_P2 <31>

USB20_N3 <29>
USB20_P3 <29>

USB20_N4 <30>
USB20_P4 <30>

USB20_N5 <30>
USB20_P5 <30>

USB20_N6 <30>
USB20_P6 <30>

USB3_RX1_N_BTB <27>

USB3_RX1_P_BTB < 27>

USB3_TX1_N_BTB <27>
USB3_TX1_P_BTB <27>

USB3_RX2_N <29>

USB3_RX2_P <29>

USB3_TX2_N <29>
USB3_TX2_P <29>

1

USB2/3 IO (IO board)

USB2/3 IO (Main Board)

USB2/3 IO (Docking)

Mini Card(WLAN+BT)

Touch Screen

Camera

FPR

USB2/3 IO(IO board)

USB2/3 (Main Board)

CAD note:
Route single-end 50-ohms and max 450-mils length.
Avoid routing next to clock pins or under stitching capacitors.
Recommended minimum spacing to other signal traces is 15 mils

USB_OC0# <27,29,9>
PCH_GPIO41 <9>
PCH_GPIO42 <9>
PCH_GPIO43 <9>

A A

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

http://sualaptop365.edu.vn

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(7/11) PCIE,USB

HSW MCP(7/11) PCIE,USB

HSW MCP(7/11) PCIE,USB

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

0.1

0.1

10 47Friday, November 02, 2012

10 47Friday, November 02, 2012

10 47Friday, November 02, 2012

0.1

5

D D

Define EC OD pin, need double confirm.

C C

SVID ALERT

+1.05VS

12

VR_SVID_ALRT#<42>

Place the PU
resistors close to CPU

R252

R252
75_0402_5%

75_0402_5%

R254

R254
43_0402_1%

43_0402_1%

12

H_CPU_SVIDALRT#

SVID DATA

+1.05VS

Place the PU
resistors close to CPU

12

R256

R256
110_0402_5%

B B

VR_SVID_DAT<42>

R257

R257
0_0402_5%

0_0402_5%

110_0402_5%

12

H_CPU_SVIDDATA

R256:
CRB r0.7 changed from 130 Ohms to
110 Ohms

VCCST_PG_EC

4

+1.05VS

12

R286

R286
10K_0402_5%

10K_0402_5%

+1.05VS

R253

R253
150_0402_1%

150_0402_1%

1 2

R255

R255
10K_0402_5%

10K_0402_5%

@

@

1 2

CPU_PWR_DEBU G

VR_SVID_CLK<42>

VR_ON<42>

VGATE<42>VCCST_PG_EC<26>

C5212

@C 5212

@

68P_0402_50V8J

68P_0402_50V8J

RF

R253: CPU_PWR_DEBUG
CRB mount
Check list ,XDP use only

3

0_0603_5%

0_0603_5%

R245

+VCCIOA_OUT

H_CPU_SVIDCLK

1

2

+VCCIO_OUT

@R245

@

1 2

+CPU_CORE

+1.35V

+1.35V

+CPU_CORE

1 2

1 2
1 2

+1.05VS

VDDQ DECOUPLING

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
C35

C35

1

2

VCCSENSE

+VCCIO_OUT_R

H_CPU_SVIDALRT#
H_CPU_SVIDCLK

R2480_0402_5% R2480_0402_5%

H_CPU_SVIDDATA
VCCST_PG_EC
VR12.5_VR_ON_R

R2500_0402_5% R2500_0402_5%

VR_READY_R

R2510_0402_5% R2510_0402_5%

CPU_PWR_DEBU G

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
C36

C36

1

2

2

HASWELL_MCP_E

U1L

U1L

L59

RSVD

J58

RSVD

AH26

VDDQ

AJ31

VDDQ

AJ33

VDDQ

AJ37

VDDQ

AN33

VDDQ

AP43

VDDQ

AR48

VDDQ

AY35

VDDQ

AY40

VDDQ

AY44

VDDQ

AY50

VDDQ

F59

VCC

N58

RSVD

AC58

RSVD

E63

VCC_SENSE

AB23

T38 @T38 @

T39 @T39 @
T40 @T40 @
T41 @T41 @
T42 @T42 @
T43 @T43 @
T44 @T44 @
T45 @T45 @
T46 @T46 @
T47 @T47 @
T48 @T48 @
T49 @T49 @
T50 @T50 @
T51 @T51 @

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

C37

C37

C38

C38

1

1

2

2

RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT

AD23

RSVD

AA23

RSVD

AE59

RSVD

L62

VIDALERT

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD

AD60

RSVD

AD59

RSVD

AA59

RSVD

AE60

RSVD

AC59

RSVD

AG58

RSVD

U59

RSVD

V59

RSVD

AC22

VCCST

AE22

VCCST

AE23

VCCST

AB57

VCC

AD57

VCC

AG57

VCC

C24

VCC

C28

VCC

C32

VCC

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

C39

C39

2

CRB:
+1.35V : 470UF/2V/7343 *2 (Un-mount)
10UF/6.3V/0603 * 6

2.2UF/6.3V/0402 * 4

1

C40

C40

2

2

HASWELL_MCP_E

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

12 OF 19

12 OF 19

HSW ULT POWER

HSW ULT POWER

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

C42

C42

C41

C41

2

10U_0603_6.3V6M

1

1

C43

C43

C44

C44

2

2

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

Rev1p2

Rev1p2

C36
C40
C44
C48
C52
C56
E23
E25
E27
E29
E31
E33
E35
E37
E39
E41
E43
E45
E47
E49
E51
E53
E55
E57
F24
F28
F32
F36
F40
F44
F48
F52
F56
G23
G25
G27
G29
G31
G33
G35
G37
G39
G41
G43
G45
G47
G49
G51
G53
G55
G57
H23
J23
K23
K57
L22
M23
M57
P57
U57
W57

1

+CPU_CORE

VCCSENSE<42>

A A

VSSSENSE<13,42>

VCCSENSE

VSSSENSE

CAD Note: PU resistor should be close to CPU

CAD Note: PD resistor should be close to CPU

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

http://sualaptop365.edu.vn

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(8/11) Power

HSW MCP(8/11) Power

HSW MCP(8/11) Power

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

0.1

0.1

11 47Friday, November 02, 2012

11 47Friday, November 02, 2012

11 47Friday, November 02, 2012

0.1

5

D D

4

3

2

1

Check Power Source

+1.05VS +1.05VS_AUSB3P LL

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

1 2

L3

C C

B B

A A

L3

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

L4

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

2.2UH_LQM2MPN2R2NG0L_30%

+1.05VS

1 2

L1

L1

1 2

L2

L2

R267
0_0805_5%

0_0805_5%

1 2

1 2

L4

1 2

L5

+3VALW_PCH

+3VALW_PCH

+1.05VS

+1.05VS

+3VALW_PCH

+1.05VS

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

@R267

@

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

L5

C49 1U_0402_ 6.3V6KC49 1U _0402_6.3V6K
C50 1U_0402_ 6.3V6KC50 1U _0402_6.3V6K

C78 22U_0603_6.3V6MC78 22U_0603_6.3V6M

C82 22U_0603_6.3V6MC82 22U_0603_6.3V6M

+3VS

C87 1U_0402_6.3V6KC87 1U_04 02_6.3V6K

C88 1U_0402_6.3V6K

C88 1U_0402_6.3V6K

C75 1U_0402_6.3V4ZC75 1U_0402_6.3V4Z

5

Close to N8

1 2

C53 1U_0402_ 6.3V6K@C 53 1U_0402_6.3V6K@

1 2

C58 1U_0402_ 6.3V6KC58 1U _0402_6.3V6K

1 2

C59 100U_120 6_6.3V6M C59 100U_120 6_6.3V6M

1 2

C63 1U_0402_ 6.3V6KC63 1U _0402_6.3V6K

1 2

C65 100U_120 6_6.3V6M C65 100U_120 6_6.3V6M

1 2

C69 1U_0402_6.3V6KC69 1U_0402_6.3V6K

1 2

C70 100U_1206_6.3V6M@C70 100U_1206_6.3V6M@

1 2

C83 1U_0402_ 6.3V6KC83 1U _0402_6.3V6K

1 2

C84 100U_120 6_6.3V6MC84 100U_1206 _6.3V6M

1 2

C85 1U_0402_ 6.3V6KC85 1U _0402_6.3V6K

1 2

C86 100U_120 6_6.3V6MC86 100U_1206 _6.3V6M

Close to K9,M9

1 2
1 2

Close to AH10

1 2

C81 0.1U_0402_16V4Z

C81 0.1U_0402_16V4Z

@

@

Close to AC9/AA9/AE20/AE21

1 2

Close to V8

1 2

Close to J17

1 2

Close to R21

1 2

Close to AH14

12

http://sualaptop365.edu.vn

HASWELL_MCP_E

mPHY

mPHY

OPI

OPI

USB3

USB3

AXALIA/HDA

AXALIA/HDA

VRM/USB2/AZALIA

VRM/USB2/AZALIA

GPIO/LCC

GPIO/LCC

LPT LP POWER

LPT LP POWER

HASWELL_MCP_E

13 OF 19

13 OF 19

RTC

RTC

SPI

SPI

CORE

CORE

THERMAL SENSOR

THERMAL SENSOR

SDIO/PLSS

SDIO/PLSS

SUS OSCILLATOR

SUS OSCILLATOR

USB2

USB2

VCCSUS3_3

VCCRTC
DCPRTC

VCCSPI

VCCASW
VCCASW

VCC1_05
VCC1_05
VCC1_05
VCC1_05

VCC1_05
DCPSUSBYP
DCPSUSBYP

VCCASW

VCCASW

VCCASW

DCPSUS1
DCPSUS1

VCCTS1_5

VCC3_3
VCC3_3

VCCSDIO

VCCSDIO

DCPSUS4

RSVD
VCC1_05
VCC1_05

Rev1p2

Rev1p2

12

1 2

@

@

1 2

R2640_0603_5% R2640_0603_5%

+RTCVCC

+3VS

+1.05VS

+1.05VS

AH11
AG10
AE7

Y8

AG14
AG13

J11
H11
H15
AE8
AF22
AG19
AG20
AE9
AF9
AG8
AD10
AD8

J15
K14
K16

U8
T9

AB8

AC20
AG16
AG17

+VCCRTCEXT

1 2

C51 1U_0402_ 6.3V6KC51 1U _0402_6.3V6K

C52 0.1U_0402_16V4ZC52 0.1U_0402_16V4Z

1 2

C57 0.1U_0402_16V4Z

C57 0.1U_0402_16V4Z

1 2

C60 10U_0603 _6.3V6M C60 10U_0603_6.3V6M

1 2

C61 1U_0402_ 6.3V6KC61 1U _0402_6.3V6K

1 2

C62 1U_0402_ 6.3V6KC62 1U _0402_6.3V6K

+PCH_VCCDSW +PCH_VCC DSW_R

R265 0_0402_5%R265 0_0402_5%

1 2

C66 22U_0603 _6.3V6M@C66 22U_0603_6.3V6M@

1 2

C67 1U_0402_ 6.3V6KC67 1U _0402_6.3V6K

T58 @T58 @
T59 @T59 @

1 2

C71 0.1U_0402_16V4ZC71 0.1U_0402_16V4Z

1 2

C73 1U_0402_6.3V6KC73 1U_0402_6.3V6K

T56 @T56 @

+1.05VS

1 2

C76 1U_0402_6.3V6KC76 1U_0402_6.3V6K

+3VALW_PCH

+1.05VS

+1.5VS
+3VS

+3VS

C64

C64
1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

+RTCVCC

C54

C54

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C55

C55

2

@

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1

C56

C56

2

2

@

@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+1.05VS

+1.05VS

+1.05VS_AUSB3PLL

+1.05VS_ASATA3PLL

+1.05VS_APLLOPI

T53 @T53 @

+3VALW_PCH

T55 @T55 @

+3VALW_PCH

+3VS

+1.05VS_AXCK_DCB

+1.05VS_AXCK_LCPLL

+1.05VS
+1.05VS

+3VALW_PCH

AA21

W21

AH14

AH13

AH10

AE20
AE21

AC9
AA9

R21

M20

L10

M9
N8

B18
B11

Y20

J13

W9

J18
K19
A20
J17

T21
K18

V21

K9

VCCHSIO
VCCHSIO
VCCHSIO
VCC1_05

P9

VCC1_05
VCCUSB3PLL
VCCSATA3PLL

RSVD
VCCAPLL
VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCSUS3_3
VCCSUS3_3
VCCDSW3_3

V8

VCC3_3
VCC3_3

VCCCLK
VCCCLK
VCCACLKPLL
VCCCLK
VCCCLK
VCCCLK
RSVD
RSVD
RSVD
VCCSUS3_3
VCCSUS3_3

U1M

U1M

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(9/11) Power

HSW MCP(9/11) Power

HSW MCP(9/11) Power

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

0.1

0.1

12 47Friday, November 02, 2012

12 47Friday, November 02, 2012

12 47Friday, November 02, 2012

0.1

5

D D

HASWELL_MCP_E

HASWELL_MCP_E

U1N

U1N

A11

VSS

A14

VSS

A18

VSS

A24

VSS

A28

VSS

A32

VSS

A36

VSS

A40

VSS

A44

VSS

A48

VSS

A52

VSS

A56

VSS

AA1

VSS

AA58

VSS

AB10

VSS

AB20

VSS

AB22

VSS

AB7

C C

B B

AC61
AD21

AD3
AD63
AE10

AE5
AE58
AF11
AF12
AF14
AF15
AF17
AF18

AG1
AG11
AG21
AG23
AG60
AG61
AG62
AG63
AH17
AH19
AH20
AH22
AH24
AH28
AH30
AH32
AH34
AH36
AH38
AH40
AH42
AH44
AH49
AH51
AH53
AH55
AH57

AJ13
AJ14
AJ23
AJ25
AJ27
AJ29

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

14 OF 19

14 OF 19

4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev1p2

Rev1p2

AJ35
AJ39
AJ41
AJ43
AJ45
AJ47
AJ50
AJ52
AJ54
AJ56
AJ58
AJ60
AJ63
AK23
AK3
AK52
AL10
AL13
AL17
AL20
AL22
AL23
AL26
AL29
AL31
AL33
AL36
AL39
AL40
AL45
AL46
AL51
AL52
AL54
AL57
AL60
AL61
AM1
AM17
AM23
AM31
AM52
AN17
AN23
AN31
AN32
AN35
AN36
AN39
AN40
AN42
AN43
AN45
AN46
AN48
AN49
AN51
AN52
AN60
AN63
AN7
AP10
AP17
AP20

AP22
AP23
AP26
AP29

AP31
AP38
AP39
AP48
AP52
AP54
AP57
AR11
AR15
AR17
AR23
AR31
AR33
AR39
AR43
AR49

AR52
AT13
AT35
AT37
AT40
AT42
AT43
AT46
AT49
AT61
AT62
AT63

AU16
AU18
AU20
AU22
AU24
AU26
AU28
AU30
AU33
AU51
AU53
AU55
AU57
AU59
AV14
AV16
AV20
AV24
AV28
AV33
AV34
AV36
AV39
AV41
AV43
AV46
AV49
AV51
AV55

AP3

AR5

AU1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U1O

U1O

3

HASWELL_MCP_E

HASWELL_MCP_E

15 OF 19

15 OF 19

Rev1p2

Rev1p2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AV59
AV8
AW16
AW24
AW33
AW35
AW37
AW4
AW40
AW42
AW44
AW47
AW50
AW51
AW59
AW60
AY11
AY16
AY18
AY22
AY24
AY26
AY30
AY33
AY4
AY51
AY53
AY57
AY59
AY6
B20
B24
B26
B28
B32
B36
B4
B40
B44
B48
B52
B56
B60
C11
C14
C18
C20
C25
C27
C38
C39
C57
D12
D14
D18
D2
D21
D23
D25
D26
D27
D29
D30
D31

2

U1P

U1P

HASWELL_MCP_E

D33
D34
D35
D37
D38
D39
D41
D42
D43
D45
D46
D47
D49

D50
D51
D53
D54
D55
D57
D59
D62

E11
E17

F20
F26
F30
F34
F38
F42
F46
F50
F54
F58

F61
G18
G22

H13

HASWELL_MCP_E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G3

VSS

G5

VSS

G6

VSS

G8

VSS
VSS

16 OF 19

16 OF 19

VSS_SENSE

Rev1p2

Rev1p2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS

VSS

H17
H57
J10
J22
J59
J63
K1
K12
L13
L15
L17
L18
L20
L58
L61
L7
M22
N10
N3
P59
P63
R10
R22
R8
T1
T58
U20
U22
U61
U9
V10
V3
V7
W20
W22
Y10
Y59
Y63

V58
AH46
V23
E62
AH16

1

VSSSENSE <42>

A A

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

5

http://sualaptop365.edu.vn

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

3

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

2

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(10/11) GND

HSW MCP(10/11) GND

HSW MCP(10/11) GND

LA-9761PR01

LA-9761PR01

LA-9761PR01

1

0.1

0.1

13 47Friday, November 02, 2012

13 47Friday, November 02, 2012

13 47Friday, November 02, 2012

0.1

T54 @T54 @

T61 @T61 @

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

DC_TEST_AY61_AW61
DC_TEST_AY62_AW62

DC_TEST_A3_B3
DC_TEST_A61_B61
DC_TEST_B62_B63

DC_TEST_C1_C2

U1Q

U1Q

AY2

DAISY_CHAIN_NCTF_AY2

AY3

DAISY_CHAIN_NCTF_AY3

AY60

DAISY_CHAIN_NCTF_AY60

AY61

DAISY_CHAIN_NCTF_AY61

AY62

DAISY_CHAIN_NCTF_AY62

B2

DAISY_CHAIN_NCTF_B2

B3

DAISY_CHAIN_NCTF_B3

B61

DAISY_CHAIN_NCTF_B61

B62

DAISY_CHAIN_NCTF_B62

B63

DAISY_CHAIN_NCTF_B63

C1

DAISY_CHAIN_NCTF_C1

C2

DAISY_CHAIN_NCTF_C2

U1S

U1S

HASWELL_MCP_E

HASWELL_MCP_E

17 OF 19

17 OF 19

HASWELL_MCP_E

HASWELL_MCP_E

DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4

DAISY_CHAIN_NCTF_A60
DAISY_CHAIN_NCTF_A61
DAISY_CHAIN_NCTF_A62

DAISY_CHAIN_NCTF_AV1
DAISY_CHAIN_NCTF_AW1
DAISY_CHAIN_NCTF_AW2
DAISY_CHAIN_NCTF_AW3

DAISY_CHAIN_NCTF_AW61
DAISY_CHAIN_NCTF_AW62
DAISY_CHAIN_NCTF_AW63

Rev1p2

Rev1p2

A3
A4

A60
A61
A62
AV1
AW1
AW2
AW3
AW61

DC_TEST_AY61_AW61

AW62

DC_TEST_AY62_AW62

AW63

DC_TEST_A3_B3

DC_TEST_A61_B61

DC_TEST_AY2_AW2
DC_TEST_AY3_AW3

1

HASWELL_MCP_E

U1R

U1R

T52@ T52@

T57@ T57@

T62@ T62@
T64@ T64@
T66@ T66@

T75@ T75@

AU44
AV44

AT2

RSVD
RSVD
RSVD

D15

RSVD

F22

RSVD

H22

RSVD

J21

RSVD

HASWELL_MCP_E

18 OF 19

18 OF 19

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

Rev1p2

Rev1p2

N23
R23
T23
U10

AL1
AM11
AP7
AU10
AU15
AW14
AY14

T63 @T63 @
T65 @T65 @
T67 @T67 @
T68 @T68 @
T69 @T69 @
T70 @T70 @
T71 @T71 @
T72 @T72 @
T73 @T73 @
T74 @T74 @

A A

T76 @T76 @
T77 @T77 @
T78 @T78 @
T79 @T79 @
T80 @T80 @
T81 @T81 @

T82 @T82 @
T83 @T83 @
T84 @T84 @
T85 @T85 @

CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
CFG15

CFG16
CFG18
CFG17
CFG19

CFG_RCOMP

TD_IREF

R275 49.9_0402_1%R275 49.9_0402_1%

R276 49.9_0402_1%R276 49.9_0402_1%

R277 8.2K_0402_5%R277 8.2K_0402_5%

AC60

CFG0

AC62

CFG1

AC63

CFG2

AA63

CFG3

AA60

CFG4

Y62

CFG5

Y61

CFG6

Y60

CFG7

V62

CFG8

V61

CFG9

V60

CFG10

U60

CFG11

T63

CFG12

T62

CFG13

T61

CFG14

T60

CFG15

AA62

CFG16

U63

CFG18

AA61

CFG17

U62

CFG19

V63

CFG_RCOMP

A5

RSVD

E1

RSVD

D1

RSVD

J20

RSVD

H18

RSVD

B12

TD_IREF

12

CFG_RCOMP

12

OPI_COMP

12

TD_IREF

RESERVED

RESERVED

19 OF 19

19 OF 19

PROC_OPI_RCOMP

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD

RSVD_TP
RSVD_TP

RSVD_TP

RSVD

RSVD
RSVD

RSVD
RSVD

VSS
VSS

RSVD
RSVD

Rev1p2

Rev1p2

AV63
AU63

C63
C62
B43

A51
B51

L60

N60

W23
Y22
AY15

AV62
D58

P22
N21

P20
R20

OPI_COMP

CFG Straps for Processor

CFG3

12

R273

R273
1K_0402_1%

1K_0402_1%

@

@

Physical Debug Enable (DFX Privacy)

1: DISABLED

CFG3

0: ENABLED; SET DFX ENABLED BIT
IN DEBUG INTERFACE MSR

CFG4

Display Port Presence Strap

1 : Disabled; No Physical Display Port

CFG4

attached to Embedded Display Port

0 : Enabled; An external Display Port device is
connected to the Embedded Display Port

12

R274

R274
1K_0402_1%

1K_0402_1%

w w w . c h i n a f i x . c o m

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

http://sualaptop365.edu.vn

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

HSW MCP(11/11) RSVD

HSW MCP(11/11) RSVD

HSW MCP(11/11) RSVD

LA-9761PR01

LA-9761PR01

LA-9761PR01

14 47Friday, November 02, 2012

14 47Friday, November 02, 2012

14 47Friday, November 02, 2012

0.1

0.1

0.1

A

+1.35V

12

R278

R278

1.8K_0402_1%

1.8K_0402_1%

12

R282

R282

1.8K_0402_1%

1.8K_0402_1%

1 1

SA_DIMM_VREFDQ<5>

* CRB 1.0

+1.35V

C95

1U_0402_6.3V6K

C95

C93

1U_0402_6.3V6K

C93

1U_0402_6.3V6K

1

2

2 2

3 3

+1.35V

C97

10U_0603_6.3V6M

C97

10U_0603_6.3V6M

1

1

2

2

+1.35V

C101

10U_0603_6.3V6M C101

10U_0603_6.3V6M

1

1

2

2

Layout Note:
Place near JDIMM1
Everage by each side

1U_0402_6.3V6K

C94

1U_0402_6.3V6K

C94

1U_0402_6.3V6K

1

1

2

2

C98

10U_0603_6.3V6M C98

10U_0603_6.3V6M

C99

10U_0603_6.3V6M

C99

10U_0603_6.3V6M

C100

10U_0603_6.3V6M C100

10U_0603_6.3V6M

1

1

2

2

C102

10U_0603_6.3V6M C102

10U_0603_6.3V6M

C103

10U_0603_6.3V6M@C103

10U_0603_6.3V6M

C104

220U_B2_2.5VM_R35

C104

220U_B2_2.5VM_R35

1

1

+

+

@

@

@

2

2

1 2

C96

1U_0402_6.3V6K

C96

1U_0402_6.3V6K

1

2

R279

R279

2_0402_1%

2_0402_1%

C92

2.2U_0402_6.3V6M@C92

2.2U_0402_6.3V6M

1

@

2

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

DDRA_CKE0_DIMMA<5>

DDR_A_BS2<5 >

SA_CLK_DDR0<5>
SA_CLK_DDR#0<5>

DDR_A_BS0<5 >

DDR_A_WE#<5>
DDR_A_CAS#<5>

DDRA_CS1_DIMMA#<5>

C89

0.1U_0402_16V4Z

C89

0.1U_0402_16V4Z

1

2

+V_DDR_REFA

DDRA_CKE0_DIMMA

DDR_A_BS2

DDRA_CS1_DIMMA#

CRB1.0 10uF *8 /1uF *8

+0.675VS

C109

1U_0402_6.3V6K C109

1U_0402_6.3V6K

C108

1U_0402_6.3V6K C108

1U_0402_6.3V6K

1

1

2

Layout Note:

4 4

Place near JDIMM1.203,204

CRB1.0 10uF *1 /1uF *4

1

2

2

C111

1U_0402_6.3V6K C111

1U_0402_6.3V6K

C110

1U_0402_6.3V6K C110

1U_0402_6.3V6K

1

2

A

+3VS

+0.675VS

C112

0.1U_0402_16V4Z C112

0.1U_0402_16V4Z

CRB1.0 0.1uF *1 /2.2uF *1

C113

2.2U_0402_6.3V6M@C113

2.2U_0402_6.3V6M

1

1

@

2

2

http://sualaptop365.edu.vn

R259

R259

10K_0402_5%

10K_0402_5%

12

DDR_A_D13
DDR_A_D8

DDR_A_D14
DDR_A_D10

DDR_A_D29
DDR_A_D28

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDR_A_D44
DDR_A_D41

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D43
DDR_A_D47

DDR_A_D51
DDR_A_D50

DDR_A_D49
DDR_A_D48

DDR_A_MA12
DDR_A_MA9

DDR_A_MA8
DDR_A_MA5

DDR_A_MA3
DDR_A_MA1

SA_CLK_DDR0
SA_CLK_DDR#0

DDR_A_MA10
DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13

DDR_A_D0
DDR_A_D1

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D2
DDR_A_D6

DDR_A_D21
DDR_A_D20

DDR_A_D17
DDR_A_D16

DDR_A_D36
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D38

DDR_A_D62
DDR_A_D58

DDR_A_D60
DDR_A_D61

12

R258

R258
10K_0402_5%

10K_0402_5%

B

JDIMM1

JDIMM1

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103

ME@

ME@

DQS0#

DQS0

DQ12
DQ13

RESET#

DQ14
DQ15

DQ20
DQ21

DQ22
DQ23

DQ28
DQ29

DQS3#

DQS3

DQ30
DQ31

CKE1

VDD

VDD

VDD

VDD

VDD

CK1#

VDD

RAS#

VDD

ODT0

VDD

ODT1

VDD

VREF_CA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5#

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7#

DQS7

DQ62
DQ63

EVENT#

GND2

BOSS2

VSS
DQ4
DQ5
VSS

VSS
DQ6
DQ7
VSS

VSS
DM1

VSS

VSS

VSS
DM2
VSS

VSS

VSS

VSS

VSS

CK1

BA1

VSS

VSS
DM4
VSS

VSS

VSS

VSS

VSS

VSS
DM6
VSS

VSS

VSS

VSS

VSS

SDA
SCL
VTT

+1.35V+1.35V

2
4

DDR_A_D9

6

DDR_A_D12

8
10

DDR_A_DQS#1

12

DDR_A_DQS1

14
16

DDR_A_D15

18

DDR_A_D11

20
22

DDR_A_D25

24

DDR_A_D24

26
28
30

DIMM_DRAMRST#

32
34

DDR_A_D27

36

DDR_A_D26

38
40

DDR_A_D45

42

DDR_A_D40

44
46
48
50

DDR_A_D42

52

DDR_A_D46

54
56

DDR_A_D52

58

DDR_A_D53

60
62

DDR_A_DQS#6

64

DDR_A_DQS6

66
68

DDR_A_D54

70

DDR_A_D55

72

74

DDRA_CKE1_DIMMA

76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

DDR_A_MA15
DDR_A_MA14

DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4

DDR_A_MA2
DDR_A_MA0

SA_CLK_DDR1
SA_CLK_DDR#1

DDR_A_BS1
DDR_A_RAS#

DDRA_CS0_DIMMA#
SA_ODT0

SA_ODT1

+VREF_CA

DDR_A_D5
DDR_A_D4

DDR_A_D3
DDR_A_D7

DDR_A_D18
DDR_A_D19

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D22
DDR_A_D23

DDR_A_D37
DDR_A_D32

DDR_A_D35
DDR_A_D39

DDR_A_D63
DDR_A_D59

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D56
DDR_A_D57

PCH_SMB_DATA

PCH_SMB_CLK

+0.675VS

A15
A14

A11

A7

A6
A4

A2
A0

S0#

NC

C

All VREF traces should
have 10 mil trace width

DIMM_DRAMRST# <4>

DDRA_CKE1_DIMMA <5>

SA_CLK_DDR1 <5>
SA_CLK_DDR#1 <5>

DDR_A_BS1 <5>
DDR_A_RAS# < 5>

DDRA_CS0_DIMMA# <5>

R288

R288

1 2

2_0402_1%

2_0402_1%

C106

0.1U_0402_16V4Z C106

0.1U_0402_16V4Z

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
C105

C105

1

1

@

@

2

2

CRB1.0 0.1uF *1 /2.2uF *1

2.2uF (reserved)

PCH_SMB_DATA <29,32,7>
PCH_SMB_CLK <29,3 2,7>

DDR_A_DQS#[0..7] < 5>

DDR_A_DQS[0..7] <5 >

DDR_A_D[0..63] <5>

DDR_A_MA[0..15] <5>

DDR_PG_CTRL<4>

+1.35V

12

12

R287

R287

1.8K_0402_1%

1.8K_0402_1%

R289

R289

1.8K_0402_1%

1.8K_0402_1%

D

U7

U7

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

74AUP1G07GW_TSSOP5

SM_DIMM_VREFCA < 5>

E

+1.35V

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C90

C90

Y

+5VALW

1

2

12

5

4

R283

R283
220K_0402_5%

220K_0402_5%

2

G

G

+1.35V

Q9

Q9

13

D

D

LBSS138LT1G_SOT-23-3

LBSS138LT1G_SOT-23-3

S

S

M_A_B_DIMM_ODT

DDR_VTT_PG_CTRL <39>

1 2

R281 66.5_0402_1%R281 66.5_0402_ 1%

1 2

R284 66.5_0402_1%R284 66.5_0402_ 1%

SA_ODT0

SA_ODT1

CHANNEL A /TYPE :Reverse / H:4mm

w w w . c h i n a f i x . c o m

CHA SPD ADDRESS IS OxA0
CHA TS ADDRESS IS Ox30

PN:SP07000LT00

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2011/12/13 2012/12/13

2011/12/13 2012/12/13

2011/12/13 2012/12/13

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Compal Electronics, Inc.

DDRIII DIMMA

DDRIII DIMMA

DDRIII DIMMA

LA-9761PR01

LA-9761PR01

LA-9761PR01

15 47Friday, November 02, 2012

15 47Friday, November 02, 2012

E

15 47Friday, November 02, 2012

0.1

0.1

0.1