JVC KD-LX555R User Manual 2

SERVICE MANUAL

CD RECEIVER

4979320034

KD-LX555R

S

STDM

SOURCE

9

7

8

KD-LX555R

0

1

12

11

Area Suffix

E ------ Continental Europe

TABLE OF CONTENTS

1 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Disassembly method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Adjustment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 Description of major ICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

No.49793

2003/5

SECTION 4

Description of major ICs

4.1 BA6956AN (IC830, IC831) : Reversible motor driver

• Block diagram

TSD

CONTROL LOGIC

1 2 3 4 5 6 7 8 9

REF

OUT2

RNF

VM

OUT1

Vcc

FIN

GND

RIN

• Pin function • Truth table

Pin No. Symbol Function

1 VREF Output high voltage level control terminal

2 OUT2 Output terminal for motor

3 RNF GND of driver division

4 OUT1 Output terminal for motor

FIN RIN OUT1 OUT2 MODE

H L H L Forward rotation mode

L H L H Reverse rotation mode

H H L L Break Mode

L L OPEN OPEN Stand-by mode

5 VM Power supply for driver division

6 Vcc Power supply for signal division

7 FIN Input terminal for control logic

8GNDGND

9 RIN Input terminal for control logic

1-32 (No.49793)

4.2 BR24C01AFV-W-X (IC1502) : EEPROM

A

•Pin layout

Vcc WP SCL SDA

A0 A1 A2 GND

• Block diagram

A0

1

7bit

A1

2

A2

3

GND

• Pin function Pin name I/O Description

Vcc - Power supply

GND - Ground (0v)

A0,A1,A2 IN Slave address set

SCL IN Serial clock input

SDA IN / OUT Slave and word addressserial data input serial data output *1

WP IN Write protect input

*1 An open drain output requires a pull-up resister.

4

ADDRESS DECODER

CONTROL LOGIC

HIGH VOLTAGE GEN.

1kbit EEPROM ARRAY

SLAVE/WORD

7bit

ADDRESS REGISTER

START

STOP

Vcc LEVEL DETECT

ACK

8bit

DATA REGISTER

Vcc

8

7

WP

6

SCL

5

SD

(No.49793)1-33

4.3 BR24C32F (IC703) : EEPROM

A

• Pin Layout

VCC

BR24C32/F

• Pin function

SDASCLWP

• Pin layout & Block diagram

PIN NAME I/O Function

VCC - Power Supply

GND - Ground (0V)

A0-A2 I Slave Address Set

SCL I Serial Clock Input

SDA I/O Slave and Word Address.

Serial Data Input$ Serial Data Output *1

WP I Write Protect Input

GNDA2A1A0

1

A0

12bit

2

A1

3

A2

4

GND

4.4 HD74HC126FP (IC771) : Changer Control

OE1

A1

Y1

1

2

3

ADDRESS DECODER

CONTROL LOGIC

HIGH VOLTAGE GEN.

14

13

12

32 Kbit EEPROM ARRAY

SLAVE WORD

12bit

ADDRESS REGISTER

START STOP

VCC LEVEL DETECT

Vcc

OE4

A4

DATA REGISTER

ACK

8bit

8

7

6

5

Vcc

WP

SCL

SD

OE2

A2

Y2

Vss

1-34 (No.49793)

4

5

6

7

HD74HC126

11

10

9

8

Y4

OE3

A3

Y3

4.5 BU1923F (IC51) : RDS decoder

A

•Pin layout

1

QUAL

RDATA

Vref

MUX

VDD1

VSS1 VSS3

CMP

2 3 4 5 6 7 8

16 15 14 13 12 11 10

• Block diagram

9

RCLK N.C. XO XI VDD2 VSS2 T1 T2

MUX

Vref

VDD1

VSS1

VDD2

VSS2

4

3

5

Power supply

6

12

Power supply

11

100k

120k

Analog

Digital

100k

+

anti-aliasing

filter

PLL 57kHz RDS/ARI

Reference clock

PLL

1187.5Hz

VSS3

8th Switched capacitor filter

Bi-phase decoder

7

CMP

Measurement

circuit

8

comparator

Differential decoder

16

1

2

RCLK

QUAL

RDAT

13

Xl

14

X0

10 9

T1

T2

(No.49793)1-35

4.6 HA13164A (IC961) : Regulator

• Terminal layout

123456789101112131415

• Block diagram

ANT OUT

EXT OUT

ANT CTRL

CTRL

CD OUT

AUDIO OUT

C3

0.1u

C4

0.1u

C5

0.1u

C6

10u

2

1

7

11

12

10

VCC ACC

8

Surge Protector

BIAS TSD

15

3

TAB

C1

100u

C2

0.1u

13

ILM AJGND GND

+B

ACC

BATT.DET OUT

9

COMPOUT

6

VDD OUT

4

SW5VOUT

5

ILMOUT

14

R1

C7

0.1u

C8

0.1u

UNIT R:

C:F

note1) TAB (header of IC)

connected to GND

• Pin function

Pin No. Symbol Function

1 EXTOUT Output voltage is VCC-1 V when M or H level applied to CTRL pin.

2 ANTOUT Output voltage is VCC-1 V when M or H level to CTRL pin and H level to ANT-CTRL.

3 ACCIN Connected to ACC.

4 VDDOUT Regular 5.7V.

5 SW5VOUT Output voltage is 5V when M or H level applied to CTRL pin.

6 COMPOUT Output for ACC detector.

7 ANT CTRL L:ANT output OFF H:ANT output ON

8 VCC Connected to VCC.

9 BATT DET Low battery detect.

10 AUDIO OUT Output voltage is 9V when M or H level applied to CTRL pin.

11 CTRL L:BIAS OFF M:BIAS ON H:CD ON

12 CD OUT Output voltage is 8V when H level applied to CTRL pin.

13 ILM AJ Adjustment pin for ILM output voltage.

14 ILM OUT Output voltage is 10V when M or H level applied to CTRL pin.

15 GND Connected to GND.

1-36 (No.49793)

4.7 HD74HCT126T-X : (IC1500,IC1503) Buffer

• Pin arrangement • Pin function

Input Output

1C

1A

1Y

2C

2A

2Y

GND

• Block diagram

1

2

3

4

5

6

7

14

13

12

11

10

Vcc

4C

4A

4Y

3C

9

3A

8

3Y

CA Y

LX Z

HL L

HH H

H : High level L : Low level X : Irrelevant Z : Off (Hhigh-impedance)state of a 3-stage output

1A

1C

2A

2C

3A

3C

4A

1Y

2Y

3Y

4Y

4C

(No.49793)1-37

4.8 LA47505 (IC941) : Power amp.

• Terminal layout

206

11

1

12

4

10

Stand by

Switch

Ripple

Filter

Protective

circuit

Mute

circuit

9

7

8

5

3

2

22

15

25

13

14

16

Muting &

On Time Control

Circuit

protective

circuit

17

19

18

21

23

24

1-38 (No.49793)

• Terminal layout

AC CONT1

GND1

OUTFR-

STBY

OUTFR+

Vcc1/2

OUTRR-

GND2

OUTRR+

VREF

INRR

INFR

SGND

INFL

INRL

ONTIME

OUTRL+

GND3

OUTRL-

Vcc3/4

OUTFL+

MUTE

OUTFL-

GND4

NC

• Pin function

Pin No. Symbol Function

1 AC CONT1 Header of IC

2 GND1 Power GND

3 OUTFR- Outpur(-) for front Rch

4 STBY Stand by input

5 OUTFR+ Output (+) for front Rch

6 Vcc1/2 Power input

7 OUTRR- Output (-) for rear Rch

8 GND2 Power GND

9 OUTRR+ Output (+) for rear Rch

10 VREF Ripple filter

11 INRR Rear Rch input

12 INFR Front Rch input

13 SGND Signal GND

14 INFL Front Lch input

15 INRL Rear Lch input

16 ONTIME Power on time control

17 OUTRL+ Output (+) for rear Lch

18 GND3 Power GND

19 OUTRL- Output (-) for rear Lch

20 Vcc3/4 Power input

21 OUTFL+ Output (+) for front

22 MUTE Muting control input

23 OUTFL- Output (-) for front

24 GND4 Power GND

25 NC No connection

(No.49793)1-39

4.9 LA6579H-X (IC1681) : 4-Channel bridge driver

W

• Pin layout & Block diagram

VIN1-A

1

+

VIN1+A

VCCP1

2

3

VIN1_SW [H]: OP-AMP_A [L]: OP-AMP_B

[H]

[L]

28

VIN1

27

VIN1-B

-

+

26

VIN1+B

VO+

VO-

VO2+

VO2-

FR

VO3+

VO3-

VO4+

4

5

6

7

FR

8

9

10

Power system GND

+

Level shift

33k

11k

-

+

All outputs ON/OFF

H : ON L : OFF

3.3VREG (External:PTP Tr)

Signal system power supply

MUTE

Power system GND

Signal system power supply

+

-

25

24

23

22

FR

21

20

19

S-GND

VIN1-S

MUTE

VREFIN

FR

VCCS

3.3VREG

REGIN

VO4-

VCCP2

VIN4

VIN4G

1-40 (No.49793)

11

12

13

14

11k

33k

+

33k

18

VIN2G

11k

-

17

VIN2

+

16

VIN3G

11k

-

15

VIN3

+

• Pin function

Pin No. Symbol Function

1 VIN1-A CH1 input AMP_inverted input

2 VIN1+A CH1 input AMP_non-inverted input

3 VCCP1 CH1 and CH2 power stage power supply

4 VO1+ Output pin(+)for channel 1

5 VO1- CH1 output pin (-) for channel 1

6 VO2+ Output pin(+)for channel 2

7 VO2- Output pin(-)for channel 2

8 VO3+ Output pin(+)for channel 3

9 VO3- Output pin(-)for channel 3

10 VO4+ Output pin(+)for channel 4

11 VO4- Output pin(-)for channel 4

12 VCCP2 CH3 and CH4 power stage powr supply

13 VIN4 Input pin for channel 4

14 VIN4G Input pin for channel 4(for gain adjustment)

15 VIN3 Input pin for channel 3

16 VIN3G Input pin for channel 3(for gain adjustment)

17 VIN2 Input pin for channel 2

18 VIN2G Input pin for channel 2(for gain adjustment)

19 REGIN External PNP transistor base connection

20 3.3VREG 3.3VREG output pin external PNP transistor,collector connection

21 VCCS Signal system GND

22 VREFIN Reference voltage application pin

23 MUTE Output ON/OFF pin

24 VIN1_SW CH1 input OP AMP_changeover pin

25 S_GND Signal system GND

26 VIN1+B CH1 AMP_B non-inverted input pin

27 VIN1-B CH1 AMP_B inverted input pin

28 VIN1 CH1 input pin input OP_AMP output pin

(No.49793)1-41