PICs physically connect the routerto network media. PICs receive incoming packets from
the network and transmit outgoing packets to the network, performing framing and
line-speed signaling for their media type as required. PICs also encapsulate outgoing
packets received from the Compact Forwarding Engine Board (CFEB) or Enhanced CFEB
(CFEB-E) beforetransmitting them. The controller ASICon each PIC performs additional
control functions specific to the PIC media type.
The router supports various PICs, including ATM, Channelized, Gigabit Ethernet, Services,
and SONET/SDH interfaces. You can install PICs of different media types on the same
router as long as the router supports those PICs.
Blank PICs resemble other PICs but do not provide any physical connection or activity.
When a slot is not occupied by a PIC, you must insert a blank PIC to fill the empty slot
and ensure proper cooling of the system.
Four PIC slots are located in one Flexible PIC Concentrator (FPC), FPC0, which is built in
to the chassis. The PIC slots are numbered from 0 (zero) through 3, right to left. The
number of ports on a PIC depends on the type of PIC.
Related
Documentation
The M7i router has a maximum throughput of 3.2 Gbps full duplex for the FPC with 4 PIC
slots. Inserting a combination of PICs with an aggregate higher than the maximum
throughput is supported, but constitutes oversubscription of the FPC. The fixed interface
card (FIC) has a maximum throughput of 1 Gbps full duplex.
PICs are hot-removable and hot-insertable.
Most PICs supported on the M7i router have the following components.
•
One or more cable connector ports—Accept a network media connector.
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LEDs—Indicate PIC and port status. Most PICs have an LED labeled STATUS on the
PIC faceplate. Some PICs have additional LEDs, often one per port. The meaning of
the LED states differs for various PICs.
•
Ejector lever—Controls the locking system that secures the PIC in the card cage.
In most cases, you can install PICs of different media types in the M7i router. However,
configuration rules might limit certain combinations of PICs. Some PICs of different PIC
families cannot be installed in PIC slots 0 and 1, or in slots 2 and 3. If you have different
PIC families in the M7i router and are running Junos OS Release 10.2 or later, review the
configuration rules to plan which PICs to install in your router. Consult the most recent
technical bulletins about configurationrules for PIC combinations on the Juniper Networks
Support site at http://www.juniper.net/support/. Newer Junos OS services for some PICs
can require significant Internet Processor ASIC memory. Ethernet and SONET PICs
typically do not use large amounts of memory. Gigabit Ethernet, ATM2, IQ serial PICs,
IQE PICs, and Multiservices PICs use more. To conserve memory, you can group PICs in
the same family together on the same router.
The PIC/CFEB compatibility matrixes list the current PICs for the m7I router. For example,
Junos OS Release 9.4 is the first release in which the CFEB-E supports the ATM2 DS3 IQ
PIC.
Table 2: CFEB/PIC Compatibility in the M7i Router
ATM2 IQ
page 16
M7i PIC/CFEB Compatibility
CFEB-ECFEBPortsPIC Model NumberPIC Family and Type
9.46.14PE-4DS3-ATM2“ATM2 DS3 IQ PIC (M7i Router)” on
9.46.12PE-2E3-ATM2“ATM2 E3 IQ PIC (M7i Router)” on page 18
“ATM2 OC3/STM1 IQ PIC (M7i Router)” on
page 20
“ATM2 OC12/STM4 IQ PIC (M7i Router)”
on page 22
Channelized IQ
page 24
page 29
page 34
on page 44
on page 51
page 53
PE-2OC3-ATM2-SMIR
PE-1OC12-ATM2-SMIR
9.46.02PE-2OC3-ATM2-MM
9.46.01PE-1OC12-ATM2-MM
9.46.04PE-4CHDS3-QPP“Channelized DS3 IQ PIC (M7i Router)” on
10PE-10CHE1-RJ48-QPP-N“Channelized E1 IQ PIC (M7i Router)” on
9.2R3
9.3R1
9.49.1R4
9.47.11PE-1CHOC3-SMIR-QPP“Channelized OC3 IQ PIC (M7i Router)” on
9.46.01PE-1CHOC12SMIR-QPP“Channelized OC12 IQ PIC (M7i Router)”
9.46.01PE-1CHSTM1-SMIR-QPP“Channelized STM1 IQ PIC (M7i Router)”
9.47.410PE-10CHT1-RJ48-QPP“Channelized T1 IQ PIC (M7i Router)” on
Channelized IQE
PIC (M7i Router)” on page 26
(M7i Router)” on page 31
PIC with SFP (M7i Router)
10.2–4PE-4CHDS3-E3–IQE-BNC“Channelized DS3/E3 Enhanced IQ (IQE)
10.2–10PE-10CHE-T1-IQE-RJ48“Channelized E1/T1 Enhanced IQ (IQE) PIC
Junos-FIPS requires an Adaptive Services II FIPS PIC for external IPSec connections. See the
Secure Configuration Guide for Common Criteria and Junos-FIPS for more information.
•
Supports tunnel services. This feature is included with the PIC and does not require an individual
license.
•
Individual licenses must be purchased for additional services such as Network Address
Translation(NAT), stateful firewall, intrusion detection services (IDS), IPSec. J-Flow accounting,
and voice services. For information about which services are supported by PIC and platform
type, see the Junos OS Services Interfaces Configuration Guide.
•
Power requirement: 0.4 A @ 48 V (19 W)
Hardware features
Software features
•
Support for up to 2000 service sets
•
Active monitoring on up to 1 million flows
•
Support for MTUs up to 9192 bytes for Gigabit Ethernet and SONET interfaces
For a list of the software features available for services PICs, see the Junos OS Services InterfacesConfiguration Guide.
Depending on your Junos OS Release and individual licenses, software features for this PIC can
include:
•
Stateful firewall with packet inspection:
•
Detects SYN attacks, ICMP and UDP floods, and ping-of-death attacks
•
NAT for IP addresses
•
Port Address Translation (PAT) for port numbers
•
J-Flow accounting exports cflowd version 5 and version 8 records
Intelligent queuing (IQ) PICs support fine-grained queuing per logical interface.
•
ATM standards compliant
Hardware features
Software features
•
16-MB SDRAM memory for ATM segmentation and reassembly (SAR)
•
ATM switch ID
•
Configurable framing options:
•
C-bit with ATM direct mapping
•
C-bit with Physical Layer Convergence Protocol (PLCP) framing (default)
•
M23 ATM direct mapping
•
M23 with PLCP framing
•
Internal and loop timing
•
Per-virtual circuit (VC) and per-virtual path (VP) traffic shaping
•
Unspecified bit rate (UBR) traffic shaping
•
Fine-grained variable bit rate (VBR) traffic shaping
•
Circuit cross-connect (CCC)
•
ATM Inverse Address Resolution Protocol (ARP), which enables routers to automatically learn
the IP address of the router on the far end of an ATM permanent virtual circuit (PVC)
Intelligent queuing (IQ) PICs support fine-grained queuing per logical interface
•
ATM standards compliant
Hardware features
Software features
•
16-MB SDRAM memory for ATM segmentation and reassembly (SAR)
•
ATM switch ID
•
Configurable framing options:
•
G.751 direct mapping
•
G.751 with PLCP encapsulation (default)
•
G.832 ATM direct mapping
•
Internal and loop timing
•
Per-virtual circuit (VC) and per-virtual path (VP) traffic shaping
•
Unspecified bit rate (UBR) traffic shaping
•
Fine-grained variable bit rate (VBR) traffic shaping
•
Circuit cross-connect (CCC)
•
ATM Inverse Address Resolution Protocol (ARP), which enables routers to automatically learn
the IP address of the router on the far end of an ATM permanent virtual circuit (PVC)
Intelligent queuing (IQ) PICs support fine-grained queuing per logical interface
•
Conforms to ANSI T1.105-1991 and T1E1.2/93-020R1
•
ATM and SONET/SDH standards compliant
•
Alarm and event counting and detection
•
Compatible with well-known ATM switches
•
ATM switch ID, which displays the switch IP address and local interface name of the adjacent
Fore ATM switches
Hardware features
Software features
•
Single 3010 SAR for segmentation and reassembly into 53 byte ATM cells
•
High-performance parsing of SONET/SDH frames
•
ASIC-basedpacketsegmentationand reassembly(SAR) management and output port queuing
•
64 MB SDRAM memory for ATM SAR
•
Packet buffering, Layer 2 parsing
•
Circuit cross-connect (CCC) for leveraging ATM access networks
•
User-configurable virtual circuit (VC) and virtual path (VP) support
•
Support for idle cell or unassigned cell transmission
•
OAM fault management processes alarm indication signal (AIS), remote defect indicator (RDI)
cells, and loop cells
•
Point-to-point and point-to-multipoint mode Layer 2 counters per VC and per VP
•
Local and remote loopback
•
ATM Inverse Address Resolution Protocol (ARP), which enables routers to automatically learn
the IP address of the router on the far end of an ATM permanent virtual circuit (PVC)
•
Simple Network Management Protocol (SNMP):
•
Management Information Base (MIB) 2 (RFC 1213)
•
ATM MIB (RFC 1695)
•
SONET MIB
•
Unspecified bit rate (UBR), non-real-time variable bit rate (VBR), and constant bit rate (CBR)
traffic shaping
Channelized DS3 and E3 Enhanced IQ (IQE) PIC (M7i Router)
•
Junos OS Release 10.2 and later (Type 1)Software release
•
Description
Four E3 or Channelized DS3 ports
•
E3 or Channelized DS3 is configurable on a per-port granularity
•
DS3 channelization:
•
4 DS3 channels
•
112 DS1 channels
•
1011 DS0 channels
•
Power requirement: 0.53 A @ 48 V (25.4 W)
•
Ports are numbered 0 through 3 from left to rightHardware features
Software features
•
Maximum transmission units (MTUs) of up to 9000 bytes
•
Dynamic, arbitrary channel configuration
•
Subrate and scrambling:
NOTE: Only DS3 interfaces support subrate and scrambling.
•
Digital Link/Quick Eagle
•
Kentrox
•
Larscom
•
ADTRAN
•
Verilink (subrate: only port A mode)
NOTE: For DS3 interfaces, Verilink does not function if an IQE interface is paired with an IQ
interface.
•
Data service unit (DSU) functionality
•
B3ZS line encoding
•
Framing: M13, C-bit parity, framed clear channel
•
Full bit error rate test (BERT) for DS0, DS1, and DS3
•
ANSI T1.403 FDL
•
Internal and loop clocking for DS3 and DS1
•
DS3 far end alarm and control (FEAC) channel
•
Local line, remote line, and remote playback loopback testing for each DS3 and DS1channels
•
Quality of service (QoS) per channel: weighted round-robin (WRR), random early detection
(RED), weighted random early detection (WRED)
•
Enhanced fine-grained queuing per logical interface. See the Junos OS Class of Service
Configuration Guide for more information about class of service features.