Intel UPI- 41A, UPI- 41AH, UPI- 42, UPI- 42AH User Manual
Microprocessor Peripherals
UPI- 41A/41AH/42/42AH
User’s Manual
October 1993
Order Number: 231318-006
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²
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COPYRIGHT©INTEL CORPORATION, 1996
Microprocessor Peripherals
UPI-41A/41AH/42/42AH User’s Manual
CONTENTS PAGE
CHAPTER 1. INTRODUCTION
Interface Registers for Multiprocessor
Configurations ААААААААААААААААААААААААААА 3
Powerful 8-Bit Processor ААААААААААААААААААА 3
Special Instruction Set Features АААААААААААА 4
Preprogrammed UPI’s АААААААААААААААААААААА 5
Development Support АААААААААААААААААААААА 6
UPI Development Support АААААААААААААААААА 6
CHAPTER 2. FUNCTIONAL
DESCRIPTION АААААААААААААААААААААААААА 7
Pin Description ААААААААААААААААААААААААААААА 7
CPU Section АААААААААААААААААААААААААААААА 10
Program Memory АААААААААААААААААААААААААА 11
Interrupt Vectors АААААААААААААААААААААААААА 11
Data Memory ААААААААААААААААААААААААААААА 11
Program Counter АААААААААААААААААААААААААА 12
Program Counter Stack ААААААААААААААААААА 12
Program Status Word ААААААААААААААААААААА 13
Conditional Branch Logic АААААААААААААААААА 13
Oscillator and Timing Circuits АААААААААААААА 14
Interval Timer/Event Counter АААААААААААААА 16
Test Inputs АААААААААААААААААААААААААААААААА 17
Interrupts ААААААААААААААААААААААААААААААААА 18
ААААААААААААА 1
CONTENTS PAGE
Reset
ААААААААААААААААААААААААААААААААААААА 19
Data Bus Buffer ААААААААААААААААААААААААААА 20
System Interface АААААААААААААААААААААААААА 21
Input/Output Interface АААААААААААААААААААА 22
Ports 1 and 2 АААААААААААААААААААААААААААААА 22
Ports 4, 5, 6, and 7 АААААААААААААААААААААААА 23
CHAPTER 3. INSTRUCTION SET АААААААА 26
Instruction Set Description АААААААААААААААА 28
Alphabetic Listing ААААААААААААААААААААААААА 30
CHAPTER 4. SINGLE-STEP AND
PROGRAMMING POWER-DOWN
MODES
Single-Step ААААААААААААААААААААААААААААААА 53
External Access ААААААААААААААААААААААААААА 55
Power Down Mode
(UPI-41AH/42AH Only)
CHAPTER 5. SYSTEM OPERATION АААААА 56
Bus Interface ААААААААААААААААААААААААААААА 56
Design Examples ААААААААААААААААААААААААА 57
General Handshaking Protocol АААААААААААА 60
CHAPTER 6. APPLICATIONS АААААААААААА 62
Abstracts ААААААААААААААААААААААААААААААААА 62
АААААААААААААААААААААААААААААААА 53
ААААААААААААААААА 55
UPI-41A/41AH/42/42AH USER’S MANUAL
CHAPTER 1
INTRODUCTION
Accompanying the introduction of microprocessors
such as the 8088, 8086, 80186 and 80286 there has been
a rapid proliferation of intelligent peripheral devices.
These special purpose peripherals extend CPU performance and flexibility in a number of important
ways.
Table 1-1. Intelligent Peripheral Devices
8255 (GPIO) Programmable Peripheral
Interface
8251A(USART) Programmable
Communication Interface
8253 (TIMER) Programmable Interval Timer
8257 (DMA) Programmable DMA Controller
8259 Programmable Interrupt
Controller
82077AA Programmable Floppy Disk
Controller
8273 (SDLC) Programmable Synchronous
Data Link Controller
8274 Programmable Multiprotocol-
Serial Communications
Controller
8275/8276 (CRT) Programmable CRT
Controllers
8279 (PKD) Programmable
Keyboard/Display Controller
8291A, 8292, 8293 Programmable GPIB System
Talker, Listener, Controller
Intelligent devices like the 82077AA floppy disk controller and 8273 synchronous data link controller (see
Table 1-1) can preprocess serial data and perform control tasks which off-load the main system processor.
Higher overall system throughput is achieved and software complexity is greatly reduced. The intelligent
peripheral chips simplify master processor control tasks
by performing many functions externally in peripheral
hardware rather than internally in main processor software.
Intelligent peripherals also provide system flexibility.
They contain on-chip mode registers which are programmed by the master processor during system initialization. These control registers allow the peripheral to
be configured into many different operation modes. The
user-defined program for the peripheral is stored in
main system memory and is transferred to the peripheral’s registers whenever a mode change is required. Of
course, this type of flexibility requires software overhead in the master system which tends to limit the benefit derived from the peripheral chip.
In the past, intelligent peripherals were designed to
handle very specialized tasks. Separate chips were designed for communication disciplines, parallel I/O,
keyboard encoding, interval timing, CRT control, etc.
Yet, in spite of the large number of devices available
and the increased flexibility built into these chips, there
is still a large number of microcomputer peripheral
control tasks which are not satisfied.
With the introduction of the Universal Peripheral Interface (UPI) microcomputer, Intel has taken the intelligent peripheral concept a step further by providing an
intelligent controller that is fully user programmable. It
is a complete single-chip microcomputer which can
connect directly to a master processor data bus. It has
the same advantages of intelligence and flexibility
which previous peripheral chips offered. In addition,
UPIs are user-programmable: it has 1K/2K bytes of
ROM or EPROM memory for program storage plus
64/128/256 bytes of RAM memory UPI-41A,
41AH/42, 42AH respectively for data storage or initialization from the master processor. The UPI device
allows a designer to fully specify his control algorithm
in the peripheral chip without relying on the master
processor. Devices like printer controllers and keyboard scanners can be completely self-contained, relying on the master processor only for data transfer.
The UPI family currently consists of seven components:
8741A microcomputer with 1K EPROM memory
#
8741AH microcomputer with 1K OTP EPROM
#
memory
8041AH microcomputer with 1K ROM memory
#
8742 microcomputer with 2K EPROM memory
#
8742AH microcomputer with 2K ‘‘OTP’’ EPROM
#
memory
8042AH microcomputer with 2K ROM memory
#
8243 I/O expander device
#
The UPI-41A/41AH/42/42AH family of microcomputers are functionally equivalent except for the type
and amount of program memory available with each.
In addition, the UPI-41AH/42AH family has a Signature Row outside the EPROM Array. The UPI-41AH/
42AH family also has a Security Feature which renders
the EPROM Array unreadable when set.
1
UPI-41A/41AH/42/42AH USER’S MANUAL
All UPI’s have the following main features:
8-bit CPU
#
8-bit data bus interface registers
#
Interval timer/event counter
#
Two 8-bit TTL compatible I/O ports
#
Resident clock oscillator circuits
#
The UPI family has the following differences:
Table 1-2
UPI-41A UPI-42 UPI-41AH UPI-42AH
1Kx8EPROM 2Kx8EPROM 1Kx8ROM 2Kx8ROM
or 1K x 8 OTP or 2K x 8 OTP
64 x 8 RAM 128 x 8 RAM 128 x 8 RAM 256 x 8 RAM
*Set Security Feature
**Signature Row Feature
32 Bytes with:
1. Test Code/Checksum
2. Intel Signature
3. Security Byte
4. User Signature
PROGRAMMING
UPI-41A UPI-42 UPI-41AH/UPI-42AH
e
V
25V 21V 12.5V
DD
e
I
50 ms 50 mA 30 mA
DD
e
21.5V–24.5V 18V 12.5V
EA
e
V
21.5V–24.5V 18V 20.V – 5.5V
PH
e
TPW
50 ms 50 ms 1 ms
PIN DESCRIPTION
UPI-41A/UPI-42 UPI-41AH/UPI-42AH
(T1) T1 functions as a test input which can be T1 functions as a test input that can be directly
directly tested using conditional branching tested using conditional branching instructions. It
instructions. It functions as the event timer input works as the event timer input under software
under software control. control. It is used during sync mode to reset the
instruction state to S1 and synchronize the
internal clock to phase 1.
(SS) Single step input used with the sync Single step input used with the sync output to
output to step the program through each step the program through each instruction.
instruction.
This pin is used to put the device in sync mode by
applying
a
12.5V to it.
Port 1 (P10–P17): 8-bit, Quasi-Bidirectional I/O Port 1 (P10–P17): 8-bit, Quasi-Bidirectional I/O
Lines. Lines. P10–P17 access the Signature Row and
Security Bit.
NOTES:
*For a complete description of the Security Feature, refer to the UPI-41AH/42AH Datasheet.
**For a complete description of the Signature Row, refer to the UPI-41AH/42AH Datasheet.
2
UPI-41A/41AH/42/42AH USER’S MANUAL
HMOS processing has been applied to the UPI family
to allow for additional performance and memory capability while reducing costs. The UPI-41A/41AH/42/
42AH are all pin and software compatible. This allows
growth in present designs to incorporate new features
and add additional performance. For new designs, the
additional memory and performance of the UPI41A/41AH/42/42AH extends the UPI ‘grow your
own solution’ concept to more complex motor control
tasks, 80-column printers and process control applications as examples.
The 8243 device is an I/O multiplexer which allows
expansion of I/O to over 100 lines (if seven devices are
used). All three parts are fabricated with N-channel
MOS technology and require a single, 5V supply for
operation.
INTERFACE REGISTERS FOR MULTIPROCESSOR CONFIGURATIONS
In the normal configuration, the UPI-41A/41AH/42/
42AH interfaces to the system bus, just like any intelligent peripheral device (see Figure 1-1). The host processor and the UPI-41A/41AH/42/42AH form a loosely coupled multi-processor system, that is, communications between the two processors are direct. Common
resources are three addressable registers located physically on the UPI-41A/41AH/42/42AH. These reg-
isters are the Data Bus Buffer Input (DBBIN), Data
Bus Buffer Output (DBBOUT), and Status (STATUS)
registers. The host processor may read data from
DBBOUT or write commands and data into DBBIN.
The status of DBBOUT and DBBIN plus user-defined
status is supplied in STATUS. The host may read
STATUS at any time. An interrupt to the UPI processor is automatically generated (if enabled) when
DBBIN is loaded.
Because the UPI contains a complete microcomputer
with program memory, data memory, and CPU it can
function as a ‘‘Universal’’ controller. A designer can
program the UPI to control printers, tape transports, or
multiple serial communication channels. The UPI can
also handle off-line arithmetic processing, or any number of other low speed control tasks.
POWERFUL 8-BIT PROCESSOR
The UPI contains a powerful, 8-bit CPU with as fast as
1.2 msec cycle time and two single-level interrupts. Its
instruction set includes over 90 instructions for easy
software development. Most instructions are single byte
and single cycle and none are more than two bytes long.
The instruction set is optimized for bit manipulation
and I/O operations. Special instructions are included to
allow binary or BCD arithmetic operations, table lookup routines, loop counters, and N-way branch routines.
Figure 1-1. Interfacing Peripherals To Microcomputer Systems
231318– 1
3
UPI-41A/41AH/42/42AH USER’S MANUAL
231318– 49
8741A
Electrically
Programmable
Light Erasable
EPROM
8741AH, 8742AH
Electrically
Programmed
OTP EPROM
Figure 1-2. Pin Compatible ROM/EPROM Versions
SPECIAL INSTRUCTION SET
FEATURES
For Loop Counters:
#
Decrement Register and Jump if not zero.
For Bit Manipulation:
#
AND to A (immediate data or Register)
OR to A (immediate data or Register)
XOR to A (immediate data or Register)
AND to Output Ports (Accumulator)
OR to Output Ports (Accumulator)
Jump Conditionally on any bit in A
231318– 47
231318– 2
8041AH, 8042AH
Programmed
ROM
For BDC Arithmetic:
#
D8742
Electrically
Programmable
Light Erasable
EPROM
Decimal Adjust A
Swap 4-bit Nibbles of A
Exchange lower nibbles of A and Register
Rotate A left or right with or without Carry
For Lookup Tables:
#
Load A from Page of ROM (Address in A)
Load A from Current Page of ROM
(Address in A)
231318– 3
Figure 1-3. Interfaces and Protocols for Multiprocessor Systems
4
231318– 5
UPI-41A/41AH/42/42AH USER’S MANUAL
Features for Peripheral Control
The UPI 8-bit interval timer/event counter can be used
to generate complex timing sequences for control applications or it can count external events such as switch
closures and position encoder pulses. Software timing
loops can be simplified or eliminated by the interval
timer. If enabled, an interrupt to the CPU will occur
when the timer overflows.
The UPI I/O complement contains two TTL-compatible 8-bit bidirectional I/O ports and two general-purpose test inputs. Each of the 16 port lines can individually function as either input or output under software
control. Four of the port lines can also function as an
interface for the 8243 I/O expander which provides
four additional 4-bit ports that are directly addressable
by UPI software. The 8243 expander allows low cost
I/O expansion for large control applications while
maintaining easy and efficient software port addressing.
The UPI program memory is available in three types to
allow flexibility in moving from design to prototype to
production with the same PC layout. The 8741A/8742
device with EPROM memory is very economical for
initial system design and development. Its program
memory can be electrically programmed using the Intel
Universal PROM Programmer. When changes are
needed, the entire program can be erased using UV
lamp and reprogrammed in about 20 minutes. This
means the 8741A/8742 can be used as a single chip
‘‘breadboard’’ for very complex interface and control
problems. After the 8741A/8742 is programmed it can
be tested in the actual production level PC board and
the actual functional environment. Changes required
during system debugging can be made in the
8741A/8742 program much more easily than they
could be made in a random logic design. The system
configuration and PC layout can remain fixed during
the development process and the turn around time between changes can be reduced to a minimum.
At any point during the development cycle, the
8741A/8742 EPROM part can be replaced with the
low cost UPI-41AH/42AH respectively with factory
mask programmed memory or OTP EPROM. The
transition from system development to mass production
is made smoothly because the 8741A/8742, 8741AH
and 8041AH, 8742AH and 8042AH parts are completely pin compatible. This feature allows extensive
testing with the EPROM part, even into initial shipments to customers. Yet, the transition to low-cost
ROMs or OTP EPROM is simplified to the point of
being merely a package substitution.
231318– 4
Figure 1-4. 8243 I/O Expander Interface
On-Chip Memory
The UPI’s 64/128/256 bytes data memory include dual
working register banks and an 8-level program counter
stack. Switching between the register banks allows fast
response to interrupts. The stack is used to store return
addresses and processor status upon entering a subroutine.
PREPROGRAMMED UPI’s
The 8242AH, 8292, and 8294 are 8042AH’s that are
programmed by Intel and sold as standard peripherals.
Intel offers a complete line of factory programmed keyboard controllers. These devices contain firmware developed by Phoenix Technologies Ltd. and Award Software Inc. See Table 1-3 for a complete listing of Intels’
entire keyboard controller product line. The 8292 is a
GPIB controller, part of a three chip GPIB system.
The 8294 is a Data Encryption Unit that implements
the National Bureau of Standards data encryption algorithm. These parts illustrate the great flexibility offered
by the UPI family.
5
UPI-41A/41AH/42/42AH USER’S MANUAL
Table 1-3. Keyboard Controller Family Product Selection Guide
UPI-42: The industry standard for desktop Keyboard Control.
Device Package ROM OTP Comments
8042 N, P 2K ROM Device
8242 N, P Phoenix firmware version 2.5
8242PC N, P Phoenix MultiKey/42 firmware, PS/2 style mouse support
8242WA N, P Award firmware version 3.57
8242WB N, P Award firmware version 4.14, PS/2 style mouse support
8742 N, P, D 2K Available as OTP (N, P) or EPROM (D)
UPI-C42: A low power CHMOS version of the UPI-42. The UPI-C42 doubles the user programmable memory size,
adds Auto A20 Gate support, includes Standby (**) and Suspend power down modes, and is available in a space
saving 44-lead QFP pkg.
Device Package ROM OTP Comments
80C42 N, P, S 4K ROM Device
82C42PC N, P, S Phoenix MultiKey/42 firmware, PS/2 style mouse support
82C42PD N, P, S Phoenix MultiKey/42L firmware, KBC and SCC for portable apps.
82C42PE N, P, S Phoenix MultiKey/42G firmware, Energy Efficient KBC solution
87C42 N, P, S 4K One Time Programmable Version
UPI-L42: The low voltage 3.3V version of the UPI-C42.
Device Package ROM OTP Comments
80L42 N, P, S 4K ROM Device
82L42PC N, P, S Phoenix MultiKey/42 firmware, PS/2 style mouse support
82L42PD N, P, S Phoenix MultiKey/42L firmware, KBC and SCC for portable apps.
87L42 N, P, S 4K One Time Programmable Version
NOTES:
e
44 lead PLCC, Pe40 lead PDIP, Se44 lead QFP, De40 lead CERDIP
N
e
Key Board Control, SCCeScan Code Control
KBC
(**) Standby feature not supported on current (B-1) stepping
DEVELOPMENT SUPPORT
The UPI microcomputer is fully supported by Intel
with development tools like the UPP PROM programmer already mentioned. The combination of device features and Intel development support make the UPI an
ideal component for low-speed peripheral control applications.
6
UPI DEVELOPMENT SUPPORT
8048/UPI-41A/41AH/42/42AH Assembler
#
Universal PROM Programmer UPP Series
#
Application Engineers
#
Training Courses
#
UPI-41A/41AH/42/42AH USER’S MANUAL
CHAPTER 2
FUNCTIONAL DESCRIPTION
The UPI microcomputer is an intelligent peripheral
controller designed to operate in iAPX-86, 88, MCS-85,
MCS-80, MCS-51 and MCS-48 systems. The UPI’s architecture, illustrated in Figure 2-1, is based on a low
cost, single-chip microcomputer with program memory, data memory, CPU, I/O, event timer and clock oscillator in a single 40-pin package. Special interface registers are included which enable the UPI to function as
a peripheral to an 8-bit master processor.
This chapter provides a basic description of the UPI
microcomputer and its system interface registers. Unless otherwise noted the descriptions in this section apply to the 8741AH, 8742AH with OTP EPROM mem-
ory, the 8741A/8742 (with UV erasable program memory) and the 8041AH, 8042AH. These devices are so
similar that they can be considered identical under
most circumstances. All functions described in this
chapter apply to the UPI-41A/41AH/42/42AH.
PIN DESCRIPTION
The UPI-41A/41AH/42/42AH are packaged in 40-pin
Dual In-Line (DIP) packages. The pin configuration
for both devices is shown in Figure 2-2. Figure 2-3 illustrates the UPI Logic Symbol.
Figure 2-1. UPI-41A/41AH/42/42AH Single Chip Microcomputer
231318– 6
7
UPI-41A/41AH/42/42AH USER’S MANUAL
Figure 2-2. Pin Configuration
231318– 7
231318– 8
Figure 2-3. Logic Symbol
8
UPI-41A/41AH/42/42AH USER’S MANUAL
The following section summarizes the functions of each UPI pin. NOTE that several pins have two or more
functions which are described in separate paragraphs.
Table 2-1. Pin Description
Symbol Pin No. Type Name and Function
D0–D
7
(BUS) lines used to interface the UPI-41A/41AH/42/42AH
P10–P
17
P20–P
27
WR 10 I WRITE: I/O write input which enables the master CPU to write
RD 8IREAD: I/O read input which enables the master CPU to read
CS 6ICHIP SELECT: Chip select input used to select one UPI-
A
0
TEST 0, 1 I TEST INPUTS: Input pins can be directly tested using
TEST 1 39 conditional branch instructions.
XTAL 1, 2 I INPUTS: Inputs for a crystal, LC or an external timing signal to
XTAL 2 3 determine the internal oscillator frequency.
SYNC 11 O OUTPUT CLOCK: Output signal which occurs once per UPI
EA 7 I EXTERNAL ACCESS: External access input which allows
PROG 25 I/O PROGRAM: Multifunction pin used as the program pulse input
RESET 4IRESET: Input used to reset status flip-flops and to set the
SS 5ISINGLE STEP: Single step input used in conjunction with the
V
CC
V
DD
V
SS
12–19 I/O DATA BUS: Three-state, bidirectional DATA BUS BUFFER
microcomputer to an 8-bit master system data bus.
27-34 I/O PORT 1: 8-bit, PORT 1 quasi-bidirectional I/O lines.
21-24 I/O PORT 2: 8-bit, PORT 2 quasi-bidirectional I/O lines. The lower
35–38 4 bits (P
device and contain address and data information during PORT
4–7 access. The upper 4 bits (P
to provide interrupt Request and DMA Handshake capability.
Software control can configure P
(OBF) interrupt, P
DMA Request (DRQ), and P
ACKnowledge (DACK
) interface directly to the 8243 I/O expander
20–P23
) can be programmed
24–P27
as Output Buffer Full
as Input Buffer Full (IBF) interrupt, P26as
25
).
as DMA
27
24
data and command words to the UPI INPUT DATA BUS
BUFFER.
data and status words from the OUTPUT DATA BUS BUFFER
or status register.
41A/41AH/42/42AH microcomputer out of several
connected to a common data bus.
9ICOMMAND/DATA SELECT: Address input used by the
master processor to indicate whether byte transfer is data
e
(A
0) or command (A
0
FREQUENCY REFERENCE: TEST 1 (T
the event timer input (under software control). TEST0 (T
used during PROM programming and verification in the UPI-
e
1).
0
) also functions as
1
0
)is
41A/41AH/42/42AH.
instruction cycle. SYNC can be used as a strobe for external
circuitry; it is also used to synchronize single step operation.
emulation, testing and PROM/ROM verification.
during PROM programming.
During I/O expander access the PROG pin acts as an
address/data strobe to the 8243.
program counter to zero. RESET
is also used during PROM
programming and verification.
SYNC output to step the program through each instruction.
40 POWER:a5V main power supply pin.
26 POWER:a5V during normal operation.a25V for UPI-41A,
21V for UPI-42 programming operation,
a
12V for
programming, UPI-41AH/42AH. Low power standby pin in
ROM version.
20 GROUND: Circuit ground potential.
9
UPI-41A/41AH/42/42AH USER’S MANUAL
The following sections provide a detailed functional description of the UPI microcomputer. Figure 2-4 illustrates the functional blocks within the UPI device.
CPU SECTION
The CPU section of the UPI-41A/41AH/42/42AH
microcomputer performs basic data manipulations and
controls data flow throughout the single chip computer
via the internal 8-bit data bus. The CPU section includes the following functional blocks shown in Figure
2-4:
Arithmetic Logic Unit (ALU)
#
Instruction Decoder
#
Accumulator
#
Flags
#
Arithmetic Logic Units (ALU)
The ALU is capable of performing the following operations:
ADD with or without carry
#
AND, OR, and EXCLUSIVE OR
#
Increment, Decrement
#
Bit complement
#
Rotate left or right
#
Swap
#
BCD decimal adjust
#
In a typical operation data from the accumulator is
combined in the ALU with data from some other
source on the UPI-41A/41AH/42/42AH internal bus
(such as a register or an I/O port). The result of an
ALU operation can be transferred to the internal bus or
back to the accumulator.
If an operation such as an ADD or ROTATE requires
more than 8 bits, the CARRY flag is used as an indicator. Likewise, during decimal adjust and other BCD
operations the AUXILIARY CARRY flag can be set
and acted upon. These flags are part of the Program
Status Word (PSW).
Instruction Decoder
During an instruction fetch, the operation code (opcode) portion of each program instruction is stored and
decoded by the instruction decoder. The decoder generates outputs used along with various timing signals to
control the functions performed in the ALU. Also, the
instruction decoder controls the source and destination
of ALU data.
Accumulator
The accumulator is the single most important register
in the processor. It is the primary source of data to the
ALU and is often the destination for results as well.
Data to and from the I/O ports and memory normally
passes through the accumulator.
Figure 2-4. UPI-41A/41AH/42/42AH Block Diagram
10
231318– 9
UPI-41A/41AH/42/42AH USER’S MANUAL
PROGRAM MEMORY
The UPI-41A/41AH/42/42AH microcomputer has
1024, 2048 8-bit words of resident, read-only memory
for program storage. Each of these memory locations is
directly addressable by a 10-bit program counter. Depending on the type of application and the number of
program changes anticipated, three types of program
memory are available:
8041AH, 8042AH with mask programmed ROM
#
Memory
8741AH, 8742AH with electrically programmable
#
OTP EPROM Memory
8741A and 8742 with electrically programmable
#
EPROM Memory
A program memory map is illustrated in Figure 2-5.
Memory is divided into 256 location ‘pages’ and three
locations are reserved for special use:
INTERRUPT VECTORS
1) Location 0
Following a RESET
instruction is automatically fetched from location 0.
2) Location 3
An interrupt generated by an Input Buffer Full
(IBF) condition (when the IBF interrupt is enabled)
causes the next instruction to be fetched from location 3.
3) Location 7
A timer overflow interrupt (when enabled) will
cause the next instruction to be fetched from location 7.
Following a system RESET
at location 0. Instructions in program memory are normally executed sequentially. Program control can be
transferred out of the main line of code by an input
buffer full (IBF) interrupt or a timer interrupt, or when
a jump or call instruction is encountered. An IBF interrupt (if enabled) will automatically transfer control to
location 3 while a timer interrupt will transfer control
to location 7.
All conditional JUMP instructions and the indirect
JUMP instruction are limited in range to the current
256-location page (that is, they alter PC bits 0 – 7 only).
If a conditional JUMP or indirect JUMP begins in location 255 of a page, it must reference a destination on
the following page.
input to the processor, the next
, program execution begins
231318– 10
Figure 2-5. Program Memory Map
Program memory can be used to store constants as well
as program instructions. The UPI-41AH, 42AH instruction set contains an instruction (MOVP3) designed specifically for efficient transfer of look-up table
information from page 3 of memory.
DATA MEMORY
The UPI-41A has 64 8-bit words of Random Access
Memory, the UPI-41AH has 128 8-bit words of Random Access Memory; the UPI-42 has 128 8-bit words
of RAM; and the UPI-42AH has 256 8-bit words of
RAM. This memory contains two working register
banks, an 8-level program counter stack and a scratch
pad memory, as shown in Figure 2-6. The amount of
scratch pad memory available is variable depending on
the number of addresses nested in the stack and the
number of working registers being used.
Addressing Data Memory
The first eight locations in RAM are designated as
working registers R
can be addressed directly by specifying a register number in the instruction. Since these locations are easily
addressed, they are generally used to store frequently
. These locations (or registers)
0–R7
11
UPI-41A/41AH/42/42AH USER’S MANUAL
accessed intermediate results. Other locations in data
memory are addressed indirectly by using R
specify the desired address.
Figure 2-6. Data Memory Map
or R1to
0
231318– 11
Working Registers
Dual banks of eight working registers are included in
the UPI-41A/41AH/42/42AH data memory. Locations 0 – 7 make up register bank 0 and locations 24 – 13
form register bank 1. A RESET
selects register bank 0. When bank 0 is selected, references to R
tions operate on locations 0 – 7 in data memory. A ‘‘select register bank’’ instruction is used to selected between the banks during program execution. If the instruction SEL RB1 (Select Register Bank 1) is executed, then program references to R
locations 24 – 31. As stated previously, registers 0 and 1
in the active register bank are used as indirect address
registers for all locations in data memory.
in UPI-41A/41AH/42/42AH instruc-
0–R7
signal automatically
will operate on
0–R7
interrupt processing, registers in bank 0 can be accessed
indirectly using R
If register bank 1 is not used, registers 24 – 31 can still
serve as additional scratch pad memory.
0
Ê
and R
.
1
Ê
Program Counter Stack
RAM locations 8–23 are used as an 8-level program
counter stack. When program control is temporarily
passed from the main program to a subroutine or interrupt service routine, the 10-bit program counter and
bits 4– 7 of the program status word (PSW) are stored
in two stack locations. When control is returned to the
main program via an RETR instruction, the program
counter and PSW bits 4–7 are restored. Returning via
an RET instruction does not restore the PSW bits,
however. The program counter stack is addressed by
three stack pointer bits in the PSW (bits 0– 2). Operation of the program counter stack and the program
status word is explained in detail in the following sections.
The stack allows up to eight levels of subroutine ‘nesting’; that is, a subroutine may call a second subroutine,
which may call a third, etc., up to eight levels. Unused
stack locations can be used as scratch pad memory.
Each unused level of subroutine nesting provides two
additional RAM locations for general use.
The following sections provide a detailed description of
the Program Counter Stack and the Program Status
Word.
PROGRAM COUNTER
The UPI-41A/41AH/42/42AH microcomputer has a
10-bit program counter (PC) which can directly address any of the 1024, 2048, or 4096 locations in program memory. The program counter always contains
the address of the next instruction to be executed and is
normally incremented sequentially for each instruction
to be executed when each instruction fetches occurs.
When control is temporarily passed from the main program to a subroutine or an interrupt routine, however,
the PC contents must be altered to point to the address
of the desired routine. The stack is used to save the
current PC contents so that, at the end of the routine,
main program execution can continue. The program
counter is initialized to zero by a RESET
signal.
Register bank 1 is normally reserved for handling interrupt service routines, thereby preserving the contents of
the main program registers. The SEL RB1 instruction
can be issued at the beginning of an interrupt service
routine. Then, upon return to the main program, an
RETR (return & restore status) instruction will automatically restore the previously selected bank. During
12
PROGRAM COUNTER STACK
The Program Counter Stack is composed of 16 locations in Data Memory as illustrated in Figure 2-7.
These RAM locations (8 through 23) are used to store
the 10-bit program counter and 4 bits of the program
status word.
UPI-41A/41AH/42/42AH USER’S MANUAL
An interrupt or Call to a subroutine causes the contents
of the program counter to be stored in one of the 8
register pairs of the program counter stack.
STACK MEMORY
POINTER LOCATION
111
110
101
100
011
010
001
000
PSW
(4–7)
PC
(4–7)
MSB LSB
PC
(8–9)
PC
(0–3)
DATA
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Figure 2-7. Program Counter Stack
A 3-bit Stack Pointer which is part of the Program
Status Word (PSW) determines the stack pair to be
used at a given time. The stack pointer is initialized by
a RESET
signal to 00H which corresponds to RAM
locations 8 and 9.
The first call or interrupt results in the program counter and PSW contents being transferred to RAM locations 8 and 9 in the format shown in Figure 2-7. The
stack pointer is automatically incremented by 1 to point
to location is 10 and 11 in anticipation of another
CALL.
Nesting of subroutines within subroutines can continue
up to 8 levels without overflowing the stack. If overflow
does occur the deepest address stored (locations 8 and
9) will be overwritten and lost since the stack pointer
overflows from 07H to 00H. Likewise, the stack pointer
will underflow from 00H to 07H.
The end of a subroutine is signaled by a return instruction, either RET or RETR. Each instruction will automatically decrement the Stack Pointer and transfer the
contents of the proper RAM register pair to the Program Counter.
PROGRAM STATUS WORD
The 8-bit program status word illustrated in Figure 2-8
is used to store general information about program execution. In addition to the 3-bit Stack Pointer discussed
previously, the PSW includes the following flags:
CY Ð Carry
#
AC Ð Auxiliary Carry
#
F0Ð Flag 0
#
BS Ð Register Bank Select
#
231318– 12
Figure 2-8. Program Status Word
The Program Status Word (PSW) is actually a collection of flip-flops located throughout the machine which
are read or written as a whole. The PSW can be loaded
to or from the accumulator by the MOV A, PSW or
MOV PSW, A instructions. The ability to write directly
to the PSW allows easy restoration of machine status
after a power-down sequence.
The upper 4 bits of the PSW (bits 4, 5, 6, and 7) are
stored in the PC Stack with every subroutine CALL or
interrupt vector. Restoring the bits on a return is optional. The bits are restored if an RETR instruction is
executed, but not if an RET is executed.
PSW bit definitions are as follows:
Bits 0 –2 Stack Pointer Bits S0,S1,S
#
Bit 3 Not Used
#
Bit 4 Working Register Bank
#
e
Bank 0
0
e
Bank 1
1
Bit 5 Flag 0 bit (F0)
#
2
This is a general purpose flag which can be cleared
or complemented and tested with conditional jump
instructions. It may be used during data transfer to
an external processor.
Bit 6 Auxiliary Carry (AC)
#
The flag status is determined by an ADD instruction and is used by the Decimal Adjustment instruction DAA
Bit 7 Carry (CY)
#
The flag indicates that a previous operation resulted
in overflow of the accumulator.
CONDITIONAL BRANCH LOGIC
Conditional Branch Logic in the UPI-41AH, 42AH allows the status of various processor flags, inputs, and
other hardware functions to directly affect program execution. The status is sampled in state 3 of the first
cycle.
13
UPI-41A/41AH/42/42AH USER’S MANUAL
Table 2-2 lists the internal conditions which are testable
and indicates the condition which will cause a jump. In
all cases, the destination address must be within the
page of program memory (256 locations) in which the
jump instruction occurs.
OSCILLATOR AND TIMING CIRCUITS
The UPI-41A/41AH/42/42AH’s internal timing generation is controlled by a self-contained oscillator and
timing circuit. A choice of crystal, L-C or external
clock can be used to derive the basic oscillator frequency.
The resident timing circuit consists of an oscillator, a
state counter and a cycle counter as illustrated in Figure 2-9. Figure 2-10 shows instruction cycle timing.
Oscillator
The on-board oscillator is a series resonant circuit with
a frequency range of 1 to 12.5 MHz depending on
Table 2-2. Conditional Branch Instructions
Device Instruction Mnemonic
Accumulator JZ addr All bits zero
JNZ addr Any bit not zero
Accumulator bit JBb addr Bit ‘‘b’’
Carry flag JC addr Carry flag
JNC addr Carry flag
User flag JFO addr F0flage1
JF1 addr F
Timer flag JTF addr Timer flage1
Test Input 0 JT0 addr T
JNT0 addr T
Test Input 1 JT1 addr T
JNT1 addr T
Input Buffer flag JNIBF addr IBF flag
Output Buffer flag JOBF addr OBF flage1
which UPI is used. Refer to Table 1.1. Pins XTAL 1
and XTAL 2 are input and output (respectively) of a
high gain amplifier stage. A crystal or inductor and
capacitor connected between XTAL 1 and XTAL 2
provide the feedback and proper phase shift for oscillation. Recommended connections for crystal or L-C are
shown in Figure 2-11.
State Counter
The output of the oscillator is divided by 3 in the state
counter to generate a signal which defines the state
times of the machine.
Each instruction cycle consists of five states as illustrated in Figure 2-10 and Table 2-3. The overlap of address
and execution operations illustrated in Figure 2-10 allows fast instruction execution.
Jump Condition
Jump if:
e
1
e
1
e
0
flage1
1
e
1
0
e
0
0
e
1
1
e
0
1
e
0
Figure 2-9. Oscillator Configuration Figure 2-10. Instruction Cycle Timing
14
231318– 14
231318– 13
UPI-41A/41AH/42/42AH USER’S MANUAL
Table 2-3. Instruction Timing Diagram
Instruction
IN A,Pp
OUTL Pp,A
ANL Pp, DATA Instruction Program Timer Immediate Program To Port
ORL Pp, DATA Instruction Program Timer Immediate Program To Port
MOVD A,Pp
MOVD Pp, A
D Pp, A
ORLD Pp, A
J (Conditional) Instruction Program Counter Condition Timer Immediate Data Program
MOV STS, A
IN A, DBB
OUT DBB, A
STRT T Fetch Increment
STRT CNT Instruction Program Counter Counter
STOP TCNT
EN I
DIS I
EN DMA Fetch Increment
EN FLAGS
S1 S2 S3 S4 S5 S1 S2 S3 S4 S5
Fetch Increment
Instruction Program Counter Timer
Fetch Increment
Instruction Program Counter Timer To Port
Fetch Increment
Fetch Increment
Fetch Increment Output Increment
Instruction Program Counter Opcode/Address Timer P2 Lower
Fetch Increment Output Increment Output Data
Instruction Program Counter Opcode/Address Timer To P2 Lower
Fetch Increment Output Increment Output
Instruction Program Counter Opcode/Address Timer Data
Fetch Increment Output Increment Output
Instruction Program Counter Opcode/Address Timer Data
Fetch Increment Sample Increment
Fetch Increment
Instruction Program Counter Timer Status Register
Fetch Increment
Instruction Program Counter Timer
Fetch Increment
Instruction Program Counter Timer To Port
Fetch Increment
Instruction Program Counter Counter
Fetch Increment
Instruction Program Counter Interrupt
Fetch Increment
Instruction Program Counter Interrupt
Instruction Program Counter DRQ Cleared
Fetch Increment
Instruction Program Counter Output Enabled
Counter Data Counter
Counter Data Counter
CYCLE 1 CYCLE 2
Ð
Ð
Ð
Ð
Ð
Ð
Ð
ÐÐ
ÐÐ
Ð
Ð
Ð
Ð
Increment
Increment Output
Increment Read Port Fetch
Increment Read Port Fetch
Increment Update
Increment
Increment Output
Enable
Disable
DMA Enabled
OBF, IBF
ÐÐ
Ð
Ð
Ð
Start
Stop
Ð
Ð
Ð
Ð
Fetch
Read Port
ÐÐÐÐÐ
Ð
Ð
Ð Read
ÐÐÐÐÐ
ÐÐÐÐÐ
ÐÐÐÐÐ
Ð
ÐÐÐ
Increment Output
Increment Output
ÐÐÐ
Update
Counter
ÐÐ
Ð
Ð
Figure 2-11. Recommended Crystal and L-C Connections
231318– 48
231318– 15
15
UPI-41A/41AH/42/42AH USER’S MANUAL
Cycle Counter
The output of the state counter is divided by 5 in the
cycle counter to generate a signal which defines a machine cycle. This signal is call SYNC and is available
continuously on the SYNC output pin. It can be used
to synchronize external circuitry or as a general purpose clock output. It is also used for synchronizing single-step.
Frequency Reference
The external crystal provides high speed and accurate
timing generation. A crystal frequency of 5.9904 MHz
is useful for generation of standard communication frequencies by the UPI-41A/41AH/42/42AH. However,
if an accurate frequency reference and maximum processor speed are not required, an inductor and capacitor
may be used in place of the crystal as shown in Figure
2-11.
A recommended range of inductance and capacitance
combinations is given below:
Le130 mH corresponds to 3 MHz
#
Le45 mH corresponds to 5 MHz
#
An external clock signal can also be used as a frequency
reference to the UPI-41A/41AH/42/42AH; however,
the levels are not TTL compatible. The signal must be
in the 1 – 12.5 MHz frequency range depending on
which UPI is used. Refer to Table 1-2. The signal must
be connected to pins XTAL 1 and XTAL 2 by buffers
with a suitable pull-up resistor to guarantee that a logic
‘‘1’’ is above 3.8 volts. The recommended connection is
shown in Figure 2-12.
INTERVAL TIMER/EVENT COUNTER
The UPI-41A/41AH/42/42AH has a resident 8-bit
timer/counter which has several software selectable
modes of operation. As an interval timer, it can generate accurate delays from 80 microseconds to 20.48 milliseconds without placing undue burden on the processor. In the counter mode, external events such as switch
closures or tachometer pulses can be counted and used
to direct program flow.
Timer Configuration
Figure 2-13 illustrates the basic timer/counter configuration. An 8-bit register is used to count pulses from
either the internal clock and prescaler or from an external source. The counter is presettable and readable with
two MOV instructions which transfer the contents of
the accumulator to the counter and vice-versa (i.e.
MOV T, A and MOV A, T). The counter is stopped by
a RESET
stopped until restarted either as a timer (START T instruction) or as a counter (START CNT instruction).
Once started, the counter will increment to its maximum count (FFH) and overflow to zero continuing its
count until stopped by a STOP TCNT instruction or
RESET
The increment from maximum count to zero (overflow)
results in setting the Timer Flag (TF) and generating an
interrupt request. The state of the overflow flag is testable with the conditional jump instruction, JTF. The
flag is reset by executing a JTF or by a RESET
The timer interrupt request is stored in a latch and
ORed with the input buffer full interrupt request. The
timer interrupt can be enabled or disabled independent
of the IBF interrupt by the EN TCNTI and DIS
TCTNI instructions. If enabled, the counter overflow
will cause a subroutine call to location 7 where the timer service routine is stored. If the timer and Input Buffer Full interrupts occur simultaneously, the IBF source
will be recognized and the call will be to location 3.
Since the timer interrupt is latched, it will remain pending until the DBBIN register has been serviced and will
immediately be recognized upon return from the service routine. A pending timer interrupt is reset by the
initiation of a timer interrupt service routine.
or STOP TCNT instruction and remains
.
signal.
Figure 2-12. Recommended Connection
For External Clock Signal
16
231318– 16
Event Counter Mode
The STRT CNT instruction connects the TEST 1 input
pin to the counter input and enables the counter. Note
this instruction does not clear the counter. The counter
is incremented on high to low transitions of the TEST 1
input. The TEST 1 input must remain high for a minimum of one state in order to be registered (250 ns at
12 MHz). The maximum count frequency is one count
per three instruction cycles (267 kHz at 12 MHz).
There is no minimum frequency limit.
UPI-41A/41AH/42/42AH USER’S MANUAL
Timer Mode
The STRT T instruction connects the internal clock to
the counter input and enables the counter. The input
clock is derived from the SYNC signal of the internal
oscillator and the divide-by-32 prescaler. The configuration is illustrated in Figure 2-13. Note this instruction
does not clear the timer register. Various delays and
timing sequences between 40 msec and 10.24 msec can
easily be generated with a minimum of software timing
loops (at 12 MHz).
Times longer than 10.24 msec can be accurately measured by accumulating multiple overflows in a register
under software control. For time resolution less than 40
msec, an external clock can be applied to the TEST 1
counter input (see Event Counter Mode). The minimum time resolution with an external clock is 3.75
msec (267 kHz at 12 MHz).
TEST 1 Event Counter Input
The TEST 1 pin is multifunctional. It is automatically
initialized as a test input by a RESET
tested using UPI-41A conditional branch instructions.
In the second mode of operation, illustrated in Figure
2-13, the TEST 1 pin is used as an input to the internal
signal and can be
8-bit event counter. The Start Counter (STRT CNT)
instruction controls an internal switch which connects
TEST 1 through an edge detector to the 8-bit internal
counter. Note that this instruction does not inhibit the
testing of TEST 1 via conditional Jump instructions.
In the counter mode the TEST 1 input is sampled once
per instruction cycle. After a high level is detected, the
next occurrence of a low level at TEST 1 will cause the
counter to increment by one.
The event counter functions can be stopped by the Stop
Timer/Counter (STOP TCNT) instruction. When this
instruction is executed the TEST 1 pin becomes a test
input and functions as previously described.
TEST INPUTS
There are two multifunction pins designated as Test
Inputs, TEST 0 and TEST 1. In the normal mode of
operation, status of each of these lines can be directly
tested using the following conditional Jump instructions:
JT0 Jump if TEST 0e1
#
JNT0 Jump if TEST 0e0
#
JT1 Jump if TEST 1e1
#
JNT1 Jump if TEST 1e0
#
231318– 17
Figure 2-13. Timer Counter
17
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