INTEL STEL-2000A User Manual
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STEL-2000A
Data Sheet
STEL-2000A+45
(45 MHz)
STEL-2000A+20
(20 MHz)
Digital, Fast Acquisition
Spread Spectrum
Burst Processor
R
FEATURES/BENEFITS ....................................................................................................................................... 3
BLOCK DIAGRAM.............................................................................................................................................. 3
PACKAGE OUTLINE.......................................................................................................................................... 4
PIN CONFIGURATION...................................................................................................................................... 4
GENERAL DESCRIPTION ................................................................................................................................. 5
FUNCTIONAL BLOCKS..................................................................................................................................... 7
Transmit and Receive Clock Generator Blocks.................................................................................. 7
Input and Output Processor Blocks .................................................................................................... 7
Differential Encoder Block.................................................................................................................... 7
Transmitter PN Code Generator Block............................................................................................... 7
BPSK/QPSK Modulator Block............................................................................................................. 8
Frequency Control Register and NCO Block..................................................................................... 8
Downconverter Block............................................................................................................................ 8
Receiver PN Code Register and PN Matched Filter Blocks............................................................. 9
Power Detector Block............................................................................................................................ 10
Symbol Tracking Processor Block........................................................................................................ 11
Differential Demodulator Block .......................................................................................................... 11
Frequency Discriminator and Loop Filter Block ............................................................................... 12
INPUT SIGNALS.................................................................................................................................................. 14
OUTPUT SIGNALS.............................................................................................................................................. 18
TRANSMITTER AND RECEIVER TEST POINTS .......................................................................................... 20
CONTROL REGISTERS ...................................................................................................................................... 21
Downconverter Registers...................................................................................................................... 21
PN Matched Filter Registers................................................................................................................. 22
Power Estimator Registers.................................................................................................................... 23
Acquisition and Tracking Processor Registers .................................................................................. 24
Demodulator Registers.......................................................................................................................... 27
Output Processor Control Registers.................................................................................................... 29
Transmit Control Registers................................................................................................................... 31
REGISTER SETTING SEQUENCE ........................................................................................................ 33
DECIMAL, HEX AND BINARY ADDRESS EQUIVALENTS....................................................................... 34
REGISTER SUMMARY ....................................................................................................................................... 35
ELECTRICAL CHARACTERISTICS ................................................................................................................. 36
ABSOLUTE MAXIMUM RATINGS.................................................................................................... 36
RECOMMENDED OPERATING CONDITIONS ............................................................................. 36
D.C. CHARACTERISTICS.................................................................................................................... 36
TRANSMITTER INPUT/OUTPUT TIMING .................................................................................... 37
RECEIVER INPUT/OUTPUT TIMING.............................................................................................. 38
MICROPROCESSOR INTERFACE TIMING..................................................................................... 39
APPENDIX I: THEORY OF OPERATION ...................................................................................................... 40
Digital Downconversion....................................................................................................................... 40
Using the STEL-2000A with a Single ADC in Direct I.F. Sampling Mode ............................... 40
Using the STEL-2000A with Two ADCs in Quadrature Sampling Mode................................ 43
Differential Demodulation ................................................................................................................... 44
BPSK Demodulation......................................................................................................................... 44
QPSK Demodulation........................................................................................................................ 44
Frequency Error Generation................................................................................................................. 45
Using the Modulator in the STEL-2000A Transmitter...................................................................... 46
APPENDIX II: TYPICAL APPLICATION ....................................................................................................... 48
––––––––––––––––––––––––––––––––––––––––––––––––––––
STEL-2000A 2
FEATURES
■ Complete direct sequence spread spectrum
burst transceiver in a single CMOS I.C.
■ Programmable functionality supports
many different operational modes
■ Supports PN chip rate of over 11
Mchips/sec. in transmit and receive modes
(STEL-2000A+45 only)
■ Acquires within one symbol duration
using digital PN Matched Filter
■ Two independent PN sequences, each up
to 64 chips long, for distinct processing of
the acquisition/preamble symbol and
subsequent data symbols
■ Power management features
■ Optional spectral whitening code
generation
■ Full or half duplex operation
■ 100-Pin PQFP packaging
BENEFITS
■ High performance and high reliability
with reduced manufacturing costs
■ Ideal for a wide range of wireless
applications including data acquisition
systems, transaction systems and wireless
Local Area Networks (WLANs)
■ Supports data rates up to 2.048 Mbps in
compliance with FCC regulations
(STEL-2000A+45 only)
■ Fast response and very low overhead when
operating in burst modes
■ Allows high processing gain to maximize
the acquisition probability, then reduced
code length for increased data rate
■ Low power consumption
■ Randomizes data to meet regulatory
requirements
■ Permits dual frequency (Frequency
Division Duplex) or single frequency
(Time Division Duplex) operation
■ Small footprint, surface mount
BLOCK DIAGRAM (Figure 1)
TXBITPLS
TXTRKPLS
TXIN
TX M CHP
TXIFCLK
MTXEN
MNCO E N
MRXEN
RXMABRT
MFLD
CSEL
WR
RESE T
DATA
7-0
ADDR
6-0
OEN
RXOUT
RXQOUT
RXIOUT
RXDRDY
RXSYMPLS
TX OVERL AY
CODE
GENERATOR
TX
CLO CK
GENER-
ATO R
CONT ROL
& µP
INTER-
FACE
RX OVERLAY
CODE
GENERATOR
OUT P UT DAT A
PROCESSOR
BIT CLOCK
SYMBOL CLOCK
CHIP CLOCK
TXIFCLK
INP UT DATA
PROCESSOR
FREQUENCY
CONT ROL
REGISTER
DISCRIMINATOR
& LOOP FILTER
DIF FERENTIAL
DEMO DULATOR
CORRECTED BIT CLOCK
CORRECTED SYMBOL CL OCK
FREQUENCY
DIF FER-
ENTIAL
ENCO DE R
SYMBOL
TRACKI NG
PROCESSOR
TX P N CO DE
GE NE RAT ORS
NCO
POWER
DETECTOR
SIN
COS
2x CHIP CLOCK
SYMBOL CLOCK
MATCHED
RXIFCLK
QPSK
MO DULATOR
RX PN CO DE
REG I S TERS
FILTER
CLOCK
CHIP
RX
CLO CK
GENER-
ATO R
DOW N
CONVERTER
TXIFOUT
TXIOUT
TXQOUT
TXCHPPLS
TXACQPLS
TXACTIVE
RXACTIVE
TXTEST
RXTEST
RXIIN
RXQIN
RXIFCLK
RXMSMPL
RXMDET
7-0
7-0
7-0
7-0
––––––––––––––––––––––––––––––––––––––––––––––––––––
3 STEL-2000A
PACKAGE OUTLINE (Figure 2)
0.941"
± 0.010"
0.742"
±0.005"
80
81
51
50
Top View
0.487"
±0.003"
0.705"
± 0.010"
0.11" nom.
Pin 1 Identifier
100
1
0.0256" ±0.002"
0.014"
± 0.002"
31
30
0.122" max.
Package style: 100-pin PQFP. Thermal characteristics: θja = 41° C/W (STEL-2000A+45),
= 68° C/W (STEL-2000A+20)
θ
ja
PIN CONFIGURATION
1V
DD
2 RXQIN
3 RXQIN
4 RXQIN
5 RXQIN
6 RXQIN
7 RXQIN
8 RXQIN
9 RXQIN
0
1
2
3
4
5
6
7
10 MRXEN
11 V
DD
12 RXIFCLK
13 V
SS
14 TXIFCLK
15 V
SS
РРРРРР
16 RESET
17 MTXEN
18 TXIN
19 TXMCHP
20 DATA
0
21 DATA
22 DATA
23 DATA
24 DATA
25 DATA
26 DATA
27 DATA
ÐÐÐ
28 WR
29 CSEL
30 V
31 V
РРРРР
SS
DD
32 ADDR
33 ADDR
34 ADDR
35 ADDR
36 ADDR
37 ADDR
38 ADDR
39 V
SS
40 V
DD
1
2
3
4
5
6
7
0
1
2
3
4
5
6
41 RXTEST
42 RXTEST
43 RXTEST
44 RXTEST
45 RXTEST
46 RXTEST
47 RXTEST
48 RXTEST
ÐÐÐÐ
49 OEN
50 V
51 V
7
6
5
4
3
2
1
0
SS
DD
52 RXSYMPLS
53 RXSPLPLS
РРРРРРРРР
54 RXDRDY
55 RXQOUT
56 RXIOUT
57 RXOUT
58 I.C.
59 TXTEST
60 TXACQPLS
61 TXTRKPLS
62 TXCHPPLS
63 TXBITPLS
64 V
SS
65 V
DD
66 TXIFOUT
67 TXIFOUT
68 TXIFOUT
69 TXIFOUT
70 TXIFOUT
71 TXIFOUT
72 TXIFOUT
73 TXIFOUT
74 V
SS
75 V
DD
76 TXQOUT
77 TXIOUT
78 TXACTIVE
79 N.C.
80 V
SS
0.009"
± 0.005"
7
6
5
4
3
2
1
0
Detail of pins
81 V
DD
82 N.C.
83 RXACTIVE
84 RXMSMPL
85 MFLD
86 MNCOEN
87 RXMABRT
88 RXMDET
89 V
SS
90 V
DD
91 RXIIN
92 RXIIN
93 RXIIN
94 RXIIN
95 RXIIN
96 RXIIN
97 RXIIN
98 RXIIN
99 N.C.
100 V
0
1
2
3
4
5
6
7
SS
0.031"
± 0.005"
Note: I.C. denotes Internal Connection. Do not use for vias.
––––––––––––––––––––––––––––––––––––––––––––––––––––
STEL-2000A 4
GENERAL DESCRIPTION
The STEL-2000A is a programmable single-chip
spread spectrum transceiver. The device performs all
the digital processing required to implement a fast
acquisition direct sequence (i.e., pseudonoise- or PNmodulated) spread spectrum full- or half-duplex sys-
tem using differentially encoded BPSK, QPSK, or π/4
QPSK. A block diagram of the STEL-2000A is shown
in Figure 1, while the package style and pin configuration are shown in Figure 2. The STEL-2000A is
available in two speed grades; the STEL-2000A+20
(20 MHz maximum clock frequency), and the
STEL-2000A+45 (45.056 MHz maximum clock frequency). The 45 MHz version features a high thermal
conductivity package for superior heat dissipation,
allowing the device to operate continuously at this
speed.
The STEL-2000A integrates the capabilities of a digital
downconverter, PN matched filter, and DPSK
demodulator into a single receiver, where the receiver
input is the analog-to-digital converted I.F. signal.
STEL-2000A transmit functions include a differential
BPSK/QPSK encoder, PN modulator (spreader), and
BPSK/QPSK modulator, where the transmitter
output is a sampled digitally modulated signal ready
for external digital-to-analog conversion (or, if
preferred, the spread baseband signal may be output
to an external modulator). These transceiver
functions have been designed and integrated for the
transmission and reception of bursts of spread data.
In particular, the PN Matched Filter has two distinct
PN coefficient registers (rather than a single one) in
order to speed and improve signal acquisition
performance. The STEL-2000A is thus optimized to
provide reliable, high-speed wireless data
communications.
The STEL-2000A operates with symbol-synchronous
PN modulation in both transmit and receive modes.
Symbol-synchronous PN modulation refers to operation where the PN code is aligned with the symbol
transitions and repeats once per symbol. By synchronizing a full PN code cycle over a symbol duration,
acquisition of the PN code at the receiver simultaneously provides symbol synchronization, thereby significantly improving overall acquisition time.
The receiver clock rate (RXIFCLK frequency) must
be at least four times the receive PN spreading rate
and is limited to a maximum speed of 45.056 MHz
(STEL-2000A+45 only, 20 MHz in the STEL2000A+20). As a result, the maximum supported PN
chip rate is 11.264 Mchips/second (5 Mcps in the
STEL-2000A+20), where a ÒchipÓ is a single ÒbitÓ of
the PN code. Since PN modulation is symbol-synchronous in the STEL-2000A, the data rate is defined
by the PN chip rate and length of the PN code; i.e., by
the number of chips per symbol. When operating
with BPSK modulation, the maximum data rate for a
PN code of length N is 11.264/N Mbps
(STEL2000A+45 only, 5/N Mbps in the STEL2000A+20). When operating with QPSK modulation
(or π/4 QPSK with an external modulator), two bits of
data are transmitted per symbol, and the maximum
data rate for a PN code of length N is 22.528/N Mbps
(STEL-2000A+45 only, 10/N Mbps in the STEL2000A+20). Conversely, for a given data rate Rb, the
length N of the PN code employed must be such that
the product of N x Rb is less than 11.264 (for BPSK) or
22.528 (for QPSK) Mcps (STEL-2000A+45 only).
The data rate (Rb) and the PN code length (N), however, cannot generally be arbitrarily chosen. United
States FCC Part 15.247 regulations require a minimum
processing gain of 10 dB for unlicensed operation in
the Industrial, Scientific, and Medical (ISM) bands,
implying that the value of N must be at least 10. To
implement such a short code, a Barker code of length
11 would typically be used in order to obtain desirable auto- and cross-correlation properties. With the
STEL-2000A, a PN code length of 11 implies that the
maximum data rate supported by the STEL-2000A in
compliance with FCC regulations is 2.048 Mbps using
differential QPSK (STEL-2000A+45 only). The STEL2000A further includes transmit and receive code
overlay generators to insure that signals spread with
such a short PN code length possess the spectral
properties required by FCC regulations.
The STEL-2000A receiver circuitry employs an NCO
and complex multiplier referenced to RXIFCLK to
perform frequency downconversion, where the input
I.F. sampling rate and the clock rate of RXIFCLK
must be identical. In Òcomplex inputÓ or Quadrature
Sampling Mode, external dual analog-to-digital converters (ADCs) sample quadrature I.F. signals so that
the STEL-2000A can perform true full single sideband
downconversion directly from I.F. to baseband. At
PN chip rates less than one-eighth the value of
RXIFCLK, downconversion may also be effected
using a single ADC in Òreal inputÓ or Direct I.F.
Sampling Mode, as discussed in Appendix I.
The input I.F. frequency is not limited by the capabilities of the STEL-2000A. To avoid destructive aliasing,
the NCO should not be programmed above 50% of
the I.F. sampling rate (the frequency of RXIFCLK);
moreover, the signal bandwidth, NCO frequency, and
––––––––––––––––––––––––––––––––––––––––––––––––––––
5 STEL-2000A
I.F. sampling rate are all interrelated, as discussed in
AppendixÊI. Higher I.F. frequencies, however, can be
supported by programming the NCO to operate on
in-band aliases as generated by the sampling process.
For example, a spread signal presented to the STEL2000AÕs receiver ADCs at an I.F. frequency of f
where f
allowed by the signalÕs bandwidth, be supported by
programming the STEL-2000AÕs NCO to a frequency
of (f
- f
I.F.
product specification. The maximum I.F. frequency is
then limited by the track-and-hold capabilities of the
ADC(s) selected. Signals at I.F. frequencies up to
about 100 MHz can be processed by currently available 8-bit ADCs, but the implementation cost as well
as the performance can typically be improved by
using an I.F. frequency of 30 MHz or lower. Downconversion to baseband is then accomplished digitally
by the STEL-2000A, with a programmable loop filter
provided to establish a frequency tracking loop
The STEL-2000A is designed to operate in either burst
or continuous mode: in burst mode, built-in symbol
counters allow bursts of up to 65,533 symbols to be
automatically transmitted or received, while, in continuous mode, the data is simply treated as a burst of
infinite length. The STEL-2000AÕs use of a digital PN
Matched Filter for code detection and despreading
permits signal and symbol timing acquisition in just
one symbol. The fast acquisition properties of this
design are exploited by preceding each data burst
with a single Acquisition/Preamble symbol, allowing
different PN codes (at the same PN chip rate) to independently spread the Acquisition/Preamble and data
symbols. In this way, a long PN code with high processing gain can be used for the Acquisition/Preamble symbol to maximize the probability of
burst detection, and a shorter PN code can be used
thereafter to permit a higher data rate.
To improve performance in the presence of high noise
and interference levels, the STEL-2000A receiverÕs
symbol timing recovery circuit incorporates a
Òflywheel circuitÓ to maximize the probability of correct symbol timing. This circuit will insert a symbol
RXIFCLK
RXIFCLK
< f
< 2 x f
I.F.
), as discussed in Appendix I of this
, can generally, as
RXIFCLK
I.F.
clock pulse if the correlation peak obtained by the PN
Matched Filter fails to exceed the programmed detect
threshold at the expected time during a given symbol.
During each burst, a missed detect counter tallies
each such event to monitor performance and allow a
,
burst to be aborted in the presence of abnormally high
interference. A timing gate circuit further minimizes
the probability of false correlation peak detection and
consequent false symbol clock generation due to noise
or interference.
To minimize power consumption, individual sections
of the device can be turned off when not in use. For
example, the receiver circuitry can be turned off during transmission and, conversely, the transmitter circuitry can be turned off during reception when the
STEL-2000A is operating in a half-duplex/time division duplex (TDD) system. If the NCO is not being
used as the BPSK/QPSK modulator (i.e., if an external
modulator is being used), the NCO can also be turned
off during transmission to conserve still more power.
The fast acquisition characteristics of the STEL-2000A
make it ideal for use in applications where bursts are
transmitted relatively infrequently. In such cases, the
device can be controlled so that it is in full ÒsleepÓ
mode with all receiver, transmitter, and NCO functions turned off over the majority of the burst cycle,
thereby significantly reducing the aggregate power
consumption. Since the multiply operations of the
PN Matched Filter consume a major part of the
overall power required during receiver operation,
two independent power-saving techniques are also
built into the PN Matched Filter to reduce
consumption during operation by a significant factor
for both short and long PN spreading codes.
The above features make the STEL-2000A an
extremely versatile and useful device for spread spectrum data communications. Operating at its highest
rates, the STEL-2000A is suitable for use in wireless
Local Area Network implementations, while its programmability allows it to be used in a variety of data
acquisition, telemetry, and transaction system
applications.
––––––––––––––––––––––––––––––––––––––––––––––––––––
STEL-2000A 6
FUNCTIONAL BLOCKS
Transmit and Receive Clock Generators
Timing in the transmitter and receiver sections of the
STEL-2000A is controlled by the Transmit and
Receive Clock Generator Blocks. These blocks are
programmable dividers providing signals at the chip
and symbol rates (as well as at multiples and submultiples of these frequencies) as programmed
through the STEL-2000AÕs control registers. If
desired, the complete independence of the transmitter
and receiver sections allows the transmit and receive
clocks to be mutually asynchronous. Additionally,
the STEL-2000A allows external signals to be
provided as references for the transmit (TXMCHP)
and receive (RXMSMPL) chip rates. Given the
transmit PN chip rate, the PN-synchronous transmit
symbol rate is then derived from the programmed
number of PN chips per transmit symbol. At the
receiver, symbol synchronization and the receive
symbol rate are determined from processing of the
PN matched filter output, or, if desired, can be
provided from the programmed number of PN chips
per receive symbol or an external symbol sync
symbol, RXMDET. Burst control is achieved by
means of the transmit and receive Symbols per Burst
counters. These programmable 16-bit counters allow
the STEL-2000A to operate automatically in burst
mode, stopping at the end of each burst without the
need of any external counters.
Input and Output Processors
When the transmitter and receiver are operating in
QPSK mode, the data to be transmitted and the
received data are processed in pairs of bits (dibits),
one bit for the in-phase (I) channel and one for the
quadrature (Q) channel. Dibits are transmitted and
received as single differentially encoded QPSK symbols. Single-bit I/O data is converted to and from this
format by the Input and Output Processors, accepting
TXIN as the serial data to be transmitted and producing RXOUT as the serial data output. If desired, the
received data is also available at the RXIOUT and
RXQOUT pins in (I and Q) dibit format prior to dibitto-serial conversion. While receive timing is derived
by the STEL-2000A Symbol Tracking Processor,
transmit timing is provided by the Input Processor.
In BPSK mode, the Input Processor will generate the
TXBITPLS signal once per symbol to request each bit
of data, while in QPSK mode it will generate the
TXBITPLS signal twice per symbol to request the two
bits of data corresponding to each QPSK symbol.
Differential Encoder
Data to be transmitted is differentially encoded before
being spread by the transmit PN code. Differential
encoding of the signal is fundamental to operation of
the STEL-2000AÕs receiver: the STEL-2000AÕs DPSK
Demodulator computes ÒdotÓ and ÒcrossÓ product
functions of the current and previous symbolsÕ downconverted I and Q signal components in order to perform differential decoding as an intrinsic part of
DPSK demodulation.
The differential encoding scheme depends on
whether the modulation format is to be BPSK or
QPSK. For DBPSK, the encoding algorithm is
straightforward: output bit(k) equals input bit(k) ⊕
output bit(kÐ1), where ⊕ represents the logical XOR
function. For DQPSK, however, the differential
encoding algorithm, as shown in Table 1, is more
complex since there are now sixteen possible new
states depending on the four possible previous output
states and four possible new input states.
New Input Previously Encoded OUT(I, Q)
IN(I, Q)
Table 1. QPSK Differential Encoder Sequence
k
00 00 01 11 10
01 01 11 10 00
11 11 10 00 01
10 10 00 01 11
00 01 11 10
Newly Encoded OUT(I, Q)
kÐ1
k
Transmitter PN Code Generation
When the STEL-2000A is used for burst signal operation, each burst is preceded by an Acquisition/Preamble symbol to facilitate acquisition. This
Acquisition/Preamble symbol is automatically generated by the STEL-2000AÕs transmitter before information data symbols are accepted for transmission. Two
separate and independent PN codes may be
employed: one for spreading the Acquisition/Preamble symbol, and one for the subsequent
information data symbols. As a result, a much higher
processing gain may be used for signal acquisition
than for signal tracking in order to improve burst
acquisition performance.
The Transmitter Acquisition/Preamble and Transmitter Data Symbol PN code lengths are completely
independent of each other and can be up to 64 chips
long. Transmit PN codes are programmed in the
STEL-2000A as binary code values. The number of
Transmitter Chips per Acquisition/Preamble Symbol
is set by the value stored in bits 5-0 of address 43
and the Transmitter Acquisition/Preamble Symbol
Code coefficient values are stored in addresses 44
4B
. The number of Transmitter Chips per Data
H
H
to
H
––––––––––––––––––––––––––––––––––––––––––––––––––––
7 STEL-2000A
,
Symbol is set by the data stored in address 42H, and
the Transmitter Data Symbol Code coefficient values
are stored in addresses 4C
A rising edge of the MTXEN input or of bit 1 of
address 37
transmit sequence by transmitting a single symbol
using the Acquisition/Preamble PN code. The completion of transmission of the Acquisition/Preamble
symbol is indicated with TXACQPLS, while the
ongoing transmission of data symbols is signaled
with TXTRKPLS. Data bits to be transmitted after
the Acquisition/Preamble symbol are requested with
TXBITPLS, where a single pulse per symbol requests
data in BPSK mode and two pulses per symbol
request data in QPSK mode. The user data symbols
are then PN modulated using the Transmitter Data
Symbol PN code.
The PN spreading codes are XORed with the data bits
(in BPSK mode) or bit pairs (in QPSK mode) to
transmit one complete code sequence for every
Acquisition/Preamble and data symbol at all times.
The resulting spread I and Q channel signals are
brought out as the TXIOUT and TXQOUT signals for
use by an external modulator and are also fed into the
STEL-2000A's internal modulator. In BPSK mode,
only TXIOUT is used by the STEL-2000AÕs modula-
tor. If an external QPSK modulator is used, the
carrier should be modulated as shown in Table 2 to be
compatible with the STEL-2000A receiver.
I, Q Bits Signal Quadrant Quadrant diagram
0 0 First
1 0 Second 2nd. 1st.
1 1 Third 3rd. 4th.
0 1 Fourth
Table 2. QPSK Differential Encoder Sequence
causes the STEL-2000A to begin the
H
to 53H.
H
BPSK/QPSK Modulator
The STEL-2000A incorporates an on-chip
BPSK/QPSK modulator which modulates the
encoded and spread transmit signal with the sine and
cosine outputs of the STEL-2000AÕs NCO to generate
a digitized I.F. output signal, TXIFOUT
NCO operates at a rate defined by RXIFCLK, the
BPSK/QPSK modulator output is also generated at
this sampling rate, and, consequently, TXIFCLK must
be held common with RXIFCLK to operate the STEL2000AÕs BPSK/QPSK Modulator. The digital
modulator output signal can then be fed into an
external 8-bit DAC (operating at RXIFCLK) to
generate an analog I.F. transmit signal, where the
chosen I.F. is the STEL-2000A's programmed NCO
frequency or one of its aliases with respect to the
. Since the
7-0
output sampling rate, RXIFCLK. Note that the
maximum frequency of TXIFCLK is specified at 20
MHz when the internal modulator is being used for
both the 20 and 45 MHz versions of the STEL-2000A.
For operation at higher frequencies than this an
external BPSK or QPSK modulator should be used in
conjunction with the TXIOUT and TXQOUT signals.
When the STEL-2000A is set to transmit in BPSK
mode (by setting bitÊ0 of address 40
signals are applied to both the I and Q channels of the
modulator so that the modulated output signal occupies only the first and third quadrants of the signal
space defined in Table 2. Note that the modulator
itself cannot generate π/4 QPSK signals, but the
STEL-2000A can receive such signals and can be used
with an external modulator for their transmission.
high), identical
H
Frequency Control Register and NCO
The STEL-2000A incorporates a Numerically Controlled Oscillator (NCO) to synthesize a local oscillator signal for both the transmitter's modulator and
receiver's downconverter. The NCO is clocked by the
master receiver clock signal, RXIFCLK, and generates
quadrature outputs with 32-bit frequency resolution.
The NCO frequency is controlled by the value stored
in the 32-bit Frequency Control Register, occupying 4
bytes at addresses 03H to 06
in-band aliasing, the NCO should not be programmed
to be greater than 50% of RXIFCLK. As desired by
the user, the output of the STEL-2000A receiverÕs
Loop Filter can then be added or subtracted to adjust
the NCO's frequency control word and create a
closed-loop frequency tracking loop. If the receiver is
disabled, either manually or automatically at the end
of a burst, the Loop Filter output correcting the
NCOÕs Frequency Control Word is disabled. When
operating the transmitter and receiver simultaneously, however, the receiverÕs frequency tracking loop
affects the NCO signals to both the receive and
transmit sides; this can either be used to advantage or
must be compensated for in the system design.
. To avoid destructive
H
Downconverter
The STEL-2000A incorporates a Quadrature (Single
Sideband) Downconverter which digitally downconverts the sampled and digitized receive I.F. signal to
baseband. Use of the Loop Filter and the NCO's builtin frequency tracking loop permits the received signal
to be accurately downconverted to baseband.
The Downconverter includes a complex multiplier in
which the 8-bit receiver input signal is multiplied by
the sine and cosine signals generated by the NCO. In
Quadrature Sampling Mode, two ADCs provide
quadrature (complex) inputs I
Direct I.F. Sampling Mode, a single ADC provides I
as a real input. The input signals can be accepted in
and QIN, while, in
IN
IN
––––––––––––––––––––––––––––––––––––––––––––––––––––
STEL-2000A 8
either twoÕs complement or offset binary formats
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
AAAAAAAAAAAAA
according to the setting of bit 3 of address 01
H
. In
Direct I.F. Sampling Mode, the unused RXQIN Q
channel input (Q
) should be held to ÒzeroÓ accord-
IN
ing to the ADC input format selected. The outputs of
the DownconverterÕs complex multiplier are then:
I
= I
OUT
Q
OUT
where ω = 2πf
. cos(ωt) Ð QIN . sin(ωt)
IN
= I
. sin(ωt) + QIN . cos(ωt)
IN
NCO
These outputs are fed into the I and Q channel Integrate and Dump Filters. The Integrate and Dump Filters allow the samples from the complex multiplier (at
the I.F. sampling rate, the frequency of RXIFCLK) to
be integrated over a number of sample periods. The
dump rate of these filters (the baseband sampling
rate) can be controlled either by an internally generated dump clock or by an external input signal
(RXMSMPL) according to the setting of bit 0 of
address 01
. Note that, while the receiver will extract
H
exact PN and symbol timing information from the
received signal, the baseband sampling rate must be
Receiver PN Code Register and PN Matched Filter
FEP BLOCK
3
INI
AQU.-PRE./DATA
COEF. SEL.
FEP BLOCK
3
INQ
T
T
2T 2T 2T 2T 2T
SEL
M
P
M
D
2T 2T 2T 2T 2T
M
M
TAP1 TAP2TAP0 TAP63TAP64
SEL
P
D
SEL
M
P
M
D
twice the nominal PN chip rate for proper receiver
operation and less than or equal to one-half the frequency of RXIFCLK. If twice the PN chip rate is a
convenient integer sub-multiple of RXIFCLK, then an
internal clock can be derived by frequency dividing
RXIFCLK according to the divisor stored in bits 5-0 of
address 02
pling clock provided by RXMSMPL must be used.
The I.F. sampling rate, the baseband sampling rate,
and the input signal levels determine the magnitudes
of the Integrate and Dump FiltersÕ accumulator outputs, and a programmable viewport is provided at
the outputs of the Integrate and Dump Filters to select
the appropriate output bits as the 3-bit inputs to the
PN Matched Filter. The viewport circuitry here and
elsewhere within the STEL-2000AÕs receiver is
designed with saturation protection so that extreme
values above or below the selected range are limited
to the correct maximum or minimum value for the
selected viewport range. The viewports for the I and
Q channels of the Integrate and Dump Filters are controlled by the values stored in bits 7-4 of address 01
I DELAY
REGI STER BLOCK
I MULTIPLIER
A R R AY BLOCK
COEFFICI ENT
MEMORY A ND
REGI STER BLOCK
Q MU LTIPLIER
A R R AY BLOCK
Q DELA Y
REGI STER BLOCK
; otherwise, an external baseband sam-
H
TAP62
+
I ADDER
+
+
+
Σ
+
+
+
SEL
SEL
M
P
M
D
SEL
M
P
M
D
Q A DDER
+
+
+
+
Σ
+
+
+
.
H
As discussed for the STEL-2000A transmitter, the
STEL-2000A is designed for burst signal operation in
which each burst begins with a single Acquisition/Preamble symbol and is then followed by data
––––––––––––––––––––––––––––––––––––––––––––––––––––
POST PROC ESSOR BLOCK
ABS
ABS
MAGNITUDE
GENERATOR
THRESHOLD
REGISTERS
Figure 3. Matched Filter Detail
symbols for information transmittal. Complementing
operation of the STEL-2000AÕs transmitter, two separate and independent PN codes may be employed in
the receiverÕs PN Matched Filter, one for despreading
9 STEL-2000A
10
10
10
COMP-
ARATOR
VIEWPORT
AND SAT.
(OUTPUT
CONTROL)
8
SUMI
8
MAG
8
SUMQ
DET
the Acquisition/Preamble symbol, and one for the
information data symbols. The code lengths are
completely independent of each other and can be each
up to 64 chips long. A block diagram of the PN
Matched Filter is shown in Figure 3.
The STEL-2000A contains a fully programmable 64tap complex (i.e., I and Q channel) PN Matched Filter
with coefficients which can be set to ±1 or zero
according to the contents of either the Acquisition/Preamble or Data Symbol Code Coefficient Registers. By setting the coefficients of the end taps of the
filter to zero, the effective length of the filter can be
reduced for use with PN codes shorter than 64 bits.
Power consumption may also be reduced by turning
off those blocks of 7 taps for which all the coefficients
are zero, using bits 6-0 of address 39
. Each ternary
H
coefficient is stored as a 2-bit number, so that a PN
code of length N is stored as N 2-bit non-zero PN
coefficients. Note that, as a convention, throughout
this document the first PN Matched Filter tap encountered by the signal as it enters the I and Q channel
tapped delay lines is referred to as ÒTap 0.Ó Tap 63 is
then the last tap of the PN Matched Filter.
The start of each burst is expected to be a single symbol PN-spread by the Acquisition/Preamble code.
The receiver section of the STEL-2000A is automatically configured into acquisition mode so that the
Matched Filter Acquisition/Preamble Coefficients
stored in addresses 07
to 16H are used to despread
H
the received signal. Provided that this symbol is successfully detected, the receiver will automatically
switch from acquisition mode, and the Matched Filter
Data Symbol Coefficients stored in addresses 17
26
will then be used to despread subsequent
H
to
H
symbols.
To allow the system to sample the incoming signal
asynchronously (at the I.F. sampling rate) with
respect to the PN spreading rate, the PN Matched Filter is designed to operate with two signal samples (at
the baseband sampling rate) per chip. A front end
processor (FEP) operating on both the I and Q channels averages the incoming data over each chip
period by adding each incoming baseband sample to
the previous one:
stored PN code coefficients at the baseband sampling
rate; i.e., twice per chip. The 3-bit signals from each
tap in the PN Matched Filter are multiplied by the
corresponding coefficient in two parallel tapped delay
lines. Each delay line consists of 64 multipliers which
multiply the delayed 3-bit signals by zero or ±1
according to the value of the tap coefficient. The
products from the I and Q tapped delay lines are
added together in the I and Q Adders to form the
sums of the products, representing the complex crosscorrelation factor. The correlation I and Q outputs are
thus:
n = 63
Output
= Σ Data
(I, Q)
* Coefficient
n(I, Q)
n(I, Q)
n = 0
These I and Q channel PN Matched Filter outputs are
10-bit signals, with I and Q channel programmable
viewports provided to select the appropriate output
bits as the 8-bit inputs to the Power Detector and
DPSK Demodulator blocks. Both I and Q channel
viewports are jointly controlled by the data stored in
bits 1-0 of address 28
and are saturation protected.
H
Two power saving methods are used in the PN
Matched Filter of the STEL-2000A. As discussed previously, the first method allows power to be shut off
in the unused taps of the PN Matched Filter when the
filter length is configured to be less than 64 taps. The
second method is a proprietary technique that
(transparently to the user) shuts down the entire PN
Matched Filter during portions of each symbol
period.
Power Detector
The complex output of the PN Matched Filter is fed
into a Power Detector which, for every cycle of the
internal baseband sampling clock, computes the magnitude of the vector of the I and Q channel correlation
sums,
imated as
Max{Abs(I),Abs(Q)} +
This 10-bit value represents the power level of the
correlated signal during each chip period and is used
in the Symbol Tracking Processor.
I2(k)+Q2(k) , where the magnitude is approx-
1/
Min{Abs(I), Abs(Q)}.
2
i.e., FEP
After the addition, the output of the FEP is rounded
to a 3-bit offset 2Õs complement word with an
effective range of ±3.5. such that the rounding process
does not introduce any bias to the data. The FEP can
be disabled by setting bit 0 of address 27
for normal operation the FEP should be enabled.
The PN Matched Filter computes the cross-correlation
between the I and Q channel signals and the locally
= FEPIN (1 + zÐ1)
OUT
to a 1, but
H
Symbol Tracking Processor
The output of the Power Detector Block represents the
signal power during each chip period. Ideally, this
output will have a high peak value once per symbol
(i.e., once per PN code cycle) when the code sequence
of the received signal in the PN Matched Filter is the
same as (and is aligned in time with) the reference PN
code used in the PN Matched Filter. At that instant,
the I and Q channel outputs of the PN Matched Filter
––––––––––––––––––––––––––––––––––––––––––––––––––––
STEL-2000A 10
are, theoretically, the optimally despread I and Q
symbols.
To detect this maximum correlation in each symbol
period, the signal power value is compared against a
10-bit user-programmable threshold value. A symbol
clock pulse is generated each time the power value
exceeds the threshold value to indicate a symbol
detect. Since the Acquisition/Preamble symbol and
subsequent data symbols can have different PN codes
with different peak correlation values (which depend
on the PN code length and code properties), the
STEL-2000A is equipped with two separate threshold
registers to store the Acquisition/Preamble Threshold
value (stored in addresses 29
Symbol Threshold value (stored in addresses 2B
2C
). The device will automatically use the appro-
H
and 2AH) and the Data
H
H
and
priate value depending on whether it is in acquisition
mode or not.
Since spread spectrum receivers are frequently
designed to operate under extremely adverse signalto-noise ratio conditions, the STEL-2000A is equipped
with a Òflywheel circuitÓ to enhance the operation of
the symbol tracking function by introducing memory
to the PN Matched Filter operation. This circuit is
designed to ignore false detects at inappropriate times
in each symbol period and to insert a symbol clock
pulse at the appropriate time if the symbol detection
is missed. The flywheel circuit operates by its a priori
knowledge of when the next detect pulse is expected.
The expected pulse will occur one symbol period after
the last correctly detected one, and a window of ±1
baseband sample time is therefore used to gate the
detect pulse. Any detects generated outside this time
window are ignored, while a symbol detect pulse will
be inserted into the symbol clock stream if the power
level does not exceed the threshold within the window, corresponding to a missed detect. An inserted
symbol detect signal will be generated precisely one
symbol after the last valid detect, the nominal symbol
length being determined by the value of Rx Chips Per
Data Symbol stored in address 2D
.
H
The cross-correlation characteristics of a noisy
received signal with the noise-free local PN code used
in the STEL-2000AÕs PN Matched Filter may result in
ÒsmearingÓ of the peak power value over adjacent
chip periods. Such smearing can result in two or
three consecutive power values (typically, the on-time
and one-sample early and late values) exceeding the
threshold. A maximum power selector circuit is
incorporated in the STEL-2000A to choose the highest
of any three consecutive power levels each time this
occurs, thereby enhancing the probability that the
optimum symbol timing will be chosen in such cases.
If desired, this function can be disabled by setting bit
3 of address 30
high.
H
The STEL-2000A also includes a circuit to keep track
of missed detects; i.e., those cases where no peak
power level exceeds the set threshold. An excessively
high rate of missed detects is an indication of poor
signal quality and can be used to abort the reception
of a burst of data. The number of symbols expected
in each receive burst, up to a maximum of 65,533, is
stored in addresses 2E
and 30H. A counter is used to
H
count the number of missed detects in each burst, and
the system can be configured to automatically abort a
burst and return to acquisition mode if this number
exceeds the Missed Detects per Burst Threshold value
stored in address 2F
. Under normal operating con-
H
ditions, the STEL-2000A will automatically return to
acquisition mode when the number of symbols processed in the burst is equal to the value of the data
stored in address 2E
and 30H. To permit the pro-
H
cessing of longer bursts or continuous data, this function can be disabled by setting bit 6 of address 30
high.
Differential Demodulator
Both DPSK demodulation and carrier discrimination
are supported in the STEL-2000A receiver by the calculation of ÒdotÓ and ÒcrossÓ products using the
despread I and Q channel information generated by
the PN Matched Filter for the current and previous
symbols. A block diagram of the DPSK DemodulatorÕs I and Q channel processing is shown in Figure 4.
Let I
and Qk represent the I and Q channel outputs,
k
respectively, for the k
products can then be defined as:
Dot(k) = I
Cross(k) = Qk I
Examination of these products in the complex plane
reveals that the dot and cross products are the real
and imaginary results, respectively, of complex multiplication of the current and previous symbols. The
dot product alone thus allows determination of the
phase shift between successive BPSK symbols, while
the dot and cross products together allow
k Ik-1
th
symbol. The dot and cross
+ Qk Q
- Ik Q
k-1
k-1
k-1
; and,
.
H
––––––––––––––––––––––––––––––––––––––––––––––––––––
11 STEL-2000A
I
8
I
k
+
17
I
k – 1
SYMBOL
ROTATOR
1 + j X
X = 0, +1, -1
8
Q
Ø = 0, +45°, -45°
T DELAY
Q
k – 1
Q
k
Figure 4. Differential Demodulator Detail
Σ
–
Σ
+
DOT(k) = Ik . I
+
17
CROSS(k) = Qk . I
k – 1
+ Qk . Q
k – 1
– Ik . Q
k – 1
k – 1
determination of the integer number of π/2 phase
shifts between successive QPSK symbols. Differential
encoding of the source data implies that an absolute
phase reference is not required, and thus knowledge
of the phase shift between successive symbols derived
from the dot and cross products unambiguously
permits correct demodulation.
Implementation of this approach is simplified if the
polarities (i.e., the signs) alone of the dot and cross
products provide the information required to make
the correct symbol decision. For BPSK and π/4 QPSK
signals, no modifications are needed: in BPSK, the
sign of the dot product fully captures the signal con-
stellation, while, in π/4 QPSK, the signal constellation
intrinsically includes the phase rotation needed to
align the decision boundaries with the four possible
combinations of the dot and cross product polarities.
Frequency Discriminator and Loop Filter
DOT
–
SIGN
SIGN
QPSK
Σ
+
MUX
17
For QPSK signals, a fixed phase rotation of π/4 (45°)
is introduced in the DPSK Demodulator to the previous symbol to simplify the decision algorithm. Rotation of the previous symbol is controlled by the settings of bits 0 and 1 of address 33
,allowing the pre-
H
vious symbol to be rotated by 0° or ±45°. As noted,
for BPSK or π/4 QPSK signals, a rotation of 0° should
be programmed, but, for QPSK signals, a Ð45° signal
rotation must be programmed to optimize the constellation boundaries in the comparison process between
successive symbols. Note also that introduction of a
±45° rotation introduces a scaling factor of
1
/√2 to the
signal level in the system as discussed in Appendix I,
where this factor should be taken into account when
calculating optimum signal levels and viewport settings after the DPSK Demodulator.
K2
8
29 32
Σ
K1
29
÷4
Σ
31
AFC
VIEWPORT
C O NTROL
4
VIEW-
PORT
CROSS
BPSK
BPSK/
QPSK
SELECT
FRZ.
LF
INV.
LF
REG.
Σ
FCW
TO
NC O
Figure 5. Frequency Discriminator and Loop Filter Detail
––––––––––––––––––––––––––––––––––––––––––––––––––––
STEL-2000A 12
The Frequency Discriminator uses the dot and cross
products discussed above to generate the AFC signal
for the frequency acquisition and tracking loop, as
illustrated in Figure 5. The specific algorithm used
depends on the signal modulation type and is controlled by the setting of bit 2 of address 33
. When
H
bit 2 is set low, the Frequency Discriminator circuit is
in BPSK mode and the following algorithm is used to
compute the Frequency Discriminator (FD) function:
FD
= Cross x Sign[Dot],
where Sign[Dot] represents the polarity of the argument. When bit 2 is set high, the discriminator circuitry is in QPSK mode and the carrier discriminator
function is instead calculated as:
FD
= (Cross x Sign[Dot]) Ð (Dot x Sign[Cross]).
In both cases, the Frequency Discriminator function
provides an error signal that reflects the change in
phase between successive symbols. With the symbol
period known, the error signal can equivalently be
seen as a frequency error signal. As a practical matter, the computation of the Frequency Discriminator
function results in a 17-bit signal, and a programmable saturation protected viewport is provided
to select the desired output bits as the 8-bit input to
the Loop Filter Block. The viewport is controlled by
the value stored in bits 7-4 of address 33
.
H
The Loop Filter is implemented with a direct gain
(K1) path and an integrated or accumulated (K2) path
to filter the Frequency Discriminator error signal and
correct the frequency tracking of the Downconverter.
The order of the Loop Filter transfer function can be
set by enabling or disabling the K1 and K2 paths, and
the coefficient values can be adjusted in powers of 2
0
from 2
The factor of
21
to 2
The Loop Filter transfer function is:
.
Transfer Fn. = K1 +
1
/4 results from truncation of the 2 LSBs
1
/4 K2
z
1ÊÐÊz
Ð1
Ð1
of the signal in the integrator path of the loop so that,
when added to the signal in the direct path, the LSBs
of the signals are aligned. The coefficients K1 and K2
are defined by the data stored in bits 4-0 of addresses
35
and 34H, respectively. In addition, bit 5 of
H
addresses 35
and 34H control whether the K1 and K2
H
paths, respectively, are enabled. These parameters
thus give the user full control of the Loop Filter
characteristics.
––––––––––––––––––––––––––––––––––––––––––––––––––––
13 STEL-2000A
INPUT SIGNALS
RXIIN
(Pins 91-98)
7-0
Receiver In-Phase Input. RXIIN is an 8-bit input port
for in-phase data from external A/D converters. Data
may be received in either two's complement or offset
binary format as selected by bit 3 of address 01
. The
H
sampling rate of the RXIIN signals (the I.F. sampling
rate of the A/Ds) may be independent of the baseband sampling rate (the Downconverter integrate and
dump rate) and the PN chip rate, but must be equal to
RXIFCLK and at least two times greater than the
baseband sampling rate. Since the baseband sampling rate must be set at twice the PN chip rate, the
I.F. sampling rate must thus be at least four times the
PN chip rate. Data on the pins is latched and processed by RXIFCLK.
RXQIN
(Pins 2-9)
7-0
Receiver Quadrature-Phase Input. RXQIN is an 8bit input port for quadrature-phase data from
external A/D converters. Data may be received in
either two's complement or offset binary format as
selected by bit 3 of address 01
. As with RXIIN, the
H
sampling rate of the RXQIN signals may be
independent of the baseband sampling and PN chip
rates in the receiver, but must be at least two times
greater than the baseband sample rate (or, equivalently, at least four times greater than the PN chip
rate). Data on the pins is latched and processed by
RXIFCLK.
Note that if the STEL-2000A is to be used in Direct I.F.
Sampling Mode, then the I.F. signal should be input
to the RXIIN input port only. RXQIN must then be
held to arithmetic zero according to the chosen ADC
format as selected by bit 3 of address 01
. In other
H
words, to support Direct I.F. Sampling, RXQIN must
be tied to a value of 7F
format has been selected or to a value of 00
or 80H if offset binary input
H
if twoÕs
H
complement input format has been selected.
RXMSMPL (Pin 84)
Receiver Manual Sample Clock. RXMSMPL enables
the user to externally generate (independent of the I.F.
sampling clock, RXIFCLK) the baseband sampling
clock used for all processing after the digital downconverter, including the dump rate of the Integrate
and Dump filters. This feature is useful in cases
where a specific baseband sample rate is required that
may not be derived by the internal sample rate timing
generator which generates clock signals at integer
sub-multiples of RXIFCLK. The signal is internally
synchronized to RXIFCLK to avoid intrinsic race or
hazard timing conditions. There must be at least two
cycles of RXIFCLK to every cycle of RXMSMPL, and
RXMSMPL should be set to twice the nominal receive
PN chip rate.
When bit 0 of address 01
is set high, a rising edge on
H
RXMSMPL will initiate a baseband sampling clock
pulse to the Integrate and Dump filters and subsequent circuitry (e.g., PN Matched Filter, DPSK
Demodulator, Power Estimator, etc.). The rising edge
of RXMSMPL is synchronized internally so that, on
the second rising edge of RXIFCLK that follows the
rising edge of RXMSMPL, a pulse is internally generated that clocks the circuitry that follows. On the
third rising RXIFCLK edge, the contents of the Integrate and Dump Filters of the Downconverter are
transferred to the PN Matched Filter. The extra one
RXIFCLK delay before transfer of the contents of the
filters enables the internally generated baseband sampling clock to be free of race conditions at the interface between the Downconverter and PN Matched
Filter.
RXMDET (Pin 88)
Receiver Manual Detect. RXMDET enables the user
to externally generate symbol timing, bypassing and
overriding the internal symbol power estimation and
tracking circuitry. This function may be useful when
the dynamic characteristics of the transmission environment require unusual adjustments to the symbol
timing.
When bit 0 of address 30
Enable) and when bit 0 of address 31
is set high (Manual Detect
H
is set low, a
H
rising edge of RXMDET will generate a symbol correlation detect pulse. The function can also be performed by means of bit 0 of address 31
RXMDET input and bit 0 of address 31
are logically
H
H.
The
ORed together so that, when either one is held low, a
rising edge on the other triggers the manual detect
function. The rising edge of RXMDET is synchronized internally so that, on the second rising edge of
the baseband sampling clock that follows the rising
edge of RXMDET, the correlated outputs of the PN
Matched Filter I and Q channels will be transferred to
the DPSK demodulator.
RXMABRT (Pin 87)
Receiver Manual Abort. RXMABRT enables the user
to manually force the STEL-2000A to cease reception
of the current burst of data symbols and prepare for
acquisition of a new burst. This function can be used
to reset the receiver and prepare to receive a priority
transmission signal under precise timing control, giving the user the ability to control the status of the
receiver for reasons of priority, signal integrity, etc.
When bit 0 of address 32
is set low, a rising edge on
H
––––––––––––––––––––––––––––––––––––––––––––––––––––
STEL-2000A 14
RXMABRT will execute the abort function. The
function can also be performed under microprocessor
control by means of bit 0 of address 32
RXMABRT input and bit 0 of address 32
The
H.
are logi-
H
cally ORed together so that, when either one is held
low, a rising edge on the other triggers the abort function. The second rising edge of the baseband sampling clock that follows a rising edge of RXMABRT
will execute the abort and also clear the symbols-perburst, samples-per-symbol, and missed-detects-perburst counters. The counters will be reactivated on
the detection of the next burst preamble or by a manual detect signal.
RXIFCLK (Pin 12)
Receiver I.F. Clock. RXIFCLK is the master clock of
the NCO and all the receiver blocks. All clocks in the
receiver section and the NCO, internal or external, are
generated or synchronized internally to the rising
edge of RXIFCLK. The frequency of RXIFCLK must
be at least four times the PN chip rate of the received
signal. When bit 0 of address 01
is set low, the base-
H
band sampling clock, required to be at twice the nominal PN chip rate, will be derived from RXIFCLK
according to the setting of bits 5-0 of addressÊ02
.
H
MNCOEN (Pin 86)
Manual NCO Enable. MNCOEN allows the power
consumed by the operation of the NCO circuitry to be
minimized when the STEL-2000A is not receiving and
not transmitting data. The NCO can also be disabled
while the STEL-2000A is transmitting as long as the
STEL-2000A's on-chip BPSK/QPSK modulator is not
being used. With the instantaneous acquisition properties of the PN Matched Filter, it is often desirable to
shut down the receiver circuitry to reduce power consumption, resuming reception periodically until an
Acquisition/Preamble symbol is acquired. Setting
MNCOEN low will do this by holding the NCO in a
reset state. After MNCOEN has been set high again
to re-activate the NCO it will be necessary to reload
the frequency control word into the NCO. Note that
MNCOEN operates independently of MTXEN and
MRXEN, where those pins have similar control over
the transmit and receive circuitry, respectively.
MNCOEN performs the same function as bit 0 of
address 37
together to form the overall control function. When
this bit is set low, MNCOEN controls the activity of
the NCO circuitry; when MNCOEN is set low, bit 0 of
address 37
When either bit 0 or MNCOEN (whichever is in control, as defined above) goes low, a reset sequence
occurs on the following RXIFCLK cycle to effectively
disable all of the NCO circuitry, although the user
programmable control registers are not affected by
, and these two signals are logically ORed
H
controls the activity of the NCO circuitry.
H
this power down sequence. Upon reactivation (when
either MNCOEN or bit 0 of address 37
return high),
H
the NCO must be reloaded with frequency control
information either by means of the MFLD input or by
writing 01
H into address 00H.
MTXEN (Pin 17)
Manual Transmitter Enable. A rising edge on
MTXEN causes the transmit sequence to begin, where
the STEL-2000A first transmits a single Acquisition/Preamble symbol followed by data symbols.
MTXEN should be set low after the last symbol has
been transmitted. When MTXEN is set low, power
consumption of the transmitter circuit is minimized.
MTXEN operates independently of MRXEN and
MNCOEN, where these signals have similar control
over the receive and NCO circuitry, respectively.
MTXEN performs the same function as bit 1 of
address 37
. and these two signals are logically ORed
H
together to form the overall control function. When
bit 1 of address 37
is set low, MTXEN controls the
H
activity of the transmitter circuitry, and, when
MTXEN is set low, bit 1 of address 37
controls the
H
activity of the transmitter circuitry. A rising edge on
either MTXEN or bit 1 (whichever is in control, as
defined above) initiates a transmit sequence. A
falling edge initiates a reset sequence on the following
TXIFCLK cycle to disable all of the transmitter data
path, although the user programmable control registers are not affected by the power down sequence.
MRXEN (Pin 10)
Manual Receiver Enable. MRXEN allows power
consumption of the STEL-2000A receiver circuitry to
be minimized when the device is not receiving. With
the instantaneous acquisition properties of the PN
Matched Filter, it is often desirable to shut down the
receiver circuitry to reduce power consumption,
resuming reception periodically until an Acquisition/Preamble symbol is acquired. Setting MRXEN
low reduces the power consumption substantially.
When MRXEN is set high, the receiver will automati-
cally power up in acquisition mode regardless of its
prior state when it was powered down. MRXEN
operates independently of MTXEN and MNCOEN,
where these signals have similar control over the
transmit and NCO circuitry, respectively.
MRXEN performs the same function as bit 2 of
address 37
together to form the overall control function. When
bit 2 of address 37
activity of the receiver circuitry and, when MRXEN is
set low, bit 2 of address 37
the receiver circuitry. When either MRXEN or bit 2
(whichever is in control, as defined above) goes low, a
reset sequence begins on the following RXIFCLK
, and these two signals are logically ORed
H
is set low, MRXEN controls the
H
controls the activity of
H
––––––––––––––––––––––––––––––––––––––––––––––––––––
15 STEL-2000A
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