INTEL STEL-1209 User Manual

查询STEL-1209供应商

STEL-1209

Data Sheet

STEL-1209/CE

BPSK/QPSK/16 QAM

Burst Modulator Assembly

KEY FEATURES

n Evaluation tool for STEL-1109 digital

modulator ASICs

n Burst or continuous BPSK, QPSK, 16QAM

modulator at rates up to 10 Msps

n On-board or external clock capability

– Up to 165 MHz

n Up to 65 MHz output frequency n High frequency resolution

– 24 bits, 10 Hz @ 165 MHz

n Digitally filtered data results in low

modulation side lobes – Typically -52 dBc

n High spectral purity

– Typically -50 dBc

BLOCK DIAGRAM

µPROC.

Control I/F RS-232C

6 8

Reset

BURST MODE PARAMETERS:

n Default at burst QPSK modulation

– Data rate at 2.56 Mbps

n Programmable packet length

– 1 to 16,381 symbols of data

n Programmable guard time

– 2 to 16,382 symbols

n Programmable burst quantity

– 1 to 10 million and auto repeat

n Programmable preamble size

– 0 to 255 symbols of data

n Master or slave mode

JP1

-5V

AGnd

DGnd

+5V

Filter

65 MHz

5VDD*

EXTERNAL DATAJ1 EXTERNAL

DATA CLK

EXTERNAL TCLK

J16

MASTER CLOCK

STEL 1109

PSK/QAM

Modulator U X

Burst

Controller

(FPGA)

8 11

DATA ADDR

SRAM

10 Bit

DAC

JP4

JP3

Xtal. Osc.

102.4 MHz

Prog.

ATTEN.

Filter

42 MHz

JP5

Aux. Output

SYNC

*Driven by 5 Volt

on STEL-1209

JP6

IF Out

75Ω

WCP 52841.c-5/9/97

STEL-1209 2

DESCRIPTION

The STEL-1209 is the latest member in Stanford Telecom's line of BPSK/QPSK Burst Modulator board level products. It uses the STEL-1109 ASIC to provide all the convenience of supporting BPSK, QPSK, or 16QAM up-stream modulation with a maximum data rate of 10 Mbps, 20 Mbps, and 40 Mbps; respectively. The STEL-1109 has a Reed-Solomon encoder, a scrambler, a differential encoder, a 10 bit DAC, and many more features needed to build robust communication systems that satisfy today's demanding requirements. For further feature details please refer to the STEL-1109 ASIC data sheet.

Besides the STEL-1109, there is additional logic circuitry implemented in Altera's FPGA to provide burst BPSK, QPSK, and 16QAM modulation modes. Several improvements in these burst modulation modes are included; e.g. external/internal preamble and data sources; variable bursts quantity (includes single to 10 -million and auto repeat); variable packet length, guard time, and preamble size (including zero preamble size). This flexibility allows the STEL-1209 to be customized easily into customers' specific environment. Connectors J3 and J4 are digital test pins provided for easy monitoring of the burst control/signal timing relationships.

With a 0.35 micron ASIC process the STEL-1109 can support a maximum clock frequency of 165 MHz. The frequency of the output modulated carrier is programmable between 5 to 65 MHz; the upper limit is approximately 40% of the master clock. The STEL-1209 has a 102.4 MHz crystal oscillator on-board. Hence, its maximum modulated carrier frequency can be set to 40 MHz. However, an external clock (+10 to +13 dBm) can be selected as the master (through connector J2 and jumper JP4) and carrier frequency of 65 MHz can be achieved easily. An obvious difference between this board and its predecessor (STEL-1208) is the absence of a DAC. A 10 bit DAC is built in the STEL-1109 and observable spur level is -50 dB or better. It has a pair of differential current outputs which swings ±0.96 volt peak-to-peak at 50 ohm termination. Single-ended output of the DAC (using transformer T1 as a double to single-ended converter) can be obtained from J7 (expects 50 or 75 ohm termination impedance from instrumentation). Also included is a choice between

two output low pass filters (jumper JP5 and JP6) with cut-off frequency at 42 and 65 MHz. The output of the filter is amplified and is obtainable from J5 (75 ohm source impedance). JP3 routes the DAC output to either J7 or J5.

The board (running at 102.4 MHz in continuous modulation mode) takes about 430 mA at the 5 volt supply. Power is supplied to the board through JP1. Its pins are clearly labeled on the board (pin 1 = -5 volt, pin 2 = AGND, pin 3 = DGND, pin 4 = VCC (+5 volt)). Reversing the polarity of the supply pins would cause damage to the board. When clock enable line is taken low (grounded), the board consumes 200 mA or less. Current drawn on the -5 volt supply is 10 mA. There are two 5 volt to 3.3 volt converters on the board and the design serves to demonstrate the inter-operability of the STEL-1109 in a 5 volt or 3.3 volt system. The STEL1109 ASIC, which is a 3.3V device, consumes 1.8 mA/MHz in continuous mode. Current consumption by the ASIC can be easily measured by connecting pin 2 of JP9 (see package outline) to a 3.3 V power supply that has a current meter.

STEL-1209's operating mode can be modified by writing new values to the STEL-1109 and the burst controller's registers. These registers can be read and written through a Graphical User Interface (GUI) program that comes with the STEL-1209 board. The GUI software allows the user to select different modulation methods, preamble size, interpolation ratio, etc. with the ease of button clicking on a Personal Computer running Microsoft's Windows 95 operating system. A serial cable with 9 pin D-sub connector must be connected between P2 of the STEL -1209 and the PC's COM port for the GUI software to work. At power up or upon reset, the STEL -1209 is automatically loaded with default values to give repeating QPSK burst modulation (50% duty cycle) centered at 10 MHz (master mode). This default mode allows the STEL1209 to communicate with the STEL -9244, up-stream burst demodulator. External data must be provided to connector J1 (75 ohm unipolar unbalance) to complete the communication loop. Clock for the external data is provided through connector J6 (75 ohm unipolar unbalance).

3 STEL-1209

SPECIFICATIONS

π•f

OUT

CLK

Output Frequency Range:

5 MHz to 65 MHz using an external clock frequency of 165 MHz (or up to 40 MHz using the provided onboard clock at 102.4 MHz).

Resolution:

10 Hz @ f

J2 -- Master Clock Input:

To use the on-board 102.4 MHz crystal oscillator, jump pin 2 and pin 3 on JP4.

To use an external master clock, jump pin 1 and pin 2 on JP4.

Maximum Frequency, f BNC connector, input power at +10 dBm to +13 dBm,

A.C. coupled, 50 Ohms

J16 -- External TCLK Input:

BNC connector, HCMOS levels.

J7 -- Aux. Output:

SMB connector for single ended DAC output. Transformer T1 is used to do the double-to-single ended conversion.

JP3 is used to route the single ended output to either J7 or J5.

J8 -- SYNC Output:

BNC connector, HCMOS levels Pulse covering the period of bursting symbols. This

signal (equivalent to DATAENO inverted) can be used as a scope trigger.

J5 -- IF Output:

BNC connector, 75 Ohms. Output power: + 0 dBm @ default settings Return loss: ≥ 15 dB Stop band: ≥ 30 dB at 85 MHz with 65 MHz LPF

Note: The output level of the DAC falls as the carrier frequency rises according to the equation:

OUT

165 MHz (24 bits)

CLK

OUT(DC)

CLK(MAX)

(sine f)

= 165 MHz

where : f =

Note: The on-board low pass filter (LPF) cut-off frequency can be selected between 42 MHz or 65 MHz by properly configuring JP5 and JP6.

J1 -- External Serial Data Input:

BNC connector, HCMOS levels.

Output Level Control:

The output level can be controlled over a range of 15 dB in 1 dB steps by means of the control software supplied.

P2 -- RS-232C Control Interface:

Connector Type: 9-pin Subminiature ‘D’, female (DCE). Pin 2 TXD Pin 3 RXD

Pin 5 GND Pin 7 GND

Power Requirements (Typical):

JP1, pin 1: -5 volts ±5%, 10 mA JP1, pin 2: Analog GND JP1, pin 3: Digital GND JP1, pin 4: +5 volts ±5%, 330 mA

(@ fclk = 100 MHz)

Temperature Range, Ambient:

0-70° Operating

Connector J3:

Pin 1 NC Pin 2 NC Pin 3 AUXCLK Pin 4 RDSLEN Pin 5 SCRMEN Pin 6 CLKEN Pin 7 TCLK Pin 8 DATAEN Pin 9 TSDATA Pin 10 WRB Pin 11 DSB Pin 12 DIFFEN Pin 13 TXCLK_B Pin 14 TXDATA_B Pin 15 BURSTGATE_B Pin 16 CKSUM Pin 17 DATAENO Pin 18 SYMPLS Pin 19 BITCLK Pin 20 GND

Connector J4:

Pin 1 NC Pin 2 NC Pin 3 EXT_TCLK_B Pin 4 SYMCLK Pin 5 uP_WRB Pin 6 uP_RDB Pin 7 CLKEN_LOW Pin 8 (SPARE) Pin 9 BURST Pin 10 (SPARE) Pin 11 PREAMBLE_SRAM Pin 12 LOAD_RUN Pin 13 (SPARE) Pin 14 uP_BURSTGATE Pin 15 Burst/Done Pin 16 (SPARE) Pin 17 VCC (SPARE) Pin 18 VCC (SPARE) Pin 19 NCO_LOAD Pin 20 GND

STEL-1209 4

ORDERING INFORMATION

To order, specify Model Number STEL-1209/CE. “CE” indicates a commercial grade, board-level product.

PACKAGE OUTLINE

6.3"

(16 cm)

Reset

SYNC

EXT DATA

EXT DATA CLK

MASTER CLK

BURST GATE

J16

EXT TCLK

EPROM

U11

Xtal. Osc.

JP4

JP8

JP9

Micro

STEL1109

Burst Controller

MOLEX 4455C-A

-5V +5V

JP3

U19 JP7

EEPROM

JP1

P2: 9‘D’

JP5

JP6

2 1

WCP 52850.c-4/25/97

4.7"

(12 cm)

IF OUT

5 STEL-1209

+ 16 hidden pages