INTEL STEL-1109 User Manual

STEL-1109

STEL-1109

Data Sheet

STEL-1109/CR

5 - 65 MHz

Burst Transmitter

R

TABLE OF CONTENTS
TRADEMARKS................................................................................................................................................................	4
KEY FEATURES................................................................................................................................................................	5
INTRODUCTION............................................................................................................................................................	6
PIN CONFIGURATION .................................................................................................................................................	7
POWER SUPPLY PINS....................................................................................................................................................	7
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS............................................................................................	8
Overview ........................................................................................................................................................................	8
Data Path Description ...................................................................................................................................................	9
Bit Sync Block.............................................................................................................................................................	9
Bit Encoder Block.......................................................................................................................................................	10
Data Path Control (Multiplexers)........................................................................................................................	10
Scrambler ................................................................................................................................................................	11
Reed-Solomon Encoder.........................................................................................................................................	12
Symbol Mapper Block...............................................................................................................................................	13
Bit Mapper..............................................................................................................................................................	13
Differential Encoder..............................................................................................................................................	14
Symbol Mapper......................................................................................................................................................	15
Nyquist Fir Filter .......................................................................................................................................................	18
Interpolating Filter ....................................................................................................................................................	19
Modulator ...................................................................................................................................................................	20
10-Bit DAC..................................................................................................................................................................	20
Control Unit Description..............................................................................................................................................	20
Bus Interface Unit......................................................................................................................................................	20
Clock Generator .........................................................................................................................................................	20
NCO.............................................................................................................................................................................	21
TIMING DIAGRAMS.....................................................................................................................................................	23
Clock Timing..................................................................................................................................................................	23
Pulse Width ....................................................................................................................................................................	23
Bit Clock Synchronization............................................................................................................................................	24
Input Data and Clock Timing......................................................................................................................................	25
Write Timing ..................................................................................................................................................................	26
Read Timing ...................................................................................................................................................................	27
NCO Loading (User Controlled).................................................................................................................................	28
NCO Loading (Automatic) ..........................................................................................................................................	28
Digital Output Timing..................................................................................................................................................	29
DATAEN to DATAENO Timing ................................................................................................................................	30
BURST TIMING EXAMPLES........................................................................................................................................	30
Burst Timing: Full Burst (Slave Mode, QPSK) ..........................................................................................................	31
Master Mode, BPSK Burst Timing Signal Relationships .........................................................................................	32
Slave Mode, BPSK Burst Timing Signal Relationships ............................................................................................	32
Master Mode, QPSK Burst Timing Signal Relationships ........................................................................................	33
Slave Mode, QPSK Burst Timing Signal Relationships ...........................................................................................	33
Master Mode, 16QAM Burst Timing Signal Relationships....................................................................................	34
Slave Mode, 16QAM Burst Timing Signal Relationships........................................................................................	34
ELECTRICAL SPECIFICATIONS ................................................................................................................................	35
RECOMMENDED INTERFACE CIRCUITS..............................................................................................................	38
Slave Mode Interface.....................................................................................................................................................	38
Master Mode Interface..................................................................................................................................................	38
EXAMPLE OUTPUT LOAD SCHEMATIC ................................................................................................................	39
MECHANICAL SPECIFICATIONS .............................................................................................................................	39

STEL-1109

2

PRELIMINARY PRODUCT INFORMATION

LIST OF ILLUSTRATIONS

Figure 1.	STEL-1109 Block Diagram....................................................................................................................	9
Figure 2.	Bit Encoder Functional Diagram ........................................................................................................	10
Figure 3.	Scrambler Block Diagram ....................................................................................................................	11
Figure 4.	DAVIC Scrambler..................................................................................................................................	12
Figure 5.	Mapping Block Functional Diagram..................................................................................................	13
Figure 6.	BPSK Constellation ...............................................................................................................................	15
Figure 7.	QPSK Constellation ..............................................................................................................................	16
Figure 8.	Natural Mapping Constellation..........................................................................................................	16
Figure 9.	Gray Coded Constellation ...................................................................................................................	17
Figure 10.	Left Coded Constellation .....................................................................................................................	17
Figure 11.	DAVIC Coded Constellation ...............................................................................................................	18
Figure 12.	Right Coded Constellation ..................................................................................................................	18
Figure 13.	Nyquist FIR Filter..................................................................................................................................	19
Figure 14.	Interpolation Filter Block Diagram.....................................................................................................	19
Figure 15.	Duty Cycle Derating Versus Temperature (@3.3v)..........................................................................	36
Figure 16.	STEL-1109 Mechanical Characteristics ..............................................................................................	39

PRELIMINARY PRODUCT INFORMATION

3

STEL-1109

LIST OF TABLES

Table 1.	STEL-1109 Features ..............................................................................................................................	5
Table 2.	I/O Signal Pin Assignments................................................................................................................	7
Table 3.	STEL -1109 Configuration Register Data Fields...............................................................................	8
Table 4.	Data Latching Options .........................................................................................................................	9
Table 5.	Bit Encoding Data Path Options.........................................................................................................	11
Table 6.	Scrambler Parameters ..........................................................................................................................	11
Table 7.	Sample Scramble Register Values ......................................................................................................	12
Table 8.	Reed-Solomon Encoder Parameters...................................................................................................	13
Table 9.	Bit Mapping Options............................................................................................................................	14
Table 10.	Differential Encoder Control...............................................................................................................	14
Table 11.	Qpsk Differential Encoding and Phase Shift ....................................................................................	15
Table 12.	Symbol Mapping Selections................................................................................................................	16
Table 13.	Symbol Mapping ..................................................................................................................................	17
Table 14.	FIR Filter Configuration Options .......................................................................................................	18
Table 15.	FIR Filter Coefficient Storage..............................................................................................................	18
Table 16.	Interpolation Filter Bypass Control....................................................................................................	19
Table 17.	Interpolation Filter Signal Level Control ..........................................................................................	19
Table 18.	Signal Inversion Control......................................................................................................................	20
Table 19.	FCW Selection .......................................................................................................................................	22
Table 20.	Clock Timing AC Characteristics .......................................................................................................	23
Table 21.	Pulse Width AC Characteristics .........................................................................................................	23
Table 22.	Bit Clock Synchronization AC Characteristics .................................................................................	24
Table 23.	Input Data and Clock AC Characteristics .........................................................................................	25
Table 24.	Write Timing AC Characteristics .......................................................................................................	26
Table 25.	Read Timing AC Characteristics ........................................................................................................	27
Table 26.	NCO Loading AC Characteristics......................................................................................................	28
Table 27.	Digital Output Timing AC Characteristics .......................................................................................	29
Table 28.	DATAEN to DATAENO Timing AC Characteristics......................................................................	30
Table 29.	Absolute Maximum Ratings ...............................................................................................................	35
Table 30.	Recommended Operating Conditions...............................................................................................	36
Table 31.	DC Characteristics ................................................................................................................................	37

TRADEMARKS

Stanford Telecom and STEL are registered trademarks of Stanford Telecommunications, Incorporated.

STEL-1109

4

PRELIMINARY PRODUCT INFORMATION

KEY FEATURES

nComplete BPSK/QPSK/16QAM modulator in a CMOS ASIC

nProgrammable over a wide range of data rates

nNCO modulator provides fine frequency resolution

n165 MHz maximum clock rate generates a modulated carrier at frequencies programmable from 5 to 65 MHz

nOperates in continuous and burst modes

nDifferential Encoder, Programmable Scrambler, and Programmable Reed-Solomon FEC Encoder

nProgrammable 32-tap FIR Filter for signal shaping before modulation

n10-bit DAC implemented on chip

nComplete upstream modulator solution – serial data in and RF signal out

nCompatible with DAVIC, IEEE 802.14 (preliminary), Intelsat IESS-308, ITU J.83 Annex A, MCNS Standards

nSupports low data rates for voice applications and high data rates for wideband applications

nSmall Footprint, Surface Mount 80-Pin MQFP Package

	Table 1. STEL-1109 Features
Feature	Characteristic
Carrier frequency:	5 to 65 MHz (maximum of approximately 40% of master clock)
Symbol rate:	From Master clock divided by 16 down to Master clock divided by
	16384 (in steps of 4) yielding a maximum symbol rate of 10Msps with a
	160 MHz clock.
FIR filter tap coefficients:	32 programmable taps (10 bits each), symmetric response
Modulation:	BPSK, QPSK, or 16QAM
16QAM constellation:	Eight selectable bit-to-symbol mappings
	Five selectable symbol-to-constellation mappings
I and Q modulator signs / Spectral	Signs of I and Q plus the mapping to Sine and Cosine carriers is
Inversion	programmable.
Reed-Solomon encoder:	Selectable on/off
	Two selectable generator polynomials
	Block length shortened any amount
	Error correction capability T = 1 to 10
Scrambler:	Selectable on/off
	Self-synchronizing or frame synchronized (sidestream)
	Location before or after RS Encoder
	Programmable generator polynomial
	Programmable length up to 224 - 1
	Programmable initial seed
Differential encoder:	Selectable on/off

PRELIMINARY PRODUCT INFORMATION

5

STEL-1109

INTRODUCTION

The STEL-11091 is a highly integrated, maximally flexible, burst transmitter targeted to the cable modem market. It receives serial data, randomizes the data, performs FEC and differential encoding, maps the data to a constellation before modulation, and outputs an analog RF signal.

The STEL-1109 is the latest in a series of modulator chips that comprise the STEL-1103 through STEL-1108 modulators. Several key components (e.g., a 10-bit DAC, FECs, etc.) have been incorporated in the STEL-1109 and the enhancements have resulted in significant changes to the chipÕs electrical and software interfaces.

The STEL-1109 is capable of operating at data rates of up to 10 Mbps in BPSK mode, 20 Mbps in QPSK mode, and 40 Mbps in 16QAM mode. It operates at clock frequencies of up to 165 MHz, which allows its internal, 10-bit Digital-to-Analog Converter (DAC) to generate RF carrier frequencies of 5 to 65 MHz.

The STEL-1109 also uses digital FIR filtering to optimally shape the spectrum of the modulating data prior to modulation. This optimizes the spectrum of the modulated signal, and minimizes the analog filtering required after the modulator. The filters are

designed to have a symmetrical (mirror image) polynomial transfer function, thereby making the phase response of the filter linear. This also eliminates the inter-symbol interference that results from group delay distortion. In this way, it is possible to change the carrier frequency over a wide frequency range without having to change filters, thus providing the ability to operate a single system in many channels.

The STEL-1109 can operate with very short gaps between transmitted bursts to increase the efficiency of TDMA systems. The STEL-1109 (as well as the STEL1103 and STEL-1108) operates properly even when the interburst gap is less than four (4) symbols (half the length of the FIR filter response). In this case the postcursor of the previous burst overlaps and is superimposed on the precursor of the following burst.

Signal level scaling is provided after the FIR filter to allow the STEL-1109Õs maximum arithmetic dynamic range to be utilized. Signal levels can be changed over a wide range depending on how the device is programmed.

In addition, the STEL-1109 is designed to operate from a 3.3 Vdc power supply and the chip can be interfaced with logic that operates at 5 Vdc.

1The STEL-1109 utilizes advanced signal processing techniques which are covered by U.S. Patent Number 5,412,352.

STEL-1109

6

PRELIMINARY PRODUCT INFORMATION

PIN CONFIGURATION

The STEL-1109 input and output signal pin assignments are listed in Table 2. The location of the pin numbers is shown by Figure 16 (page 39). The

STEL-1109 power supply pins are described in the following paragraph.

Table 2. I/O Signal Pin Assignments

1

VDD

[7]

(S)

21

FCWSEL1

[21]

(I)

41

VDD

[7]

(S)

61

VSS

[7]

(T)

2

DATA4

[20]

(B)

22

VSS

[7]

(T)

42

SYMPLS

[20]

(O)

62

VDD

[7]

(S)

3

DATA5

[20]

(B)

23

VSS

[7]

(T)

43

VSS

[7]

(S)

63

VDD

[7]

(T)

4

DATA6

[20]

(B)

24

VSS

[7]

(T)

44

VSS

[7]

(T)

64

VSS

[7]

(S)

5

DATA7

[20]

(B)

25

VDD

[7]

(S)

45

VSS

[7]

(T)

65

VDD

[7]

(T)

6

VSS

[7]

(S)

26

CLKEN

[9,20]

(I)

46

VSS

[7]

(T)

66

VSS

[7]

(S)

7

VSS

[7]

(S)

27

VSS

[7]

(S)

47

VSS

[7]

(T)

67

RSTB

[20]

(I)

8

ADDR5

[20]

(I)

28

CLK

[20]

(I)

48

VSS

[7]

(T)

68

VSS

[7]

(T)

9

ADDR4

[20]

(I)

29

RDSLEN

[10]

(I)

49

VSS

[7]

(S)

69

VSS

[7]

(S)

10

ADDR3

[20]

(I)

30

VDD

[7]

(S)

50

[7]

(N.C.)

70

DIFFEN

[13]

(I)

11

VDD

[7]

(S)

31

5VDD

[7]

(I)

51

AVDD

[7]

(S)

71

NCO LD

[21]

(I)

12

ADDR2

[20]

(I)

32

SCRMEN

[10]

(I)

52

OUT

[20]

(AO)

72

[20]

(I)

CSEL

13

ADDR1

[20]

(I)

33

VSS

[7]

(S)

53

OUTN

[20]

(AO)

73

[20]

(I)

DSB

14

ADDR0

[20]

(I)

34

VSS

[7]

(T)

54

AVSS

[7]

(S)

74

[20]

(I)

WR

15

VSS

[7]

(S)

35

CKSUM

[12]

(O)

55

[7]

(N.C.)

75

VDD

[7]

(S)

16

VSS

[7]

(S)

36

VSS

[7]

(S)

56

VSS

[7]

(S)

76

DATA0

[20]

(B)

17

TSDATA

[9]

(I)

37

ACLK

[20]

(O)

57

VSS

[7]

(T)

77

DATA1

[20]

(B)

18

DATAEN

[10]

(I)

38

VDD

[7]

(S)

58

VSS

[7]

(T)

78

DATA2

[20]

(B)

19

TCLK

[9]

(I)

39

DATAENO [20]

(O)

59

VSS

[7]

(T)

79

DATA3

[20]

(B)

20

FCWSEL0

[21]

(I)

40

BITCLK

[9,20]

(O)

60

VSS

[7]

(T)

80

VSS

[7]

(S)

Notes:

Legend:

1.

Pin 31 is applied to input buffers only.

(AO)

Analog Output

(O)

Output signal

2.

See Package Outline (Figure 16) for pin

(B)

Bi-directional (I/O) signal

(S)

Source

identification.

(I)

Input signal

(T)

Factory Test Pin

(N.C.)

Not Connected

[#]

Page Reference

POWER SUPPLY PINS

There are three separate power supply systems within the STEL-1109. The primary supply for the digital logic circuits is nominally 3.3 volts and is input on the VDD pins. The digital inputs have a separate supply, 5VDD, which can be connected to a 5 volt supply if the STEL1109 inputs are driven from 5 volt logic. If the logic driving the STEL-1109 is run on 3.3 volts, then the 5VDD

pin should be connected to 3.3 volts. The return for both digital supplies is VSS. The DAC has a separate analog power supply and return, AVDD and AVSS. The 3.3 volt AVDD input allows the user to provide a separate well filtered supply for the DAC to prevent spurs that might be created from digital noise on the VDD supply system.

PRELIMINARY PRODUCT INFORMATION

7

STEL-1109

FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS

OVERVIEW

The STEL-1109 is comprised of the Data Path and Control Unit sections shown in Figure 1. The Data Path is comprised of a Bit Sync Block, Bit Encoder Block (i.e.,Êthe Scrambler, Reed-Solomon Encoder, and two Multiplexers shown in Figure 2), Symbol Mapper Block (i.e., the Bit Mapper, Differential Encoder, and Symbol Mapper are shown in FigureÊ5), two channels (one for I and one for Q), a Combiner, and a 10-bit DAC. Each channel consists of a Nyquist Filter, Interpolation Filter, and Modulator. The Control Unit is comprised of a Bus Interface Unit (BIU), Clock Generator, and NCO.

Table 1 summarizes the main features of the circuits described by the remaining paragraphs of this section.

The STEL-1109 provides 58, programmable, read/write registers (Configuration Registers). Table 3 provides a graphic representation of the STEL-1109Õs Configuration Registers and their data fields. Each register can be selected for a write or read operation using addresses 00H through 39H.

Table 3. STEL-1109 Configuration Register Data Fields

Address

Contents

(Hex)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

08 - 00

NCO

21

28 - 09

FIR Filter Coefficients

18

29

LSB Sampling Rate Control (see address 39 for MSB)

20

2A

Interpolation Filter Gain Control

19

Auxiliary Clock Rate Divider

20

2B

Set To Zero

Set To Zero

Interpolation Filt. Bypass19

Set To One

Set To Zero

Invert I/Q Chan. 20

2C

TCLK Sel.

9

Set To Zero

Set To Zero

Set To Zero

MOD

14

FIR bypass

18

Set To Zero

2D

FZSINB21

Bit Mapping13

Set To One

Set To Zero

PN Code Sel9

PN On/Off9

2E

Symbol Mapping

15

CLRFIR

18

Bit Sync Re-arm

9

2F

Set To Zero

32-30

SCRAMBLER Init Registers

11

35-33

SCRAMBLER Mask Registers

11

36

PPolynomial

13

BypassB

10

10

Self-Sync

11

T

12

S-RS

37

K

12

38

DATAENBPB

10

10

10

10

SCRMENBPB

10

10

DiffDCBPB

14

DiffDCSEL

14

DATAENSEL

RSENBPB

RSENSEL

SCRMENSEL

39

Set To Zero

Set To Zero

TRLSBF

12

LDLSBF

12

MSB Sampling Rate Control (see address 29 for LSB)

20

Note: Superscripted numbers are page references where discussion on setting the particular register(s) or bit(s) begins.

STEL-1109

8

PRELIMINARY PRODUCT INFORMATION

DIFFEN
TCLK						DATA PATH
TSDATA	BIT
	Sync			I[1:0]				OUT
	Block				Nyquist	Interpolating	10-Bit	OUTN
				2	Filter	Filter	DAC
		I[1:0],	Symbol
						Modulator
		Q[1:0]	Mapper	Q[1:0]
			Block		Nyquist	Interpolating		DATAENO
DATAEN	BIT	4		2	Filter	Filter
RDSLEN	Encoder
	Block
SCRMEN								CKSUM
AVDD
5VDD	SAMPLS
VDD		MASTER CLOCK
RST								BITCLK
	Clock							SYMPLS
CLKEN	Generator							ACLK
CLK						COS 2πFT
NCO LD
FCWSEL1-0			Numerically			SIN 2πFT
			Controlled
DATA7-0			Oscillator
ADDR5-0
DSB	Bus
WR	Interface
	Unit
CSEL
						CONTROL UNIT
								WCP 52981.c-5/2/97

Figure 1. STEL-1109 Block Diagram

DATA PATH DESCRIPTION

BIT SYNC BLOCK

The Bit Sync Block has two functions, latching input data, and synchronizing the STEL-1109 BITCLK and symbol counters to the user data.

Latching Input Data

Latching of input data is accomplished in three ways:

•Externally supplied TSDATA is latched by the internal BITCLK.

•Externally supplied TSDATA is latched by an externally provided TCLK

•Internally generated PN code data is latched by the internal BITCLK

See Table 4 for register settings to implement each mode.

Table 4. Data Latching Options

Data Source		Latched By		Register 2C Bit 7		Register 2D Bits 1,0		Mode Name
TSDATA		BITCLK	0			X,0		Master Mode
TSDATA		TCLK	1			X,0		Slave Mode
PN Code 10, 3		BITCLK	0		0,1			Test Mode
PN Code 23, 18		BITCLK	0		1,1			Test Mode

PRELIMINARY PRODUCT INFORMATION

9

STEL-1109

BITCLK latches data on its falling edge. TCLK latches data on its rising edge.

Whenever the CLKEN input is low, the BITCLK output will stop. In order to provide customers with a continuous clock, the STEL-1109 provides an auxiliary clock (ACLK) output which is discussed later in the clock generator section. The ACLK output is primarily for use in master mode where users may need a clock to run control circuits during the guard time between bursts.

When using slave mode, the data that is latched by the rising edge of TCLK is re-latched internally by the next falling edge of BITCLK which re-synchronizes the data to the internal master clock.

Synchronizing BITCLK / SYMPLS

The synchronization circuit aligns the STEL-1109 BITCLK and its SYMPLS counter circuits to the beginning of the first user data symbol. The circuit has two parts, an arming circuit and a trigger circuit. Once armed, the first rising edge on the TCLK input will activate (trigger) the synchronization process.

The circuit can be armed in two ways; taking CLKEN from low to high, or toggling Configuration Register 2EH bit 0 from low to high to low again. In a normal burst mode application, the circuit is automatically rearmed between bursts because CLKEN goes low. For applications that will not allow CLKEN to cycle low between bursts, some system level precautions should be observed to maintain synchronization of user data to the STEL-1109 BITCLK.

Once triggered, the sync circuit re-starts the BITCLK and SYMPLS counters. The BITCLK output starts high, and SYMPLS resets to the start of a symbol. There is a delay equal to about three cycles of the master clock from the rising edge of the TCLK input before this restart occurs. During this brief delay period, the BITCLK and SYMPLS counters are still free running and may or may not have transitions.

In master mode, the rising edge of TCLK normally marks the transition of the first user data bit (which will be latched in by the next falling edge of BITCLK). In slave mode, the first user data bit must already be valid at this first rising edge of TCLK.

BIT ENCODER BLOCK

The Bit Encoder Block consists of a Scrambler, a Reed-Solomon Encoder, and data path controls (multiplexers), as shown in Figure 2.

SCRMEN
SERIAL	Input Multiplexer	Scrambler	Output Multiplexer
				ENCODED
DATA
				SERIAL DATA
DATAEN
		Reed-Solomon
		Encoder
				CHKSUM
RDSLEN				SIGNAL
S-RS
				WCP 52982.c-4/26/97

Figure 2. Bit Encoder Functional Diagram

Data Path Control (Multiplexers)

The STEL-1109 provides a great deal of flexibility and control over the routing of data through or around the encoding functions. With appropriate register selections, data can be routed around (bypass) both encoders, through either one and around the other, through the scrambler then the RS Encoder, or through the RS Encoder and then the scrambler. Control over the bypassing can be set for software control or external (user) input signal control. Generally, if an encoding function will be left either on or off continuously, then software control is appropriate. If the function must be turned on and off dynamically (typically in order to send the preamble Ôin the clearÕ i.e. unencoded), then external (user) input control is required. If the ReedSolomon encoder will not be used at all, then a separate bypass option can be activated to remove an 8 bit delay register from the data path that is required if the possibility of turning on the encoder exists. Each of the external (user) input control pins (if enabled) turns on the encoding function when high and bypasses the function when low.

The DATAEN input signal determines whether or not data will advance (shift through) the encoding blocks. The presence of a high on the DATAEN input when the BITCLK output goes low allows the circuits to advance data through them. The DATAEN signal is delayed

STEL-1109

10

PRELIMINARY PRODUCT INFORMATION

internally to allow the rising edge of DATAEN to coincide with the first rising edge of TCLK.

See Table 5 for a summary of register settings required to achieve the various data path possibilities.

Table 5. BIT Encoding Data Path Options

Data Path	Register 36 Bits 6,5	Register 38 Bits 7-2
Data stopped (continuously)	X,X	01	XXÊXX
Data path on (continuously)	X,X	11	XXÊXX
Data path enabled by pin 18	X,X	X0	XXÊXX
Scrambler off (continuously)	X,X	XX XX 01
Scrambler on (continuously)	X,X	XX XX 11
Scrambler enabled by pin 32	X,X	XX XX X0
RS Encode off (continuously)	1,X	XX 01 XX
RS Encode on (continuously)	1,X	XXÊ11 XX
RS Encode enabled by pin 29	1,X	XXÊX0 XX
Scrambler then RS Encoder	1,1	XXÊXXÊXX
RS Encoder then Scrambler	1,0	XXÊXXÊXX
Bypass RS Encoder	0,X	XXÊXXÊXX

Scrambler

The scrambler can be used to randomize the serial data in order to avoid a strong spectral component that might otherwise arise from the occurrence of repeating patterns in the input data. The Scrambler (Figure 3) uses a Pseudo-Random (PN) generator to generate a PN code pattern. All 24 registers are presettable and any combination of the registers can be connected (tapped) to form any polynomial of up to 24 bits. The scrambler may be either frame synchronized or self synchronized. Table 6 shows the registers involved.

The value in the INIT registers is loaded into the scrambler shift registers whenever the scrambler is disabled. The scrambler will scramble data one bit at a time at each falling edge of BITCLK that occurs while both the scrambler and DATAEN are active (enabled). Internal delays on the SCRMEN control signal input allow for a rising edge to occur coincident with the rising edge of BITCLK that precedes the latching of the first data bit to be scrambled.

24-bit Mask Reg	1	2	3	22	23	24
24-bit INIT Reg	1	2	3	22	23	24
24-bit Shift Reg
	1	2	3	22	23	24
			XOR
SCRMEN		AND		SERIAL OUTPUT
			XOR
SERIAL INPUT
			SELF	FRAME
			SYNC	SYNC
SSYNC				MUX
					WCP 52983.c-4/26/97

Figure 3. Scrambler Block Diagram

	Table 6.	Scrambler Parameters
Parameter	Characteristic				Configuration Register Setting
Generator	p(x) = c24x24 + c23x23 + É + c1x + 1		Register 35		Bit 0	Register 34		Bit 0	Register 33		Bit 0
Polynomial	where ci is a binary value (0, 1)		Bit 7	to		Bit 7	to		Bit 7	to
(Mask Reg)			c24	to	c17	c16	to	c9	c8	to	c1
Seed	Any 24 bit binary value, s24-1		Register 32		Bit 0	Register 31		Bit 0	Register 30		Bit 0
(INIT Reg)			Bit 7	to		Bit 7	to		Bit 7	to
			s24	to	s17	s16	to	s9	s8	to	s1
Scrambler	Frame synchronized (sidestream)		Register 36 Bit 4
Type			Set to zero
Scrambler	Self-synchronized		Register 36 Bit 4

PRELIMINARY PRODUCT INFORMATION

11

STEL-1109

Type		Set to one

The Mask, Init, and SSync fields can be programmed for different scrambler configurations. For example, the DAVIC Scrambler configuration shown in FigureÊ4 can

be implemented by programming the Mask, Init, and SSync fields with the values indicated by Table 7.

Table 7. Sample Scramble Register Values

Parameter	Characteristic	Configuration Register Setting
Generator	p(x) = x15 + x14 + 1	Register 35	Register 34	Register 33
Polynomial		Bit 7 to Bit 0	Bit 7 to Bit 0	Bit 7 to Bit 0
(Mask Reg)		0000Ê0000	0110Ê0000	0000Ê0000
Seed	0000A9 Hex	Register 32	Register 31	Register 30
(INIT Reg)		Bit 7 to Bit 0	Bit 7 to Bit 0	Bit 7 to Bit 0
		0000Ê0000	0000Ê0000	1010 1001
Scrambler	Frame synchronized (sidestream)	Register 36 Bit 4
Type		Set to zero

Reed-Solomon Encoder

The STEL-1109 uses a standard Reed-Solomon (RS) Encoder for error correction encoding of the serial data stream.

When DATAEN is high and the RS Encoder is enabled, the serial data stream both passes straight through the RS Encoder and also into encoding circuitry. The encoding circuitry computes a checksum that is 2T bytes long for every k bytes of input data. After the last bit of each block of k bytes of input data, the RS Encoder inserts its checksum (2T bytes of data) into the data path. There is no adverse effect to letting TCLK or TSDATA continue to run during the checksum; the data input will be ignored. CKSUM (pin 35) will be asserted high to indicate that the checksum bytes are being inserted into the data stream and will be lowered at the end of the checksum data insertion. The width of the CKSUM pulse is 2T bytes.

The STEL-1109 registers include two bits for determining the bit order for data into and checksum out of the RS Encoder circuitry. Set these to match the

Reed-Solomon decoding circuitry along with the other parameters.

The error correction encoding uses GF (256) and can be programmed for an error correction capability of 1 to 10, a block length of 3 to 255, and one of two primitive polynomials using the data fields listed in Table 8.

1	0	0	1	0	1	0	1	0	0	0	0	0	0	0
1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
									EX-OR
			AND									Randomized Data
								EX-OR
Enable					Clear Data Input
													WCP 52984.c-4/26/97

Figure 4. DAVIC Scrambler

STEL-1109

12

PRELIMINARY PRODUCT INFORMATION