INTEL STEL-1109 User Manual

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STEL-1109

Data Sheet

STEL-1109/CR

5 - 65 MHz

Burst Transmitter

TABLE OF CONTENTS

TRADEMARKS................................................................................................................................................................ 4

KEY FEATURES................................................................................................................................................................ 5

INTRODUCTION............................................................................................................................................................ 6

PIN CONFIGURATION ................................................................................................................................................. 7

POWER SUPPLY PINS.................................................................................................................................................... 7

FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS............................................................................................ 8

Overview ........................................................................................................................................................................ 8

Data Path Description ................................................................................................................................................... 9

Bit Sync Block............................................................................................................................................................. 9

Bit Encoder Block....................................................................................................................................................... 10

Data Path Control (Multiplexers)........................................................................................................................ 10

Scrambler ................................................................................................................................................................ 11

Reed-Solomon Encoder......................................................................................................................................... 12

Symbol Mapper Block............................................................................................................................................... 13

Bit Mapper.............................................................................................................................................................. 13

Differential Encoder.............................................................................................................................................. 14

Symbol Mapper...................................................................................................................................................... 15

Nyquist Fir Filter ....................................................................................................................................................... 18

Interpolating Filter .................................................................................................................................................... 19

Modulator ................................................................................................................................................................... 20

10-Bit DAC.................................................................................................................................................................. 20

Control Unit Description.............................................................................................................................................. 20

Bus Interface Unit...................................................................................................................................................... 20

Clock Generator ......................................................................................................................................................... 20

NCO............................................................................................................................................................................. 21

TIMING DIAGRAMS..................................................................................................................................................... 23

Clock Timing.................................................................................................................................................................. 23

Pulse Width .................................................................................................................................................................... 23

Bit Clock Synchronization............................................................................................................................................ 24

Input Data and Clock Timing...................................................................................................................................... 25

Write Timing .................................................................................................................................................................. 26

Read Timing ................................................................................................................................................................... 27

NCO Loading (User Controlled)................................................................................................................................. 28

NCO Loading (Automatic) .......................................................................................................................................... 28

Digital Output Timing.................................................................................................................................................. 29

DATAEN to DATAENO Timing ................................................................................................................................ 30

BURST TIMING EXAMPLES........................................................................................................................................ 30

Burst Timing: Full Burst (Slave Mode, QPSK) .......................................................................................................... 31

Master Mode, BPSK Burst Timing Signal Relationships ......................................................................................... 32

Slave Mode, BPSK Burst Timing Signal Relationships............................................................................................ 32

Master Mode, QPSK Burst Timing Signal Relationships ........................................................................................ 33

Slave Mode, QPSK Burst Timing Signal Relationships ........................................................................................... 33

Master Mode, 16QAM Burst Timing Signal Relationships.................................................................................... 34

Slave Mode, 16QAM Burst Timing Signal Relationships........................................................................................ 34

ELECTRICAL SPECIFICATIONS ................................................................................................................................ 35

RECOMMENDED INTERFACE CIRCUITS.............................................................................................................. 38

Slave Mode Interface..................................................................................................................................................... 38

Master Mode Interface.................................................................................................................................................. 38

EXAMPLE OUTPUT LOAD SCHEMATIC ................................................................................................................ 39

MECHANICAL SPECIFICATIONS ............................................................................................................................. 39

STEL-1109 2 PRELIMINARY PRODUCT INFORMATION

LIST OF ILLUSTRATIONS

Figure 1. STEL-1109 Block Diagram.................................................................................................................... 9

Figure 2. Bit Encoder Functional Diagram ........................................................................................................ 10

Figure 3. Scrambler Block Diagram .................................................................................................................... 11

Figure 4. DAVIC Scrambler.................................................................................................................................. 12

Figure 5. Mapping Block Functional Diagram.................................................................................................. 13

Figure 6. BPSK Constellation ............................................................................................................................... 15

Figure 7. QPSK Constellation .............................................................................................................................. 16

Figure 8. Natural Mapping Constellation.......................................................................................................... 16

Figure 9. Gray Coded Constellation ................................................................................................................... 17

Figure 10. Left Coded Constellation ..................................................................................................................... 17

Figure 11. DAVIC Coded Constellation ............................................................................................................... 18

Figure 12. Right Coded Constellation .................................................................................................................. 18

Figure 13. Nyquist FIR Filter.................................................................................................................................. 19

Figure 14. Interpolation Filter Block Diagram..................................................................................................... 19

Figure 15. Duty Cycle Derating Versus Temperature (@3.3v).......................................................................... 36

Figure 16. STEL-1109 Mechanical Characteristics .............................................................................................. 39

PRELIMINARY PRODUCT INFORMATION 3 STEL-1109

LIST OF TABLES

Table 1. STEL-1109 Features .............................................................................................................................. 5

Table 2. I/O Signal Pin Assignments................................................................................................................ 7

Table 3. STEL -1109 Configuration Register Data Fields............................................................................... 8

Table 4. Data Latching Options ......................................................................................................................... 9

Table 5. Bit Encoding Data Path Options......................................................................................................... 11

Table 6. Scrambler Parameters .......................................................................................................................... 11

Table 7. Sample Scramble Register Values ...................................................................................................... 12

Table 8. Reed-Solomon Encoder Parameters................................................................................................... 13

Table 9. Bit Mapping Options............................................................................................................................ 14

Table 10. Differential Encoder Control............................................................................................................... 14

Table 11. Qpsk Differential Encoding and Phase Shift.................................................................................... 15

Table 12. Symbol Mapping Selections................................................................................................................ 16

Table 13. Symbol Mapping .................................................................................................................................. 17

Table 14. FIR Filter Configuration Options ....................................................................................................... 18

Table 15. FIR Filter Coefficient Storage.............................................................................................................. 18

Table 16. Interpolation Filter Bypass Control.................................................................................................... 19

Table 17. Interpolation Filter Signal Level Control .......................................................................................... 19

Table 18. Signal Inversion Control...................................................................................................................... 20

Table 19. FCW Selection ....................................................................................................................................... 22

Table 20. Clock Timing AC Characteristics....................................................................................................... 23

Table 21. Pulse Width AC Characteristics ......................................................................................................... 23

Table 22. Bit Clock Synchronization AC Characteristics................................................................................. 24

Table 23. Input Data and Clock AC Characteristics......................................................................................... 25

Table 24. Write Timing AC Characteristics ....................................................................................................... 26

Table 25. Read Timing AC Characteristics........................................................................................................ 27

Table 26. NCO Loading AC Characteristics...................................................................................................... 28

Table 27. Digital Output Timing AC Characteristics ....................................................................................... 29

Table 28. DATAEN to DATAENO Timing AC Characteristics...................................................................... 30

Table 29. Absolute Maximum Ratings ............................................................................................................... 35

Table 30. Recommended Operating Conditions............................................................................................... 36

Table 31. DC Characteristics................................................................................................................................ 37

TRADEMARKS

Stanford Telecom and STEL are registered trademarks of Stanford Telecommunications, Incorporated.

STEL-1109 4 PRELIMINARY PRODUCT INFORMATION

KEY FEATURES

Complete BPSK/QPSK/16QAM modulator in

a CMOS ASIC

n Programmable over a wide range of data

rates

n NCO modulator provides fine frequency

resolution

n 165 MHz maximum clock rate generates a

modulated carrier at frequencies programmable from 5 to 65 MHz

n Operates in continuous and burst modes n Differential Encoder, Programmable

Scrambler, and Programmable Reed-Solomon FEC Encoder

Table 1. STEL-1109 Features

Feature Characteristic

Carrier frequency: 5 to 65 MHz (maximum of approximately 40% of master clock)

Symbol rate: From Master clock divided by 16 down to Master clock divided by

16384 (in steps of 4) yielding a maximum symbol rate of 10Msps with a 160 MHz clock.

FIR filter tap coefficients: 32 programmable taps (10 bits each), symmetric response

Modulation: BPSK, QPSK, or 16QAM

16QAM constellation: Eight selectable bit-to-symbol mappings

Five selectable symbol-to-constellation mappings

I and Q modulator signs / Spectral Inversion

Reed-Solomon encoder: Selectable on/off

Scrambler: Selectable on/off

Differential encoder: Selectable on/off

Signs of I and Q plus the mapping to Sine and Cosine carriers is programmable.

Two selectable generator polynomials

Block length shortened any amount

Error correction capability T = 1 to 10

Self-synchronizing or frame synchronized (sidestream)

Location before or after RS Encoder

Programmable generator polynomial

Programmable length up to 224 - 1

Programmable initial seed

n Programmable 32-tap FIR Filter for signal

shaping before modulation

n 10-bit DAC implemented on chip n Complete upstream modulator solution –

serial data in and RF signal out

n Compatible with DAVIC, IEEE 802.14

(preliminary), Intelsat IESS-308, ITU J.83 Annex A, MCNS Standards

n Supports low data rates for voice

applications and high data rates for wideband applications

n Small Footprint, Surface Mount 80-Pin

MQFP Package

PRELIMINARY PRODUCT INFORMATION 5 STEL-1109

INTRODUCTION

The STEL-11091 is a highly integrated, maximally flexible, burst transmitter targeted to the cable modem market. It receives serial data, randomizes the data, performs FEC and differential encoding, maps the data to a constellation before modulation, and outputs an analog RF signal.

The STEL-1109 is the latest in a series of modulator chips that comprise the STEL-1103 through STEL-1108 modulators. Several key components (e.g., a 10-bit DAC, FECs, etc.) have been incorporated in the STEL-1109 and the enhancements have resulted in significant changes to the chipÕs electrical and software interfaces.

The STEL-1109 is capable of operating at data rates of up to 10 Mbps in BPSK mode, 20 Mbps in QPSK mode, and 40 Mbps in 16QAM mode. It operates at clock frequencies of up to 165 MHz, which allows its internal, 10-bit Digital-to-Analog Converter (DAC) to generate RF carrier frequencies of 5 to 65 MHz.

The STEL-1109 also uses digital FIR filtering to optimally shape the spectrum of the modulating data prior to modulation. This optimizes the spectrum of the modulated signal, and minimizes the analog filtering required after the modulator. The filters are

designed to have a symmetrical (mirror image) polynomial transfer function, thereby making the phase response of the filter linear. This also eliminates the inter-symbol interference that results from group delay distortion. In this way, it is possible to change the carrier frequency over a wide frequency range without having to change filters, thus providing the ability to operate a single system in many channels.

The STEL-1109 can operate with very short gaps between transmitted bursts to increase the efficiency of TDMA systems. The STEL-1109 (as well as the STEL1103 and STEL-1108) operates properly even when the interburst gap is less than four (4) symbols (half the length of the FIR filter response). In this case the postcursor of the previous burst overlaps and is superimposed on the precursor of the following burst.

Signal level scaling is provided after the FIR filter to allow the STEL-1109Õs maximum arithmetic dynamic range to be utilized. Signal levels can be changed over a wide range depending on how the device is programmed.

In addition, the STEL-1109 is designed to operate from a 3.3 Vdc power supply and the chip can be interfaced with logic that operates at 5 Vdc.

The STEL-1109 utilizes advanced signal processing techniques which are covered by U.S. Patent Number 5,412,352.

STEL-1109 6 PRELIMINARY PRODUCT INFORMATION

PIN CONFIGURATION

The STEL-1109 input and output signal pin assignments are listed in Table 2. The location of the pin numbers is shown by Figure 16 (page 39). The

Table 2. I/O Signal Pin Assignments

2 DATA

3 DATA

4 DATA

5 DATA

8 ADDR

9 ADDR

10 ADDR

11 V

12 ADDR

13 ADDR

14 ADDR

15 V

16 V

17 TSDATA [9] (I) 37 ACLK [20] (O) 57 V

18 DATAEN [10] (I) 38 V

19 TCLK [9] (I) 39 DATAENO [20] (O) 59 V

20 FCWSEL

Notes:

1. Pin 31 is applied to input buffers only.

2. See Package Outline (Figure 16) for pin identification.

[7] (S) 21 FCWSEL1[21] (I) 41 V

[20] (B) 22 V

[20] (B) 23 V

[20] (B) 24 V

[20] (B) 25 V

[7] (T) 42 SYMPLS [20] (O) 62 V

[7] (T) 43 V

[7] (T) 44 V

[7] (S) 45 V

[7] (S) 26 CLKEN [9,20] (I) 46 V

[7] (S) 27 V

[7] (S) 47 V

[20] (I) 28 CLK [20] (I) 48 V

[20] (I) 29 RDSLEN [10] (I) 49 V

[20] (I) 30 V

[7] (S) 31 5V

[7] (S) 50 [7] (N.C.) 70 DIFFEN [13] (I)

[7] (I) 51 AV

[20] (I) 32 SCRMEN [10] (I) 52 OUT [20] (AO) 72

[20] (I) 33 V

[20] (I) 34 V

[7] (S) 53 OUTN [20] (AO) 73 DSB [20] (I)

[7] (T) 54 AV

[7] (S) 35 CKSUM [12] (O) 55 [7] (N.C.) 75 V

[7] (S) 36 V

[21] (I) 40 BITCLK [9,20] (O) 60 V

[7] (S) 56 V

[7] (S) 58 V

Legend: (AO) Analog Output (O) Output signal (B) Bi-directional (I/O) signal (S) Source (I) Input signal (T) Factory Test Pin (N.C.) Not Connected [#] Page Reference

STEL-1109 power supply pins are described in the following paragraph.

[7] (S) 61 V

[7] (S) 63 V

[7] (T) 64 V

[7] (T) 65 V

[7] (T) 66 V

[7] (T) 67 RSTB [20] (I)

[7] (T) 68 V

[7] (S) 69 V

[7] (S) 71 NCO LD [21] (I)

CSEL

[7] (S) 74 WR [20] (I)

[7] (S) 76 DATA

[7] (T) 77 DATA

[7] (T) 78 DATA

[7] (T) 79 DATA

[7] (T) 80 V

[7] (T)

[7] (S)

[7] (T)

[7] (S)

[7] (T)

[7] (S)

[7] (T)

[7] (S)

[20] (I)

[7] (S)

[20] (B)

[7] (S)

POWER SUPPLY PINS

There are three separate power supply systems within the STEL-1109. The primary supply for the digital logic circuits is nominally 3.3 volts and is input on the V pins. The digital inputs have a separate supply, 5VDD, which can be connected to a 5 volt supply if the STEL1109 inputs are driven from 5 volt logic. If the logic driving the STEL-1109 is run on 3.3 volts, then the 5V

PRELIMINARY PRODUCT INFORMATION 7 STEL-1109

pin should be connected to 3.3 volts. The return for both digital supplies is VSS. The DAC has a separate analog power supply and return, AV

3.3 volt AV

input allows the user to provide a

and AVSS. The

separate well filtered supply for the DAC to prevent spurs that might be created from digital noise on the V

supply system.

FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS

OVERVIEW

The STEL-1109 is comprised of the Data Path and Control Unit sections shown in Figure 1. The Data Path is comprised of a Bit Sync Block, Bit Encoder Block (i.e.,Êthe Scrambler, Reed-Solomon Encoder, and two Multiplexers shown in Figure 2), Symbol Mapper Block (i.e., the Bit Mapper, Differential Encoder, and Symbol Mapper are shown in FigureÊ5), two channels (one for I and one for Q), a Combiner, and a 10-bit DAC. Each channel consists of a Nyquist Filter, Interpolation Filter, and Modulator. The Control Unit is comprised of a Bus Interface Unit (BIU), Clock Generator, and NCO.

Table 3. STEL-1109 Configuration Register Data Fields

Address Contents

(Hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

08 - 00

28 - 09

Interpolation Filter Gain Control

Set To Zero Set To Zero

TCLK Sel.

FZSINB

Set To Zero Set To Zero Set To Zero

Symbol Mapping

LSB Sampling Rate Control (see address 39 for MSB)

Interpolation Filt. Bypass

Bit Mapping

FIR Filter Coefficients

Table 1 summarizes the main features of the circuits described by the remaining paragraphs of this section.

The STEL-1109 provides 58, programmable, read/write registers (Configuration Registers). Table 3 provides a graphic representation of the STEL-1109Õs Configuration Registers and their data fields. Each register can be selected for a write or read operation using addresses 00H through 39H.

NCO

Invert I/Q Chan.

Set To One Set To Zero

MOD

Set To One Set To Zero

CLRFIR

Auxiliary Clock Rate Divider

FIR bypass

PN Code Sel9PN On/Off

Set To Zero

Bit Sync Re-arm

32-30

35-33

PPolynomial

DATAENBPB10DATAENSEL10RSENBPB10RSENSEL10SCRMENBPB10SCRMENSEL10DiffDCBPB14DiffDCSEL

39 Set To Zero Set To Zero

BypassB

S-RS

TRLSBF

Set To Zero

SCRAMBLER Init Registers

SCRAMBLER Mask Registers

Self-Sync

LDLSBF

MSB Sampling Rate Control (see address 29 for LSB)

Note: Superscripted numbers are page references where discussion on setting the particular register(s)

or bit(s) begins.

STEL-1109 8 PRELIMINARY PRODUCT INFORMATION

DIFFEN TCLK

TSDATA

DATAEN RDSLEN

SCRMEN

RST

CLKEN CLK

NCO LD FCWSEL

DATA

7-0

ADDR

5-0

DSB WR CSEL

1-0

BIT

Sync

Block

BIT

Encoder

Block

Clock

Generator

Bus

Interface

Unit

[1:0]

SAMPLS

MASTER CLOCK

Symbol Mapper

Block

Numerically

Controlled

Oscillator

[1:0] 2

[1:0]

Nyquist

Filter

Nyquist

Filter

Interpolating

Filter

Interpolating

Filter

COS 2πFT

DATA PATH

Modulator

SIN 2πFT

10-Bit

DAC

OUT OUTN

DATAENO

CKSUM

BITCLK SYMPLS ACLK

Figure 1. STEL-1109 Block Diagram

DATA PATH DESCRIPTION

BIT SYNC BLOCK

The Bit Sync Block has two functions, latching input data, and synchronizing the STEL-1109 BITCLK and symbol counters to the user data.

Latching Input Data

Latching of input data is accomplished in three ways:

• Externally supplied TSDATA is latched by the

internal BITCLK.

Table 4. Data Latching Options

Data Source Latched By Register 2C Bit 7 Register 2D Bits 1,0 Mode Name

TSDATA BITCLK 0 X,0 Master Mode TSDATA TCLK 1 X,0 Slave Mode PN Code 10, 3 BITCLK 0 0,1 Test Mode PN Code 23, 18 BITCLK 0 1,1 Test Mode

CONTROL UNIT

WCP 52981.c-5/2/97

• Externally supplied TSDATA is latched by an

externally provided TCLK

• Internally generated PN code data is latched by the

internal BITCLK

See Table 4 for register settings to implement each mode.

PRELIMINARY PRODUCT INFORMATION 9 STEL-1109

BITCLK latches data on its falling edge. TCLK latches data on its rising edge.

Whenever the CLKEN input is low, the BITCLK output will stop. In order to provide customers with a continuous clock, the STEL-1109 provides an auxiliary clock (ACLK) output which is discussed later in the clock generator section. The ACLK output is primarily for use in master mode where users may need a clock to run control circuits during the guard time between bursts.

When using slave mode, the data that is latched by the rising edge of TCLK is re-latched internally by the next falling edge of BITCLK which re-synchronizes the data to the internal master clock.

Synchronizing BITCLK / SYMPLS

The synchronization circuit aligns the STEL-1109 BITCLK and its SYMPLS counter circuits to the beginning of the first user data symbol. The circuit has two parts, an arming circuit and a trigger circuit. Once armed, the first rising edge on the TCLK input will activate (trigger) the synchronization process.

The circuit can be armed in two ways; taking CLKEN from low to high, or toggling Configuration Register 2EH bit 0 from low to high to low again. In a normal burst mode application, the circuit is automatically rearmed between bursts because CLKEN goes low. For applications that will not allow CLKEN to cycle low between bursts, some system level precautions should be observed to maintain synchronization of user data to the STEL-1109 BITCLK.

Once triggered, the sync circuit re-starts the BITCLK and SYMPLS counters. The BITCLK output starts high, and SYMPLS resets to the start of a symbol. There is a delay equal to about three cycles of the master clock from the rising edge of the TCLK input before this restart occurs. During this brief delay period, the BITCLK and SYMPLS counters are still free running and may or may not have transitions.

BIT ENCODER BLOCK

The Bit Encoder Block consists of a Scrambler, a Reed-Solomon Encoder, and data path controls (multiplexers), as shown in Figure 2.

SCRMEN

Input

Multiplexer

Scrambler

Reed-Solomon

Encoder

ENCODED SERIAL DATA

Output

Multiplexer

CHKSUM SIGNAL

WCP 52982.c-4/26/97

SERIAL DATA

DATAEN

RDSLEN

S-RS

Figure 2. Bit Encoder Functional Diagram

Data Path Control (Multiplexers)

The STEL-1109 provides a great deal of flexibility and control over the routing of data through or around the encoding functions. With appropriate register selections, data can be routed around (bypass) both encoders, through either one and around the other, through the scrambler then the RS Encoder, or through the RS Encoder and then the scrambler. Control over the bypassing can be set for software control or external (user) input signal control. Generally, if an encoding function will be left either on or off continuously, then software control is appropriate. If the function must be turned on and off dynamically (typically in order to send the preamble Ôin the clearÕ i.e. unencoded), then external (user) input control is required. If the ReedSolomon encoder will not be used at all, then a separate bypass option can be activated to remove an 8 bit delay register from the data path that is required if the possibility of turning on the encoder exists. Each of the external (user) input control pins (if enabled) turns on the encoding function when high and bypasses the function when low.

In master mode, the rising edge of TCLK normally marks the transition of the first user data bit (which will be latched in by the next falling edge of BITCLK). In slave mode, the first user data bit must already be valid at this first rising edge of TCLK.

The DATAEN input signal determines whether or not data will advance (shift through) the encoding blocks. The presence of a high on the DATAEN input when the BITCLK output goes low allows the circuits to advance data through them. The DATAEN signal is delayed

STEL-1109 10 PRELIMINARY PRODUCT INFORMATION

internally to allow the rising edge of DATAEN to coincide with the first rising edge of TCLK.

Table 5. BIT Encoding Data Path Options

Data Path Register 36 Bits 6,5 Register 38 Bits 7-2

Data stopped (continuously) X,X 01 XXÊXX Data path on (continuously) X,X 11 XXÊXX Data path enabled by pin 18 X,X X0 XXÊXX Scrambler off (continuously) X,X XX XX 01 Scrambler on (continuously) X,X XX XX 11 Scrambler enabled by pin 32 X,X XX XX X0 RS Encode off (continuously) 1,X XX 01 XX RS Encode on (continuously) 1,X XXÊ11 XX RS Encode enabled by pin 29 1,X XXÊX0 XX Scrambler then RS Encoder 1,1 XXÊXXÊXX RS Encoder then Scrambler 1,0 XXÊXXÊXX Bypass RS Encoder 0,X XXÊXXÊXX

Scrambler

The scrambler can be used to randomize the serial data in order to avoid a strong spectral component that might otherwise arise from the occurrence of repeating patterns in the input data. The Scrambler (Figure 3) uses a Pseudo-Random (PN) generator to generate a PN code pattern. All 24 registers are presettable and any combination of the registers can be connected (tapped) to form any polynomial of up to 24 bits. The scrambler may be either frame synchronized or self synchronized. Table 6 shows the registers involved.

See Table 5 for a summary of register settings required to achieve the various data path possibilities.

24-bit Mask Reg

24-bit INIT Reg

24-bit Shift Reg

123 222324

XOR

The value in the INIT registers is loaded into the scrambler shift registers whenever the scrambler is disabled. The scrambler will scramble data one bit at a time at each falling edge of BITCLK that occurs while both the scrambler and DATAEN are active (enabled).

SCRMEN SERIAL INPUT

SSYNC

AND

XOR

SELF SYNC

MUX

FRAME SYNC

SERIAL OUTPUT

WCP 52983.c-4/26/97

Internal delays on the SCRMEN control signal input allow for a rising edge to occur coincident with the

Figure 3. Scrambler Block Diagram

rising edge of BITCLK that precedes the latching of the first data bit to be scrambled.

Table 6. Scrambler Parameters

Parameter Characteristic Configuration Register Setting

Generator Polynomial (Mask Reg)

Seed (INIT Reg)

Scrambler Type

p(x) = c24x24 + c23x23 + É + c1x + 1 where c

Any 24 bit binary value, s

is a binary value (0, 1)

24-1

to c

to s

Frame synchronized (sidestream) Register 36 Bit 4

Set to zero

to c

to s

Scrambler Self-synchronized Register 36 Bit 4

PRELIMINARY PRODUCT INFORMATION 11 STEL-1109

Type

The Mask, Init, and SSync fields can be programmed for different scrambler configurations. For example, the DAVIC Scrambler configuration shown in FigureÊ4 can

Table 7. Sample Scramble Register Values

Parameter Characteristic Configuration Register Setting

Generator Polynomial (Mask Reg)

Seed (INIT Reg)

Scrambler Type

p(x) = x15 + x14 + 1 Register 35

0000A9 Hex Register 32

Frame synchronized (sidestream) Register 36 Bit 4

Reed - Solomon Encoder

The STEL-1109 uses a standard Reed-Solomon (RS) Encoder for error correction encoding of the serial data stream.

When DATAEN is high and the RS Encoder is enabled, the serial data stream both passes straight through the RS Encoder and also into encoding circuitry. The encoding circuitry computes a checksum that is 2T bytes long for every k bytes of input data. After the last bit of each block of k bytes of input data, the RS Encoder inserts its checksum (2T bytes of data) into the data path. There is no adverse effect to letting TCLK or TSDATA continue to run during the checksum; the data input will be ignored. CKSUM (pin 35) will be asserted high to indicate that the checksum bytes are being inserted into the data stream and will be lowered at the end of the checksum data insertion. The width of the CKSUM pulse is 2T bytes.

The STEL-1109 registers include two bits for determining the bit order for data into and checksum out of the RS Encoder circuitry. Set these to match the

Set to one

be implemented by programming the Mask, Init, and SSync fields with the values indicated by Table 7.

Bit 7 to Bit 0 0000Ê0000

Set to zero

Reed-Solomon decoding circuitry along with the other parameters.

The error correction encoding uses GF (256) and can be programmed for an error correction capability of 1 to 10, a block length of 3 to 255, and one of two primitive polynomials using the data fields listed in Table 8.

100101010000000

123456789101112131415

EX-OR

Enable

AND

EX-OR

Clear Data Input

Randomized Data

WCP 52984.c-4/26/97

Figure 4. DAVIC Scrambler

STEL-1109 12 PRELIMINARY PRODUCT INFORMATION

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