INTEL STEL-1108 User Manual

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STEL-1108

Data Sheet

STEL-1108/CR

126 MHz BPSK/QPSK

Digital Modulator

R

TCP 960257

TABLE OF CONTENTS

FEATURES/BENEFITS ................................................................................................................ 3

BLOCK DIAGRAM....................................................................................................................... 3

PACKAGE OUTLINE................................................................................................................... 4

PIN CONFIGURATION................................................................................................................ 4

INTRODUCTION......................................................................................................................... 5

FUNCTION BLOCKS – DESCRIPTION......................................................................................... 6

Clock Generator Block ...................................................................................................... 6

Input Data Processor Block................................................................................................ 6

FIR Filter Block................................................................................................................. 6

Interpolating Filter Block................................................................................................... 6

Frequency Control Word Buffer Block................................................................................ 6

Phase Accumulator & Sine/Cosine Lookup Table Block...................................................... 6

Complex Modulator Block................................................................................................. 6

Adder Block..................................................................................................................... 6

INPUT SIGNAL DESCRIPTIONS.................................................................................................. 7

OUTPUT SIGNAL DESCRIPTIONS............................................................................................... 9

MODE CONTROL REGISTERS..................................................................................................... 10

DECIMAL, HEX AND BINARY ADDRESS EQUIVALENTS ........................................................... 13

REGISTER SUMMARY................................................................................................................. 14

ELECTRICAL CHARACTERISTICS............................................................................................... 15

ABSOLUTE MAXIMUM RATINGS................................................................................... 15

RECOMMENDED OPERATING CONDITIONS................................................................. 15

D.C. CHARACTERISTICS................................................................................................. 15

FREQUENCY CHANGE AND OUTPUT TIMING.............................................................. 16

REGISTER WRITE TIMING............................................................................................... 16

INPUT DATA AND CLOCK TIMING ............................................................................... 17

BURST MODE TIMING.................................................................................................... 19

RECOMMENDED INTERFACE CIRCUIT...................................................................................... 21

SYNCHRONIZING THE 1108 BIT CLOCK .................................................................................... 21

STEL-1108 2

FEATURES

BENEFITS

■ Complete BPSK/DBPSK/QPSK/DQPSK

modulator in a CMOS ASIC

■ Operates at up to 6.3 Mbps in BPSK mode

and up to 12.6 Mbps in QPSK mode.

■ Programmable over a wide range of data

rates

■ NCO modulator provides fine frequency

resolution

■ 126 MHz maximum clock rate generates

modulated carrier at frequencies to 50 MHz

■ Eliminates most analog circuitry

■ Operates in continuous and burst mode

■ Selectable 10- or 12-bit outputs

■ 32-tap FIR filter for signal shaping before

modulation

■ 80-Pin MQFP Package

■ High performance and high reliability with

reduced manufacturing costs

■ Supports data rates for voice and other

applications

■ Supports multiple data rate applications

■ Rapidly retunable to any frequency in the

operating band

■ Simplifies upconversion of signal to higher

frequencies

■ Low cost, small, allows quick prototyping

■ Optimizes performance in all modes

■ Optimum interfacing to suitable DAC

■ Optimum spectral purity of output

minimizes external filtering

■ Small Footprint, Surface Mount

BLOCK DIAGRAM

3 STEL-1108

PACKAGE OUTLINE

WCP 51833.c-8/21/96

Top View

Pin 1 Identifier

0.012"/0.018"0.0315"

±0.008"

65

64

80

1

40

41

24

25

0.130" max.

Note: Tolerance on pin spacing is not cumulative

Package style: 80-pin MQFP. Thermal coefficient, θja = 58° C/W

Detail of pins

0.01" max.

0.029"/

0.041"

0.551"

± 0.008"

0.677"

± 0.008"

0.913"

±0.008"

0.787"

±0.008"

PIN CONFIGURATION

1 V

DD

2 DATA
3 DATA
4 DATA
5 DATA
6 V
7 V
8 ADDR
9 ADDR
10 ADDR
11 V
12 ADDR
13 ADDR
14 ADDR
15 V
16 V

SS
SS

DD

SS
SS

4
5
6
7

5
4
3

2
1
0

Notes: I.C. denotes Internal Connection. Do not use for vias.

17 TSDATA
18 DATAENI
19 TCLK
20 FCWSEL
21 FCWSEL
22 I.C.
23 I.C.
24 I.C.
25 V
26 CLKEN
27 V
28 CLK
29 NC
30 V
31 5V
32 N.C.

DD

SS

DD

DD

0
1

33 V

SS

34 I.C.
35 I.C.
36 I.C.
37 ACLKOUT
38 V

DD

39 DATAENO
40 BITCLK
41 V

DD

42 RFCLK
43 V

SS

44 RFDATA
45 RFDATA
46 V

SS

47 RFDATA
48 RFDATA

49 V
50 RFDATA
51 V
52 RFDATA
53 V
54 RFDATA
55 V
56 RFDATA
57 RFDATA
58 V
59 RFDATA

0
1

60 RFDATA
61 V
62 RFDATA

2
3

63 V
64 V

SS

DD

SS

SS

SS

SS

DD
SS

––––––––

65 RFCLKD

4

5

66 V

––––––

67 RESET
68 RFCLKD
69 V

6

7
8

70 DIFFEN
71 NCO LD

–––––

72 CSEL

–––

73 WR

SS

SS

74 I.C.

9
10

11

75 V

DD

76 DATA
77 DATA
78 DATA
79 DATA
80 V

SS

0
1
2

3

STEL-1108 4

INTRODUCTION

The STEL-1108 is a BPSK/QPSK modulator in a single
ASIC.* It is capable of operating at data rates up to

6.3 Mbps in BPSK mode and 12.6 Mbps in QPSK
mode. The STEL-1108 will operate at a clock
frequency of up to 126 MHz, allowing it to generate
output signals at carrier frequencies up to 50 MHz.
The STEL-1108 uses digital FIR filtering to optimally
shape the spectrum of the modulating data prior to
modulation, thereby optimizing the spectrum of the
modulated signal while minimizing the analog
filtering required after the modulator. The filters are
designed to have a symmetrical (mirror image)
polynomial transfer function, thereby making the
phase response of the filter linear and eliminating
inter symbol interference as a result of group delay
distortion. In this way it is possible to change the
carrier frequency over a wide range without having to

*The STEL-1108 utilizes advanced signal processing
techniques which are covered by U.S. Patent Number
5,412,352.

change filters, providing the ability to operate a single
system in many channels. Signal level scaling is
provided after the FIR filter to allow the maximum
dynamic range of the arithmetic to be utilized since
the signal levels can be changed over a wide range
according to how the device is programmed. To
facilitate interfacing the STEL-1108 to a Digital to
Analog Converter (DAC) an output clock with
programmable delay is provided. In addition, the
STEL-1108 is designed to operate from a 3.3 volt
power supply; provision is made to allow the device
to interface with other logic operating at 5 volts.

See Application Note 125 for example calculations of
control register values.

5 STEL-1108

FUNCTION BLOCKS – DESCRIPTION

Clock Generator Block

The timing of the STEL-1108 is controlled by the Clock
Generator Block. This block generates all the clocks
required in the device from the CLK input, as well as
the output clocks. The divider which determines the bit
rate, symbol rate and sampling rate of the FIR filter is
programmed by the data “n” written into address 29H,
with the sampling frequency set to f

/(n+1), where n

CLK

can be from 4 to 255. A second divider is used to
generate the auxiliary output clock (ACLKOUT) from
the clock input. This divider is controlled by the data,
“n”, stored in bit 3-0 in address 2AH, with the frequency
set to f

/(n+1), where n can be from 2 to 15. Of all

CLK

the clock signals generated, only the auxiliary clock
continues to run when the clock enable is low. The bit
clock output runs at twice the symbol rate, even in
BPSK mode.

Input Data Processor Block

The STEL-1108 is designed to operate as a BPSK, QPSK,
DBPSK or DQPSK modulator according to the setting of
bit 3 in address 2CH and the DIFFEN input. When
operating in QPSK mode the input data processor
assembles pairs of data bits for each symbol to be
modulated. The symbol data can then be differentially
encoded in a way which depends on whether the
modulation format is to be DBPSK or DQPSK. For
DBPSK, the encoding algorithm is straightforward:

output bit(k) = input bit(k) ⊕ output bit(k–1),
where ⊕ represents the logical EXOR function. For

DQPSK, however, the differential encoding algorithm is
more complex since there are now sixteen possible new
states depending on the four possible previous output
states and four possible new input states, as shown in
the table below:

New Input Previously Encoded OUT(I, Q)
IN(I, Q)

k

0 0 0 1 1 1 1 0

k–1

0 0 0 0 0 1 1 1 1 0
0 1 0 1 1 1 1 0 0 0
1 1 1 1 1 0 0 0 0 1
1 0 1 0 0 0 0 1 1 1

Newly Encoded OUT(I, Q)

k

FIR Filter Block

The encoded data is filtered to minimize the sidelobes of
its spectrum using a 32-tap, linear phase FIR filter. The
10-bit filter coefficients are completely programmable
for any symmetrical (mirror image) polynomial and are
stored in the registers at addresses 09H to 28H, giving
the user full control (apart from the symmetry
constraint) of the filter response. The clock (sampling)

frequency of the FIR filter is set to be four times the
symbol rate. This frequency is determined by the data,
“n”, written into address 29H, with the sampling
frequency set to f

/(n+1), where n can be from 4 to

CLK

255.

Interpolating Filter Block

The output of the FIR filter is interpolated up to the
clock frequency, f

, in a one, two or three stage

CLK

interpolating filter. Since the gain of the integrators in
the interpolating filter can vary over a wide range, a
gain control function is provided at its input to select
the significance of the 14-bit outputs of the FIR filter
relative to the 24-bit inputs of the interpolating filter.
This level shift function is controlled by the data stored
in bit 7-4 in address 2AH.

Frequency Control Word Buffer Block

The STEL-1108 incorporates a Numerically Controlled
Oscillator (NCO) to synthesize the carrier in the mod­ulator. The frequency of the NCO is programmed by
means of the Frequency Control Word (FCW) registers
at addresses 00H through 08H. The STEL-1108
incorporates provision for three separate FCWs (FCW
A, FCW B and FCW C) to be stored in these registers.
The modulator frequency can be switched between
these values by means of the FCWSEL

inputs. The

1-0

fourth setting of this 2-bit input selects a zero-frequency
value, causing the modulator output to stop instantly at
its current phase.

Phase Accumulator and Sine/Cosine
Lookup Table Block

The 24-bit NCO gives a frequency resolution of
approximately 6 Hz at a clock frequency of 100 MHz.
The 12-bit sine and cosine lookup tables (LUTs)
synthesize a carrier with very high spectral purity, typi­cally better than 75 dBc at the digital outputs.

Complex Modulator Block

The interpolated I and Q data signals are fed into the
Complex Modulator Block to be multiplied by the sine
and cosine carriers from the Sin/Cos LUT Block.

Adder Block

The modulated sine and cosine carriers are fed into the
Adder Block where they are either added or subtracted
together to form the sum:

Sum = ± I

.

cos(ωt) ± Q

The signs of the I and Q components can be controlled
by the settings of bits 0 and 1 in address 2BH, giving
complete control over the characteristics of the RF signal
generated.

.

sin(ωt)

STEL-1108 6

INPUT SIGNAL DESCRIPTIONS

–––––––

RESET

Reset. RESET

clears or presets all registers when it is set low. Setting

––––––

RESET

the STEL-1108 is powered up, it is necessary to assert
the RESET
configuring the chip.

CLK (Pin 28)

Master Clock. CLK is the master clock of all the blocks.
Its frequency must be an integer multiple of four times
the data rate used (i.e., an integer multiple of the FIR
Filter sampling rate) so that the programmable binary
divider in the Clock Generator Block can generate the
bit clock from the CLK signal.

CLKEN (Pin 26)

Clock Enable. CLKEN provides a gate to control the
master clock. Setting CLKEN low will disable all
functions in the STEL-1108 (except for the auxiliary
clock output) by stopping the clock internally, thereby
reducing the power consumption almost to the static
level. Setting CLKEN high enables normal operation.
When bit 7 is set high in address 2CH, the STEL-1108
will be configured to operate with an externally
provided data clock, TCLK. When CLKEN is set high
BITCLK will be resynchronized to the first rising edge
of TCLK after the rising edge of CLKEN.

CAUTION: CLKEN must be held low con­tinuously while programming addresses 2AH and

2BH. Failure to do so will cause the interpolator
to lock up, requiring the STEL-1108 to be reset

before normal operation resumes.

––––

WR

Write. WR
DATA

by the ADDR
data on the DATA
goes high again.

DATA

Data Bus. DATA

bus that provides access to all internal mode control
register inputs for programming. DATA
conjunction with WR
information into the control and coefficient registers.

ADDR

Address Bus. ADDR
selects the mode control register location into which the
information provided on the DATA
written. ADDR

DATA

coefficient registers.

(Pin 67)

––––––

is the master reset of the STEL-1108 and

high enables operation of the circuitry. After

––––––

pin low for greater than 100 nS prior to

(Pin 73)

–––

is used to control the writing of data to the

bus. When WR

7-0

(Pins 2 - 5, 76 - 79)

7-0

(Pins 8 - 10, 12 - 14)

5-0

to write the information into the control and

7-0

–––

is set low the register selected

lines will become transparent and the

5-0

bus will be latched in when WR

7-0

is an 8-bit microprocessor interface

7-0

is used in

–––

and ADDR

is a 6-bit address bus that

5-0

is used in conjunction with WR

5-0

7-0

to write the

5-0

bus will be

7-0

–––

–––

and

––––––

CSEL

(Pin 72)

Chip Select. CSEL
the microprocessor operation of the STEL-1108. When

–––––
CSEL

is set high all write operations are disabled.

–––––

When CSEL

–––––

is provided to enable or disable

is set low the data bus become active and

write operations are enabled.

NCO LD (Pin 71)

NCO Load Input. The frequency control word selected
by the FCWSEL

inputs will be loaded into the NCO

1-0

on the rising edge of NCO LD. This function is also
executed automatically each time the DATAENI input
is set high. There is a pipeline delay of 16 CLK cycles
from the rising edges of both NCO LD and
DATAENI to the point where the NCO outputs are
multiplied by the modulating signal in the Modulator
Block. There is a further pipeline delay of 11 CLK
cycles to the output pins, making a total of 27 CLK
cycles from the load command to the output.

FCWSEL

(Pins 20, 21)

1-0

Frequency Control Word Select. FCWSEL
input that permits the selection of one of four frequency
control words for the NCO. In this way the NCO can be
rapidly switched between these four frequencies
without having to reload the FCW data in the FCW
registers. The FCW is selected as follows:

FCWSEL

1-0

FCW data register/addresses

00 FCW ’A’
01 FCW ’B’
10 FCW ’C’
11 FCW = 0 (zero frequency)

Whenever FCWSEL

is changed the NCO frequency

1-0

will change after the NCO is reloaded with a rising edge
on either the NCO LD or the DATAENI inputs.. When

FCWSEL

= 11 the FCW data is unconditionally set to

1-0

00 00 00 00H, setting the NCO to zero frequency. When
this occurs the NCO output will remain at its current
phase value until FCWSEL

is changed and the NCO

1-0

is reloaded.

DATAENI (Pin 18)

Data Enable Input. The DATAENI input is used to
signify the beginning and end of a burst of data. It
should be set high before the first (when the STEL-1108
is configured for BPSK modulation by setting bit 3 in
address 2CH high) or second (when the STEL-1108 is
configured for QPSK modulation by setting bit 3 in
address 2CH low) falling edge of BITCLK (the edge on
which the Q-channel bit is loaded in the QPSK mode) of
each burst and set low again after the last falling edge of
BITCLK of each burst. DATAENO will go high after
the first two symbol periods of eachburst. At this time
the NCO will be reloaded according to the current
setting of FCWSEL

1-0

.

is a 2-bit

1-0

7 STEL-1108