Intel SE7320SP2, SE7525GP2 User Manual
®
Intel
Server Board SE7320SP2 &
Intel Server Board SE7525GP2
Technical Product Specification
Revision 2.0
November 2004
Enterprise Platforms and Services Marketing
Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Revision History
Revision History
Date Revision
Number
June 2004 1.0 Initial Release
November 2004 2.0
Updated and clarified memory support, removed LX SKU references, added MTBF
calculations, performed general grammar and spelling updates.
Modifications
Revision 2.0
ii
Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Disclaimers
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
This document contains information on products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is
available. Verify with your local sales office that you have the latest datasheet before finalizing
a design.
The SE7320SP2 and server board SE7525GP2s may contain design defects or errors known
as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
This document and the software described in it is furnished under license and may only be used
or copied in accordance with the terms of the license. The information in this manual is
furnished for informational use only, is subject to change without notice, and should not be
construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or
liability for any errors or inaccuracies that may appear in this document or any software that may
be provided in association with this document.
Except as permitted by such license, no part of this document may be reproduced, stored in a
retrieval system, or transmitted in any form or by any means without the express written consent
of Intel Corporation.
Xeon is a registered trademark of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2004.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
Table of Contents
1. Introduction ........................................................................................................................17
1.1 Chapter Outline...................................................................................................... 17
1.2 Server Board Use Disclaimer ................................................................................ 18
2. Server Board Overview...................................................................................................... 19
2.1 SE7320SP2 SKU Availability................................................................................. 19
2.1.1 SE7320SP2 Feature Set .......................................................................................19
2.2 SE7525GP2 SKU Availability ................................................................................22
2.2.1 SE7525GP2 Feature Set ....................................................................................... 22
3. Functional Architecture .....................................................................................................25
3.1 Processor Sub-system........................................................................................... 27
3.1.1 Processor VRD ...................................................................................................... 27
3.1.2 Reset Configuration Logic .....................................................................................27
3.1.3 Processor Module Presence Detection .................................................................27
3.1.4 GTL2006................................................................................................................ 27
3.1.5 Common Enabling Kit (CEK) Design Support ....................................................... 28
3.1.6 Processor Support ................................................................................................. 28
3.1.6.1 Processor Mis-population Detection.....................................................................29
3.1.6.2 Mixed Processor Steppings...................................................................................29
3.1.6.3 Mixed Processor Models.......................................................................................29
3.1.6.4 Mixed Processor Families.....................................................................................29
3.1.6.5 Mixed Processor Cache Sizes ...............................................................................29
3.1.6.6 Jumperless Processor Speed Settings....................................................................30
3.1.6.7 Microcode .............................................................................................................30
3.1.6.8 Processor Cache....................................................................................................30
3.1.6.9 Hyper-Threading Technology...............................................................................30
3.1.6.10 Intel® SpeedStep® Technology ...........................................................................30
3.1.6.11 EM64T Technology Support ..............................................................................30
3.1.6.12 Execute Disable Bit support................................................................................30
3.1.7 Multiple Processor Initialization .............................................................................31
3.1.8 CPU Thermal Sensors........................................................................................... 31
3.1.9 Processor Thermal Control Sensor .......................................................................31
3.1.10 Processor Thermal Trip Shutdown ........................................................................ 31
3.1.11 Processor IERR .....................................................................................................31
3.2 E7320 Chipset ....................................................................................................... 32
3.2.1 Memory Controller Hub (MCH) .............................................................................. 32
3.2.1.1 Front Side Bus (FSB)............................................................................................32
3.2.1.2 MCH Memory Sub-System Overview..................................................................32
3.2.1.3 PCI Express*.........................................................................................................33
3.2.1.4 Hub Interface ........................................................................................................33
3.3 E7525 Chipset ....................................................................................................... 33
3.3.1 Memory Controller Hub (MCH) .............................................................................. 34
3.3.1.1 Front Side Bus (FSB)............................................................................................34
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
3.3.1.2 MCH Memory Sub-System Overview..................................................................34
3.3.1.3 PCI Express*.........................................................................................................34
3.3.1.4 Hub Interface ........................................................................................................35
3.4 Intel® 6300ESB ICH .............................................................................................. 35
3.4.1 PCI Interface.......................................................................................................... 35
3.4.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode).................... 36
3.4.3 SATA Controller..................................................................................................... 36
3.4.4 Low Pin Count (LPC) Interface .............................................................................. 36
3.4.5 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) ..... 36
3.4.6 Advanced Programmable Interrupt Controller (APIC) ........................................... 37
3.4.7 Universal Serial Bus (USB) Controller ................................................................... 37
3.4.8 RTC .......................................................................................................................37
3.4.9 GPIO...................................................................................................................... 37
3.4.10 Enhanced Power Management ............................................................................. 37
3.4.11 System Management Bus (SMBus 2.0)................................................................. 37
3.5 Memory Sub-System ............................................................................................. 38
3.5.1 Memory Sizing .......................................................................................................38
3.5.2 Memory Population................................................................................................ 39
3.5.3 I2C Bus ..................................................................................................................42
3.5.4 Disabling DIMMs.................................................................................................... 42
3.5.5 Memory RASUM Features..................................................................................... 42
3.5.5.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC).................43
3.5.5.2 Integrated Memory Scrub Engine.........................................................................43
3.5.5.3 Retry on Uncorrectable Error................................................................................43
3.5.5.4 Integrated Memory Initialization Engine..............................................................44
3.5.5.5 DIMM Sparing Function.......................................................................................44
3.6 I/O Sub-System .....................................................................................................45
3.6.1 PCI Subsystem ......................................................................................................45
3.6.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem ...............................................................45
3.6.1.2 P64-A: 64-bit, 66MHz PCI Subsystem.................................................................46
3.6.1.3 P64-Express4: x4 PCI-Express Bus Segment.......................................................46
3.6.1.4 P64-Express16: x16 PCI-Express bus segment ....................................................46
3.6.1.5 Scan Order ............................................................................................................46
3.6.1.6 Resource Assignment............................................................................................46
3.6.1.7 Automatic IRQ Assignment..................................................................................46
3.6.1.8 Option ROM Support............................................................................................46
3.6.1.9 PCI APIs ...............................................................................................................46
3.6.2 Split Option ROM................................................................................................... 47
3.6.3 Interrupt Routing .................................................................................................... 47
3.6.3.1 Legacy Interrupt Routing......................................................................................47
3.6.3.2 APIC Interrupt Routing.........................................................................................47
3.6.3.3 Legacy Interrupt Sources ......................................................................................47
3.6.3.4 Serialized IRQ Support .........................................................................................48
3.6.3.5 IRQ Scan for PCIIRQ ...........................................................................................48
3.6.4 IDE Support ........................................................................................................... 51
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3.6.4.1 Ultra ATA/100 ......................................................................................................51
3.6.4.2 IDE Initialization ..................................................................................................51
3.6.5 SATA Support........................................................................................................ 51
3.6.5.1 SATA RAID .........................................................................................................51
3.6.5.2 Intel® RAID Technology Option ROM ...............................................................52
3.6.6 Video Controller ..................................................................................................... 52
3.6.6.1 Video Modes.........................................................................................................53
3.6.6.2 Video Memory Interface.......................................................................................53
3.6.7 Network Interface Controller (NIC) ........................................................................ 54
3.6.7.1 Intel 82541 ............................................................................................................54
3.6.7.2 NIC Connector and Status LEDs ..........................................................................54
3.6.8 USB 2.0 Support.................................................................................................... 54
3.6.9 Super I/O Chip ....................................................................................................... 55
3.6.9.1 GPIOs....................................................................................................................56
3.6.9.2 Serial Ports............................................................................................................57
3.6.9.3 Floppy Disk Controller .........................................................................................57
3.6.9.4 Keyboard and Mouse ............................................................................................57
3.6.9.5 Wake-up Control...................................................................................................57
3.6.10 BIOS Flash ............................................................................................................57
3.7 Configuration and Initialization............................................................................... 58
3.7.1 Memory Space....................................................................................................... 58
3.7.1.1 DOS Compatibility Region...................................................................................59
3.7.1.2 Extended Memory.................................................................................................60
3.7.1.3 Memory Shadowing..............................................................................................62
3.7.1.4 System Management Mode Handling...................................................................62
3.7.2 I/O Map ..................................................................................................................63
3.7.3 Accessing Configuration Space............................................................................. 65
3.7.3.1 CONFIG_ADDRESS Register .............................................................................66
3.8 Clock Generation and Distribution .........................................................................68
3.8.1 Real Time Clock ....................................................................................................68
4. System BIOS.......................................................................................................................69
4.1 BIOS Identification String....................................................................................... 69
4.2 BIOS POST Splash Screen ................................................................................... 70
4.2.1 User Interface ........................................................................................................ 70
4.2.1.1 System State Window...........................................................................................70
4.2.1.2 Logo/Diagnostic Window.....................................................................................70
4.2.1.3 Current Activity Window .....................................................................................71
4.2.1.4 System Diagnostic Screen.....................................................................................71
4.2.1.5 Static Information Display....................................................................................71
4.3 BIOS Setup Utility ..................................................................................................72
4.3.1 Localization............................................................................................................ 72
4.3.2 Console Redirection ..............................................................................................72
4.3.3 Configuration Reset ............................................................................................... 72
4.3.4 Keyboard Commands ............................................................................................ 73
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4.4 Entering BIOS Setup .............................................................................................74
4.4.1 Main Menu .............................................................................................................74
4.4.2 Advanced Menu..................................................................................................... 75
4.4.2.1 Processor Configuration Sub-menu ......................................................................76
4.4.2.2 IDE Configuration Sub-menu...............................................................................77
4.4.2.3 Floppy Configuration Sub-menu ..........................................................................80
4.4.2.4 Super I/O Configuration Sub-menu......................................................................80
4.4.2.5 USB Configuration Sub-menu..............................................................................80
4.4.2.6 USB Mass Storage Device Configuration Sub-menu...........................................81
4.4.2.7 PCI Configuration Sub-menu ...............................................................................82
4.4.2.8 Memory Configuration Sub-menu........................................................................83
4.4.3 Boot Menu .............................................................................................................84
4.4.3.1 Boot Settings Configuration Sub-menu Selections...............................................84
4.4.3.2 Boot Device Priority Sub-menu Selections ..........................................................85
4.4.4 Security Menu........................................................................................................ 86
4.4.5 Server Menu .......................................................................................................... 87
4.4.5.1 System Management Sub-menu Selections..........................................................88
4.4.5.2 Serial Console Features Sub-menu Selections......................................................89
4.4.5.3 Event Log Configuration Sub-menu Selections ...................................................89
4.4.6 Exit Menu............................................................................................................... 90
4.5 Flash Update Utility................................................................................................ 90
4.6 Rolling BIOS and On-line Updates ........................................................................ 91
4.7 Flash Update Utility................................................................................................ 91
4.7.1 Flash BIOS ............................................................................................................92
4.7.1.1 Updating the BIOS from DOS..............................................................................92
4.7.1.2 Updating the BIOS from Microsoft* Windows* 2000/2003/XP .........................92
4.7.1.3 Updating the BIOS from Linux ............................................................................92
4.7.1.4 Updating the BIOS from the EFI Shell.................................................................93
4.7.2 User Binary Area ...................................................................................................93
4.7.3 Recovery Mode...................................................................................................... 93
4.7.3.1 BIOS Recovery .....................................................................................................93
4.7.3.2 Multi-disk Recovery .............................................................................................94
4.7.4 Update OEM Logo .................................................................................................95
4.7.4.1 Changing the OEM logo for DOS ........................................................................95
4.7.4.2 Changing the OEMlogo for Microsoft* Windows* 2000/2003/XP.....................96
4.8 OEM Binary ...........................................................................................................96
4.9 Operating System Boot, Sleep, and Wake ............................................................ 97
4.9.1 Microsoft* Windows* Compatibility ........................................................................ 97
4.9.2 Advanced Configuration and Power Interface (ACPI) ........................................... 98
4.9.3 Sleep and Wake Functionality ............................................................................... 99
4.9.4 Power Switch Off to On ......................................................................................... 99
4.9.5 On to Off (OS absent)............................................................................................ 99
4.9.6 On to Off (OS present)........................................................................................... 99
4.9.7 System Sleep States .............................................................................................99
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4.10 Security................................................................................................................ 100
4.10.1 Operating Model .................................................................................................. 101
4.10.2 Administrator/User Passwords and F2 Setup Usage Model................................ 102
4.10.3 Password Clear Jumper ......................................................................................103
4.11 Extensible Firmware Interface (EFI) .................................................................... 103
4.11.1 EFI Shell .............................................................................................................. 103
5. Platform Management...................................................................................................... 104
5.1.1 5V Standby .......................................................................................................... 105
5.1.2 IPMI Messaging, Commands, and Abstractions.................................................. 105
5.1.3 IPMI ‘Sensor Model’............................................................................................. 105
5.1.4 Private Management Busses............................................................................... 106
5.1.5 Mini-Baseboard Management Controller ............................................................. 106
5.2 Onboard Platform Instrumentation Features and Functionality ........................... 108
5.2.1 Overview of mBMC.............................................................................................. 108
5.2.2 mBMC Self-test.................................................................................................... 108
5.2.3 SMBus Interfaces ................................................................................................109
5.2.4 External Interface to mBMC................................................................................. 109
5.2.4.1 Private Management I2C Buses..........................................................................109
5.2.5 Messaging Interfaces........................................................................................... 110
5.2.5.1 Channel Management .........................................................................................110
5.2.5.2 User Model..........................................................................................................110
5.2.5.3 Request/Response Protocol.................................................................................110
5.2.5.4 Host to mBMC Communication Interface..........................................................110
5.2.5.5 LAN Interface .....................................................................................................111
5.2.6 Direct Platform Control (IPMI over LAN).............................................................. 112
5.2.6.1 LAN Channel Specifications ..............................................................................113
5.2.6.2 LAN Drivers and Setup ......................................................................................113
5.2.6.3 BIOS Boot Flags .................................................................................................113
5.2.6.4 Boot Flags and LAN Console Redirection .........................................................114
5.2.7 Wake On LAN / Power On LAN and Magic Packet Support................................114
5.2.7.1 Wake On LAN in S4/S5 .....................................................................................114
5.2.8 Watchdog Timer ..................................................................................................114
5.2.9 System Event Log (SEL) ..................................................................................... 114
5.2.9.1 Timestamp Clock................................................................................................114
5.2.10 Sensor Data Record (SDR) Repository ............................................................... 115
5.2.10.1 Initialization Agent ...........................................................................................115
5.2.11 Event Message Reception................................................................................... 115
5.2.12 Event Filtering and Alerting.................................................................................. 115
5.2.12.1 Platform Event Filtering (PEF).........................................................................116
5.2.12.2 Alert over LAN.................................................................................................117
5.2.12.3 System Identification in Alerts .........................................................................118
5.2.12.4 Platform Alerting Setup ....................................................................................118
5.2.12.5 Alerting On Power Down Events .....................................................................118
5.2.12.6 Alerting On System Reset Events.....................................................................118
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5.2.12.7 Alert-in-Progress Termination..........................................................................118
5.2.13 NMI Generation ...................................................................................................118
5.2.14 SMI Generation.................................................................................................... 119
5.3 Platform Management Interconnects................................................................... 119
5.3.1 Power Supply Interface Signals........................................................................... 119
5.3.1.1 Power-up Sequence.............................................................................................120
5.3.1.2 Power-down Sequence........................................................................................120
5.3.1.3 Power Control Sources .......................................................................................120
5.3.2 System Reset Control.......................................................................................... 120
5.3.2.1 Reset Signal Output ............................................................................................120
5.3.2.2 Reset Control Sources.........................................................................................121
5.3.3 Temperature-based Fan Speed Control ..............................................................121
5.3.3.1 Fan Kick Start .....................................................................................................121
5.3.4 Front Panel Control.............................................................................................. 122
5.3.4.1 Power Button ......................................................................................................122
5.3.4.2 Reset Button........................................................................................................122
5.3.4.3 Diagnostic Interrupt Button (Front Panel NMI) .................................................122
5.3.4.4 Chassis ID Button and LED................................................................................123
5.3.4.5 Status/Fault LED.................................................................................................123
5.3.4.6 Chassis Intrusion Switch.....................................................................................124
5.3.4.7 Front Panel Lockout............................................................................................124
5.3.5 Secure Mode Operation....................................................................................... 125
5.3.6 FRU Information ..................................................................................................125
5.3.6.1 mBMC FRU Inventory Area Format..................................................................126
5.4 Sensors................................................................................................................ 126
5.4.1 Sensor Type Codes .............................................................................................126
6. Error Reporting and Handling......................................................................................... 132
6.1 Error Logging ....................................................................................................... 132
6.1.1 Error Sources and Types..................................................................................... 132
6.1.2 SMI Handler......................................................................................................... 132
6.1.2.1 PCI Bus Error......................................................................................................132
6.1.2.2 Processor Bus Error ............................................................................................133
6.1.2.3 Memory Bus Error ..............................................................................................133
6.1.2.4 System Limit Error .............................................................................................133
6.1.2.5 Processor Failure.................................................................................................133
6.1.2.6 Boot Event ..........................................................................................................133
6.1.2.7 Logging Format Conventions .............................................................................133
6.1.3 Single-bit ECC Error Throttling Prevention .......................................................... 134
6.2 Error Messages and Error Codes ........................................................................ 134
6.2.1 POST Error Codes and Messages ...................................................................... 134
6.2.2 Boot Block Error Beep Codes.............................................................................. 137
6.2.3 POST Error Beep Codes ..................................................................................... 138
6.2.3.1 Troubleshooting BIOS Beep Codes....................................................................138
6.2.4 "POST Error Pause" option ................................................................................. 138
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
6.3 Checkpoints ......................................................................................................... 139
6.3.1 System ROM BIOS POST Task Test Point (Port 80h Code)............................... 139
6.3.2 Diagnostic LEDs .................................................................................................. 139
6.3.3 POST Code Checkpoints..................................................................................... 140
6.3.4 Bootblock Initialization Code Checkpoints........................................................... 142
6.3.5 Bootblock Recovery Code Checkpoint ................................................................ 143
6.3.6 DIM Code Checkpoints........................................................................................ 144
6.3.7 ACPI Runtime Checkpoints ................................................................................. 144
6.3.8 Memory Error Codes ...........................................................................................145
6.4 Light Guided Diagnostics..................................................................................... 145
7. Connector Definitions and Pin-Outs .............................................................................. 146
7.1 Main Power Connector ........................................................................................ 146
7.2 Memory Module Connector .................................................................................147
7.3 Processor Socket................................................................................................. 148
7.4 I2C Headers .........................................................................................................151
7.5 PCI Slot Connector ..............................................................................................151
7.6 Front Panel Connector......................................................................................... 155
7.7 VGA Connector.................................................................................................... 156
7.8 NIC Connector .....................................................................................................156
7.9 IDE Connector ..................................................................................................... 157
7.10 SATA Connectors ................................................................................................157
7.11 USB Connector.................................................................................................... 158
7.12 Floppy Connector ................................................................................................159
7.13 Serial Port Connector ..........................................................................................159
7.14 Keyboard and Mouse Connector ......................................................................... 160
7.15 Miscellaneous Headers .......................................................................................160
7.15.1 Fan Header.......................................................................................................... 160
7.15.2 Intrusion Cable Connector ................................................................................... 161
7.15.3 SCSI LED Header................................................................................................ 161
7.16 Configuration Jumpers......................................................................................... 161
7.17 System Recovery and Update Jumpers ..............................................................161
7.18 Rolling BIOS Bank Selection Jumper .................................................................. 162
8. General Specifications..................................................................................................... 164
8.1 Absolute Maximum Ratings ................................................................................. 164
8.2 Mean Time Between Failure (MTBF)................................................................... 164
8.3 Processor Power Support.................................................................................... 164
8.4 Power Supply Specifications ...............................................................................165
8.4.1 Power Timing....................................................................................................... 165
8.4.2 Voltage Recovery Timing Specifications ............................................................. 168
9. Product Regulatory Compliance..................................................................................... 170
9.1 Product Safety Compliance ................................................................................. 170
9.1.1 Product EMC Compliance ...................................................................................170
9.1.2 Mandatory/Standard: Certifications, Registration, Declarations ..........................171
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9.1.3 Product Regulatory Compliance Markings ..........................................................171
9.2 Electromagnetic Compatibility Notices ................................................................ 171
9.2.1 Europe (CE Declaration of Conformity) ............................................................... 171
9.2.2 Australian Communications Authority (ACA) (C-Tick Declaration of Conformity) 171
9.2.3 Ministry of Economic Development (New Zealand) Declaration of Conformity ...171
9.2.4 BSMI (Taiwan) .....................................................................................................171
9.3 Replacing the Back up Battery ............................................................................172
Appendix A: Integration and Usage Tips.............................................................................. 174
Appendix B: Glossary of Terms ............................................................................................ 175
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Figures
List of Figures
Figure 1 - SE7320SP2 Board Layout ............................................................................................20
Figure 2 - SE7525GP2 Board Layout............................................................................................23
Figure 3 – Server Board SE7320SP2 Block Diagram ...................................................................25
Figure 4 –Server Board SE7525GP2 Block Diagram....................................................................26
Figure 5. CEK Processor Mounting...............................................................................................28
Figure 6 - DIMM Socket Configuration ........................................................................................40
Figure 7 - Interrupt Routing Diagram (Intel 6300ESB Internal) ...................................................49
Figure 8 - Interrupt Routing Diagram............................................................................................50
Figure 9 - Intel® Xeon™ Processor Memory address Space........................................................58
Figure 10 - DOS Compatibility Region .........................................................................................59
Figure 11 - Extended Memory Map...............................................................................................61
Figure 12 - CONFIG_ADDRES Register......................................................................................66
Figure 13 - Block Diagram of Platform Managment Architecture..............................................104
Figure 14: mBMC in a Server Management System...................................................................108
Figure 15: External Interfaces to mBMC.....................................................................................109
Figure 16 - IPMI-over-LAN ........................................................................................................112
Figure 17: Power Supply Control Signals ...................................................................................119
Figure 18 - Location of Diagnostic LEDs on Server board (Example only) ...............................139
Figure 19. System Configuration Jumpers (J17) .........................................................................162
Figure 20. BIOS Bank Jumper (J26)............................................................................................162
Figure 21. Output Voltage Timing...............................................................................................166
Figure 22. Turn on / off Timing...................................................................................................168
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Tables
List of Tables
Table 1: server board SE7320SP2 Layout Reference....................................................................21
Table 2: server board SE7525GP2 Layout Reference ...................................................................24
Table 3: Processor Support Matrix ................................................................................................29
Table 4: Supported DDR-266 DIMM Populations........................................................................41
Table 5: Supported DDR-333 DIMM Populations........................................................................41
Table 6: DIMM Module Capacities...............................................................................................41
Table 7: Possible Memory Capacities............................................................................................42
Table 8: PCI Bus Segment Characteristics ....................................................................................45
Table 9: PCI Interrupt Routing/Sharing.........................................................................................47
Table 10: Interrupt Definitions ......................................................................................................48
Table 11: Video Modes..................................................................................................................53
Table 12: Video Memory Interface................................................................................................54
Table 13: Super I/O GPIO Usage Table ........................................................................................56
Table 14: Serial B Header Pin-out.................................................................................................57
Table 15: SMM Space Table .........................................................................................................63
Table 16: I/O Map.........................................................................................................................63
Table 17: PCI Configuration IDs and Device Numbers ................................................................67
Table 18: Sample BIOS Popup Menu...........................................................................................72
Table 19: BIOS Setup Keyboard Command Bar Options .............................................................73
Table 20. BIOS Setup, Main Menu Options.................................................................................74
Table 21. BIOS Setup, Advanced Menu Options.........................................................................75
Table 22. BIOS Setup, Processor Configuration Sub-menu Options ...........................................76
Table 23. BIOS Setup IDE Configuration Menu Options ............................................................77
Table 24. Mixed P-ATA-S-ATA Configuration with only Primary P-ATA................................78
Table 25. BIOS Setup, IDE Device Configuration Sub-menu Selections....................................79
Table 26. BIOS Setup, Floppy Configuration Sub-menu Selections............................................80
Table 27. BIOS Setup, Super I/O Configuration Sub-menu.........................................................80
Table 28. BIOS Setup, USB Configuration Sub-menu Selections ...............................................80
Table 29. BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections ............81
Table 30. BIOS Setup, PCI Configuration Sub-menu Selections.................................................82
Table 31. BIOS Setup, Memory Configuration Sub-menu Selections .........................................83
Table 32. BIOS Setup, Boot Menu Selections..............................................................................84
Table 33. BIOS Setup, Boot Settings Configuration Sub-menu Selections .................................84
Table 34. BIOS Setup, Boot Device Priority Sub-menu Selections.............................................85
Table 35. BIOS Setup, Hard Disk Drive Sub-Menu Selections ...................................................85
Table 36. BIOS Setup, Removable Drives Sub-menu Selections ................................................85
Table 37. BIOS Setup, CD/DVD Drives Sub-menu Selections ...................................................86
Table 38. BIOS Setup, Security Menu Options............................................................................86
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Tables
Table 39. BIOS Setup, Server Menu Selections...........................................................................87
Table 40. BIOS Setup, System Management Sub-menu Selections.............................................88
Table 41. BIOS Setup, Serial Console Features Sub-menu Selections ........................................89
Table 42. BIOS Setup, Event Log Configuration Sub-menu Selections ......................................89
Table 43. BIOS Setup, Exit Menu Selections...............................................................................90
Table 44. Supported Wake Events..............................................................................................100
Table 45. Security Features Operating Model ............................................................................101
Table 46: Supported Channel Assigments...................................................................................110
Table 47: LAN Channel Capacity................................................................................................111
Table 48: LAN Channel Specifications .......................................................................................113
Table 49: PEF Action Priorities...................................................................................................116
Table 50. mBMC Factory Default Event Filters..........................................................................117
Table 51: Power Control Initiators ..............................................................................................120
Table 52: System Reset Sources and Actions..............................................................................121
Table 53: Chassis ID LEDs..........................................................................................................123
Table 54: Fault/Status LED .........................................................................................................123
Table 55: mBMC Built-in Sensors ..............................................................................................127
Table 56. SE7320SP2/SE7525GP2 Built-in Platform Sensors....................................................128
Table 57. SE7320SP2/SE7525GP2 External Platform Sensors ..................................................129
Table 58. POST Error Messages and Handling..........................................................................135
Table 59. Boot Block Error Beep Codes ....................................................................................137
Table 60. POST Error Beep Codes.............................................................................................138
Table 61. Troubleshooting BIOS Beep Codes............................................................................138
Table 62: POST Progress Code LED Example ...........................................................................139
Table 63: POST Code Checkpoints .............................................................................................140
Table 64: Bootblock Initialization Code Checkpoints.................................................................142
Table 65: Bootblock Recovery Code Checkpoint .......................................................................143
Table 66: DIM Code Checkpoints ...............................................................................................144
Table 67: ACPI Runtime Checkpoints ........................................................................................144
Table 68: Memory Error Codes ...................................................................................................145
Table 69. Power Connector Pin-out (J12)....................................................................................146
Table 70. Auxiliary Signal Connector (J5)..................................................................................146
Table 71. Auxiliary CPU Power Connector Pin-out (J22) ..........................................................146
Table 72. DIMM Connectors (J16,J18,J20,J21)..........................................................................147
Table 73. Socket 604 Processor Socket Pin-out (J36, J37)..........................................................148
Table 74. HSBP Header Pin-out (J54).........................................................................................151
Table 75. SATA Back Plane (J56)...............................................................................................151
Table 76. Remote Management Card Header Pin-out (J33)........................................................151
Table 77. P32-A 5V 32-bit/33-MHz PCI Slot Pin-out (J10, J11)................................................152
Table 78. P64-B 3.3V 64-bit/66-MHz PCI-X Slot Pin-out (J8, J9).............................................153
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Tables
Table 79. PCI Express Slot Pin-out (J13 for x4, J14 for x16) .....................................................154
Table 80. Front Panel 34-Pin Header Pin-out (J38).....................................................................155
Table 81. VGA Connector Pin-out (J4) .......................................................................................156
Table 82. NIC1-82541GI(10/100/1000) Connector Pin-out (JA1)..............................................156
Table 84. ATA 40-pin Connector Pin-out (J41, J43)...................................................................157
Table 85. SATA Connector Pin-out (J28, J32)............................................................................157
Table 86. USB Connectors Pin-out (J3) ......................................................................................158
Table 87. Optional USB Connection Header Pin-out (J31).........................................................158
Table 88. Legacy 34-pin Floppy Connector Pin-out (J47) ..........................................................159
Table 89. External DB9 Serial A Port Pin-out (J8A1).................................................................159
Table 90. 9-pin Header Serial B Port Pin-out (J15).....................................................................160
Table 91. Keyboard and Mouse PS/2 Connectors Pin-out (J2) ...................................................160
Table 92. Three-pin Fan Headers Pin-out (J51, J52, J7, J1, J45, J48).........................................160
Table 93 . Six-pin Fan headers Pin-out (J44, J46)......................................................................161
Table 94. Intrusion Cable Connector (J19) Pin-Out ....................................................................161
Table 95. SCSI LED Header Pin-out (J26)..................................................................................161
Table 96. Configuration Jumper Options.....................................................................................162
Table 97. BIOS Bank Jumper Option..........................................................................................163
Table 98. Absolute Maximum Ratings ........................................................................................164
Table 99. MTBF calculation........................................................................................................164
Table 100. Intel® Xeon™ processor DP TDP Guidelines ..........................................................165
Table 101. SE7520AF2 Power Supply Voltage Specification ....................................................165
Table 102. Voltage Timing Parameters .......................................................................................166
Table 103. Turn On / Off Timing ................................................................................................167
Table 104. Transient Load Requirements....................................................................................169
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Introduction
1. Introduction
This Technical Product Specification (TPS) provides detail to the architecture and feature set of
the Intel
The target audience for this document is anyone wishing to obtain more in depth detail of the
server board than what is generally made available in the board’s Users Guide. It is a technical
document meant to assist people with understanding and learning more about the specific
features of the board.
This is one of several technical documents available for this server board. All of the functional
sub-systems that make up the board are described in this document. However, certain low level
detail of specific sub-systems is not included. Design level information for specific sub-systems
can be obtained by ordering the External Product Specification (EPS) for a given sub-system.
The EPS documents available for this server board include the following:
These documents are not made publicly available and must be ordered by your local Intel
representative.
®
Server Board SE7320SP2 and the Intel Server Board SE7525GP2.
o SE7320SP2 BIOS EPS
o SE7320SP2 Baseboard Management Controller (BMC) Firmware EPS
o Mini-Baseboard Management Controller (mBMC) Core EPS
1.1 Chapter Outline
This document is divided into the following chapters
Chapter 1 – Introduction
Chapter 2 – Server Board Overview
Chapter 3 – Functional Architecture
Chapter 4 – System BIOS
Chapter 5 – Platform Management
Chapter 6 – Error Reporting and Handling
Chapter 7 – Connector Definitions and Pin-Outs
Chapter 8 – General Specifications
Chapter 9 – Product Regulatory Compliance
Appendix A – Integration and Usage Tips
Appendix B – Glossary of Terms
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Introduction
1.2 Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density VLSI and power delivery
components which need adequate airflow to cool. Intel ensures through its own chassis
development and testing that when Intel server building blocks are used together, the fully
integrated system will meet the intended thermal requirements of these components. It is the
responsibility of the system integrator who chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of air
flow required for their specific application and environmental conditions. Intel Corporation can
not be held responsible, if components fail or the server board does not operate correctly when
used outside any of their published operating or non-operating limits.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
2. Server Board Overview
The Intel® Server Boards SE7320SP2 and SE7525GP2 are both monolithic printed circuit
boards with features that were designed to support the entry level server market. Additionally,
the server board SE7525GP2 also has features making it suitable for the entry level workstation
market. The features of both boards will be discussed in detail in this document.
2.1 SE7320SP2 SKU Availability
There is one SKU of the server board SE7320SP2. This product is based on the Intel E7320
chipset and provides an interface to a single PCI-Express bus, one 32-bit / 33MHz PCI Bus and
one 64-bit / 66MHz PCI-X bus. Additionally, integrated on the board is a gigabit NIC and an
ATI* Rage XL video solution. A detailed list of the features is listed below.
2.1.1 SE7320SP2 Feature Set
• Dual processor slots supporting Intel® Xeon™ processors operating at 800MT/s
system bus
• Intel E7320 Chipset (MCH, 6300ESB)
• Four DIMM slots supporting DDR 266/333 MHz memory
• Single Intel 82541 10/100/1000 Network Interface Controller (NIC)
• On board ATI* Rage XL video controller w/8MB SDRAM
• Intel Server Management support
• External IO connectors
o Stacked PS2 ports for keyboard and mouse
o DB-9 Serial A Port
o RJ45 NIC connector
o 15 pin video connector
o 2 - USB 2.0 ports
• Internal IO Connectors / Headers
o On-board USB port headers (capable of supporting 2 USB ports)
o DH10 Serial B Header
o 2 – SATA-100 connectors w/integrated chipset RAID 0/1 support
o 2 – ATA100 connectors
o Floppy connector
o SSI compliant front panel headers
o SSI compliant 24 pin main power connector (will support ATX-12V standard in
first 20 pins)
• Internal expansion connectors
o 1 – x 8 PCI-Express connector (on x4 PCI-Express bus)
o 2 – 32-bit/33MHz PCI connectors
o 2 – 64-bit/66MHz PCI-X connectors
• Light Guided Diagnostics on some FRU devices (Processors, Memory)
• Port-80 Diagnostic LEDs displaying POST Codes
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
The following figure shows the board layout of the server board SE7320SP2. Each connector
and major component is identified by number and identified in Table 1: server board
SE7320SP2 Layout Reference.
13
11
12
19
18
14
15
10
8
17
6
2
16
Figure 1 - SE7320SP2 Board Layout
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
Table 1: server board SE7320SP2 Layout Reference
Ref # Description Ref # Description
1 Processor Sockets 11 Front panel header
DIMM connectors (from left to right 2A,
2
2B, 1A, 1B) 12
3 2 External USB connectors 13 Floppy connector
4 Keyboard and mouse connector 14 Main jumper block
5 Stacked video and serial 15 Serial B header
6 Main power 16 12V CPU power
7 RJ45 Gigabit NIC connector 17 Post Code LEDs
8 32-bit PCI slots 18 SATA connectors (left to right A2, A1)
9 PCI-Express x8 connector (x4 bus) 19 Front panel USB header
10 PCI-X 64-bit 66MHz
PATA HDD connectors (primary = blue,
secondary = white)
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
2.2 SE7525GP2 SKU Availability
One SKU of the server board SE7525GP2 is offered. This section describes its feature set.
While largely similar to the server board SE7320SP2, there are specific features making this
server board suitable for an entry level workstation solution as well as an entry server
environment.
2.2.1 SE7525GP2 Feature Set
• Dual processor slots supporting Intel® Xeon™ processors operating on the 800MT/s
system bus
• Intel E7525 Chipset (MCH, ICH-5R)
• Four DIMM slots supporting DDR 266/333 MHz memory
• Single Intel 82541 10/100/1000 Network Interface Controller (NIC)
• On board ATI* Rage XL video controller w/8MB SDRAM
• Intel Server Management support
• External IO connectors
o Stacked PS2 ports for keyboard and mouse
o DB-9 Serial A Port
o RJ45 NIC connector
o 15 pin video connector
o 2 – USB 2.0 ports
• Internal IO Connectors / Headers
o On-board USB port headers (capable of supporting 2 USB ports)
o DH10 Serial B Header
o 2 – SATA-100 connectors with integrated chipset RAID 0/1 support
o 2 – ATA100 connectors
o Floppy connector
o SSI compliant front panel headers
o SSI compliant 24 pin main power connector (will support ATX-12V standard in
first 20 pins)
• Internal expansion connectors
o 1 – x16 PCI-Express Graphics connector
o 1 – x 8 PCI-Express connector (on x4 PCI-Express bus)
o 2 – 32-bit/33MHz PCI connectors
o 2 – 64-bit/66MHz PCI-X connectors
• Light Guided Diagnostics on most FRU devices (Processors, Memory)
• Port-80 Diagnostic LEDs displaying POST Codes
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
The following figure shows the board layout of the server board SE7525GP2. Each connector
and major component is identified by number and identified in Table 2: server board
SE7525GP2 Layout Reference.
13
11
12
19
18
14
15
10
8
20
2
16
Figure 2 - SE7525GP2 Board Layout
17
6
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
Table 2: server board SE7525GP2 Layout Reference
Ref # Description Ref # Description
1 Processor Sockets 11 Front panel header
DIMM connectors (from left to right
2
3 2 External USB connectors 13 Floppy connector
4 Keyboard and mouse connector 14 Main jumper block
5 Stacked video and serial 15 Serial B header
6 Main power 16 12V CPU power
7 RJ45 Gigabit NIC connector 17 Post Code LEDs
8 32-bit PCI slots 18 SATA connectors (left to right A2, A1)
9 PCI-Express x8 connector (x4 bus) 19 Front panel USB header
10 PCI-X 64-bit 66MHz 20 PCI-Express x16 connector
2A, 2B, 1A, 1B) 12
PATA HDD connectors (primary = blue,
secondary = white)
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3. Functional Architecture
This chapter provides a high-level description of the functionality associated with the
architectural blocks that make up the Intel Server Board SE7320SP2 and the Intel Server Board
SE7525GP2.
Note: Due to the similarities between these two products, this chapter will discuss all the
features that are present on both products. Where appropriate, specific features to one product
or the other will be called out.
Figure 3 – Server Board SE7320SP2 Block Diagram
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Figure 4 –Server Board SE7525GP2 Block Diagram
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3.1 Processor Sub-system
The support circuitry for the processor sub-system consists of the following:
• Dual 604-pin zero insertion force (ZIF) processor sockets
• Processor host bus AGTL+ support circuitry
• Reset configuration logic
• Processor module presence detection logic
• BSEL detection capabilities
• CPU signal level translation
• Common Enabling Kit (CEK) CPU retention support
3.1.1 Processor VRD
The server board has two Voltage Regulator Devices (VRDs) providing the appropriate voltages
to the installed processors. Each VRD is compliant with the VRD 10.1 specification and is
designed to support Intel
of 105 Amps and peak support of 120A.
The server board supports the Flexible Mother Board (FMB) specification for all 800MHz FSB
Intel Xeon processors with respect to current requirements and processor speed requirements.
FMB is an estimation of the maximum values the 800MHz FSB versions of the Intel Xeon
processors will have over their lifetime. The value is only an estimate and actual specifications
for future processors may differ. At present, the current demand per FMB is a sustained
maximum of a 105 Amps and peak support of 120 Amps.
®
Xeon™ processors that require up to a sustained maximum current
3.1.2 Reset Configuration Logic
The BIOS determines the processor stepping, cache size, etc through the CPUID instruction. All
processors in the system must operate at the same frequency; have the same cache sizes and
same VID. No mixing of product families is supported. Processors run at a fixed speed and
cannot be programmed to operate at a lower or higher speed.
3.1.3 Processor Module Presence Detection
Logic is provided on the server board to detect the presence and identity of installed processors.
In dual processor configurations, the on-board mini Baseboard Management Controller (mBMC)
must read the processor voltage identification (VID) bits for each processor before turning on
the VRD. If the VIDs of the two processors are not identical, then the mBMC will not turn on the
VRD. Prior to enabling the embedded VRD, circuitry on the server board ensures that the
following criteria are met:
• In a uni-processor configuration, CPU 1 is installed.
• Only supported processors are installed in the system to prevent damage to the MCH.
• In dual processor configurations, both processors support the same FSB frequency.
3.1.4 GTL2006
The GTL2006 is a 13-bit translator designed for 3.3V to GTL/GTL+ translations to the system
bus. The translator incorporates all the level shifting and logic functions required to interface
between the processor subsystem and the rest of the system.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3.1.5 Common Enabling Kit (CEK) Design Support
The server board has been designed to comply with Intel’s Common Enabling Kit (CEK)
processor mounting and heat sink retention solution. The server board will ship with a CEK
spring snapped onto the bottom side of the board beneath each processor socket. The CEK
spring is removable, allowing for the use of non-Intel heat sink retention solutions.
Heatsink assembly with
integrated hardware
Thermal Interface
Material (TIM)
Server board
CEK Spring
Chassis
Figure 5. CEK Processor Mounting
3.1.6 Processor Support
The server board SE7320SP2 and the server board SE7525GP2 are designed to support one
or two Intel
2.8 GHz. Previous generations of Intel Xeon processors are not supported on either of these
server boards.
The server board is designed to provide current up to 120A per processors. Processors with
higher current requirements are not supported.
Note: Only Intel
the server board SE7320SP2 and server board SE7525GP2. See the table below for the
supported processors.
®
Xeon™ processors utilizing an 800MHz Front Side Bus with frequencies starting at
®
Xeon™ processors that support an 800MHz Front Side Bus are supported on
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Table 3: Processor Support Matrix
Processor Family FSB Frequency Frequency Support
Intel® Xeon™ 533 MHz 2.8 GHz No
Intel® Xeon™ 533 MHz 3.06 GHz No
Intel® Xeon™ 533 MHz 3.2 GHz No
Intel® Xeon™ 800MHz 2.8 GHz Yes
Intel® Xeon™ 800MHz 3.0 GHz Yes
Intel® Xeon™ 800MHz 3.2 GHz Yes
Intel® Xeon™ 800MHz 3.4 GHz Yes
Intel® Xeon™ 800MHz 3.6 GHz Yes
3.1.6.1 Processor Mis-population Detection
The processors must be populated in the correct order for the processor Front Side Bus to be
correctly terminated. CPU socket 1 must be populated before CPU socket 2. Server board logic
will prevent the system from powering up if a single processor is present but it is not in the
correct socket. This protects the logic against voltage swings or unreliable operation that could
occur on an incorrectly terminated Front Side Bus.
If processor mis-population is detected when using the standard on-board platform
instrumentation, the mBMC will log an error against processor 1 to the System Event Log and
the server board hardware will illuminate both processor error LEDs.
3.1.6.2 Mixed Processor Steppings
For optimum system performance, only identical processors should be installed in a system.
Processor steppings within a common processor family can be mixed in a system provided that
there is no more than a one stepping difference between them. If the installed processors are
more than one stepping apart, an error is reported. Acceptable mixed steppings are not
reported as errors by the BIOS.
3.1.6.3 Mixed Processor Models
Processor models cannot be mixed in a system. If this condition is detected, an error (8196) is
logged in the SEL.
3.1.6.4 Mixed Processor Families
Processor families cannot be mixed in a system. If this condition is detected, an error (8194) is
logged in the SEL.
3.1.6.5 Mixed Processor Cache Sizes
If the installed processors have mixed cache sizes, an error (8192) will be logged in the SEL.
The size of all cache levels must match between all installed processors. Mixed cache
processors are not supported.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3.1.6.6 Jumperless Processor Speed Settings
®
The Intel
XeonTM processor does not utilize jumpers or switches to set the processor frequency.
The BIOS reads the highest ratio register from all processors in the system. If all processors are
the same speed, the Actual Ratio register is programmed with the value read from the High
Ratio register. If all processors do not match, the highest common value between High and Low
Ratio is determined and programmed to all processors. If there is no value that works for all
installed processors, all processors not capable of speeds supported by the Boot Strap
Processor (BSP) are disabled and an error is displayed.
3.1.6.7 Microcode
IA-32 processors have the capability of correcting specific errata through the loading of an Intel
supplied data block, i.e., microcode update. The BIOS is responsible for storing the update in
non-volatile memory and loading it into each processor during POST. The BIOS allows a
number of microcode updates to be stored in the flash, limited by the amount of free space
available. The BIOS supports variable size microcode updates. The BIOS verifies the
signature prior to storing the update in the flash.
3.1.6.8 Processor Cache
The BIOS enables all levels of processor cache as early as possible during POST. There are no
user options to modify the cache configuration, size or policies. The largest and highest level
cache detected is reported in the BIOS Setup.
3.1.6.9 Hyper-Threading Technology
®
Intel
XeonTM processors support Hyper-Threading Technology. The BIOS detects processors
that support this feature and enables the feature during POST. The BIOS Setup provides an
option to selectively enable or disable this feature. The default behavior is “Enabled”.
The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors.
The SMBIOS Type 4 structure shows only the physical processors installed. It does not
describe the virtual processors because some operating systems are not able to efficiently
utilize the Hyper-Threading Technology.
3.1.6.10 Intel
Intel Xeon processors support the Geyserville3 (GV3) feature of the Intel
®
SpeedStep® Technology
®
SpeedStep®
Technology. This feature changes the processor operating ratio and voltage similar to the
Thermal Monitor 2 (TM2) feature. It must be used in conjunction with the TM1 or TM2 feature.
The BIOS implements the GV3 feature in conjunction with the TM2 feature.
3.1.6.11 EM64T Technology Support
The system BIOS on the server board SE7320SP2 and server board SE7525GP2 supports the
Intel Extended Memory 64 technology (EM64T) of the Intel Xeon processors. There is no BIOS
setup option to enable or disable this support. The system will be in IA-32 compatibility mode
when booting to an operating system. Operating system specific drivers are then loaded to
enable this capability.
3.1.6.12 Execute Disable Bit support
The system BIOS on the server board SE7320SP2 and server board SE7525GP2 supports the
Execute Disable (NX) bit in the latest Intel Xeon processors. This option can be enabled or
disabled in the BIOS setup utility. It is disabled by default to allow users to opt-in to the
protection this feature provides.
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