®
Intel
Server Board SE7320SP2 &
Intel Server Board SE7525GP2
Technical Product Specification
Revision 2.0
November 2004
Enterprise Platforms and Services Marketing
Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Revision History
Revision History
Date Revision
Number
June 2004 1.0 Initial Release
November 2004 2.0
Updated and clarified memory support, removed LX SKU references, added MTBF
calculations, performed general grammar and spelling updates.
Modifications
Revision 2.0
ii
Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Disclaimers
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked
"reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
This document contains information on products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is
available. Verify with your local sales office that you have the latest datasheet before finalizing
a design.
The SE7320SP2 and server board SE7525GP2s may contain design defects or errors known
as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
This document and the software described in it is furnished under license and may only be used
or copied in accordance with the terms of the license. The information in this manual is
furnished for informational use only, is subject to change without notice, and should not be
construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or
liability for any errors or inaccuracies that may appear in this document or any software that may
be provided in association with this document.
Except as permitted by such license, no part of this document may be reproduced, stored in a
retrieval system, or transmitted in any form or by any means without the express written consent
of Intel Corporation.
Xeon is a registered trademark of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2004.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
Table of Contents
1. Introduction ........................................................................................................................17
1.1 Chapter Outline...................................................................................................... 17
1.2 Server Board Use Disclaimer ................................................................................ 18
2. Server Board Overview...................................................................................................... 19
2.1 SE7320SP2 SKU Availability................................................................................. 19
2.1.1 SE7320SP2 Feature Set .......................................................................................19
2.2 SE7525GP2 SKU Availability ................................................................................22
2.2.1 SE7525GP2 Feature Set ....................................................................................... 22
3. Functional Architecture .....................................................................................................25
3.1 Processor Sub-system........................................................................................... 27
3.1.1 Processor VRD ...................................................................................................... 27
3.1.2 Reset Configuration Logic .....................................................................................27
3.1.3 Processor Module Presence Detection .................................................................27
3.1.4 GTL2006................................................................................................................ 27
3.1.5 Common Enabling Kit (CEK) Design Support ....................................................... 28
3.1.6 Processor Support ................................................................................................. 28
3.1.6.1 Processor Mis-population Detection.....................................................................29
3.1.6.2 Mixed Processor Steppings...................................................................................29
3.1.6.3 Mixed Processor Models.......................................................................................29
3.1.6.4 Mixed Processor Families.....................................................................................29
3.1.6.5 Mixed Processor Cache Sizes ...............................................................................29
3.1.6.6 Jumperless Processor Speed Settings....................................................................30
3.1.6.7 Microcode .............................................................................................................30
3.1.6.8 Processor Cache....................................................................................................30
3.1.6.9 Hyper-Threading Technology...............................................................................30
3.1.6.10 Intel® SpeedStep® Technology ...........................................................................30
3.1.6.11 EM64T Technology Support ..............................................................................30
3.1.6.12 Execute Disable Bit support................................................................................30
3.1.7 Multiple Processor Initialization .............................................................................31
3.1.8 CPU Thermal Sensors........................................................................................... 31
3.1.9 Processor Thermal Control Sensor .......................................................................31
3.1.10 Processor Thermal Trip Shutdown ........................................................................ 31
3.1.11 Processor IERR .....................................................................................................31
3.2 E7320 Chipset ....................................................................................................... 32
3.2.1 Memory Controller Hub (MCH) .............................................................................. 32
3.2.1.1 Front Side Bus (FSB)............................................................................................32
3.2.1.2 MCH Memory Sub-System Overview..................................................................32
3.2.1.3 PCI Express*.........................................................................................................33
3.2.1.4 Hub Interface ........................................................................................................33
3.3 E7525 Chipset ....................................................................................................... 33
3.3.1 Memory Controller Hub (MCH) .............................................................................. 34
3.3.1.1 Front Side Bus (FSB)............................................................................................34
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
3.3.1.2 MCH Memory Sub-System Overview..................................................................34
3.3.1.3 PCI Express*.........................................................................................................34
3.3.1.4 Hub Interface ........................................................................................................35
3.4 Intel® 6300ESB ICH .............................................................................................. 35
3.4.1 PCI Interface.......................................................................................................... 35
3.4.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode).................... 36
3.4.3 SATA Controller..................................................................................................... 36
3.4.4 Low Pin Count (LPC) Interface .............................................................................. 36
3.4.5 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) ..... 36
3.4.6 Advanced Programmable Interrupt Controller (APIC) ........................................... 37
3.4.7 Universal Serial Bus (USB) Controller ................................................................... 37
3.4.8 RTC .......................................................................................................................37
3.4.9 GPIO...................................................................................................................... 37
3.4.10 Enhanced Power Management ............................................................................. 37
3.4.11 System Management Bus (SMBus 2.0)................................................................. 37
3.5 Memory Sub-System ............................................................................................. 38
3.5.1 Memory Sizing .......................................................................................................38
3.5.2 Memory Population................................................................................................ 39
3.5.3 I2C Bus ..................................................................................................................42
3.5.4 Disabling DIMMs.................................................................................................... 42
3.5.5 Memory RASUM Features..................................................................................... 42
3.5.5.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC).................43
3.5.5.2 Integrated Memory Scrub Engine.........................................................................43
3.5.5.3 Retry on Uncorrectable Error................................................................................43
3.5.5.4 Integrated Memory Initialization Engine..............................................................44
3.5.5.5 DIMM Sparing Function.......................................................................................44
3.6 I/O Sub-System .....................................................................................................45
3.6.1 PCI Subsystem ......................................................................................................45
3.6.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem ...............................................................45
3.6.1.2 P64-A: 64-bit, 66MHz PCI Subsystem.................................................................46
3.6.1.3 P64-Express4: x4 PCI-Express Bus Segment.......................................................46
3.6.1.4 P64-Express16: x16 PCI-Express bus segment ....................................................46
3.6.1.5 Scan Order ............................................................................................................46
3.6.1.6 Resource Assignment............................................................................................46
3.6.1.7 Automatic IRQ Assignment..................................................................................46
3.6.1.8 Option ROM Support............................................................................................46
3.6.1.9 PCI APIs ...............................................................................................................46
3.6.2 Split Option ROM................................................................................................... 47
3.6.3 Interrupt Routing .................................................................................................... 47
3.6.3.1 Legacy Interrupt Routing......................................................................................47
3.6.3.2 APIC Interrupt Routing.........................................................................................47
3.6.3.3 Legacy Interrupt Sources ......................................................................................47
3.6.3.4 Serialized IRQ Support .........................................................................................48
3.6.3.5 IRQ Scan for PCIIRQ ...........................................................................................48
3.6.4 IDE Support ........................................................................................................... 51
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3.6.4.1 Ultra ATA/100 ......................................................................................................51
3.6.4.2 IDE Initialization ..................................................................................................51
3.6.5 SATA Support........................................................................................................ 51
3.6.5.1 SATA RAID .........................................................................................................51
3.6.5.2 Intel® RAID Technology Option ROM ...............................................................52
3.6.6 Video Controller ..................................................................................................... 52
3.6.6.1 Video Modes.........................................................................................................53
3.6.6.2 Video Memory Interface.......................................................................................53
3.6.7 Network Interface Controller (NIC) ........................................................................ 54
3.6.7.1 Intel 82541 ............................................................................................................54
3.6.7.2 NIC Connector and Status LEDs ..........................................................................54
3.6.8 USB 2.0 Support.................................................................................................... 54
3.6.9 Super I/O Chip ....................................................................................................... 55
3.6.9.1 GPIOs....................................................................................................................56
3.6.9.2 Serial Ports............................................................................................................57
3.6.9.3 Floppy Disk Controller .........................................................................................57
3.6.9.4 Keyboard and Mouse ............................................................................................57
3.6.9.5 Wake-up Control...................................................................................................57
3.6.10 BIOS Flash ............................................................................................................57
3.7 Configuration and Initialization............................................................................... 58
3.7.1 Memory Space....................................................................................................... 58
3.7.1.1 DOS Compatibility Region...................................................................................59
3.7.1.2 Extended Memory.................................................................................................60
3.7.1.3 Memory Shadowing..............................................................................................62
3.7.1.4 System Management Mode Handling...................................................................62
3.7.2 I/O Map ..................................................................................................................63
3.7.3 Accessing Configuration Space............................................................................. 65
3.7.3.1 CONFIG_ADDRESS Register .............................................................................66
3.8 Clock Generation and Distribution .........................................................................68
3.8.1 Real Time Clock ....................................................................................................68
4. System BIOS.......................................................................................................................69
4.1 BIOS Identification String....................................................................................... 69
4.2 BIOS POST Splash Screen ................................................................................... 70
4.2.1 User Interface ........................................................................................................ 70
4.2.1.1 System State Window...........................................................................................70
4.2.1.2 Logo/Diagnostic Window.....................................................................................70
4.2.1.3 Current Activity Window .....................................................................................71
4.2.1.4 System Diagnostic Screen.....................................................................................71
4.2.1.5 Static Information Display....................................................................................71
4.3 BIOS Setup Utility ..................................................................................................72
4.3.1 Localization............................................................................................................ 72
4.3.2 Console Redirection ..............................................................................................72
4.3.3 Configuration Reset ............................................................................................... 72
4.3.4 Keyboard Commands ............................................................................................ 73
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4.4 Entering BIOS Setup .............................................................................................74
4.4.1 Main Menu .............................................................................................................74
4.4.2 Advanced Menu..................................................................................................... 75
4.4.2.1 Processor Configuration Sub-menu ......................................................................76
4.4.2.2 IDE Configuration Sub-menu...............................................................................77
4.4.2.3 Floppy Configuration Sub-menu ..........................................................................80
4.4.2.4 Super I/O Configuration Sub-menu......................................................................80
4.4.2.5 USB Configuration Sub-menu..............................................................................80
4.4.2.6 USB Mass Storage Device Configuration Sub-menu...........................................81
4.4.2.7 PCI Configuration Sub-menu ...............................................................................82
4.4.2.8 Memory Configuration Sub-menu........................................................................83
4.4.3 Boot Menu .............................................................................................................84
4.4.3.1 Boot Settings Configuration Sub-menu Selections...............................................84
4.4.3.2 Boot Device Priority Sub-menu Selections ..........................................................85
4.4.4 Security Menu........................................................................................................ 86
4.4.5 Server Menu .......................................................................................................... 87
4.4.5.1 System Management Sub-menu Selections..........................................................88
4.4.5.2 Serial Console Features Sub-menu Selections......................................................89
4.4.5.3 Event Log Configuration Sub-menu Selections ...................................................89
4.4.6 Exit Menu............................................................................................................... 90
4.5 Flash Update Utility................................................................................................ 90
4.6 Rolling BIOS and On-line Updates ........................................................................ 91
4.7 Flash Update Utility................................................................................................ 91
4.7.1 Flash BIOS ............................................................................................................92
4.7.1.1 Updating the BIOS from DOS..............................................................................92
4.7.1.2 Updating the BIOS from Microsoft* Windows* 2000/2003/XP .........................92
4.7.1.3 Updating the BIOS from Linux ............................................................................92
4.7.1.4 Updating the BIOS from the EFI Shell.................................................................93
4.7.2 User Binary Area ...................................................................................................93
4.7.3 Recovery Mode...................................................................................................... 93
4.7.3.1 BIOS Recovery .....................................................................................................93
4.7.3.2 Multi-disk Recovery .............................................................................................94
4.7.4 Update OEM Logo .................................................................................................95
4.7.4.1 Changing the OEM logo for DOS ........................................................................95
4.7.4.2 Changing the OEMlogo for Microsoft* Windows* 2000/2003/XP.....................96
4.8 OEM Binary ...........................................................................................................96
4.9 Operating System Boot, Sleep, and Wake ............................................................ 97
4.9.1 Microsoft* Windows* Compatibility ........................................................................ 97
4.9.2 Advanced Configuration and Power Interface (ACPI) ........................................... 98
4.9.3 Sleep and Wake Functionality ............................................................................... 99
4.9.4 Power Switch Off to On ......................................................................................... 99
4.9.5 On to Off (OS absent)............................................................................................ 99
4.9.6 On to Off (OS present)........................................................................................... 99
4.9.7 System Sleep States .............................................................................................99
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4.10 Security................................................................................................................ 100
4.10.1 Operating Model .................................................................................................. 101
4.10.2 Administrator/User Passwords and F2 Setup Usage Model................................ 102
4.10.3 Password Clear Jumper ......................................................................................103
4.11 Extensible Firmware Interface (EFI) .................................................................... 103
4.11.1 EFI Shell .............................................................................................................. 103
5. Platform Management...................................................................................................... 104
5.1.1 5V Standby .......................................................................................................... 105
5.1.2 IPMI Messaging, Commands, and Abstractions.................................................. 105
5.1.3 IPMI ‘Sensor Model’............................................................................................. 105
5.1.4 Private Management Busses............................................................................... 106
5.1.5 Mini-Baseboard Management Controller ............................................................. 106
5.2 Onboard Platform Instrumentation Features and Functionality ........................... 108
5.2.1 Overview of mBMC.............................................................................................. 108
5.2.2 mBMC Self-test.................................................................................................... 108
5.2.3 SMBus Interfaces ................................................................................................109
5.2.4 External Interface to mBMC................................................................................. 109
5.2.4.1 Private Management I2C Buses..........................................................................109
5.2.5 Messaging Interfaces........................................................................................... 110
5.2.5.1 Channel Management .........................................................................................110
5.2.5.2 User Model..........................................................................................................110
5.2.5.3 Request/Response Protocol.................................................................................110
5.2.5.4 Host to mBMC Communication Interface..........................................................110
5.2.5.5 LAN Interface .....................................................................................................111
5.2.6 Direct Platform Control (IPMI over LAN).............................................................. 112
5.2.6.1 LAN Channel Specifications ..............................................................................113
5.2.6.2 LAN Drivers and Setup ......................................................................................113
5.2.6.3 BIOS Boot Flags .................................................................................................113
5.2.6.4 Boot Flags and LAN Console Redirection .........................................................114
5.2.7 Wake On LAN / Power On LAN and Magic Packet Support................................114
5.2.7.1 Wake On LAN in S4/S5 .....................................................................................114
5.2.8 Watchdog Timer ..................................................................................................114
5.2.9 System Event Log (SEL) ..................................................................................... 114
5.2.9.1 Timestamp Clock................................................................................................114
5.2.10 Sensor Data Record (SDR) Repository ............................................................... 115
5.2.10.1 Initialization Agent ...........................................................................................115
5.2.11 Event Message Reception................................................................................... 115
5.2.12 Event Filtering and Alerting.................................................................................. 115
5.2.12.1 Platform Event Filtering (PEF).........................................................................116
5.2.12.2 Alert over LAN.................................................................................................117
5.2.12.3 System Identification in Alerts .........................................................................118
5.2.12.4 Platform Alerting Setup ....................................................................................118
5.2.12.5 Alerting On Power Down Events .....................................................................118
5.2.12.6 Alerting On System Reset Events.....................................................................118
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5.2.12.7 Alert-in-Progress Termination..........................................................................118
5.2.13 NMI Generation ...................................................................................................118
5.2.14 SMI Generation.................................................................................................... 119
5.3 Platform Management Interconnects................................................................... 119
5.3.1 Power Supply Interface Signals........................................................................... 119
5.3.1.1 Power-up Sequence.............................................................................................120
5.3.1.2 Power-down Sequence........................................................................................120
5.3.1.3 Power Control Sources .......................................................................................120
5.3.2 System Reset Control.......................................................................................... 120
5.3.2.1 Reset Signal Output ............................................................................................120
5.3.2.2 Reset Control Sources.........................................................................................121
5.3.3 Temperature-based Fan Speed Control ..............................................................121
5.3.3.1 Fan Kick Start .....................................................................................................121
5.3.4 Front Panel Control.............................................................................................. 122
5.3.4.1 Power Button ......................................................................................................122
5.3.4.2 Reset Button........................................................................................................122
5.3.4.3 Diagnostic Interrupt Button (Front Panel NMI) .................................................122
5.3.4.4 Chassis ID Button and LED................................................................................123
5.3.4.5 Status/Fault LED.................................................................................................123
5.3.4.6 Chassis Intrusion Switch.....................................................................................124
5.3.4.7 Front Panel Lockout............................................................................................124
5.3.5 Secure Mode Operation....................................................................................... 125
5.3.6 FRU Information ..................................................................................................125
5.3.6.1 mBMC FRU Inventory Area Format..................................................................126
5.4 Sensors................................................................................................................ 126
5.4.1 Sensor Type Codes .............................................................................................126
6. Error Reporting and Handling......................................................................................... 132
6.1 Error Logging ....................................................................................................... 132
6.1.1 Error Sources and Types..................................................................................... 132
6.1.2 SMI Handler......................................................................................................... 132
6.1.2.1 PCI Bus Error......................................................................................................132
6.1.2.2 Processor Bus Error ............................................................................................133
6.1.2.3 Memory Bus Error ..............................................................................................133
6.1.2.4 System Limit Error .............................................................................................133
6.1.2.5 Processor Failure.................................................................................................133
6.1.2.6 Boot Event ..........................................................................................................133
6.1.2.7 Logging Format Conventions .............................................................................133
6.1.3 Single-bit ECC Error Throttling Prevention .......................................................... 134
6.2 Error Messages and Error Codes ........................................................................ 134
6.2.1 POST Error Codes and Messages ...................................................................... 134
6.2.2 Boot Block Error Beep Codes.............................................................................. 137
6.2.3 POST Error Beep Codes ..................................................................................... 138
6.2.3.1 Troubleshooting BIOS Beep Codes....................................................................138
6.2.4 "POST Error Pause" option ................................................................................. 138
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Table of Contents
6.3 Checkpoints ......................................................................................................... 139
6.3.1 System ROM BIOS POST Task Test Point (Port 80h Code)............................... 139
6.3.2 Diagnostic LEDs .................................................................................................. 139
6.3.3 POST Code Checkpoints..................................................................................... 140
6.3.4 Bootblock Initialization Code Checkpoints........................................................... 142
6.3.5 Bootblock Recovery Code Checkpoint ................................................................ 143
6.3.6 DIM Code Checkpoints........................................................................................ 144
6.3.7 ACPI Runtime Checkpoints ................................................................................. 144
6.3.8 Memory Error Codes ...........................................................................................145
6.4 Light Guided Diagnostics..................................................................................... 145
7. Connector Definitions and Pin-Outs .............................................................................. 146
7.1 Main Power Connector ........................................................................................ 146
7.2 Memory Module Connector .................................................................................147
7.3 Processor Socket................................................................................................. 148
7.4 I2C Headers .........................................................................................................151
7.5 PCI Slot Connector ..............................................................................................151
7.6 Front Panel Connector......................................................................................... 155
7.7 VGA Connector.................................................................................................... 156
7.8 NIC Connector .....................................................................................................156
7.9 IDE Connector ..................................................................................................... 157
7.10 SATA Connectors ................................................................................................157
7.11 USB Connector.................................................................................................... 158
7.12 Floppy Connector ................................................................................................159
7.13 Serial Port Connector ..........................................................................................159
7.14 Keyboard and Mouse Connector ......................................................................... 160
7.15 Miscellaneous Headers .......................................................................................160
7.15.1 Fan Header.......................................................................................................... 160
7.15.2 Intrusion Cable Connector ................................................................................... 161
7.15.3 SCSI LED Header................................................................................................ 161
7.16 Configuration Jumpers......................................................................................... 161
7.17 System Recovery and Update Jumpers ..............................................................161
7.18 Rolling BIOS Bank Selection Jumper .................................................................. 162
8. General Specifications..................................................................................................... 164
8.1 Absolute Maximum Ratings ................................................................................. 164
8.2 Mean Time Between Failure (MTBF)................................................................... 164
8.3 Processor Power Support.................................................................................... 164
8.4 Power Supply Specifications ...............................................................................165
8.4.1 Power Timing....................................................................................................... 165
8.4.2 Voltage Recovery Timing Specifications ............................................................. 168
9. Product Regulatory Compliance..................................................................................... 170
9.1 Product Safety Compliance ................................................................................. 170
9.1.1 Product EMC Compliance ...................................................................................170
9.1.2 Mandatory/Standard: Certifications, Registration, Declarations ..........................171
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9.1.3 Product Regulatory Compliance Markings ..........................................................171
9.2 Electromagnetic Compatibility Notices ................................................................ 171
9.2.1 Europe (CE Declaration of Conformity) ............................................................... 171
9.2.2 Australian Communications Authority (ACA) (C-Tick Declaration of Conformity) 171
9.2.3 Ministry of Economic Development (New Zealand) Declaration of Conformity ...171
9.2.4 BSMI (Taiwan) .....................................................................................................171
9.3 Replacing the Back up Battery ............................................................................172
Appendix A: Integration and Usage Tips.............................................................................. 174
Appendix B: Glossary of Terms ............................................................................................ 175
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Figures
List of Figures
Figure 1 - SE7320SP2 Board Layout ............................................................................................20
Figure 2 - SE7525GP2 Board Layout............................................................................................23
Figure 3 – Server Board SE7320SP2 Block Diagram ...................................................................25
Figure 4 –Server Board SE7525GP2 Block Diagram....................................................................26
Figure 5. CEK Processor Mounting...............................................................................................28
Figure 6 - DIMM Socket Configuration ........................................................................................40
Figure 7 - Interrupt Routing Diagram (Intel 6300ESB Internal) ...................................................49
Figure 8 - Interrupt Routing Diagram............................................................................................50
Figure 9 - Intel® Xeon™ Processor Memory address Space........................................................58
Figure 10 - DOS Compatibility Region .........................................................................................59
Figure 11 - Extended Memory Map...............................................................................................61
Figure 12 - CONFIG_ADDRES Register......................................................................................66
Figure 13 - Block Diagram of Platform Managment Architecture..............................................104
Figure 14: mBMC in a Server Management System...................................................................108
Figure 15: External Interfaces to mBMC.....................................................................................109
Figure 16 - IPMI-over-LAN ........................................................................................................112
Figure 17: Power Supply Control Signals ...................................................................................119
Figure 18 - Location of Diagnostic LEDs on Server board (Example only) ...............................139
Figure 19. System Configuration Jumpers (J17) .........................................................................162
Figure 20. BIOS Bank Jumper (J26)............................................................................................162
Figure 21. Output Voltage Timing...............................................................................................166
Figure 22. Turn on / off Timing...................................................................................................168
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Tables
List of Tables
Table 1: server board SE7320SP2 Layout Reference....................................................................21
Table 2: server board SE7525GP2 Layout Reference ...................................................................24
Table 3: Processor Support Matrix ................................................................................................29
Table 4: Supported DDR-266 DIMM Populations........................................................................41
Table 5: Supported DDR-333 DIMM Populations........................................................................41
Table 6: DIMM Module Capacities...............................................................................................41
Table 7: Possible Memory Capacities............................................................................................42
Table 8: PCI Bus Segment Characteristics ....................................................................................45
Table 9: PCI Interrupt Routing/Sharing.........................................................................................47
Table 10: Interrupt Definitions ......................................................................................................48
Table 11: Video Modes..................................................................................................................53
Table 12: Video Memory Interface................................................................................................54
Table 13: Super I/O GPIO Usage Table ........................................................................................56
Table 14: Serial B Header Pin-out.................................................................................................57
Table 15: SMM Space Table .........................................................................................................63
Table 16: I/O Map.........................................................................................................................63
Table 17: PCI Configuration IDs and Device Numbers ................................................................67
Table 18: Sample BIOS Popup Menu...........................................................................................72
Table 19: BIOS Setup Keyboard Command Bar Options .............................................................73
Table 20. BIOS Setup, Main Menu Options.................................................................................74
Table 21. BIOS Setup, Advanced Menu Options.........................................................................75
Table 22. BIOS Setup, Processor Configuration Sub-menu Options ...........................................76
Table 23. BIOS Setup IDE Configuration Menu Options ............................................................77
Table 24. Mixed P-ATA-S-ATA Configuration with only Primary P-ATA................................78
Table 25. BIOS Setup, IDE Device Configuration Sub-menu Selections....................................79
Table 26. BIOS Setup, Floppy Configuration Sub-menu Selections............................................80
Table 27. BIOS Setup, Super I/O Configuration Sub-menu.........................................................80
Table 28. BIOS Setup, USB Configuration Sub-menu Selections ...............................................80
Table 29. BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections ............81
Table 30. BIOS Setup, PCI Configuration Sub-menu Selections.................................................82
Table 31. BIOS Setup, Memory Configuration Sub-menu Selections .........................................83
Table 32. BIOS Setup, Boot Menu Selections..............................................................................84
Table 33. BIOS Setup, Boot Settings Configuration Sub-menu Selections .................................84
Table 34. BIOS Setup, Boot Device Priority Sub-menu Selections.............................................85
Table 35. BIOS Setup, Hard Disk Drive Sub-Menu Selections ...................................................85
Table 36. BIOS Setup, Removable Drives Sub-menu Selections ................................................85
Table 37. BIOS Setup, CD/DVD Drives Sub-menu Selections ...................................................86
Table 38. BIOS Setup, Security Menu Options............................................................................86
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Tables
Table 39. BIOS Setup, Server Menu Selections...........................................................................87
Table 40. BIOS Setup, System Management Sub-menu Selections.............................................88
Table 41. BIOS Setup, Serial Console Features Sub-menu Selections ........................................89
Table 42. BIOS Setup, Event Log Configuration Sub-menu Selections ......................................89
Table 43. BIOS Setup, Exit Menu Selections...............................................................................90
Table 44. Supported Wake Events..............................................................................................100
Table 45. Security Features Operating Model ............................................................................101
Table 46: Supported Channel Assigments...................................................................................110
Table 47: LAN Channel Capacity................................................................................................111
Table 48: LAN Channel Specifications .......................................................................................113
Table 49: PEF Action Priorities...................................................................................................116
Table 50. mBMC Factory Default Event Filters..........................................................................117
Table 51: Power Control Initiators ..............................................................................................120
Table 52: System Reset Sources and Actions..............................................................................121
Table 53: Chassis ID LEDs..........................................................................................................123
Table 54: Fault/Status LED .........................................................................................................123
Table 55: mBMC Built-in Sensors ..............................................................................................127
Table 56. SE7320SP2/SE7525GP2 Built-in Platform Sensors....................................................128
Table 57. SE7320SP2/SE7525GP2 External Platform Sensors ..................................................129
Table 58. POST Error Messages and Handling..........................................................................135
Table 59. Boot Block Error Beep Codes ....................................................................................137
Table 60. POST Error Beep Codes.............................................................................................138
Table 61. Troubleshooting BIOS Beep Codes............................................................................138
Table 62: POST Progress Code LED Example ...........................................................................139
Table 63: POST Code Checkpoints .............................................................................................140
Table 64: Bootblock Initialization Code Checkpoints.................................................................142
Table 65: Bootblock Recovery Code Checkpoint .......................................................................143
Table 66: DIM Code Checkpoints ...............................................................................................144
Table 67: ACPI Runtime Checkpoints ........................................................................................144
Table 68: Memory Error Codes ...................................................................................................145
Table 69. Power Connector Pin-out (J12)....................................................................................146
Table 70. Auxiliary Signal Connector (J5)..................................................................................146
Table 71. Auxiliary CPU Power Connector Pin-out (J22) ..........................................................146
Table 72. DIMM Connectors (J16,J18,J20,J21)..........................................................................147
Table 73. Socket 604 Processor Socket Pin-out (J36, J37)..........................................................148
Table 74. HSBP Header Pin-out (J54).........................................................................................151
Table 75. SATA Back Plane (J56)...............................................................................................151
Table 76. Remote Management Card Header Pin-out (J33)........................................................151
Table 77. P32-A 5V 32-bit/33-MHz PCI Slot Pin-out (J10, J11)................................................152
Table 78. P64-B 3.3V 64-bit/66-MHz PCI-X Slot Pin-out (J8, J9).............................................153
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS List of Tables
Table 79. PCI Express Slot Pin-out (J13 for x4, J14 for x16) .....................................................154
Table 80. Front Panel 34-Pin Header Pin-out (J38).....................................................................155
Table 81. VGA Connector Pin-out (J4) .......................................................................................156
Table 82. NIC1-82541GI(10/100/1000) Connector Pin-out (JA1)..............................................156
Table 84. ATA 40-pin Connector Pin-out (J41, J43)...................................................................157
Table 85. SATA Connector Pin-out (J28, J32)............................................................................157
Table 86. USB Connectors Pin-out (J3) ......................................................................................158
Table 87. Optional USB Connection Header Pin-out (J31).........................................................158
Table 88. Legacy 34-pin Floppy Connector Pin-out (J47) ..........................................................159
Table 89. External DB9 Serial A Port Pin-out (J8A1).................................................................159
Table 90. 9-pin Header Serial B Port Pin-out (J15).....................................................................160
Table 91. Keyboard and Mouse PS/2 Connectors Pin-out (J2) ...................................................160
Table 92. Three-pin Fan Headers Pin-out (J51, J52, J7, J1, J45, J48).........................................160
Table 93 . Six-pin Fan headers Pin-out (J44, J46)......................................................................161
Table 94. Intrusion Cable Connector (J19) Pin-Out ....................................................................161
Table 95. SCSI LED Header Pin-out (J26)..................................................................................161
Table 96. Configuration Jumper Options.....................................................................................162
Table 97. BIOS Bank Jumper Option..........................................................................................163
Table 98. Absolute Maximum Ratings ........................................................................................164
Table 99. MTBF calculation........................................................................................................164
Table 100. Intel® Xeon™ processor DP TDP Guidelines ..........................................................165
Table 101. SE7520AF2 Power Supply Voltage Specification ....................................................165
Table 102. Voltage Timing Parameters .......................................................................................166
Table 103. Turn On / Off Timing ................................................................................................167
Table 104. Transient Load Requirements....................................................................................169
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Introduction
1. Introduction
This Technical Product Specification (TPS) provides detail to the architecture and feature set of
the Intel
The target audience for this document is anyone wishing to obtain more in depth detail of the
server board than what is generally made available in the board’s Users Guide. It is a technical
document meant to assist people with understanding and learning more about the specific
features of the board.
This is one of several technical documents available for this server board. All of the functional
sub-systems that make up the board are described in this document. However, certain low level
detail of specific sub-systems is not included. Design level information for specific sub-systems
can be obtained by ordering the External Product Specification (EPS) for a given sub-system.
The EPS documents available for this server board include the following:
These documents are not made publicly available and must be ordered by your local Intel
representative.
®
Server Board SE7320SP2 and the Intel Server Board SE7525GP2.
o SE7320SP2 BIOS EPS
o SE7320SP2 Baseboard Management Controller (BMC) Firmware EPS
o Mini-Baseboard Management Controller (mBMC) Core EPS
1.1 Chapter Outline
This document is divided into the following chapters
Chapter 1 – Introduction
Chapter 2 – Server Board Overview
Chapter 3 – Functional Architecture
Chapter 4 – System BIOS
Chapter 5 – Platform Management
Chapter 6 – Error Reporting and Handling
Chapter 7 – Connector Definitions and Pin-Outs
Chapter 8 – General Specifications
Chapter 9 – Product Regulatory Compliance
Appendix A – Integration and Usage Tips
Appendix B – Glossary of Terms
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Introduction
1.2 Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density VLSI and power delivery
components which need adequate airflow to cool. Intel ensures through its own chassis
development and testing that when Intel server building blocks are used together, the fully
integrated system will meet the intended thermal requirements of these components. It is the
responsibility of the system integrator who chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of air
flow required for their specific application and environmental conditions. Intel Corporation can
not be held responsible, if components fail or the server board does not operate correctly when
used outside any of their published operating or non-operating limits.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
2. Server Board Overview
The Intel® Server Boards SE7320SP2 and SE7525GP2 are both monolithic printed circuit
boards with features that were designed to support the entry level server market. Additionally,
the server board SE7525GP2 also has features making it suitable for the entry level workstation
market. The features of both boards will be discussed in detail in this document.
2.1 SE7320SP2 SKU Availability
There is one SKU of the server board SE7320SP2. This product is based on the Intel E7320
chipset and provides an interface to a single PCI-Express bus, one 32-bit / 33MHz PCI Bus and
one 64-bit / 66MHz PCI-X bus. Additionally, integrated on the board is a gigabit NIC and an
ATI* Rage XL video solution. A detailed list of the features is listed below.
2.1.1 SE7320SP2 Feature Set
• Dual processor slots supporting Intel® Xeon™ processors operating at 800MT/s
system bus
• Intel E7320 Chipset (MCH, 6300ESB)
• Four DIMM slots supporting DDR 266/333 MHz memory
• Single Intel 82541 10/100/1000 Network Interface Controller (NIC)
• On board ATI* Rage XL video controller w/8MB SDRAM
• Intel Server Management support
• External IO connectors
o Stacked PS2 ports for keyboard and mouse
o DB-9 Serial A Port
o RJ45 NIC connector
o 15 pin video connector
o 2 - USB 2.0 ports
• Internal IO Connectors / Headers
o On-board USB port headers (capable of supporting 2 USB ports)
o DH10 Serial B Header
o 2 – SATA-100 connectors w/integrated chipset RAID 0/1 support
o 2 – ATA100 connectors
o Floppy connector
o SSI compliant front panel headers
o SSI compliant 24 pin main power connector (will support ATX-12V standard in
first 20 pins)
• Internal expansion connectors
o 1 – x 8 PCI-Express connector (on x4 PCI-Express bus)
o 2 – 32-bit/33MHz PCI connectors
o 2 – 64-bit/66MHz PCI-X connectors
• Light Guided Diagnostics on some FRU devices (Processors, Memory)
• Port-80 Diagnostic LEDs displaying POST Codes
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
The following figure shows the board layout of the server board SE7320SP2. Each connector
and major component is identified by number and identified in Table 1: server board
SE7320SP2 Layout Reference.
13
11
12
19
18
14
15
10
8
17
6
2
16
Figure 1 - SE7320SP2 Board Layout
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Table 1: server board SE7320SP2 Layout Reference
Ref # Description Ref # Description
1 Processor Sockets 11 Front panel header
DIMM connectors (from left to right 2A,
2
2B, 1A, 1B) 12
3 2 External USB connectors 13 Floppy connector
4 Keyboard and mouse connector 14 Main jumper block
5 Stacked video and serial 15 Serial B header
6 Main power 16 12V CPU power
7 RJ45 Gigabit NIC connector 17 Post Code LEDs
8 32-bit PCI slots 18 SATA connectors (left to right A2, A1)
9 PCI-Express x8 connector (x4 bus) 19 Front panel USB header
10 PCI-X 64-bit 66MHz
PATA HDD connectors (primary = blue,
secondary = white)
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
2.2 SE7525GP2 SKU Availability
One SKU of the server board SE7525GP2 is offered. This section describes its feature set.
While largely similar to the server board SE7320SP2, there are specific features making this
server board suitable for an entry level workstation solution as well as an entry server
environment.
2.2.1 SE7525GP2 Feature Set
• Dual processor slots supporting Intel® Xeon™ processors operating on the 800MT/s
system bus
• Intel E7525 Chipset (MCH, ICH-5R)
• Four DIMM slots supporting DDR 266/333 MHz memory
• Single Intel 82541 10/100/1000 Network Interface Controller (NIC)
• On board ATI* Rage XL video controller w/8MB SDRAM
• Intel Server Management support
• External IO connectors
o Stacked PS2 ports for keyboard and mouse
o DB-9 Serial A Port
o RJ45 NIC connector
o 15 pin video connector
o 2 – USB 2.0 ports
• Internal IO Connectors / Headers
o On-board USB port headers (capable of supporting 2 USB ports)
o DH10 Serial B Header
o 2 – SATA-100 connectors with integrated chipset RAID 0/1 support
o 2 – ATA100 connectors
o Floppy connector
o SSI compliant front panel headers
o SSI compliant 24 pin main power connector (will support ATX-12V standard in
first 20 pins)
• Internal expansion connectors
o 1 – x16 PCI-Express Graphics connector
o 1 – x 8 PCI-Express connector (on x4 PCI-Express bus)
o 2 – 32-bit/33MHz PCI connectors
o 2 – 64-bit/66MHz PCI-X connectors
• Light Guided Diagnostics on most FRU devices (Processors, Memory)
• Port-80 Diagnostic LEDs displaying POST Codes
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
The following figure shows the board layout of the server board SE7525GP2. Each connector
and major component is identified by number and identified in Table 2: server board
SE7525GP2 Layout Reference.
13
11
12
19
18
14
15
10
8
20
2
16
Figure 2 - SE7525GP2 Board Layout
17
6
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Server Board Overview
Table 2: server board SE7525GP2 Layout Reference
Ref # Description Ref # Description
1 Processor Sockets 11 Front panel header
DIMM connectors (from left to right
2
3 2 External USB connectors 13 Floppy connector
4 Keyboard and mouse connector 14 Main jumper block
5 Stacked video and serial 15 Serial B header
6 Main power 16 12V CPU power
7 RJ45 Gigabit NIC connector 17 Post Code LEDs
8 32-bit PCI slots 18 SATA connectors (left to right A2, A1)
9 PCI-Express x8 connector (x4 bus) 19 Front panel USB header
10 PCI-X 64-bit 66MHz 20 PCI-Express x16 connector
2A, 2B, 1A, 1B) 12
PATA HDD connectors (primary = blue,
secondary = white)
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3. Functional Architecture
This chapter provides a high-level description of the functionality associated with the
architectural blocks that make up the Intel Server Board SE7320SP2 and the Intel Server Board
SE7525GP2.
Note: Due to the similarities between these two products, this chapter will discuss all the
features that are present on both products. Where appropriate, specific features to one product
or the other will be called out.
Figure 3 – Server Board SE7320SP2 Block Diagram
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Figure 4 –Server Board SE7525GP2 Block Diagram
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3.1 Processor Sub-system
The support circuitry for the processor sub-system consists of the following:
• Dual 604-pin zero insertion force (ZIF) processor sockets
• Processor host bus AGTL+ support circuitry
• Reset configuration logic
• Processor module presence detection logic
• BSEL detection capabilities
• CPU signal level translation
• Common Enabling Kit (CEK) CPU retention support
3.1.1 Processor VRD
The server board has two Voltage Regulator Devices (VRDs) providing the appropriate voltages
to the installed processors. Each VRD is compliant with the VRD 10.1 specification and is
designed to support Intel
of 105 Amps and peak support of 120A.
The server board supports the Flexible Mother Board (FMB) specification for all 800MHz FSB
Intel Xeon processors with respect to current requirements and processor speed requirements.
FMB is an estimation of the maximum values the 800MHz FSB versions of the Intel Xeon
processors will have over their lifetime. The value is only an estimate and actual specifications
for future processors may differ. At present, the current demand per FMB is a sustained
maximum of a 105 Amps and peak support of 120 Amps.
®
Xeon™ processors that require up to a sustained maximum current
3.1.2 Reset Configuration Logic
The BIOS determines the processor stepping, cache size, etc through the CPUID instruction. All
processors in the system must operate at the same frequency; have the same cache sizes and
same VID. No mixing of product families is supported. Processors run at a fixed speed and
cannot be programmed to operate at a lower or higher speed.
3.1.3 Processor Module Presence Detection
Logic is provided on the server board to detect the presence and identity of installed processors.
In dual processor configurations, the on-board mini Baseboard Management Controller (mBMC)
must read the processor voltage identification (VID) bits for each processor before turning on
the VRD. If the VIDs of the two processors are not identical, then the mBMC will not turn on the
VRD. Prior to enabling the embedded VRD, circuitry on the server board ensures that the
following criteria are met:
• In a uni-processor configuration, CPU 1 is installed.
• Only supported processors are installed in the system to prevent damage to the MCH.
• In dual processor configurations, both processors support the same FSB frequency.
3.1.4 GTL2006
The GTL2006 is a 13-bit translator designed for 3.3V to GTL/GTL+ translations to the system
bus. The translator incorporates all the level shifting and logic functions required to interface
between the processor subsystem and the rest of the system.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3.1.5 Common Enabling Kit (CEK) Design Support
The server board has been designed to comply with Intel’s Common Enabling Kit (CEK)
processor mounting and heat sink retention solution. The server board will ship with a CEK
spring snapped onto the bottom side of the board beneath each processor socket. The CEK
spring is removable, allowing for the use of non-Intel heat sink retention solutions.
Heatsink assembly with
integrated hardware
Thermal Interface
Material (TIM)
Server board
CEK Spring
Chassis
Figure 5. CEK Processor Mounting
3.1.6 Processor Support
The server board SE7320SP2 and the server board SE7525GP2 are designed to support one
or two Intel
2.8 GHz. Previous generations of Intel Xeon processors are not supported on either of these
server boards.
The server board is designed to provide current up to 120A per processors. Processors with
higher current requirements are not supported.
Note: Only Intel
the server board SE7320SP2 and server board SE7525GP2. See the table below for the
supported processors.
®
Xeon™ processors utilizing an 800MHz Front Side Bus with frequencies starting at
®
Xeon™ processors that support an 800MHz Front Side Bus are supported on
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
Table 3: Processor Support Matrix
Processor Family FSB Frequency Frequency Support
Intel® Xeon™ 533 MHz 2.8 GHz No
Intel® Xeon™ 533 MHz 3.06 GHz No
Intel® Xeon™ 533 MHz 3.2 GHz No
Intel® Xeon™ 800MHz 2.8 GHz Yes
Intel® Xeon™ 800MHz 3.0 GHz Yes
Intel® Xeon™ 800MHz 3.2 GHz Yes
Intel® Xeon™ 800MHz 3.4 GHz Yes
Intel® Xeon™ 800MHz 3.6 GHz Yes
3.1.6.1 Processor Mis-population Detection
The processors must be populated in the correct order for the processor Front Side Bus to be
correctly terminated. CPU socket 1 must be populated before CPU socket 2. Server board logic
will prevent the system from powering up if a single processor is present but it is not in the
correct socket. This protects the logic against voltage swings or unreliable operation that could
occur on an incorrectly terminated Front Side Bus.
If processor mis-population is detected when using the standard on-board platform
instrumentation, the mBMC will log an error against processor 1 to the System Event Log and
the server board hardware will illuminate both processor error LEDs.
3.1.6.2 Mixed Processor Steppings
For optimum system performance, only identical processors should be installed in a system.
Processor steppings within a common processor family can be mixed in a system provided that
there is no more than a one stepping difference between them. If the installed processors are
more than one stepping apart, an error is reported. Acceptable mixed steppings are not
reported as errors by the BIOS.
3.1.6.3 Mixed Processor Models
Processor models cannot be mixed in a system. If this condition is detected, an error (8196) is
logged in the SEL.
3.1.6.4 Mixed Processor Families
Processor families cannot be mixed in a system. If this condition is detected, an error (8194) is
logged in the SEL.
3.1.6.5 Mixed Processor Cache Sizes
If the installed processors have mixed cache sizes, an error (8192) will be logged in the SEL.
The size of all cache levels must match between all installed processors. Mixed cache
processors are not supported.
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3.1.6.6 Jumperless Processor Speed Settings
®
The Intel
XeonTM processor does not utilize jumpers or switches to set the processor frequency.
The BIOS reads the highest ratio register from all processors in the system. If all processors are
the same speed, the Actual Ratio register is programmed with the value read from the High
Ratio register. If all processors do not match, the highest common value between High and Low
Ratio is determined and programmed to all processors. If there is no value that works for all
installed processors, all processors not capable of speeds supported by the Boot Strap
Processor (BSP) are disabled and an error is displayed.
3.1.6.7 Microcode
IA-32 processors have the capability of correcting specific errata through the loading of an Intel
supplied data block, i.e., microcode update. The BIOS is responsible for storing the update in
non-volatile memory and loading it into each processor during POST. The BIOS allows a
number of microcode updates to be stored in the flash, limited by the amount of free space
available. The BIOS supports variable size microcode updates. The BIOS verifies the
signature prior to storing the update in the flash.
3.1.6.8 Processor Cache
The BIOS enables all levels of processor cache as early as possible during POST. There are no
user options to modify the cache configuration, size or policies. The largest and highest level
cache detected is reported in the BIOS Setup.
3.1.6.9 Hyper-Threading Technology
®
Intel
XeonTM processors support Hyper-Threading Technology. The BIOS detects processors
that support this feature and enables the feature during POST. The BIOS Setup provides an
option to selectively enable or disable this feature. The default behavior is “Enabled”.
The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors.
The SMBIOS Type 4 structure shows only the physical processors installed. It does not
describe the virtual processors because some operating systems are not able to efficiently
utilize the Hyper-Threading Technology.
3.1.6.10 Intel
Intel Xeon processors support the Geyserville3 (GV3) feature of the Intel
®
SpeedStep® Technology
®
SpeedStep®
Technology. This feature changes the processor operating ratio and voltage similar to the
Thermal Monitor 2 (TM2) feature. It must be used in conjunction with the TM1 or TM2 feature.
The BIOS implements the GV3 feature in conjunction with the TM2 feature.
3.1.6.11 EM64T Technology Support
The system BIOS on the server board SE7320SP2 and server board SE7525GP2 supports the
Intel Extended Memory 64 technology (EM64T) of the Intel Xeon processors. There is no BIOS
setup option to enable or disable this support. The system will be in IA-32 compatibility mode
when booting to an operating system. Operating system specific drivers are then loaded to
enable this capability.
3.1.6.12 Execute Disable Bit support
The system BIOS on the server board SE7320SP2 and server board SE7525GP2 supports the
Execute Disable (NX) bit in the latest Intel Xeon processors. This option can be enabled or
disabled in the BIOS setup utility. It is disabled by default to allow users to opt-in to the
protection this feature provides.
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3.1.7 Multiple Processor Initialization
IA-32 processors have a microcode-based Boot Strap Processor (BSP) arbitration protocol. On
reset, all of the processors compete to become the BSP. If a serious error is detected during a
Built-in Self-Test (BIST), that processor does not participate in the initialization protocol. A single
processor that successfully passes BIST is automatically selected by the hardware as the BSP
and starts executing from the reset vector (F000:FFF0h). A processor that does not perform the
role of BSP is referred to as an application processor (AP).
The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the
machine to boot the operating system. At boot time, the system is in virtual wire mode and the
BSP alone is programmed to accept local interrupts (INTR driven by programmable interrupt
controller (PIC) and non-maskable interrupt (NMI)).
As a part of the boot process, the BSP wakes each AP. When awakened, an AP programs its
Memory Type Range Registers (MTRRs) to be identical to those of the BSP. All APs execute a
halt instruction with their local interrupts disabled. If the BSP determines that an AP exists that is
a lower-featured processor or that has a lower value returned by the CPUID function, the BSP
switches to the lowest-featured processor in the system.
3.1.8 CPU Thermal Sensors
The CPU temperature will be indirectly measured via the thermal diodes. These are monitored
by the LM93 device. The mBMC configures the LM93 device to monitor these sensors. The
temperatures are available via mBMC IPMI sensors.
3.1.9 Processor Thermal Control Sensor
The Intel Xeon processors generate a signal indicating throttling due to thermal conditions. The
mBMC implements an IPMI sensor that provides the percentage of time a processor has been
throttling over the last 1.46 seconds. Server board management forces a thermal control
condition when reliable system operation requires reduced power consumption.
3.1.10 Processor Thermal Trip Shutdown
If a thermal overload condition exists (thermal trip) an Intel Xeon processor outputs a digital
signal that is monitored by the server board management sub-system. A thermal trip is a critical
condition and indicates that the processor may become damaged if it continues to run. To help
protect the processor, the management controller automatically powers off the system. In
addition it will assert the System Status LED and generate an event in the System Event Log.
3.1.11 Processor IERR
The IERR signal is asserted by the Intel Xeon processor as a result of an internal error. The
mBMC configures the heceta7 device to monitor this signal. When this signal is asserted, the
mBMC generates a processor IERR event.
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Intel® Server Board SE7320SP2 & Intel Server Board SE7525GP2 TPS Functional Architecture
3.2 E7320 Chipset
The architecture of the Intel Server Board SE7320SP2 is designed around the Intel® E7320
chipset. The Intel Server Board SE7525GP2 is designed around the Intel
®
E7525 chipset and
will be discussed in the next section. The Intel E7320 chipset is a subset of the Intel E7520
chipset and consists of two components which together are responsible for providing the
interface between all major sub-systems found on the server board including the processor,
memory, and I/O sub-systems. These components are the:
• Memory Controller Hub (MCH)
• I/O Controller Hub (Intel 6300ESB)
The following sub-sections will provide an overview describing the primary functions and
supported features of each chipset component. Later sections will discuss how these features
are implemented on the server board SE7320SP2 in greater detail.
3.2.1 Memory Controller Hub (MCH)
The MCH integrates four functions into a single 1077-ball FC-BGA package:
• Front Side Bus
• Memory Controller
• PCI-Express Controller
• Hub Link Interface
3.2.1.1 Front Side Bus (FSB)
The Intel E7320 MCH supports either single or dual processor configurations using Intel Xeon
processors designed for the 800MHz system bus. The MCH supports a base system bus
frequency of 200MHz. The address and request interface is double pumped to 400MHz while
the 64-bit data interface (+ parity) is quad pumped to 800MHz. This provides a matched system
bus address and data bandwidths of 6.4 GB/s.
3.2.1.2 MCH Memory Sub-System Overview
The Intel E7320 MCH provides an integrated memory controller for direct connection to two
channels of registered DDR266, DDR333 or DDR2-400 memory (stacked or unstacked). Peak
theoretical memory data bandwidth using DDR266 technology is 4.26 GB/s and 5.33 GB/s for
DDR333 technology. For DDR2-400 technology, this increases to 6.4 GB/s.
When both DDR channels are populated and operating, they function in lock-step mode. For the
Intel E7320 MCH, the maximum supported memory size at DDR266, DDR333 or DDR2-400
memory configuration is 12GB. On the server board SE7320SP2, the maximum supported
memory size at DDR266 or DDR333 is 8GB. DDR2-400 memory is not supported on server
board SE7320SP2.
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There are several RASUM (Reliability, Availability, Serviceability, Usability and Manageability)
features built into the Intel E7320 MCH memory interface:
• DIMM sparing allows for one DIMM per channel to be held in reserve and brought on-
line if another DIMM in the channel becomes defective.
• Hardware periodic memory scrubbing, including demand scrub support.
• Retry on uncorrectable memory errors.
• x4 SDDC (Single Device Data Correction) for memory error detection and correction of
any number of bit failures in a single x4 memory device.
3.2.1.3 PCI Express*
The Intel E7320 MCH is part of the first family of Intel chipsets to support the new PCI Express*
high speed serial I/O interface for high I/O bandwidth. The Intel E7320 MCH implementation of
the scalable PCI Express interface complies with the PCI Express Interface Specification, Rev
1.0a. The E7320 MCH provides one configurable x8 PCI Express interface with a maximum
theoretical bandwidth of 4GB/s. The x8 PCI Express interface may alternatively be configured
(bifurcated) as two independent x4 PCI Express interfaces. On the server board SE7320SP2,
the PCI-Express bandwidth is divided between two independent PCI-Express buses; one
operating at x4 for add-in cards, and one embedded on the board for possible future
upgradeability.
The Intel E7320 MCH is a root class component as defined in the PCI Express Interface
Specification, Rev 1.0a. The PCI Express interfaces of the MCH support connection to a variety
of bridges and devices compliant with the same revision of the specification. Refer to the
SE7320SP2/SE7525GP2 Tested Hardware and OS List for the adapters tested on those
systems.
3.2.1.4 Hub Interface
The MCH interfaces with the Intel 6300ESB I/O Controller Hub via a dedicated Hub Interface
supporting a peak bandwidth of 266MB/s using a x4 base clock of 66MHz. The 6300ESB I/O
controller will be discussed in further detail later in this document.
3.3 E7525 Chipset
The architecture of the server board SE7525GP2 is designed around the Intel® E7525 chipset.
The server board SE7320SP2 is designed around the E7320 chipset and was discussed in the
previous section. The Intel E7525 chipset is a subset of the Intel E7520 chipset and consists of
two components which together are responsible for providing the interface between all major
sub-systems found on the server board including the processor, memory, and I/O sub-systems.
These components are the:
• Memory Controller Hub (MCH)
• I/O Controller Hub (Intel 6300ESB)
The following sub-sections will provide an overview describing the primary functions and
supported features of each chipset component. Later sections will discuss how these features
are implemented on the server board SE7525GP2 in greater detail.
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3.3.1 Memory Controller Hub (MCH)
The MCH integrates four functions into a single 1077-ball FC-BGA package:
• Front Side Bus
• Memory Controller
• PCI-Express Controller
• Hub Link Interface
3.3.1.1 Front Side Bus (FSB)
The Intel
processors designed for the 800MHz system bus. The MCH supports a base system bus
frequency of 200MHz. The address and request interface is double pumped to 400MHz while
the 64-bit data interface (+ parity) is quad pumped to 800MHz. This provides a matched system
bus address and data bandwidths of 6.4 GB/s.
3.3.1.2 MCH Memory Sub-System Overview
The Intel E7525 MCH provides an integrated memory controller for direct connection to two
channels of registered DDR266, DDR333 or DDR2-400 memory (stacked or unstacked). Peak
theoretical memory data bandwidth using DDR266 technology is 4.26 GB/s and 5.33 GB/s for
DDR333 technology. For DDR2-400 technology, this increases to 6.4 GB/s.
®
E7525 MCH supports either single or dual processor configurations using Intel Xeon
When both DDR channels are populated and operating, they function in lock-step mode. For the
Intel E7525 MCH, the maximum supported memory size at DDR266, DDR333 or DDR2-400 is
12GB. On the server board SE7525GP2, the maximum supported memory size at DDR266 or
DDR333 is 8GB. DDR2-400 memory is not supported on the server board SE7525GP2.
There are several RASUM (Reliability, Availability, Serviceability, Usability and Manageability)
features built into the Intel E7525 MCH memory interface:
• DIMM sparing allows for one DIMM per channel to be held in reserve and brought on-
line if another DIMM in the channel becomes defective.
• Hardware periodic memory scrubbing, including demand scrub support.
• Retry on uncorrectable memory errors.
• x4 SDDC (Single Device Data Correction) for memory error detection and correction of
any number of bit failures in a single x4 memory device.
3.3.1.3 PCI Express*
The Intel E7525 MCH is part of the first family of Intel chipsets to support the new PCI Express*
high speed serial I/O interface for high I/O bandwidth. The Intel E7525 MCH implementation of
the scalable PCI Express interface complies with the PCI Express Interface Specification, Rev
1.0a. The MCH provides one x16 and one configurable x8 PCI Express interface with a
maximum theoretical bandwidth of 4GB/s. The x8 PCI Express interface may alternatively be
configured (bifurcated) as two independent x4 PCI Express interfaces. On the server board
SE7525GP2, the PCI-Express bandwidth is implemented as one x16 slot for high bandwidth
PCI-Express graphics adapters and one x4 slot for PCI-Express add-in cards.
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The Intel E7525 MCH is a root class component as defined in the PCI Express Interface
Specification, Rev 1.0a. The PCI Express interfaces of the MCH support connection to a variety
of bridges and devices compliant with the same revision of the specification. Refer to the
SE7320SP2 / SE7525GP2 Tested Hardware and OS List for the add-in cards tested on this
platform.
3.3.1.4 Hub Interface
The MCH interfaces with the Intel 6300ESB I/O Controller Hub via a dedicated Hub Interface
supporting a peak bandwidth of 266MB/s using a x4 base clock of 66MHz.
3.4 Intel® 6300ESB ICH
The Intel 6300ESB is a multi-function device providing an upstream hub interface for access to
several embedded I/O functions and features including:
• PCI Local Bus Specification, Revision 2.3 with support for 33MHz PCI operations.
• PCI-X 2.2 specification support for up to PCI-X 66MHz operation
• ACPI power management logic support
• Enhanced DMA controller, interrupt controller, and timer functions
• Integrated IDE controller with support for Ultra ATA100/66/33
• Integrated SATA controller
• USB host interface with support for four USB ports; four UHCI host controllers; one EHCI
high-speed USB 2.0 host controller
• System Management Bus (SMBus) Specification, Version 2.0 with additional support for
I2C devices
• Low Pin Count (LPC) interface
• Firmware Hub (FWH) interface support
Each function within the Intel 6300ESB I/O Controller has its own set of configuration registers.
Once configured, each appears to the system as a distinct hardware controller sharing the same
PCI bus interface.
3.4.1 PCI Interface
The Intel 6300ESB I/O Controller PCI interface provides a 33MHz, Revision 2.3 compliant
implementation. All PCI signals are 5-V tolerant, except PME#. The Intel 6300ESB I/O
Controller integrates a PCI arbiter that supports up to four external PCI bus masters in addition
to the internal Intel 6300ESB requests. On the server boards SE7320SP2 and SE7525GP2 this
PCI interface is used to support on-board PCI devices including the ATI* video controller, Intel
82541 Gigabit NIC, and the Super I/O chip.
Additionally the Intel 6300ESB I/O Controller Hub provides a 64-bit/66MHz revision 2.2
compliant PCI-X implementation. The bus is also PCI 2.2 compliant to provide backwards
compatibility with PCI devices. The Intel 6300ESB ICH also works as the PCI arbiter on this
bus and supports up to four external PCI bus masters in addition to the Intel 6300ESB I/O
Controller. On the server boards SE7320SP2 and SE7525GP2 there are two 3.3V PCI-X
connectors on this bus.
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3.4.2 IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks
and ATAPI devices. Each IDE device can have independent timings. The IDE interface supports
PIO IDE transfers up to 16 Mbytes/sec and Ultra ATA transfers up 100 Mbytes/sec. It does not
consume any ISA DMA resources. The IDE interface integrates 16x32-bit buffers for optimal
transfers. The Intel 6300ESB I/O Controller IDE system contains two independent IDE signal
channels. They can be electrically isolated independently. They can be configured to the
standard primary and secondary channels (four devices).
3.4.3 SATA Controller
The SATA controller supports two SATA devices providing an interface for SATA hard disks and
ATAPI devices. The SATA interface supports PIO IDE transfers up to 16 Mb/s and Serial ATA
transfers up to 1.5 Gb/s (150 MB/s). The Intel 6300ESB I/O Controller SATA system contains
two independent SATA signal ports. They can be electrically isolated independently. Each
SATA device can have independent timings. They can be configured to the standard primary
and secondary channels.
3.4.4 Low Pin Count (LPC) Interface
The Intel 6300ESB I/O Controller implements an LPC Interface as described in the Low Pin
Count Interface Specification, Revision 1.1. The Low Pin Count (LPC) Bridge function of the
Intel 6300ESB I/O Controller resides in PCI Device 31:Function 0. In addition to the LPC bridge
interface function, D31:F0 contains other functional units including DMA, interrupt controllers,
timers, power management, system management, GPIO, and RTC.
3.4.5 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt
Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.
The Intel 6300ESB I/O Controller supports two types of DMA (LPC and PC/PCI). LPC DMA and
PC/PCI DMA use the Intel 6300ESB I/O Controller DMA controller. The PC/PCI protocol allows
PCI-based peripherals to initiate DMA cycles by encoding requests and grants via two PC/PC
REQ#/GNT# pairs. LPC DMA is handled through the use of the LDRQ# lines from peripherals
and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes
are supported on the LPC interface. Channels 0–3 are 8 bit channels. Channels 5–7 are 16 bit
channels. Channel 4 is reserved as a generic bus master request.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The Intel 6300ESB I/O Controller provides an ISA-compatible Programmable Interrupt
Controller (PIC) that incorporates the functionality of two 82C59 interrupt controllers. The two
interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. In
addition, the Intel 6300ESB I/O Controller supports a serial interrupt scheme. All of the registers
in these modules can be read and restored. This is required to save and restore the system
state after power has been removed and restored to the platform.
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3.4.6 Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA-compatible PIC described in the previous section, the Intel
6300ESB I/O Controller incorporates the Advanced Programmable Interrupt Controller (APIC).
3.4.7 Universal Serial Bus (USB) Controller
The Intel 6300ESB I/O Controller contains an Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0 compliant host controller that supports USB high-speed
signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is 40 times faster
than full-speed USB. The Intel 6300ESB I/O Controller also contains four Universal Host
Controller Interface (UHCI) controllers that support USB full-speed and low-speed signaling. On
the server board SE7320SP2, the Intel 6300ESB I/O Controller supports four USB 2.0 ports. All
four ports are high-speed, full-speed, and low-speed capable. Intel 6300ESB I/O Controller portrouting logic determines whether a USB port is controlled by one of the UHCI controllers or by
the EHCI controller.
3.4.8 RTC
The Intel 6300ESB I/O Controller contains the real-time clock with 256 bytes of battery backed
RAM. The real-time clock performs two key functions: keeping track of the time of day and
storing system data, even when the system is powered down. The RTC operates on a 32.768
KHz crystal and a separate 3 V lithium battery. The RTC also supports two lockable memory
ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to read and
write accesses. This prevents unauthorized reading of passwords or other system security
information. The RTC also supports a date alarm that allows for scheduling a wake up event up
to 30 days in advance, rather than just 24 hours in advance.
3.4.9 GPIO
Various general purpose inputs and outputs are provided for custom system design. The
number of inputs and outputs varies depending on the Intel 6300ESB I/O Controller
configuration. All unused GPI pins must be pulled high or low, so that they are at a predefined
level and do not cause undue side effects.
3.4.10 Enhanced Power Management
The Intel 6300ESB I/O Controller power management functions include enhanced clock control,
local and global monitoring support for 14 individual devices, and various low-power (suspend)
states (e.g., Suspend-to-DRAM and Suspend-to-Disk). A hardware-based thermal management
circuit permits software-independent entrance to low-power states. The Intel 6300ESB I/O
Controller contains full support for the Advanced Configuration and Power Interface (ACPI)
Specification, Revision 2.0b.
3.4.11 System Management Bus (SMBus 2.0)
The Intel 6300ESB I/O Controller contains an SMBus Host interface that allows the processor to
communicate with SMBus slaves. This interface is compatible with most I2C devices. Special
I2C commands are implemented. The Intel 6300ESB I/O Controller SMBus host controller
provides a mechanism for the processor to initiate communications with SMBus peripherals
(slaves). Also, the Intel 6300ESB I/O Controller supports slave functionality, including the Host
Notify protocol. Hence, the host controller supports eight command protocols of the SMBus
interface (see System Management Bus (SMBus) Specification, Version 2.0): Quick Command,
Send Byte, Receive Byte, Write Byte/Word, Read Byte/Word, Process Call, Block Read/Write,
and Host Notify.
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3.5 Memory Sub-System
On the Intel Server Board SE7320SP2 and Intel Server Board SE7525GP2, the MCH provides
an integrated memory controller for direct connection to two channels of registered DDR266 or
DDR333 memory (stacked or unstacked). Peak theoretical memory data bandwidth using
DDR266 technology is 4.26 GB/s and 5.33 GB/s for DDR333 technology.
When both DDR channels are populated and operating, they function in lock-step mode. The
maximum supported memory size for either memory speed is 8GB.
The MCH supports a burst length of four whether in single or dual channel mode. In dual
channel mode this results in eight 64-bit chunks (64-byte cache line) from a single read or write.
In single channel mode two reads or writes are required to access a cache line of data.
3.5.1 Memory Sizing
Both the Intel Server Board SE7320SP2 and Intel Server Board SE7525GP2 provide four
DDR266 / DDR333 DIMM sites. There are two DIMM sites on each memory channel.
DIMMs on channel A are paired with DIMMs on channel B to configure 2-way interleaving. The
minimum memory configuration to support interleaving is two DIMMs, which requires same
DIMM populated from each channel. Each board does support single channel memory
operation with a single DIMM populated in DIMM location 1 on either bank (1A or 2A). It should
be noted that single channel operation greatly reduces memory bandwidth and RAS capabilities.
Memory DIMM technologies supported are: 128Mb, 256Mb, 512Mb, 1Gb and 2Gb. Physical
DIMM sizes supported are 256MB, 512MB, 1GB, and 2GB.
Please refer to the Tested Memory List located on the support website for a complete list of
supported memory.
http://support.intel.com/support/motherboards/server/se7320sp2
http://support.intel.com/support/motherboards/server/se7525gp2
The BIOS reads the Serial Presence Detect (SPD) SEEPROMs on each installed memory
module to determine the size and timing of the installed memory modules. The memory sizing
algorithm determines the size of each row of DIMMs. The BIOS programs the Memory
Controller in the chipset accordingly. The total amount of configured memory can be found
using BIOS Setup.
The DIMM pair, which constitutes interleaving, is referred to as a bank. The bank can be further
divided into two rows, based on single-sided or double-sided DIMMs. If both DIMMs in a pair are
single-sided, only one row is said to be present in the system. For double-sided DIMMs, both
rows are said to be present.
For interleaving and RAS to be enabled, memory DIMMs must be populated in pairs. The Intel
Server Board SE7320SP2 and Intel Server Board SE7525GP2 each have four DIMM slots, or
two DIMM banks. Both DIMMs in a bank should be identical (same manufacturer, CAS latency,
number of rows, columns and devices, timing parameters etc.). Although DIMMs within a bank
must be identical, the BIOS supports various DIMM sizes and configurations, allowing the banks
of memory to be different. Memory sizing and configuration is guaranteed only for qualified
DIMMs approved by Intel.
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3.5.2 Memory Population
The mixing of memory DDR266 and DDR333 is supported on server board SE7320SP2 and
server board SE7525GP2. However, when mixing DIMM speeds, DDR333 will be treated as
DDR266.
DIMM search rules for standard mode:
1. If DIMM dual pair# >= 1, set memory controller to dual channel mode. Otherwise, go to
step (2).
2. If Channel A DIMM is present, set memory controller to single channel mode A.
Otherwise, go to step (3).
3. If Channel B DIMM is present, set memory controller to single channel mode B.
Otherwise, memory configuration error.
The DIMM population rules are as follows:
• DIMMs should be populated starting from the bank furthest from the MCH –
DIMM slots 1A and 1B.
• Starting with Bank 1, mixed DIMMs must be populated by single rank, then dual
rank.
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The following diagram identifies the memory bank locations on the server board.
Figure 6 - DIMM Socket Configuration
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The following tables show supported memory populations for the server boards SE7320SP2
and SE7525GP2.
Table identifiers:
S/R = single rank
D/R = dual rank
E = Empty
Table 4: Supported DDR-266 DIMM Populations
DIMM
Slot
A2
E S/R E E
S/R S/R E E
E D/R E E
D/R D/R E E
D/R S/R E E
DIMM
Slot
A1
DIMM
Slot
B2
DIMM
Slot
B1
MCH
Table 5: Supported DDR-333 DIMM Populations
DIMM
Slot
A2
E S/R E E
S/R S/R E E
E D/R E E
D/R D/R E E
D/R S/R E E
DIMM
Slot
A1
DIMM
Slot
B2
DIMM
Slot
B1
MCH
Table 6: DIMM Module Capacities
Parts 128Mb 256Mb 512Mb 1Gb
X8, single row 256MB 512MB 1GB
X8, double row 256MB 512MB 1GB 2GB
X4, single row 256MB 512MB 1GB 2GB
X4, Stacked, double
512MB 1GB 2GB 4GB
row
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Table 7: Possible Memory Capacities
# of
DIMMS
1 256MB 512MB 1GB 2GB
2 Single Chan 512MB 1GB 2GB 4GB
2 1GB 2GB 4GB 8GB
4 X 1GB 2GB 4GB 8GB
4 X 2GB 4GB 8GB
Spare 128Mb 256Mb 512Mb 1Gb
Note: Memory between 4GB and 4GB minus 512MB will not be accessible for use by the
operating system and may be lost to the user, because this area is reserved for BIOS, APIC
configuration space, PCI adapter interface, and virtual video memory space. This means that if
4GB of memory is installed, 3.5GB of this memory is usable. The chipset should allow the
remapping of unused memory above the 4GB address, but this memory may not be accessible
to an operating system that has a 4GB memory limit.
The minimum memory installed may be 256MB (one 256MB DIMM).
3.5.3 I2C Bus
To boot the system, the system BIOS uses a dedicated I2C bus to retrieve DIMM information
needed to program the MCH memory registers.
3.5.4 Disabling DIMMs
The BIOS provides a mechanism to disable a DIMM if it is detected to be faulty. A faulty DIMM
is defined to have either multiple correctable errors or a single uncorrectable error on a single
DIMM. Memory errors are logged during runtime and single bit ECC Errors are counted.
Though DIMMs are marked as “Disabled”, they are actually disabled only during the next reboot.
At the next system boot, memory-sizing code reads the recorded state of the DIMMs and skips
sizing DIMMs marked as disabled. Because DIMMs are always used in 2-way interleaving, the
DIMM pair is disabled. The disabled DIMMs are indicated by an LED next to the DIMM socket.
If all DIMMs in a system have been disabled, the BIOS generates beep codes to indicate that
the system has no usable memory.
Disabled DIMMs/rows may be re-enabled through a BIOS Setup option. The DIMM slot will no
longer be disabled if the system boots without memory in the DIMM slot.
3.5.5 Memory RASUM Features
The Intel E7320 MCH and Intel E7525 MCH support several memory RASUM (Reliability,
Availability, Serviceability, Usability, and Manageability) features that have traditionally been
found only on high end server systems. These features include x4 SDDC for memory error
detection and correction, Memory Scrubbing, Retry on Correctable Errors, Integrated Memory
Initialization, and DIMM Sparing. The following sections describe how each is supported on the
Intel Server Boards SE7320SP2 and SE7525GP2.
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3.5.5.1 DRAM ECC – Intel® x4 Single Device Data Correction (x4 SDDC)
The DRAM interface uses two different ECC algorithms. The first is a standard SEC/DED ECC
across a 64-bit data quantity. The second ECC method is a distributed, 144-bit S4EC-D4ED
mechanism, which provides x4 SDDC protection for DIMMS that utilize x4 devices. Bits from x4
parts are presented in an interleaved fashion such that each bit from a particular part is
represented in a different ECC word. DIMMs that use x8 devices, can use the same algorithm
but will not have x4 SDDC protection, since at most only four bits can be corrected with this
method. The algorithm does provide enhanced protection for the x8 parts over a standard SECDED implementation. With two memory channels, either ECC method can be utilized with equal
performance, although single-channel mode only supports standard SEC/DED.
When memory mirroring is enabled, x4 SDDC ECC is supported in single channel mode when
the second channel has been disabled during a fail-down phase. x4 SDDC ECC is not
supported during single-channel operation outside of DIMM mirroring fail-down as it does have
significant performance impacts in that environment.
3.5.5.2 Integrated Memory Scrub Engine
The Intel E7320 and Intel E7525 MCHs include an integrated engine to walk the populated
memory space proactively seeking out soft errors in the memory subsystem. In the case of a
single bit correctable error, this hardware detects, logs, and corrects the data except when an
incoming write to the same memory address is detected. For any uncorrectable errors detected,
the scrub engine logs the failure. Both types of errors may be reported via multiple alternate
mechanisms under configuration control. The scrub hardware will also execute “demand scrub”
writes when correctable errors are encountered during normal operation (on demand reads,
rather than scrub-initiated reads). This functionality provides incremental protection against
time-based deterioration of soft memory errors from correctable to uncorrectable.
Using this method, an 8GB system can be completely scrubbed in less than one day. (The
effect of these scrub writes do not cause any noticeable degradation to memory bandwidth,
although they will cause a greater latency for that one very infrequent read that is delayed due
to the scrub write cycle.)
Note that an uncorrectable error encountered by the memory scrub engine is a “speculative
error.” This designation is applied because no system agent has specifically requested use of
the corrupt data, and no real error condition exists in the system until that occurs. It is possible
that the error resides in an unmodified page of memory that will be simply dropped on a swap
back to disk. Were that to occur, the speculative error would simply “vanish” from the system
undetected without adverse consequences.
3.5.5.3 Retry on Uncorrectable Error
The Intel E7320 and Intel E7525 MCHs include specialized hardware to resubmit a memory
read request upon detection of an uncorrectable error. When a demand fetch (as opposed to a
scrub) of memory encounters an uncorrectable error as determined by the enabled ECC
algorithm, the memory control hardware will cause a (single) full resubmission of the entire
cache line request from memory to verify the existence of corrupt data. This feature is expected
to greatly reduce or eliminate the reporting of false or transient uncorrectable errors in the
DRAM array.
Note that any given read request will only be retried a single time on behalf of this error
detection mechanism. If the uncorrectable error is repeated it will be logged and escalated as
directed by device configuration. In the memory mirror mode, the retry on an uncorrectable error
will be issued to the mirror copy of the target data, rather than back to the devices responsible
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for the initial error detection. This has the added benefit of making uncorrectable errors in
DRAM fully correctable unless the same location in both primary and mirror happens to be
corrupt (statistically very unlikely). This RASUM feature may be enabled and disabled via
configuration.
3.5.5.4 Integrated Memory Initialization Engine
The Intel E7320 and Intel E7525 MCHs provide hardware managed ECC auto-initialization of all
populated DRAM space under software control. Once internal configuration has been updated
to reflect the types and sizes of populated DIMM devices, the MCH will traverse the populated
address space initializing all locations with good ECC. This not only speeds up the mandatory
memory initialization step, but also frees the processor to pursue other machine initialization
and configuration tasks.
Additional features have been added to the initialization engine to support high speed
population and verification of a programmable memory range with one of four known data
patterns (0/F, A/5, 3/C, and 6/9). This function facilitates a limited, very high speed memory test,
as well as provides a BIOS accessible memory zeroing capability for use by the operating
system.
3.5.5.5 DIMM Sparing Function
To provide a more fault tolerant system, the Intel E7320 MCH and Intel E7525 MCH include
specialized hardware to support fail-over to a spare DIMM device in the event that a primary
DIMM in use exceeds a specified threshold of runtime errors. One of the DIMMs installed per
channel will not be used, but kept in reserve. In the event of significant failures in a particular
DIMM, it and its corresponding partner in the other channel (if applicable), will, over time, have
its data copied over to the spare DIMM(s) held in reserve. When all the data has been copied,
the reserve DIMM(s) will be put into service and the failing DIMM will be removed from service.
Only one sparing cycle is supported. If this feature is not enabled, then all DIMMs will be visible
in normal address space.
Note: DIMM Sparing feature requires that the spare DIMM be at least the size of the largest
primary DIMM in use.
Hardware additions for this feature include the implementation of tracking register per DIMM to
maintain a history of error occurrence, and a programmable register to hold the fail-over error
threshold level. The operational model is straightforward: set the fail-over threshold register to a
non-zero value to enable the feature, and if the count of errors on any DIMM exceeds that value,
fail-over will commence. The tracking registers themselves are implemented as “leaky buckets,”
such that they do not contain an absolute cumulative count of all errors since power-on; rather,
they contain an aggregate count of the number of errors received over a running time period.
The “drip rate” of the bucket is selectable by software, so it is possible to set the threshold to a
value that will never be reached by a “healthy” memory subsystem experiencing the rate of
errors expected for the size and type of memory devices in use.
The fail-over mechanism is slightly more complex. Once fail-over has been initiated the MCH
must execute every write twice; once to the primary DIMM, and once to the spare. (This
requires that the spare DIMM be at least the size of the largest primary DIMM in use.) The MCH
will also begin tracking the progress of its built-in memory scrub engine. Once the scrub engine
has covered every location in the primary DIMM, the duplicate write function will have copied
every data location to the spare. At that point, the MCH can switch the spare into primary use,
and take the failing DIMM off-line.
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Note that this entire mechanism requires no software support once it has been programmed and
enabled, until the threshold detection has been triggered to request a data copy. Hardware will
detect the threshold initiating fail-over, and escalate the occurrence of that event as directed
(signal an SMI, generate an interrupt, or wait to be discovered via polling). Whatever software
routine responds to the threshold detection must select a victim DIMM (in case multiple DIMMs
have crossed the threshold prior to sparing invocation) and initiate the memory copy. Hardware
will automatically isolate the “failed” DIMM once the copy has completed. The data copy is
accomplished by address aliasing within the DDR control interface, thus it does not require
reprogramming of the DRAM row boundary (DRB) registers, nor does it require notification to
the operating system that anything has occurred in memory.
3.6 I/O Sub-System
The I/O sub-system is made up of several components: the MCH providing the PCI-Express
interface and the Intel 6300ESB I/O Controller providing the interface for the onboard video
controller, Super IO chip, and Management Sub-system. This section describes the function of
each I/O interface and how they operate on the Intel Server Boards SE7320SP2 and
SE7525GP2.
3.6.1 PCI Subsystem
The primary I/O interface for the Server Boards SE7320SP2 and SE7525GP2 is PCI, with two
independent PCI bus segments. A PCI 33 MHz 32-bit bus segment (P32-A) with two connectors
and a PCI-X 64-bit / 66MHz segment (P64-A) are controlled through the Intel 6300ESB I/O
Controller. Additionally, one x4 PCI-Express (P64-Express4) bus segment controlled from the
MCH on the Intel Server Board SE7320SP2 is available. Or one x4 PCI-Express bus segment
and one x16 PCI-Express bus segment (P64-Express16) are available on the Intel Server Board
SE7525GP2. The table below lists the characteristics of the different PCI bus segments.
Table 8: PCI Bus Segment Characteristics
PCI Bus Segment Voltage Width Speed Type PCI I/O Card Slots
P32-A 5 V 32-bits 33 MHz PCI 2 slots
P64-A 3.3 V 64-bits 66 MHz PCI-X 2 slots
P64-Express4 1.6 V 64-bits x4 PCI-E 1 slot
P64-Express16 1.6 V 64-bits x16 PCI-E 1 slot (SE7525GP2 only)
3.6.1.1 P32-A: 32-bit, 33-MHz PCI Subsystem
All 32-bit, 33-MHz PCI I/O for the Intel Server Boards SE7320SP2 and server board
SE7525GP2s are directed through the Intel 6300ESB I/O Controller. The 32-bit, 33-MHz PCI
segment created by the Intel 6300ESB I/O Controller is known as the P32-A segment. The P32A segment supports the following devices:
• 2D/3D Graphics Accelerator: ATI* Rage XL Video Controller
• SIO Chip: National Semiconductor* PC87417 Super I/O
• Hardware monitoring sub-system: SMBUS
• Intel 82541 PCI Gigabit NIC
• 2 Expansion Slots
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3.6.1.2 P64-A: 64-bit, 66MHz PCI Subsystem
There is a single 64-bit PCI-X bus segments directed through the Intel 6300ESB I/O Hub. The
PCI-X segment, P64-A supports the interface for two 3.3V 64-bit PCI-X slots.
3.6.1.3 P64-Express4: x4 PCI-Express Bus Segment
The P64-Express4 bus segment supports x4 PCI-Express signaling. The Intel Server Boards
SE7320SP2 and SE7525GP2 implement a x8 PCI-Express connector on this bus to enhance
the breadth of supported devices, however all devices will operate at a maximum speed of x4
(2GB/s).
3.6.1.4 P64-Express16: x16 PCI-Express bus segment
The P64-Express16 bus segment supports x16 PCI-Express signaling on the Intel Server Board
SE7525GP2 only.
3.6.1.5 Scan Order
The BIOS assigns PCI bus numbers in a depth-first hierarchy, in accordance with the PCI Local
Bus Specification. When a bridge device is located, the bus number is incremented in exception
of a bridge device in the chipsets. Scanning continues on the secondary side of the bridge until
all subordinate buses are defined. PCI bus numbers may change when PCI-PCI bridges are
added or removed. If a bridge is inserted in a PCI bus, all subsequent PCI bus numbers below
the current bus will be increased by one.
3.6.1.6 Resource Assignment
The resource manager assigns the PIC-mode interrupt for the devices that will be accessed by
the legacy code. The BIOS will ensure the PCI BAR registers and the command register for all
devices are correctly set up to match the behavior of the legacy BIOS. Code cannot make
assumptions about the scan order of devices or the order in which resources will be allocated to
them. The BIOS will support the INT 1Ah PCI BIOS interface calls.
3.6.1.7 Automatic IRQ Assignment
The BIOS automatically assigns IRQs to devices in the system for legacy compatibility. No
method is provided to manually configure the IRQs for devices
.
3.6.1.8 Option ROM Support
The option ROM support code in the BIOS will dispatch the option ROMs in available memory
space in the address range 0c0000h-0e7fffh and will follow all rules with respect to the option
ROM space. The BIOS for the Intel Server Boards SE7320SP2 and SE7525GP2 will integrate
option ROMs for all the integrated components on the board.
3.6.1.9 PCI APIs
The system BIOS supports the INT 1Ah, AH = B1h functions as defined in the PCI BIOS
Specification. The system BIOS supports the real mode interfaces and does not support the
protected mode interfaces.
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3.6.2 Split Option ROM
The BIOS supports the split option ROM algorithm per the PCI 3.0 specification.
3.6.3 Interrupt Routing
Both the Intel Server Board SE7320SP2 and SE7525GP2 interrupt architectures accommodate
both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O
APICs in the Intel 6300ESB I/O Controller.
3.6.3.1 Legacy Interrupt Routing
For PC-compatible mode, the Intel 6300ESB I/O Controller provides two 82C59-compatible
interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on
level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is
presented to the processors, to which only one processor will respond for servicing. The Intel
6300ESB I/O Controller contains configuration registers that define which interrupt source
logically maps to I/O APIC INTx pins.
Interrupts, both PCI and IRQ types, are handled by the Intel 6300ESB I/O Controller. The Intel
6300ESB I/O Controller then translates these to the APIC bus. The numbers in the table below
indicate the Intel 6300ESB I/O Controller PCI interrupt input pin to which the associated device
interrupt (INTA, INTB, INTC, INTD) is connected. The Intel 6300ESB I/O Controller I/O APIC
exists on the I/O APIC bus with the processors.
Table 9: PCI Interrupt Routing/Sharing
Interrupt INT A INT B INT C INT D
Video PIRQB
Intel 82541 NIC PIRQA
PCI Slot 3 (PCI 32b/33M) PIRQF PIRQD PIRQB PIRQH
PCI Slot 5 (PCI 32b/33M) PIRQE PIRQB PIRQH PIRQD
PCI Slot 2 (64b/66M) PXIRQ1 PXIRQ2 PXIRQ3 PXIRQ0
PCI Slot 1 (64b/66M) PXIRQ0 PXIRQ1
3.6.3.2 APIC Interrupt Routing
For APIC mode, the Intel Server Boards SE7320SP2 and SE7525GP2 interrupt architectures
incorporate three Intel I/O APIC devices to manage and broadcast interrupts to local APICs in
each processor. The Intel I/O APICs monitor each interrupt on each PCI device including PCI
slots in addition to the ISA compatibility interrupts IRQ(0-15).
When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire
serial interface to the local APICs. The APIC bus minimizes interrupt latency time for
compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to
the processor(s). This APIC bus consists of an APIC clock and two bidirectional data lines.
3.6.3.3 Legacy Interrupt Sources
The table below recommends the logical interrupt mapping of interrupt sources on the Intel
Server Boards SE7320SP2 and SE7525GP2. The actual interrupt map is defined using
configuration registers in the Intel 6300ESB I/O Controller.
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Table 10: Interrupt Definitions
ISA Interrupt Description
INTR Processor interrupt.
NMI NMI to processor.
IRQ0 System timer
IRQ1 Keyboard interrupt.
IRQ2 Slave PIC
IRQ3 Serial port 1 or 2 interrupt from SUPER IO device, user-configurable.
IRQ4 Serial port 1 or 2 interrupt from SUPER IO device, user-configurable.
IRQ5 Parallel Port / Generic
IRQ6 Floppy disk.
IRQ7 Generic
IRQ8_L Active low RTC interrupt.
IRQ9 SCI*
IRQ10 Generic
IRQ11 Generic
IRQ12 Mouse interrupt.
IRQ13 Floating point processor.
IRQ14 Compatibility IDE interrupt from primary channel IDE devices 0 and 1.
IRQ15 Secondary IDE Cable
SMI*
System Management Interrupt. General purpose indicator sourced by the 6300ESB to the
processors.
3.6.3.4 Serialized IRQ Support
The Intel Server Boards SE7320SP2 and SE7525GP2 support a serialized interrupt delivery
mechanism. Serialized Interrupt Requests (SERIRQ) consists of a start frame, a minimum of 17
IRQ / data channels, and a stop frame. Any slave device in the quiet mode may initiate the start
frame. While in the continuous mode, the start frame is initiated by the host controller.
3.6.3.5 IRQ Scan for PCIIRQ
The IRQ / data frame structure includes the ability to handle up to 32 sampling channels with
the standard implementation using the minimum 17 sampling channels. The Intel Server Boards
SE7320SP2 and SE7525GP2 have an external PCI interrupt serializer for PCIIRQ scan
mechanism of Intel 6300ESB I/O Controller to support 16 PCIIRQs.
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6300ESB ICH I/O APIC
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ20
IRQ21
IRQ22
IRQ23
6300ESB
ICH
6300ESB
ICH
8259PIC
HI1.5 INTERFACE
X4 PCI-E interface
X8
connector
MCH
CPU1
INTR
X16 PCI-E interface
(Supported by SE7525GP2 only)
INTR
CPU2
X16
Connector
Figure 7 - Interrupt Routing Diagram (Intel 6300ESB Internal)
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y
ppy
p
Q
,
,
Q
Q
Q
,
Timer
Ke
board
Cascade
Serial Port2/ISA
Serial Port1/ISA
ISA
Flo
/ISA
ISA
RTC
SCI/ISA
ISA
ISA
Mouse/ISA
Co
rocessor Error
P IDE/ISA
Not Used
Super I/O
Serialized IRQ Interface
SERIR
SERIRQ
PCI Interface
Intel 6300ESB ICH
Interrupt Routing
Intel 82541 INTA
Video INTA, Slot 3 INTC, Slot 5 INTB
Slot 3 INTB
Slot 5 INTD
Slot 5 INTA
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#
Slot 3 INTA
Slot 3 INTD
Slot 5 INTC
PIRQF#
PIRQG#
PIRQH#
Slot 1 INTA, Slot 2 INTD
PXIR
0
Slot 1 INTB
Slot 2 INTA
PXIR
1
interface
PCI-X
Slot 2 INTB
Slot 2 INTC
PXIR
2
PXIRQ3
Figure 8 - Interrupt Routing Diagram
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3.6.4 IDE Support
Integrated IDE controllers of the Intel 6300ESB I/O Controller provide two independent IDE
channels, each capable of supporting up to two drives. Both channels provide a standard 40pin IDE connector on the server board. Each IDE channel can be configured or
enabled/disabled by accessing the BIOS Setup Utility during POST.
3.6.4.1 Ultra ATA/100
The IDE interfaces of the Intel 6300ESB I/O Controller DMA protocol redefines signals on the
IDE cable to allow both host and target throttling of data and transfer rates of up to 100 MB/s.
3.6.4.2 IDE Initialization
The BIOS supports the ATA/ATAPI Specification, version 6 or later. The BIOS initializes the
embedded IDE controller in the chipset (Intel 6300ESB I/O Controller) and the IDE devices that
are connected to these devices. The BIOS scans the IDE devices and programs the controller
and the devices with their optimum timings. The IDE disk read/write services that are provided
by the BIOS will use PIO mode, but the BIOS will program the necessary Ultra DMA registers in
the IDE controller so that the operating system can use the Ultra DMA Modes.
3.6.5 SATA Support
The integrated Serial ATA (SATA) controller of the Intel 6300ESB I/O Controller provides two
SATA ports on the server board. The SATA ports can be enabled/disabled and/or configured by
accessing the BIOS Setup Utility during POST.
The SATA function in the Intel 6300ESB I/O Controller has dual modes of operation to support
different operating system conditions. In the case of Native IDE enabled operating systems, the
Intel 6300ESB I/O Controller has separate PCI functions for serial and parallel ATA. To support
legacy operating systems, there is only one PCI function for both the serial and parallel ATA
ports. The MAP register provides the ability to share PCI functions. When sharing is enabled, all
decode of I/O is done through the SATA registers. Device 31, Function 1 (IDE controller) is
hidden by software writing to the Function Disable Register (D31, F0, offset F2h, bit 1), and its
configuration registers are not used. The SATA Capability Pointer Register (offset 34h) will
change to indicate that MSI is not supported in combined mode.
The Intel 6300ESB I/O Controller SATA controller features two sets of interface signals that can
be independently enabled or disabled. Each interface is supported by an independent DMA
controller. The Intel 6300ESB I/O Controller SATA controller interacts with an attached mass
storage device through a register interface that is equivalent to that presented by a traditional
IDE host adapter. The host software follows existing standards and conventions when
accessing the register interface and follows standard command protocol conventions.
SATA interface transfer rates are independent of UDMA mode settings. SATA interface transfer
rates will operate at the bus’s maximum speed, regardless of the UDMA mode reported by the
SATA device or the system BIOS.
3.6.5.1 SATA RAID
The Intel® RAID Technology solution, available with the Intel 6300ESB I/O Controller offers
data stripping for higher performance (RAID Level 0) or data mirroring for better data protection
(RAID 1). There is no loss of PCI resources (request/grant pair) or add-in card slot.
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Intel RAID Technology functionality requires the following items:
• Intel 6300ESB
• Intel RAID Technology Option ROM must be on the platform
• Intel® Application Accelerator RAID Edition drivers, most recent revision.
• Two SATA hard disk drives.
• Intel RAID Technology is not available in the following configurations:
o The SATA controller in compatible mode.
o Intel RAID Technology has been disabled - D31:F0:AE bits [7:6] have been
cleared
3.6.5.2 Intel® RAID Technology Option ROM
The Intel RAID Technology for SATA Option ROM provides a pre-OS user interface for the Intel
RAID Technology implementation and provides the ability for a Intel RAID Technology volume
to be used as a boot disk as well as to detect any faults in the Intel RAID Technology volume(s)
attached to the Intel RAID controller.
3.6.6 Video Controller
Both server boards provide an ATI* Rage XL PCI graphics accelerator, along with 8 MB of video
SDRAM and support circuitry for an embedded SVGA video subsystem. The ATI Rage XL chip
contains a SVGA video controller, clock generator, 2D and 3D engine, and RAMDAC in a 272pin PBGA. One 2Mx32 SDRAM chip provides 8 MB of video memory.
The SVGA subsystem supports a variety of modes, up to 1600 x 1200 resolution in 8/16/24/32
bpp modes under 2D, and up to 1024 x 768 resolution in 8/16/24/32 bpp modes under 3D. It
also supports both CRT and LCD monitors up to 100 Hz vertical refresh rate.
Video is accessed using a standard 15-pin VGA connector found on the back edge of the server
board. On-board video can be disabled using the BIOS Setup Utility which is accessed during
POST or when a add-in video card is installed in any of the PCI slots.
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3.6.6.1 Video Modes
The Rage XL chip supports all standard IBM VGA modes. The following table shows the 2D/3D
modes supported for both CRT and LCD.
Table 11: Video Modes
2D Video Mode Support 2D Mode Refresh Rate (Hz)
8 bpp 16 bpp 24 bpp 32 bpp
640x480 60,72,75,90,100 Supported Supported Supported Supported
800x600 60,70,75,90,100 Supported Supported Supported Supported
1024x768 60,72,75,90,100 Supported Supported Supported Supported
1280x1024 43,60 Supported Supported Supported Supported
1280x1024 70,72 Supported – Supported Supported
1600x1200 60,66 Supported Supported Supported Supported
1600x1200 76,85 Supported Supported Supported –
3D Mode Refresh Rate (Hz) 3D Video Mode Support with Z Buffer Enabled
640x480 60,72,75,90,100 Supported Supported Supported Supported
800x600 60,70,75,90,100 Supported Supported Supported Supported
1024x768 60,72,75,90,100 Supported Supported Supported Supported
1280x1024 43,60,70,72 Supported Supported – –
1600x1200 60,66,76,85 Supported – – –
3D Mode Refresh Rate (Hz) 3D Video Mode Support with Z Buffer Disabled
640x480 60,72,75,90,100 Supported Supported Supported Supported
800x600 60,70,75,90,100 Supported Supported Supported Supported
1024x768 60,72,75,90,100 Supported Supported Supported Supported
1280x1024 43,60,70,72 Supported Supported Supported –
1600x1200 60,66,76,85 Supported Supported – –
3.6.6.2 Video Memory Interface
The memory controller subsystem of the Rage XL arbitrates requests from direct memory
interface, the VGA graphics controller, the drawing coprocessor, the display controller, the video
scalar, and hardware cursor. Requests are serviced in a manner that ensures display integrity
and maximum CPU/coprocessor drawing performance.
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Both boards support an 8MB (512Kx32bitx4 Banks) SDRAM device for video memory. The
following table shows the video memory interface signals:
Table 12: Video Memory Interface
Signal Name I/O Type Description
CAS# O Column Address Select
CKE O Clock Enable for Memory
CS#[1..0] O Chip Select for Memory
DQM[7..0] O Memory Data Byte Mask
DSF O Memory Special Function Enable
HCLK O Memory Clock
[11..0] O Memory Address Bus
MD[31..0] I/O Memory Data Bus
RAS# O Row Address Select
WE# O Write Enable
3.6.7 Network Interface Controller (NIC)
3.6.7.1 Intel 82541
The Intel 82541 gigabit network interface controller supplies the server board with a single
network interface. The 82541 controller is capable of supporting 10/100/1000 operation and
alert-on-LAN functionality. The controller can be disabled by using the BIOS Setup Utility
accessed during POST. The 82541 supports the following features:
• 32-bit PCI Rev. 2.3 compliant master interface
• Integrated IEEE 802.3 10Base-T, 100Base-TX and 1000Base-TX compatible PHY
• IEEE 820.3ab auto-negotiation support
• Full duplex support at 10 Mbps, 100Mbps and 1000 Mbps operation
• Integrated UNDI ROM support
• MDI/MDI-X and HWI support
3.6.7.2 NIC Connector and Status LEDs
The Intel 82541 network controller drives two LEDs located on the network interface connector.
The link/activity LED (to the left of the connector) indicates network connection when on, and
Transmit/Receive activity when blinking. The speed LED (to the right of the connector) indicates
1000-Mbps operations when amber, 100-Mbps operations when green, and 10-Mbps when off.
3.6.8 USB 2.0 Support
The USB controller functionality integrated into Intel 6300ESB I/O Controller provides the server
board with the interface for up to four USB 2.0 ports. Two external connectors are located on
the back edge of the server board. One internal 2x5 header is provided which is capable of
supporting an additional 2 optional connectors.
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3.6.9 Super I/O Chip
The Server I/O is the National Semiconductor* PC87427 controller. It is located on the Intel
6300ESB I/O Controller LPC bus. For LPC and SMBus access, the PC87427features a fast XBus, over which boot flash and I/O devices can be accessed. The PC87427supports X-Bus
address line forcing (to 0 or 1) to access two BIOS code and data sets. The SMBus also
controls serial port float, RTC access, and serial port interconnection (snoop and take-over
modes). The PC87427 system health support includes a serial interface to LMPC0 health
sensors, fan monitoring and control, and a chassis intrusion detector. The PC87427 also
incorporates a Floppy Disk controller (FDC), two serial ports (UARTs), a keyboard and mouse
controller (KBC), General-Purpose I/O (GPIO), GPIO extension for additional off-chip GPIO
ports, and an interrupt serializer for parallel IRQs.
PC87427 Features:
• 3.3V operation, Standby powered.
• Legacy modules: FDC, two Serial ports (UARTs) and a keyboard and mouse controller
(KBC).
• LPC interface
• 8/16-bit fast X-Bus extension for boot flash, memory and I/O.
• Two sets of BIOS code and data support, for main and back-up BIOS.
• System health support, including LMPC sensor interface, fan monitor/control, and
chassis intrusion detection, for all configurations (i.e., with or without a BMC or mBMC).
• Serial Interface for manageability (Serial Interface M). Two-to-one internally multiplexing
of Serial Ports 1 and 2.
• One external serial port
• One internal serial port.
• 52 GPIO ports with a variety of wake-up events plus GPIO extension for additional off-
chip GPIO ports.
• Watchdog for autonomous system recovery for BIOS Boot process and for Operating
System use.
• Pulse-Width-Modulated Fan Speed Control and Fan Tachometer Monitoring
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3.6.9.1 GPIOs
The National Semiconductor* PC87427 Super I/O provides nine general-purpose input/output
pins that the SE7320SP2 and server board SE7525GP2s utilizes. The following table identifies
the pin and the signal name used in the schematic:
Table 13: Super I/O GPIO Usage Table
Pin Name
GPIO00 Standby Input MANUF_DET_N
GPIO05/LMPCIF2 Standby Input/Output SIO_TEMP_SENSOR
GPIO6 Standby Output BIOS_SEL
GPIO7/HFCKOUT Standby Output CLK_10M_MBMC
GPIO27/SUPER IOSMI Standby Output SUPER IO_SMI_N
GPIOE40 Standby Input 2U_RISER_DETECT
GPIOE41 Standby Input/Output RISER_PRESENT2
GPIOE42 Standby Input/Output PCIE_WAKE_N
GPIOE43 Standby Input/Output PME_N Intput- PME from PCI Bus
GPIOE44/SCI Standby Input/Output SUPER IO_PME_N
GPIOE45/LED Standby Input/Output PME_PCIX_N Input- PME from PCI-X Bus
GPIO50/DCDM_N Standby Input/Output NWY_DIS_N
GPIO51/DSRM_N Standby Input/Output KNI_DIS_N
GPIO52/CTSM/XCS1 Standby Input/Output FRU_LEDSEL_N Output – FRU LED Selection
GPIO54/SINM Standby Input/Output MROMB_PRESENT_N
GPO60/WDO_N Standby Output MBMC_RST_BTN_N
GPO61/SMBSA Standby Output
GPO62/LFCLK Standby Output TP_SIO_45 Unused
GPEXC/GPIO56 Standby Output SUPER IO_SERIAL_CLK1
GPEXD/GPIO57 Standby Input/Output SUPER IO_SERIAL_DAT
GPEXC2 / LMPCLK Standby Output SUPER IO_SERIAL_CLK2
LED1 Standby Output FP_PWR_LED_N Output- Power LED
(Powe
Well)
GPI / GPO /
Function
Signal Name Function Description
Active Low when Manufacturing
Mode Detect (J35)
Single wire temp sensor from
LM30.
Selects BIOS flash bank (A21 bit)
for rolling BIOS feature.
HFCKOUT- 10MHz clock to
mBMC (not used)
Active Low to generate a SMI to
6300ESB ICH
Riser card type detect – Pin B92
of PCI-X Slot 1.
Riser card type detect – Pin B93
of PCI-X Slot 1.
Input- Wake up Event from PCI-E
Bus
Output- Active Low to generate a
PME to the 6300ESB ICH
Output- Active Low to disable
Intel 82570EI
Output – Active low to disable
Kenai-II
Input- Active Low when ZCR card
detect
Output- Active Low to reset
system
SUPER
IO_SMBUS_ADDR
SMBus slave address (SMBSA)
select – pulled to ground with
10K resistor.
Output- Serial Clock to Port 80
circuit
Output- Serial data to Port 80
circuit/FRU LED circuit
Output- Serial Clock to FRU LED
circuit
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3.6.9.2 Serial Ports
Both the SE7320SP2 and server board SE7525GP2s provide two serial ports: an external DB9
Serial port, and an internal DH-10 Serial header. The following sub-sections provide details on
the use of the serial ports.
3.6.9.2.1 Serial Port A
Serial A is an external 9-pin DB-9 connector that is located on the back edge of the server board.
3.6.9.2.2 Serial Port B
Serial B is an optional port, accessed through a 9-pin internal DH-10 header. A standard DH-10
to DB9 cable can be used to direct Serial A out the back of a given chassis. The Serial B
interface follows the standard RS232 pin-out as defined in the following table.
Table 14: Serial B Header Pin-out
Pin Signal Name Serial Port A Header Pin-out
1 DCD
2 DSR
3 RX
4 RTS
5 TX
6 CTS
7 DTR
8 RI
9 GND
3.6.9.3 Floppy Disk Controller
The 34 pin floppy disk controller (FDC) in the SIO is functionally compatible with floppy disk
controllers in the DP8473 and N844077. All FDC functions are integrated into the SIO including
analog data separator and 16-byte FIFO.
3.6.9.4 Keyboard and Mouse
Dual stacked PS/2 ports, located on the back edge of the server board, are provided for
keyboard and mouse support. Either port can support a mouse or keyboard. Neither port will
support “hot plugging” or connector insertion while the system is turned on.
3.6.9.5 Wake-up Control
The Super I/O contains functionality that allows various events to control the power-on and
power-off the system.
3.6.10 BIOS Flash
An Intel 3 Volt Advanced+ Boot Block 28F320C3 Flash memory component is used as the BIOS
flash device. The 28F320C3 is a high-performance 32-megabit memory component that
provides 2048K x 16 (4MB) of BIOS and non-volatile storage space. The flash device is
connected through the X-bus from the SIO.
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3.7 Configuration and Initialization
This section describes the initial programming environment including address maps for memory
and I/O, techniques and considerations for programming ASIC registers, and hardware options
configuration.
3.7.1 Memory Space
At the highest level, the Intel Xeon processor address space is divided into 4 regions, as shown
in the following figure. Each region contains sub-regions as described in following sections.
Attributes can be independently assigned to regions and sub-regions using the Intel Server
Board SE7320SP2 or SE7525GP2 registers. The Intel E7320 and Intel E7525 chipsets each
supports 64GB of host-addressable memory space and 64KB+3 of host-addressable I/O space.
The SE7320SP2 and server board SE7525GP2s support up to 8GB of main memory for DDR266 or DDR-333 configurations.
64GB
Hi PCI
Memory
Upper Memory
Ranges
Lo PCI
Memory Space
Range
Main Memory
Address Range
DOS Legacy
Address Range
Additional Main
Memory Address
TSEG SMRAM
Optional ISA Hole
4GB
Top of Low Memory (TOLM)
16MB
15MB
1MB
640KB
512KB
0
Figure 9 - Intel® Xeon™ Processor Memory address Space
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3.7.1.1 DOS Compatibility Region
The first region of memory below 1 MB was defined for early PCs, and must be maintained for
compatibility reasons. The region is divided into sub-regions as shown in the following figure.
0FFFFFh 1MB
System BIOS
0F0000h
0EFFFFh
0E0000h
0DFFFFh
0C0000h
0BFFFFh
0A0000h
09FFFFh
080000h
07FFFFh
Extended
System BIOS
Add-in Card BIOS
and Buffer Area
PCI/ISA Video or
SMM Area
ISA Window Area
DOS Area
960KB
896KB
768KB
640KB
512KB
= Shadowed in main memory
= Mappable to PCI or ISA memory
= Main memory only
0
000000h
Figure 10 - DOS Compatibility Region
3.7.1.1.1 DOS Area
The DOS region is 512 KB in the address range 0 to 07FFFFh. This region is fixed and all
accesses go to main memory.
3.7.1.1.2 ISA Window Memory
The ISA Window Memory is 128 KB between the address of 080000h to 09FFFFh. This area
can be mapped to the PCI bus or main memory.
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3.7.1.1.3 Video or SMM Memory
The 128 KB Graphics Adapter Memory region at 0A0000h to 0BFFFFh is normally mapped to
the VGA controller on the PCI bus. This region is also the default region for SMM space.
3.7.1.1.4 Add-in Card BIOS and Buffer Area
The 128 KB region between addresses 0C0000h to 0DFFFFh is divided into eight segments of
16 KB segments mapped to ISA memory space, each with programmable attributes, for
expansion cards buffers. Historically, the 32 KB region from 0C0000h to 0C7FFFh has
contained the video BIOS location on the video card.
3.7.1.1.5 Extended System BIOS
This 64 KB region from 0E0000h to 0EFFFFh is divided into 4 blocks of 16 KB each, and may
be mapped with programmable attributes to map to either main memory or to the PCI bus.
Typically this area is used for RAM or ROM. This region can also be used extended SMM space.
3.7.1.1.6 System BIOS
The 64 KB region from 0F0000h to 0FFFFFh is treated as a single block. By default this area is
normally read/write disabled with accesses forwarded to the PCI bus. Through manipulation of
R/W attributes, this region can be shadowed into main memory.
3.7.1.2 Extended Memory
Extended memory is defined as all address space greater than 1MB. Extended Memory region
covers 8GB maximum of address space from addresses 0100000h to FFFFFFFh, as shown in
the following figure. PCI memory space can be remapped to top of memory (TOM).
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g
A
g
64GB
Extended
chipset region
PCI
Memory
Main Memory
Address Region
Hi
h BIOS Area
PIC Space
512KB Extended System
mana
ement RAM
Optional Fixed
Memory Hole
Top Of Memory (TOM)
FFFFFFFFh
FFE00000h
FEC0FFFFh
FEC00000h
Top of Low Memory (TOLM)
16MB
15MB
100000h
Figure 11 - Extended Memory Map
3.7.1.2.1 Main Memory
All installed memory greater than 1 MB is mapped to local main memory, up to 8 GB of physical
memory. Memory between 1 MB to 15 MB is considered to be standard ISA extended memory.
1 MB of memory starting at 15 MB can be optionally mapped to the PCI bus memory space.
The remainder of this space, up to 8 GB, is always mapped to main memory, unless TBSG
SMM is used which just under TOLM. The range can be from 128KB till 1MB. 1MB depends on
the BIOS setting C SMRAM is used which limits the top of memory to 256MB. BIOS occupies
512KB for 32bit SMI handler.
3.7.1.2.2 PCI Memory Space
Memory addresses below 4 GB range are mapped to the PCI bus. This region is divided into
three sections: High BIOS, APIC Configuration Space, and General-purpose PCI Memory. The
General-purpose PCI Memory area is typically used memory-mapped I/O to PCI devices. The
memory address space for each device is set using PCI configuration registers.
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3.7.1.2.3 High BIOS
The top 1 MB of Extended Memory under 4GB is reserved for the system BIOS, extended BIOS
for PCI devices, and A20 aliasing by the system BIOS. The lntel Xeon processor begins
executing from the high BIOS region after reset.
3.7.1.2.4 I/O APIC Configuration Space
A 64 KB block located 20 MB below 4 GB (0FEC00000 to 0FEC0FFFFh) is reserved for the I/O
APIC configuration space. The first I/O APIC is located at FEC00000h. The second I/O APIC is
located at FEC80000h. The third I/O APIC is located at FEC80100h.
®
3.7.1.2.5 Extended lntel
Xeon™ Processor Region (above 4GB)
An lntel Xeon processor based system can have up to 64 GB of addressable memory. With the
chipset only supporting 16GB of addressable memory, the BIOS uses an extended addressing
mechanism to use the address ranges.
3.7.1.3 Memory Shadowing
System BIOS and option ROM can be shadowed in main memory. Typically this is done to allow
ROM code to execute more rapidly out of RAM. ROM is designated read-only during the copy
process while RAM at the same address is designated write-only. After copying, the RAM is
designated read-only. After the BIOS is shadowed, the attributes for that memory area are set to
read only so that all writes are forwarded to the expansion bus.
3.7.1.4 System Management Mode Handling
The chipset supports System Management Mode (SMM) operation in one of three modes.
System Management RAM (SMRAM) provides code and data storage space for the SMI_L
handler code, and is made visible to the processor only on entry to SMM, or other conditions
which can be configured using Intel Lindenhurst PF chipset.
The MCH supports three SMM options:
• Compatible SMRAM (C_SMRAM)
• High Segment (HSEG)
• Top of Memory Segment (TSEG)
Three abbreviations are used later in the table that describes SMM Space Transaction Handling.
SMM Space Enabled Transaction Address Space (Adr) DRAM Space (DRAM)
Compatible (C) A0000h to BFFFFh A0000h to BFFFFh
High (H) 0FEDA0000h TO 0FEDBFFFFh A0000h to BFFFFh
TSEG (T) (TOLM-TSEG_SZ) to TOLM (TOLM-TSEG_SZ) to TOLM
Notes: High SMM is different than in previous chipsets. In previous chipsets the High segment
was the 384KB region from A_0000h to F_FFFFh. However C_0000h to F_FFFFh was not
useful so it is deleted in MCH.
TSEG SMM is different than in previus chipset. In previous chipsets the TSEG address space
was offset by 256MB to allow for simpler decoding and the TSEG was remapped to directly
under th TOLM. In the MCH the TSEG region is not offset by 256MB and it is not remapped.
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Table 15: SMM Space Table
Global Enable
G_SMRAME
0 X X Disable Disable Disable
1 0 0 Enable Disable Disable
1 0 1 Enable Disable Enable
1 1 0 Disable Enable Disable
1 1 1 Disable Enable Enable
High Enable
H_SMRAME
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
3.7.2 I/O Map
The server board I/O addresses to be mapped to the processor bus or through designated
bridges in a multi-bridge system. Other PCI devices, including the Intel 6300ESB I/O Controller,
have built-in features that support PC-compatible I/O devices and functions, which are mapped
to specific addresses in I/O space. On SE7320SP2 and SE7525GP2, the Intel 6300ESB I/O
Controller provides the bridge to ISA functions.
The I/O map in the following table shows the location in I/O space of all direct I/O-accessible
registers. PCI configuration space registers for each device control mapping in I/O and memory
spaces, and other features that may affect the global I/O map.
Table 16: I/O Map
Address (es) Resource Notes
0000h – 000Fh DMA Controller 1
0010h – 001Fh DMA Controller 2 Aliased from 0000h – 000Fh
0020h – 0021h Interrupt Controller 1
0022h – 0023h
0024h – 0025h Interrupt Controller 1 Aliased from 0020 – 0021h
0026h – 0027h
0028h – 0029h Interrupt Controller 1 Aliased from 0020h – 0021h
002Ah – 002Bh
002Ch – 002Dh Interrupt Controller 1 Aliased from 0020h – 0021h
002Eh – 002Fh Super I/O (SIO) index and Data ports
0030h – 0031h Interrupt Controller 1 Aliased from 0020h – 0021h
0032h – 0033h
0034h – 0035h Interrupt Controller 1 Aliased from 0020h – 0021h
0036h – 0037h
0038h – 0039h Interrupt Controller 1 Aliased from 0020h – 0021h
003Ah – 003Bh
003Ch – 003Dh Interrupt Controller 1 Aliased from 0020h – 0021h
003Eh – 003Fh
0040h – 0043h Programmable Timers
0044h – 004Fh
0050h – 0053F Programmable Timers
0054h – 005Fh
0060h, 0064h Keyboard Controller Keyboard chip select from 87417
0061h NMI Status & Control Register
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Address (es) Resource Notes
0063h NMI Status & Control Register Aliased
0065h NMI Status & Control Register Aliased
0067h NMI Status & Control Register Aliased
0070h NMI Mask (bit 7) & RTC address (bits 6::0)
0072h NMI Mask (bit 7) & RTC address (bits 6::0) Aliased from 0070h
0074h NMI Mask (bit 7) & RTC address (bits 6::0) Aliased from 0070h
0076h NMI Mask (bit 7) & RTC address (bits 6::0) Aliased from 0070h
0071h RTC Data
0073h RTC Data Aliased from 0071h
0075h RTC Data Aliased from 0071h
0077h RTC Data Aliased from 0071h
0080h – 0081h BIOS Timer
0080h – 008F DMA Low Page Register
0090h – 0091h DMA Low Page Register (aliased)
0092h
0093h – 009Fh DMA Low Page Register (aliased)
0094h Video Display Controller
00A0h – 00A1h Interrupt Controller 2
00A4h – 00A5h Interrupt Controller 2 (aliased)
00A8h – 00A9h Interrupt Controller 2 (aliased)
00ACh – 00ADh Interrupt Controller 2 (aliased)
00B0h – 00B1h Interrupt Controller 2 (aliased)
00B4h – 00B5h Interrupt Controller 2 (aliased)
00B8h – 00B9h Interrupt Controller 2 (aliased)
00BCh – 00BDh Interrupt Controller 2 (aliased)
00C0h – 00DFh DMA Controller 2
00F0h Clear NPX error Resets IRQ13
00F8h – 00FFh X87 Numeric Coprocessor
0102h Video Display Controller
0170h – 0177h Secondary Fixed Disk Controller (IDE)
01F0h – 01F7h Primary Fixed Disk Controller (IDE)
0200h – 0207h Game I/O Port
0220h – 022Fh Serial Port A
0238h – 023Fh Serial Port B
0278h – 027Fh Parallel Port 3
0290h – 0298h NS HW monitor
02E8h – 02EFh Serial Port B
02F8h – 02FFh Serial Port B
0338h – 033Fh Serial Port B
0370h – 0375h Secondary Floppy
0376h Secondary IDE
0377h Secondary IDE/Floppy
0378h – 037Fh Parallel Port 2
03B4h – 03Bah Monochrome Display Port
System Control Port A (PC-AT control Port) (this
port not aliased in DMA range)
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Address (es) Resource Notes
03BCh – 03BFh Parallel Port 1 (Primary)
03C0h – 03CFh Video Display Controller
03D4h – 03Dah Color Graphics Controller
03E8h – 03Efh Serial Port A
03F0h – 03F5h Floppy Disk Controller
03F6h – 03F7h Primary IDE – Sec Floppy
03F8h – 03FFh Serial Port A (primary)
0400h – 043Fh DMA Controller 1, Extended Mode Registers
0461h Extended NMI / Reset Control
0480h – 048Fh DMA High Page Register
04C0h – 04CFh DMA Controller 2, High Base Register
04D0h – 04D1h Interrupt Controllers 1 and 2 Control Register
04D4h – 04D7h DMA Controller 2, Extended Mode Register
04D8h – 04DFh Reserved
04E0h – 04FFh DMA Channel Stop Registers
051Ch Software NMI (051Ch)
0678h – 067Ah Parallel Port (ECP)
0778h – 077Ah Parallel Port (ECP)
07BCh – 07Beh Parallel Port (ECP)
0CF8h PCI CONFIG_ADDRESS Register
0CF9h
0CFCh PCI CONFIG_DATA Register
Intel® Server Board SUNPRAIRIE Turbo and
Reset Control
3.7.3 Accessing Configuration Space
All PCI devices contain PCI configuration space, accessed using mechanism #1 defined in the
PCI Local Bus Specification. If dual processors are used, only the processor designated as the
Boot Strap Processor (BSP) should perform PCI configuration space accesses. Precautions
should be taken to guarantee that only one processor performs system configuration.
Two Dword I/O registers in the chipset are used for the configuration space register access:
• CONFIG_ADDRESS (I/O address 0CF8h)
• CONFIG_DATA (I/O address 0CFCh)
When CONFIG_ADDRESS is written to with a 32-bit value selecting the bus number, device on
the bus, and specific configuration register in the device, a subsequent read or write of
CONFIG_DATA initiates the data transfer to/from the selected configuration register. Byte
enables are valid during accesses to CONFIG_DATA; they determine whether the configuration
register is being accessed or not. Only full Dword reads and writes to CONFIG_ADDRESS are
recognized as a configuration access by the chipset. All other I/O accesses to
CONFIG_ADDRESS are treated as normal I/O transactions.
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3.7.3.1 CONFIG_ADDRESS Register
CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure.
Bits [23::16] choose a specific bus in the system. Bits [15::11] choose a specific device on the
selected bus. Bits [10:8] choose a specific function in a multi-function device. Bit [8::2] select a
specific register in the configuration space of the selected device or function on the bus.
017 810 11 15 16 23 24 30 31
Function Device Bus Number Reserved
Register
Enable bit (‘1’ = enabled, ‘0’ = disabled)
Figure 12 - CONFIG_ADDRES Register
3.7.3.1.1 Bus Number
PCI configuration space protocol requires that all PCI buses in a system be assigned a Bus
Number, Furthermore, bus numbers must be assigned in ascending order within hierarchical
buses. Each PCI bridge has registers containing its PCI Bus Number and subordinate PCI Bus
Number, which must be loaded by POST code. The Subordinate PCI Bus Number is the bus
number of the last hierarchical PCI bus under the current bridge. The PCI Bus Number and the
Subordinate PCI Bus Number are the same in the last hierarchical bridge.
3.7.3.1.2 Device Number and IDSEL Mapping
Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus
address/data signals AD[31::11] for the PCI bus. Each IDSEL-mapped AD bit acts as a chip
select for each device on PCI. The host bridge responds to a unique PCI device ID value, that
along with the bus number, cause the assertion of IDSEL for a particular device during
configuration cycles. The following table shows the correspondence between IDSEL values and
PCI device numbers for the PCI bus. The lower 5-bits of the device number are used in
CONFIG_ADDRESS bits [15::11].
00
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Table 17: PCI Configuration IDs and Device Numbers
PCI Device IDSEL Bus# / Device# / Function#
MCH host-HI bridge/DRAM controller 00 / 00 / 0
MCH DRAM Controller Error Reporting 00/00/1
MCH DMA controller 00/01/00
MCH EXP Bridge A0 00/02/00
MCH EXP Bridge A1 00/03/00
MCH EXP Bridge B0 00/04/00
MCH EXP Bridge B1 00/05/00
MCH EXP Bridge C0 00/06/00
MCH EXP Bridge C1 00/07/00
MCH Extended Configuration 00/08/00
ICH5R Hub interface to PCI bridge 00 / 30 / 00
ICH5R PCI to LPC interface 00 / 31 / 00
ICH5R IDE controller 00 / 31 / 01
ICH5R Serial ATA 00 / 31 / 02
ICH5R SMBus controller 00 / 31 / 03
ICH5R USB UHCI controller #1 00 / 29 / 00
ICH5R USB UHCI controller #2 00 / 29 / 01
ICH5R USB UHCI controller #3 00 / 29 / 02
ICH5R USB 2.0 EHCI controller 00 / 29 / 07
FL Slot1 (64-bit, PCIX-100) P1A_AD17 / 01 /
FL Slot2(64-bit, PCI-X-100) P1A_AD18 / 02 /
FL Slot3 (64-bit, PCI-X-100) P1A_AD19 / 03 /
FL PXH-D Slot1 P2A_AD17 /01/
FL PXH-D Slot 2 P2B_AD17 /01/
FL PCI-E x4 Slot1 /??/
FL PCI-E x4 Slot2 /??/
LP Slot1 (64-bit, PCI-X-100) P1B_AD17 / 01 /
LP Slot2 (64-bit, PCI-X-100) P1B_AD18 / 02 /
LF Slot3 (64-bit, PCI-X-100) P1B_AD19 / 03 /
LP PCI-E x8 Slot1 /??/
On board device
Intel 82546GB (1Gb) NIC w/ dual
channel
LSI 53C1030 Ultra 320 SCSI w/ dual
channel
ATI Rage XL (PCI VGA) PC_AD28 / 12 /0
P1B_AD20 / 04 /0,1
P1A_AD21 /05/0,1
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3.8 Clock Generation and Distribution
All buses on the server board operate using synchronous clocks. Clock synthesizer/driver
circuitry on the server board generates clock frequencies and voltage levels as required,
including the following:
• 200MHz differential Clock at 0.7 V logic levels. For Processor 0, Processor 1, Debug
Port and MCH.
• 100 MHz differential Clock at 0.7 V logic levels on CK409B. For DB800 clock buffer.
• 100 MHz differential Clock at 0.7 V logic levels on DB800. For PCI Express Device is
MCH. And for SATA is Intel 6300ESB.
• 66 MHz at 3.3 V logic levels: For MCH and Intel 6300ESB
• 48 MHz at 3.3V logic levels: For Intel 6300ESB and SIO.
• 33 MHz at 3.3V logic levels: For Intel 6300ESB, Video, BMC and SIO.
• 14.318 MHz at 2.5 V logic levels: For Intel 6300ESB and Video.
• 10 Mhz at 5V logic levels: For mini BMC.
3.8.1 Real Time Clock
The real time clock is specified to operate within the following criteria and environmental
conditions:
RTC Accuracy: 1 minute per month = 2 seconds per day
Environmental Conditions:
Temperature 10 ~ 35 C
Humidity 20 ~80% (non-condensing)
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g
4. System BIOS
This section details the functionality and features supported of the System Basic Input/Output
System (BIOS) which is based on an AMI 8.0 core architecture. The BIOS is implemented as
firmware that resides in Flash ROM. It provides hardware-specific initialization algorithms and
standard PC-compatible basic input/output (I/O) services, and standard Intel
features. The Flash ROM also contains firmware for embedded PCI devices.
The SE7320SP2 / SE7525GP2 BIOS is comprised of the following components:
• IA-32 core BIOS. This component contains most of the standard services and
components found in an IA-32 system, such as the PCI Resource manager, ACPI
support, POST, and RUNTIME functionality.
• The “EFI” is the extensible firmware interface. This is an abstraction layer between the
operating system and system hardware.
• Server BIOS extensions: Support for Baseboard Management Controller (BMC) and
Intelligent Platform Management Interface (IPMI).
• Processor Microcode Updates: The BIOS also includes latest processor microcode
updates.
®
Server Board
4.1 BIOS Identification String
The BIOS Identification string is used to uniquely identify the revision of the BIOS being used on
the system. The string is formatted as follows:
BoardId.OEMID.BuildType.Major.Minor.BuildID.BuildDateTime.Mod
Dxx = Development
Xxx = Power On
N character ID:
AN430TX, etc.
Axx = Alpha BIOS
Bxx = Beta BIOS
RCxx= Release Candidate
P = Production
xx = 2 di
it number N/A for Production
Three characters:
86A = Intel DPG
86B = Intel EPG
10A = Some OEM, etc.
two digits:
two digits:
During board development, the system BIOS will have a unique BIOS ID for Intel Sever Board
SE7320SP2 and SE7525GP2. The following is a sample data string that will be displayed
during POST:
Build Date and time in
MMDDYYYYHHMM format
Four digits:
Increment
on each build
One digit:
non-zero if any Separately
Updateable
Module has been updated
SE7320SP2.86B.P.05.00.0028.10072004
SE7525GP2.86B.P.05.00.0028.10072004
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4.2 BIOS POST Splash Screen
The BIOS supports one system splash screen. When the system is booting, the BIOS will
display the splash screen instead of BIOS messages. BIOS messages can be viewed by
pressing the ‘ESC’ key during POST. Once the BIOS POST message screen is selected, the
splash screen is no longer accessible during the current boot sequence. The splash screen can
be customized by with the ‘Change Logo’ utility. Refer to the Change Logo for AMIBIOS User’s
Guide (Version 2.22) for details.
4.2.1 User Interface
During the system boot-up POST process, there are two types of consoles used for displaying
the user interface: graphical or text based. Graphics consoles are in 640x480 mode; text
consoles use 80x25 mode.
The console output is partitioned into three areas: the System Activity/State, Logo/Diagnostic,
and Current Activity windows. The System Activity Window displays information about the
current state of the system. The Logo/Diagnostic Window displays the OEM splash screen logo
or a diagnostic boot screen. The Current Activity Window displays information about the
currently executing portion of POST as well as user prompts and status messages.
System State Window
Logo/Diagnostic Window
Current Activity Window
4.2.1.1 System State Window
The top row of the screen is reserved for the system state window. On a graphics console, the
window is 640x48. On a text console, the window is 80x2.
The system state window may be in one of three forms, either an activity bar that scrolls while
the system is busy, a progress bar that measures percent complete for the current task, or an
attention required bar. The attention bar is useful for tasks that require user attention to
continue.
4.2.1.2 Logo/Diagnostic Window
The middle portion of the screen is reserved for the Logo/Diagnostic Window. On a graphics
console, the window is 640x384. On a text console, the window is 80x20.
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The Logo/Diagnostic Window may be in one of two forms depending on whether Quiet Boot
Mode is selected in the BIOS Setup. If selected, the BIOS displays a logo splash screen. If not,
the BIOS displays a system summary and diagnostic screen in verbose mode. The default is to
display the logo in Quiet Boot mode. If no logo is present in the flash ROM, or Quiet Boot mode
is disabled in the system configuration, the summary and diagnostic screen is displayed. If the
user presses <Esc>, the system transfers from the logo screen to the diagnostic screen.
4.2.1.3 Current Activity Window
The bottom portion of the screen is reserved for the Current Activity Window. On a graphics
console, the window is 640x48. On a text console, the window is 80x2.
The Current Activity Window is used to display prompts for hot keys, as well as provide
information on system status.
4.2.1.4 System Diagnostic Screen
The diagnostic screen is the console where boot information, options and detected hardware
information are displayed.
4.2.1.5 Static Information Display
The Static Information Display area presents the following information:
• Copyright message
• BIOS ID
• Current processor configuration
• Installed physical memory size
4.2.1.5.1 Quiet Boot / OEM Splash Screen
The BIOS implements Quiet Boot, providing minimal startup display during BIOS POST.
System start-up must only draw the end user’s attention in the event of errors or when there is a
need for user action. By default, the system must be configured so that the local screen does
not display memory counts, device status, etc. It must present a "clean" BIOS start-up. The
only screen display allowed is the OEM splash screen and copyright notices.
The Quiet Boot process is controlled by a Setup Quiet-Boot option. If this option is set, the
BIOS displays an activity indicator at the top of the screen and a logo splash screen in the
middle section of the screen on the local console. The activity indicator measures POST
progress and continues until the operating system gains control of the system. The splash
screen covers up any diagnostic messages in the middle section of the screen. While the logo
is being displayed on the local console, diagnostic messages are being displayed on the remote
text consoles.
Quiet Boot may be disabled by clearing the Setup Quiet-Boot option or by the user pressing the
<Esc> key while in Quiet Boot mode. If Quiet Boot is disabled, the BIOS displays diagnostic
messages in place of the activity indicator and the splash screen.
With the use of an Intel supplied utility, the BIOS allows OEMs to override the standard Intel
logo with one of their own design.
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4.2.1.5.2 BIOS Boot Popup Menu
The BIOS Boot Specification (BBS) provides for a Boot Menu Popup invoked by pressing the
<ESC> key during POST. The BBS Popup menu displays all available boot devices. The list
order in the popup menu is not the same as the boot order in BIOS setup; it simply lists all the
bootable devices from which the system can be booted.
Table 18: Sample BIOS Popup Menu
Please select boot device:
1st Floppy
Hard Drives
ATAPI CDROM
LAN PXE
EFI Boot Manager
↓and↑ to move selection
Enter to select boot device
ESC to boot using defaults
4.3 BIOS Setup Utility
The BIOS Setup utility is provided to perform system configuration changes and to display
current settings and environment information.
The BIOS Setup utility stores configuration settings in system non-volatile storage. Changes
affected by BIOS Setup will not take effect until the system is rebooted. The BIOS Setup Utility
can be accessed when prompted during POST by using the F2 key.
4.3.1 Localization
The BIOS Setup utility uses the Unicode standard and is capable of displaying setup forms in
(EFIGS) languages currently included in the Unicode standard. The BIOS supports English,
Spanish, French, German, and Italian. Intel provides translations for console strings in the
supported languages. The language can be selected using BIOS user interface.
4.3.2 Console Redirection
The BIOS Setup utility is functional via console redirection over various terminal standards
emulation. This may limit some functionality for compatibility, e.g., usage of colors or some
keys or key sequences or support of pointing devices.
4.3.3 Configuration Reset
Setting the Clear CMOS jumper (board location J17) produces a “reset system configuration”
request. When a request is detected, the BIOS loads the default system configuration values
during the next POST.
Alternatively, the user can clear CMOS without opening the chassis. Using the control panel,
the user can hold the reset button for 4 seconds and then press the power button while still
pressing the reset button and then release both simultaneously.
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4.3.4 Keyboard Commands
The Keyboard Command Bar supports the following:
Table 19: BIOS Setup Keyboard Command Bar Options
Key Option Description
Enter
ESC Exit
↑
↓
↔
Tab Select Field
- Change Value
+ Change Value
F9 Setup Defaults Pressing F9 causes the following to appear:
F10 Save and Exit Pressing F10 causes the following message to appear:
Execute
Command
Select Item
Select Item
Select Menu
The Enter key is used to activate sub-menus when the selected feature is a submenu, or to display a pick list if a selected option has a value field, or to select a subfield for multi-valued features like time and date. If a pick list is displayed, the Enter
key will undo the pick list, and allow another selection in the parent menu.
The ESC key provides a mechanism for backing out of any field. This key will undo
the pressing of the Enter key. When the ESC key is pressed while editing any field or
selecting features of a menu, the parent menu is re-entered.
When the ESC key is pressed in any sub-menu, the parent menu is re-entered. When
the ESC key is pressed in any major menu, the exit confirmation window is displayed
and the user is asked whether changes can be discarded. If “No” is selected and the
Enter key is pressed, or if the ESC key is pressed, the user is returned to where they
were before ESC was pressed without affecting any existing any settings. If “Yes” is
selected and the Enter key is pressed, setup is exited and the BIOS continues with
POST.
The up arrow is used to select the previous value in a pick list, or the previous options
in a menu item's option list. The selected item must then be activated by pressing the
Enter key.
The down arrow is used to select the next value in a menu item’s option list, or a value
field’s pick list. The selected item must then be activated by pressing the Enter key.
The left and right arrow keys are used to move between the major menu pages. The
keys have no affect if a sub-menu or pick list is displayed.
The Tab key is used to move between fields. For example, Tab can be used to move
from hours to minutes in the time item in the main menu.
The minus key on the keypad is used to change the value of the current item to the
previous value. This key scrolls through the values in the associated pick list without
displaying the full list.
The plus key on the keypad is used to change the value of the current menu item to
the next value. This key scrolls through the values in the associated pick list without
displaying the full list. On 106-key Japanese keyboards, the plus key has a different
scan code than the plus key on the other keyboard, but will have the same effect
Load Optional
Defaults?
[OK] [Cancel]
If “OK” is selected and the Enter key is pressed, all Setup fields are set to their default
values. If “Cancel” is selected and the Enter key is pressed, or if the ESC key is
pressed, the user is returned to BIOS setup without affecting any existing field values
Save Configuration changes and exit setup?
[OK] [Cancel]
If “OK” is selected and the Enter key is pressed, all changes are saved and Setup is
exited. If “Cancel” is selected and the Enter key is pressed, or the ESC key is pressed,
the user is returned to BIOS setup without affecting any existing values.
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4.4 Entering BIOS Setup
The BIOS Setup utility is accessed by pressing the <F2> hotkey during POST.
4.4.1 Main Menu
The first screen displayed when entering the BIOS Setup Utility is the Main Menu selection
screen. This screen displays the major menu selections available. The following tables describe
the available options on the top level and lower level menus. Default values are shown in bold
text.
Table 20. BIOS Setup, Main Menu Options
Feature Options Help Text Description
System Overview
AMI BIOS
Version N/A N/A
Build Date N/A N/A BIOS build date
Processor
Type N/A N/A Processor brand ID string
Speed N/A N/A Calculated processor speed
Count N/A N/A
System Memory
Size N/A N/A
Server Board MCH Stepping
Stepping N/A N/A Stepping of the MCH component
System Time HH:MM:SS
System Date DAY MM/DD/YYYY
Use [ENTER], [TAB] or [SHIFTTAB] to select a field.
Use [+] or [-] to configure system
Time.
Use [ENTER], [TAB] or [SHIFTTAB] to select a field.
Use [+] or [-] to configure system
Date.
BIOS ID string (excluding the build
time and date)
Detected number of physical
processors
Amount of physical memory
detected
Configures the system time on a
24 hour clock. Default is 00:00:00
Configures the system date.
Default is [Build Date]. Day of the
week is automatically calculated.
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4.4.2 Advanced Menu
Table 21. BIOS Setup, Advanced Menu Options
Feature Options Help Text Description
Advanced Settings
WARNING: Setting wrong values in below sections may cause system to malfunction.
Processor Configuration N/A Configure processors. Selects submenu.
IDE Configuration N/A Configure the IDE device(s). Selects submenu.
Floppy Configuration N/A Configure the Floppy drive(s). Selects submenu.
Super I/O Configuration N/A Configure the Super I/O Chipset. Selects submenu.
USB Configuration N/A Configure the USB support. Selects submenu.
PCI Configuration N/A Configure PCI devices. Selects submenu.
Memory Configuration N/A Configure memory devices. Selects submenu.
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4.4.2.1 Processor Configuration Sub-menu
Table 22. BIOS Setup, Processor Configuration Sub-menu Options
Feature Options Help Text Description
Configure Advanced Processor Settings
Manufacturer Intel N/A
Brand String N/A N/A
Frequency N/A N/A
FSB Speed N/A N/A
CPU 1
CPUID N/A N/A
Cache L1 N/A N/A Displays cache L1 size.
Cache L2 N/A N/A Displays cache L2 size.
Cache L3 N/A N/A
CPU 2
CPUID N/A N/A
Cache L1 N/A N/A Displays cache L1 size.
Cache L2 N/A N/A Displays cache L2 size.
Cache L3 N/A N/A
Max CPUID Value Limit
Hyper-Threading
Technology
Disabled
Enabled
Disabled
Enabled
This should be enabled in
order to boot legacy OSes
that cannot support
processors with extended
CPUID functions.
Enable Hyper-Threading
Technology only if OS
supports it.
Displays processor
manufacturer string
Displays processor brand ID
string
Displays the calculated
processor speed
Displays the processor Front
Side Bus speed.
Displays the CPUID of the
processor.
Displays cache L3 size.
Visible only if the processor
contains an L3 cache.
Displays the CPUID of the
processor.
Displays cache L3 size.
Visible only if the processor
contains an L3 cache.
Controls Hyper-Threading
state. Primarily used to
support older Operating
Systems that do not support
Hyper Threading.
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4.4.2.2 IDE Configuration Sub-menu
Table 23. BIOS Setup IDE Configuration Menu Options
Feature Options Help Text Description
IDE Configuration
Onboard P-ATA
Channels
Disabled
Primary
Secondary
Both
Onboard S-ATA
Channels
Configure S-ATA as
RAID
S-ATA Ports
Definition
Mixed P-ATA / S-
Disabled
Enabled
Disabled
Enabled
A1-3
A1-4
N/A
ATA
Primary IDE Master N/A
Primary IDE Slave N/A
Secondary IDE
N/A
Master
Secondary IDE
N/A
Slave
Third IDE Master N/A
rd
M/A2-4
th
M/A2-3
Disabled: disables the
integrated P-ATA Controller.
Primary: enables only the
Primary P-ATA Controller.
Secondary: enables only the
Secondary P-ATA Controller.
Both: enables both P-ATA
Controllers.
Disabled: disables the
integrated S-ATA Controller.
Enabled: enables the
integrated S-ATA Controller.
When enabled the S-ATA
channels are reserved to be
used as RAID.
th
M
rd
M
Defines priority between SATA channels.
Lets you remove a P-ATA and
replace it by S-ATA in a given
channel. Only 1 channel can
be S-ATA.
While entering setup, BIOS
auto detects the presence of
IDE devices. This displays the
status of auto detection of IDE
devices.
While entering setup, BIOS
auto detects the presence of
IDE devices. This displays the
status of auto detection of IDE
devices.
While entering setup, BIOS
auto detects the presence of
IDE devices. This displays the
status of auto detection of IDE
devices.
While entering setup, BIOS
auto detects the presence of
IDE devices. This displays the
status of auto detection of IDE
devices.
While entering setup, BIOS
auto detects the presence of
IDE devices. This displays the
status of auto detection of IDE
devices.
Controls state of integrated PATA controller.
Controls state of integrated SATA controller.
Default set the S-ATA Port0 to
3rd IDE Master channel & Port1
th
to 4
IDE Master channel.
Otherwise set S-ATA Port0 to 4
IDE Master channel & Port1 to
3rd IDE Master channel.
Selects submenu for configuring
mixed P-ATA and S-ATA.
Selects submenu with additional
device details.
Selects submenu with additional
device details.
Selects submenu with additional
device details.
Selects submenu with additional
device details.
Selects submenu with additional
device details.
th
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Fourth IDE Master N/A
Hard Disk Write
Protect
Disabled
Enabled
IDE Detect Time Out
(Sec)
0
5
10
15
20
25
30
35
ATA(PI) 80Pin Cable
Detection
Host & Device
Host
Device
While entering setup, BIOS
auto detects the presence of
IDE devices. This displays the
status of auto detection of IDE
devices.
Disable/Enable device write
protection. This will be
effective only if device is
accessed through BIOS.
Select the time out value for
detecting ATA/ATAPI
device(s).
Select the mechanism for
detecting 80Pin ATA(PI)
Cable.
Selects submenu with additional
device details.
Primarily used to prevent
unauthorized writes to hard
drives.
Primarily used with older IDE
devices with longer spin up
times.
The 80 pin cable is required for
UDMA-66 and above. BIOS
detects the cable by querying
the host and/or device.
Table 24. Mixed P-ATA-S-ATA Configuration with only Primary P-ATA
Feature Options Help Text Description
Mixed P-ATA / S-ATA
First ATA
Channel
P-ATA M-S
S-ATA M-S
Configure this channel to P-ATA or S-ATA.
P-ATA: Parallel ATA Primary channel.
S-ATA: Serial ATA.
Defines the S-ATA
device for this
channel. If the
Second ATA is
assigned S-ATA, this
option reverts to PATA.
Second ATA
Channel
P-ATA M-S
S-ATA M-S
Configure this channel to P-ATA or S-ATA.
P-ATA: Parallel ATA Primary channel.
S-ATA: Serial ATA.
Defines the S-ATA
device for this
channel. If the First
ATA is assigned SATA, this option
reverts to P-ATA.
3rd & 4th ATA
Channels
A1-3
A1-4
None
rd
th
M/A2-3
M/A2-4
th
M
rd
Configure this channel to P-ATA or S-ATA.
M
P-ATA: Parallel ATA Primary channel.
S-ATA: Serial ATA.
Display only. If the
First ATA or Second
ATA is assigned SATA, this option
reverts to None.
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Table 25. BIOS Setup, IDE Device Configuration Sub-menu Selections
Feature Options Help Text Description
Primary/Secondary/Third/Fourth IDE Master/Slave
Device N/A N/A Display detected device info
Vendor N/A N/A. Display IDE device vendor.
Size N/A N/A Display IDE DISK size.
LBA Mode N/A N/A Display LBA Mode
Block Mode N/A N/A Display Block Mode
PIO Mode N/A N/A Display PIO Mode
Async DMA N/A N/A Display Async DMA mode
Ultra DMA N/A N/A Display Ultra DMA mode.
S.M.A.R.T. N/A N/A Display S.M.A.R.T. support.
Type
LBA/Large Mode
Block (Multi-Sector
Transfer) Mode
PIO Mode
DMA Mode
S.M.A.R.T.
32Bit Data Transfer
Not Installed
Auto
CDROM
ARMD
Disabled
Auto
Disabled
Auto
Auto
0
1
2
3
4
Auto
SWDMA0-0
SWDMA0-1
SWDMA0-2
MWDMA0-0
MWDMA0-1
MWDMA0-2
UWDMA0-0
UWDMA0-1
UWDMA0-2
UWDMA0-3
UWDMA0-4
UWDMA0-5
Auto
Disabled
Enabled
Disabled
Enabled
Select the type of device
connected to the system.
Disabled: Disables LBA Mode.
Auto: Enabled LBA Mode if the
device supports it and the device is
not already formatted with LBA
Mode disabled.
Disabled: The Data transfer from
and to the device occurs one
sector at a time.
Auto: The data transfer from and
to the device occurs multiple
sectors at a time if the device
supports it.
Select PIO Mode.
Select DMA Mode.
Auto :Auto detected
SWDMA :SinglewordDMAn
MWDMA :MultiwordDMAn
UWDMA :UltraDMAn
Self-Monitoring, Analysis and
Reporting Technology.
Enable/Disable 32-bit Data
Transfer
The Auto setting should work in
most cases.
The Auto setting should work in
most cases.
The Auto setting should work in
most cases.
The Auto setting should work in
most cases.
The Auto setting should work in
most cases.
The Auto setting should work in
most cases.
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4.4.2.3 Floppy Configuration Sub-menu
Table 26. BIOS Setup, Floppy Configuration Sub-menu Selections
Feature Options Help Text Description
Floppy Configuration
Floppy A Disabled
720 KB 3 1/2"
1.44 MB 3 1/2"
2.88 MB 3 1/2"
Onboard Floppy Controller
Disabled
Enabled
Select the type of floppy drive
connected to the system.
Allows BIOS to Enable or
Disable Floppy Controller.
Note: Intel no longer
validates 720Kb &
2.88Mb drives.
4.4.2.4 Super I/O Configuration Sub-menu
Table 27. BIOS Setup, Super I/O Configuration Sub-menu
Feature Options Help Text Description
Configure Nat42x Super IO Chipset
Serial Port A
Address
Serial Port B
Address
Disabled
3F8/IRQ4
2F8/IRQ3
3E8/IRQ4
2E8/IRQ3
Disabled
3F8/IRQ4
2F8/IRQ3
3E8/IRQ4
2E8/IRQ3
Allows BIOS to Select Serial Port A
Base Addresses.
Allows BIOS to Select Serial Port B
Base Addresses.
Option that is used by other serial
port is hidden to prevent conflicting
settings.
Option that is used by other serial
port is hidden to prevent conflicting
settings.
4.4.2.5 USB Configuration Sub-menu
Table 28. BIOS Setup, USB Configuration Sub-menu Selections
Feature Options Help Text Description
USB Configuration
USB Devices
Enabled
USB Function
Legacy USB
Support
Port 60/64
Emulation
N/A N/A
Disabled
Enabled
Disabled
Keyboard only
Auto
Keyboard and
Mouse
Disabled
Enabled
Enables USB HOST controllers.
Enables support for legacy USB. AUTO option
disables legacy support if no USB devices are
connected. If disabled, USB Legacy Support
will not be disabled until booting an OS.
Enables I/O port 60/64h emulation support.
This should be enabled for the complete USB
keyboard legacy support for non-USB aware
OSes.
List of USB
devices detected
by BIOS.
When set to
disabled, other
USB options are
grayed out.
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USB 2.0 Controller
USB 2.0 Controller
mode
USB Mass Storage
Device
Configuration
Disabled
Enabled
FullSpeed
HiSpeed
N/A
N/A
Configures the USB 2.0 controller in HiSpeed
(480Mbps) or FullSpeed (12Mbps).
Configure the USB Mass Storage Class
Devices.
Selects submenu
with USB Device
enable.
4.4.2.6 USB Mass Storage Device Configuration Sub-menu
Table 29. BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections
Feature Options Help Text Description
USB Mass Storage Device Configuration
USB Mass Storage
Reset Delay
Device #1 N/A N/A
Emulation Type
Device #n N/A N/A
Emulation Type
10 Sec
20 Sec
30 Sec
40 Sec
Auto
Floppy
Forced
FDD
Hard Disk
CDROM
Auto
Floppy
Forced
FDD
Hard Disk
CDROM
Number of seconds POST waits for the USB
mass storage device after start unit command.
If Auto, USB devices less than 530MB will be
emulated as Floppy and remaining as hard
drive. Forced FDD option can be used to force
a HDD formatted drive to boot as FDD (Ex. ZIP
drive).
If Auto, USB devices less than 530MB will be
emulated as Floppy and remaining as hard
drive. Forced FDD option can be used to force
a HDD formatted drive to boot as FDD (Ex. ZIP
drive).
Only displayed if a
device is detected,
includes a DeviceID
string returned by the
USB device.
Only displayed if a
device is detected,
includes a DeviceID
string returned by the
USB device.
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4.4.2.7 PCI Configuration Sub-menu
This sub-menu provides control over PCI devices and their option ROMs. If the BIOS is
reporting POST error 146, use this menu to disable option ROMs that are not required to boot
the system.
Table 30. BIOS Setup, PCI Configuration Sub-menu Selections
Feature Options Help Text Description
PCI Configuration
Onboard Video Disabled
Enabled
Dual Monitor Video
Onboard NIC 1 (Left) Disabled
Onboard NIC 1 ROM Disabled
Slot 1 Option ROM Disabled
Slot 2 Option ROM Disabled
Slot 3 Option ROM Disabled
Slot 4 Option ROM Disabled
Slot 5 Option ROM Disabled
Slot 6 Option ROM Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enable/Disable on board VGA
Controller
Select which graphics controller to
use as the primary boot device.
Enabled selects the on board device.
Full Height PCI-X 64/66
Full Height PCI-X 64/66
Full Height PCI 32/33
Full Height PCI-Express X4
Full Height PCI 32/33
Full Height PCI-Express X16
Grayed out if Onboard
Video is set to "Disabled."
Grayed out if device is
disabled.
Available only when PCI
card installed.
Available only when PCI
card installed.
Available only when PCI
card installed.
Available only when PCI
card installed.
Available only when PCI
card installed.
Available only when PCI
card installed. Not visible
on the SE7320SP2 SKU.
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4.4.2.8 Memory Configuration Sub-menu
This sub-menu provides information about the DIMMs detected by the BIOS. The DIMM
number is printed on the server board next to each device.
Table 31. BIOS Setup, Memory Configuration Sub-menu Selections
Feature Options Help Text Description
System Memory Settings
DIMM 1A Installed
Not Installed
Disabled
Spare
DIMM 1B Installed
Not Installed
Disabled
Spare
DIMM 2A Installed
Not Installed
Disabled
Spare
DIMM 2B Installed
Not Installed
Disabled
Spare
Extended Memory Test 1 MB
1 KB
Every Location
Disabled
Memory Retest
Memory Remap Feature Disabled
Memory Sparing
Disabled
Enabled
Enabled
Disabled
Spare
Informational display.
Informational display.
Informational display.
Informational display.
Settings for extended memory
test
If "Enabled", BIOS will activate
and retest all DIMMs on the next
system boot.
This option will automatically
reset to "Disabled" on the next
system boot.
Enable: Allow remapping of
overlapped PCI memory above
the total physical memory.
Disable: Do not allow remapping
of memory.
Disabled provides the most
memory space. Sparing reserves
memory to replace failures.
Grayed out if the installed
DIMM configuration does
not support it.
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4.4.3 Boot Menu
Table 32. BIOS Setup, Boot Menu Selections
Feature Options Help Text Description
Boot Settings
Boot Settings Configuration N/A Configure settings during system boot. Selects submenu.
Boot Device Priority N/A Specifies the boot device priority sequence. Selects submenu.
Hard Disk Drives N/A
Removable Drives N/A
CD/DVD Drives N/A
Specifies the boot device priority sequence from
available hard drives.
Specifies the boot device priority sequence from
available removable drives.
Specifies the boot device priority sequence from
available CD/DVD drives.
Selects submenu.
Selects submenu.
Selects submenu.
4.4.3.1 Boot Settings Configuration Sub-menu Selections
Table 33. BIOS Setup, Boot Settings Configuration Sub-menu Selections
Feature Options Help Text Description
Boot Settings Configuration
Quick Boot Disabled
Enabled
Quiet Boot Disabled
Enabled
Bootup Num-Lock
PS/2 Mouse Support Disabled
POST Error Pause
Hit ‘F2’ Message Display
Scan User Flash Area
Off
On
Enabled
Auto
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Allows BIOS to skip certain tests while booting. This
will decrease the time needed to boot the system.
Disabled: Displays normal POST messages.
Enabled: Displays OEM Logo instead of POST
messages.
Select power-on state for Numlock.
Select support for PS/2 mouse.
If enabled, the system will wait for user intervention
on critical POST errors. If disabled, the system will
boot with no intervention, if possible.
Displays "Press ‘F2’ to run Setup" in POST.
Allows BIOS to scan the Flash ROM for user
binaries.
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4.4.3.2 Boot Device Priority Sub-menu Selections
Table 34. BIOS Setup, Boot Device Priority Sub-menu Selections
Feature Options Help Text Description
Boot Device Priority
1st Boot Device Varies
nth Boot Device Varies
Specifies the boot sequence from the
available devices.
A device enclosed in parenthesis has
been disabled in the corresponding type
menu.
Specifies the boot sequence from the
available devices.
A device enclosed in parenthesis has
been disabled in the corresponding type
menu.
Number of entries will vary based on
system configuration.
Note: The boot sequence will be reset by the BIOS anytime a controller card listed in the boot
menu is changed or removed from the system. Remember to return to this menu any time a
configuration change is made to a bootable controller card.
4.4.3.2.1 Hard Disk Drive Sub-menu Selections
Table 35. BIOS Setup, Hard Disk Drive Sub-Menu Selections
Feature Options Help Text Description
Hard Disk Drives
1st Drive Varies
nth Drive Varies
Specifies the boot sequence from the available
devices.
Specifies the boot sequence from the available
devices.
Varies based on system configuration.
Varies based on system configuration.
4.4.3.2.2 Removable Drive Sub-menu Selections
Table 36. BIOS Setup, Removable Drives Sub-menu Selections
Feature Options Help Text Description
Removable Drives
1st Drive Varies
nth Drive Varies
Specifies the boot sequence from the available
devices.
Specifies the boot sequence from the available
devices.
Varies based on system configuration.
Varies based on system configuration.
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4.4.3.2.3 ATAPI CDROM drives sub-menu selections
Table 37. BIOS Setup, CD/DVD Drives Sub-menu Selections
Feature Options Help Text Description
CD/DVD Drives
1st Drive Varies
nth Drive Varies
Specifies the boot sequence from the available
devices.
Specifies the boot sequence from the available
devices.
Varies based on system configuration.
Varies based on system configuration.
4.4.4 Security Menu
Table 38. BIOS Setup, Security Menu Options
Feature Options Help Text Description
Security Settings
Administrator
Password is
User Password is N/A Install / Not installed Informational display.
Set Admin
Password
Set User
Password
User Access Level No Access
Clear User
Password
Fixed disk boot
sector protection
Password On Boot
Secure Mode
Timer
N/A Install / Not installed Informational display.
N/A Set or clear Admin password
N/A Set or clear User password
LIMITED: allows only limited
View Only
Limited
Full Access
N/A
Disabled
Enabled
Disabled
Enabled
1 minute
2 minutes
5 minutes
10 minutes
20 minutes
60 minutes
120 minutes
fields to be changed such as Date
and Time.
NO ACCESS: prevents User
access to the Setup Utility.
VIEW ONLY: allows access to the
Setup Utility but the fields can not
be changed.
FULL: allows any field to be
changed.
Immediately clears the user
password.
Enable/Disable Boot Sector Virus
Protection.
If enabled, requires password
entry before boot.
Period of key/PS/2 mouse
inactivity specified for Secure
Mode to activate. A password is
required for Secure Mode to
function. Has no effect unless at
least one password is enabled.
Pressing enter twice will clear the
password. This option is grayed
our when entering setup with a
user password.
Pressing enter twice will clear the
password.
This node is grayed out and
becomes active only when Admin
password is set.
Admin uses this option to clear
User password (Admin password
is used to enter setup is
required).
This node is gray if Administrator
password is not installed.
This node is grayed out if a user
password is not installed.
This node is grayed out if a user
password is not installed.
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Secure Mode Hot
Key (Ctrl-Alt- )
Secure Mode Boot
Front Panel Switch
Inhibit
NMI Control
[L]
[Z]
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Key assigned to invoke the
secure mode feature. Cannot be
enabled unless at least one
password is enabled. Can be
disabled by entering a new key
followed by a backspace or by
entering delete.
When enabled, allows the host
system to complete the boot
process without a password. The
keyboard will remain locked until
a password is entered. A
password is required to boot from
diskette.
When disabled, allows the use of
Front Panel Switch. When
enabled, inhibits Power Switch
and Reset Switch button.
Disables the Power Switch and
the Reset Switch when Secure
mode is activated.
Enable / disable NMI control for
the front panel NMI button.
This node is grayed out if a user
password is not installed.
This node is grayed out if a user
password is not installed.
This node is grayed out if a
password is not installed or if the
AC Policy is set to “Stays Off.”
4.4.5 Server Menu
Table 39. BIOS Setup, Server Menu Selections
Feature Options Help Text Description
System management N/A N/A Selects submenu.
Serial Console Features N/A N/A Selects submenu.
Event Log configuration N/A Configures event logging. Selects submenu.
Assert NMI on SERR Disabled
Enabled
Assert NMI on PERR Disabled
Enabled
Resume on AC Power
Loss
FRB-2 Policy
Late POST Timeout
Stays Off
Power On
Retry on Next Boot
Disable FRB2 Timer
Disabled
5 minutes
10 minutes
15 minutes
20 minutes
If enabled, NMI is generated on
SERR and logged.
If enabled, NMI is generated.
SERR option needs to be
enabled to activate this option.
Determines the mode of
operation if a power loss occurs.
Stays off, the system will remain
off once power is restored.
Power On, boots the system
after power is restored.
This controls action if the boot
processor will be disabled or not.
This controls the time limit for
add-in card detection. The
system is reset on timeout.
Grayed out if “NMI on
SERR” is disabled.
When set to “Stays Off,”
“Front Panel Switch
Inhibit” is disabled.
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Feature Options Help Text Description
Hard Disk OS Boot
Timeout
PXE OS Boot Timeout
OS Watchdog Timer Policy
Platform Event Filtering Disabled
Disabled
5 minutes
10 minutes
15 minutes
20 minutes
Disabled
5 minutes
10 minutes
15 minutes
20 minutes
Stay On
Reset
Power Off
Enabled
This controls the time limit
allowed for booting an operating
system from a Hard disk drive.
The action taken on timeout is
determined by the OS Watchdog
Timer policy setting.
This controls the time limit
allowed for booting an operating
system using PXE boot. The
action taken on timeout is
determined by OS Watchdog
Timer policy setting.
Controls the policy upon timeout.
Stay on action will take no overt
action. Reset will force the
system to reset. Power off will
force the system to power off.
Disable trigger for system
sensor events.
4.4.5.1 System Management Sub-menu Selections
Table 40. BIOS Setup, System Management Sub-menu Selections
Feature Options Help Text Description
System Management
Server Board Part Number N/A N/A Field contents varies
Server Board Serial Number N/A N/A Field contents varies
NIC 1 MAC Address N/A N/A Field contents varies
System Part Number N/A N/A Field contents varies
System Serial Number N/A N/A Field contents varies
Chassis Part Number N/A N/A Field contents varies
Chassis Serial Number N/A N/A Field contents varies
BIOS Version N/A N/A
BMC Device ID N/A N/A Field contents varies
BMC Firmware Revision N/A N/A Field contents varies
BMC Device Revision N/A N/A Field contents varies
PIA Revision N/A N/A Field contents varies
SDR Revision N/A N/A Field contents varies
BIOS ID string (excluding the
build time and date).
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4.4.5.2 Serial Console Features Sub-menu Selections
Table 41. BIOS Setup, Serial Console Features Sub-menu Selections
Feature Options Help Text Description
Serial Console Features
BIOS Redirection Port
Disabled
Serial A
Serial B
If enabled, BIOS uses the specified serial
port to redirect the console to a remote
ANSI terminal. Enabling this option disables
Quiet Boot.
Baud Rate 9600
19.2K
38.4K
57.6K
115.2K
Flow Control
Terminal Type PC-ANSI
ACPI Redirection port
No Flow
Control
CTS/RTS
XON/XOFF
CTS/RTS +
CD
VT100+
VT-UTF8
Disabled
Serial A
Serial B
N/A
If enabled, it will use the Flow control
selected.
CTS/RTS = Hardware
XON/XOFF = Software
CTS/RTS + CD = Hardware + Carrier
Detect for modem use.
VT100+ selection only works for English as
the selected language. VT-UTF8 uses
Unicode. PC-ANSI is the standard PC-type
terminal.
Enable / Disable the ACPI OS Headless
Console Redirection.
4.4.5.3 Event Log Configuration Sub-menu Selections
Table 42. BIOS Setup, Event Log Configuration Sub-menu Selections
Feature Options Help Text Description
Event Log Configuration
Clear All Event Logs
BIOS Event Logging Disabled
Critical Event Logging Disabled
ECC Event Logging Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
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Setting this to Enabled will clear the System
Event Log during the next boot.
Select enabled to allow logging of BIOS
events.
If enabled, BIOS will detect and log events
for system critical errors. Critical errors are
fatal to system operation. These errors
include PERR, SERR, ECC.
Enables or Disables ECC Event Logging.
Option will be
automatically set back to
Disabled at the next
reboot.
Enables BIOS to log
events to the SEL. This
option controls BIOS
events only.
Enable SMM handlers to
detect and log events to
SEL.
Grayed out if "Critical
Event Logging" option is
disabled.
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PCI Error Logging Disabled
Enabled
FSB Error Logging Disabled
Enabled
Hublink Error Logging Disabled
Enabled
Enables or Disables PCI Error Logging.
Enables or Disables Front side bus Error
Logging.
Enables or Disables Hublink Error Logging.
Grayed out if "Critical
Event Logging" option is
disabled.
Grayed out if "Critical
Event Logging" option is
disabled.
Grayed out if "Critical
Event Logging" option is
disabled.
4.4.6 Exit Menu
Table 43. BIOS Setup, Exit Menu Selections
Feature Options Help Text
Exit Options
Save
Changes and
Exit
Discard
Changes and
Exit
Discard
Changes
Load Setup
Defaults
Load Custom
Defaults
Save Custom
Defaults
N/A Exit system setup after saving the changes.
F10 key can be used for this operation.
N/A Exit system setup without saving any changes.
ESC key can be used for this operation.
N/A Discards changes done so far to any of the setup questions.
F7 key can be used for this operation.
N/A Load Setup Default values for all the setup questions.
F9 key can be used for this operation.
N/A Load custom defaults.
N/A Save custom defaults
4.5 Flash Update Utility
The flash ROM contains system initialization routines, the BIOS Setup Utility, and runtime
support routines. The exact layout is subject to change, as determined by Intel. A 64-KB user
block is available for user ROM code or custom logos. The flash ROM also contains initialization
code in compressed form for onboard peripherals, like SCSI, NIC and video controllers. It also
contains support for the rolling single-boot BIOS update feature.
The complete ROM is visible, starting at physical address 4 GB minus the size of the flash ROM
device. The Flash Memory Update utility loads the BIOS image minus the recovery block to the
secondary flash partition, and notifies the BIOS that this image should be used on the next
system re-boot. Because of shadowing, none of the flash blocks are visible at the aliased
addresses below 1 MB.
A 16-KB parameter block in the flash ROM is dedicated to storing configuration data that
controls the system configuration (ESCD). Application software must use standard APIs to
access these areas; application software cannot access the data directly.
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4.6 Rolling BIOS and On-line Updates
The Online Update nomenclature refers to the ability to update the BIOS while the server is
online and in operation, as opposed to taking the server out of operation while performing a
BIOS update. The rolling BIOS nomenclature refers to the capability of having two copies of
BIOS: the current one in use, and a second BIOS to which an updated BIOS version can be
written. When ready, the system can roll forward to the new BIOS. In case of a failure with the
new version, the system can roll back to the previous version.
The BIOS relies on specialized hardware and additional flash space to accomplish online
update/rolling of the BIOS. To this end, the flash is divided into two partitions, primary and
secondary. The active partition from which the system boots shall be referred to as the primary
partition. The AMI FLASH update suite and Intel Online updates preserve the existing BIOS
image on the primary partition. BIOS updates are diverted to the secondary partition. After the
update is complete, a notification flag is set. During the subsequent boot following the BIOS
update, the system continues to attempt to boot from the primary BIOS partition. On determining
that a BIOS update occurred in the previous boot, the system then attempts to boot from the
new BIOS. If a failure happens while booting to the new BIOS, the specialized hardware on the
system switches back to the primary BIOS partition, thus affecting a “Roll Back”.
If a user wishes to force the system to boot to the primary bank, a jumper on the server board at
location J29 is available. In the default 1-2 position, the rolling BIOS configuration is automatic.
If the jumper is set to position 2-3, then the system will boot to the primary bank every time.
The rolling one-boot update feature applies to all the update mechanisms discussed in the
following sections.
4.7 Flash Update Utility
Server platforms support a DOS-based firmware update utility. This utility loads a fresh copy of
the BIOS into the flash ROM.
The BIOS update may affect the following items:
• The system BIOS, including the recovery code, setup utility and strings.
• Onboard video BIOS, SCSI BIOS, and other option ROMS for the devices embedded on
the server board.
• OEM binary area.
• Microcode updates.
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4.7.1 Flash BIOS
The BIOS flash utility is compatible with DOS, Microsoft* Windows* 2000/2003/XP, Linux and
EFI operating environments.
An afuXXX AMI Firmware Update utility (such as AFUDOS, AFUWIN, AFULNX, or AFUEFI) is
required for a BIOS update.
The format and usage of the afuXXX utility is as follows:
afuXXX /i<ROM filename> [/n] [/p[b][n][c]] [/r<registry_path>] [/s] [/k] [/q] [/h]
/n - don't check ROM ID
/pbnc b - Program Boot Block
n - Program NVRAM
c - Destroy System CMOS
/r - registry path to store result of operation (only for Windows version)
/k - Program non-critical block only
/s - Leave signature in BIOS
/q - Silent execution
/h - Print help
4.7.1.1 Updating the BIOS from DOS
• Make sure that the flash bootable disk contains both the ROM image and the afudos
update utility.
• Boot to DOS.
• Run the afudos utility as follows:
AFUDOS /i<ROM filename> [/n][/p[b][n][c]]
4.7.1.2 Updating the BIOS from Microsoft* Windows* 2000/2003/XP
• Make sure that the flash disk contains the ROM image, AMIFLDRV.SYS and
AFUWIN.EXE.
• Boot to Microsoft Windows 2000/2003/XP.
• Run the AFUWIN utility as follows:
AFUWIN /i<ROM filename> [/n][/p[b][n][c]]
4.7.1.3 Updating the BIOS from Linux
• Make sure that the flash disk contains the ROM image and the AFULNX utility.
• Boot to Linux and set up a floppy device.
• Run the AFULNX utility as follows:
./afulnx /i<ROM filename> [/n][/p[b][n][c]]
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4.7.1.4 Updating the BIOS from the EFI Shell
• Make sure that the flash disk contains the ROM image and the AFUEFI utility.
• Boot to the EFI Shell with the flash disk.
• Do a map -r to retrieve the file system on the disk.
• Change to the flash disk, e.g., if the flash disk is fs0:, type fs0: at the prompt.
• Run the afuefi utility as follows:
afuefi [/n] [/p[b][n][c]] <ROM filename>
4.7.2 User Binary Area
The server board includes an area in flash for implementation-specific OEM add-ons. This
OEM binary area can be updated as part of the system BIOS update or it can be updated
independent of the system BIOS.
The command line usage for the UbinD utility is as follows:
UBinD </R> or </I> or </D> [/M<ModID>] /F<RomFileName> /B<NewUserBinaryFileName>
[/N<NewRomFileName>] [/O<NCB>]
</R> - replaces the user binary module
</I> - inserts the user binary module
</D> - deletes the user binary module from the ROM file.
</?> - displays help information.
/M<ModID> - is hexadecimal user binary module ID; Default ModID = 0xF0.
/O<NCB> - is the 0-based index of the non-critical block number calculated from the start of the
ROM file. Default NCB = 1, used only with the insert option. See ROMInfo for reference.
</N<NewRomFileName> - if this option is not included, the ROM is saved with the same name.
4.7.3 Recovery Mode
Three conditions can cause the system to enter recovery mode:
• Pressing a hot key
• Setting the recovery jumper (J17, labeled RCVR BOOT) to pins 2-3
• Damaging the ROM image, which will cause the system to enter recovery and update
the system ROM without the boot block.
4.7.3.1 BIOS Recovery
The BIOS has a ROM image size of 2 MB. A standard 1.44MB floppy diskette cannot hold the
entire ROM file due to the large file size. To compensate for this, a Multi-disk recovery method
is available for BIOS recover (see Section 4.7.3.2 for further details).
The BIOS contains a primary and secondary partition, and can support rolling BIOS updates
(see Section 4.6 for details). The recovery process performs an update on the secondary
partition in the same fashion that the normal flash update process updates the secondary
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partition. After recovery is complete and the power is cycled to the system, the BIOS partitions
switch and the code executing POST will be the code that was just flashed from the recovery
media. The BIOS is made up of a boot block recovery section, a main BIOS section, an OEM
logo/user binary section, and an NVRAM section. The NVRAM section will either be preserved
or destroyed based on a hot key press during invocation of the recovery. All the other sections
of the secondary BIOS will be updated during the recovery process. If an OEM wishes to
preserve the OEM section across an update, it is recommended that the OEM modify the
provided AMIBOOT.ROM file with the user binary or OEM logo tools before performing the
recovery.
A BIOS recovery can be accomplished from one of the following devices: a standard 1.44 or
2.88 MB floppy drive, an USB Disk-On-Key, or an ATAPI CD-ROM/DVD.
The recovery media must include the BIOS image file, AMIBOOT.ROM.
The recovery mode procedure is as follows:
1. Insert or plug-in the recovery media with the AMIBOOT.ROM file.
2. Power on the system. When progress code E9 is displayed on port 80h, the system
will detect the recovery media (if there is no image file present, the system will cycle
through progress code F1 to EF).
3. When F3 is displayed on port 80h, the system will read the BIOS image file.
4. The screen will display flash progress and indicate whether the NVRAM and CMOS
have been destroyed.
5. When recovery mode is complete, the system will halt and the system can be powered
off.
Note: Three different hot-keys can be invoked:
<Ctrl+Home> - Recovery with CMOS destroyed and NVRAM preserved.
<Ctrl+PageDown> - Recovery with both CMOS and NVRAM preserved.
<Ctrl+PageUp> - Recovery with both CMOS and NVRAM destroyed.
4.7.3.2 Multi-disk Recovery
The Multi-disk Recovery method is available to support ROM images greater than 1 MB when
performing a BIOS recovery from multiple floppy disks.
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Do the following to perform a multi-disk BIOS recovery:
1. Use the SPLIT.EXE utility to split the ROM image.
2. Execute the following command at the command prompt:
• split <File Name To Be Split> <New File Name> <File Size in KB>
• For Example: C:\split AMIBOOT.ROM AMIBOOT 1024
3. The above command will create files of size 1 MB each (1024 KB) with the names
AMIBOOT.000, AMIBOOT.001... and so on. The number of files (or floppy disks)
will depend upon the size of the AMIBOOT.ROM file.
4. Load the first disk with the AMIBOOT.000 file into the system.
5. After reading the file, the system will increment the file extension and begin
searching for the second file, AMIBOOT.001, on the same floppy disk.
6. If the system can’t find the file on the floppy disk, it will beep once (1sec long) and
then search again. Load the second floppy disk at this point.
7. The system will continue reading and searching for files in this fashion. Once a file
has been read, the system will increment the file extension and then begin
searching for the next file. If searching for the AMIBOOT.002 file, the system will
beep 2 times (each beep 1 sec long with a 0.5 sec gap between beeps). If
searching for the AMIBOOT.003 file, the system will beep three times with a 0.5
sec gap between beeps.
8. This process would continue until the total file size read in is equal to the size of
the ROM image.
Limitation:
The maximum number of files supported by the Multi-disk Recovery method is 1,000 files
(AMIBOOT.000 through AMIBOOT.999).
4.7.4 Update OEM Logo
The OEM logo can be changed in the BIOS for DOS and Microsoft* Windows* 2000/2003/XP.
A utility tool is used to change the OEM logo in ROM. The OEM logo can then be updated by
flashing the ROM.
For full details on how to update an OEM logo to the system, download and follow the
instructions in the Customize BIOS with OEM Logo white paper available on the Intel Support
website.
4.7.4.1 Changing the OEM logo for DOS
1. Boot to DOS.
2. Download OEMLOGOD.exe, Rombuild.exe, RomFile, and NewOEMlogoImage to
the hard drive.
3. Run the following command:
OEMLogoD <RomFileName> <NewOEMImageFileName> [/F or /FN or /N]
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4.7.4.2 Changing the OEMlogo for Microsoft* Windows* 2000/2003/XP
1. Boot to Microsoft Windows 2000/2003/XP.
2. Download OEMLOGO.exe, Rombuild.exe, RomFile, and NewOEMlogoImage to the
hard drive.
3. Run the following command:
OEMLogo <RomFileName> <NewOEMImageFileName> [/F or /FN or /N]
Usage:
OEMLogo <RomFileName> <NewOEMImageFileName> [/F or /FN or /N]
or,
OEMLogo <RomFileName> [/D]
Where,
[/F] - forces replacement of the OEM logo even if the logo formats do not match.
[/N] – inserts the 16-color BMP without converting it to the default AMI format.
[/FN] - forces replacement of the OEM logo without converting a 16-color BMP to the
default AMI format.
[/D] - deletes the logo module from the ROM file.
Supported formats are dependent on the ROM and include the following:
• 16-color BMP, size up to 640x480, even width
• 256-color BMP, 640x480
• JPEG, 640x480, 800x600, or 1024x768
• 256-color PCX, 640x480
Note: The Rombuild.exe file is NOT the same for both DOS and Microsoft Windows
2000/2003/XP. The user must use the correct Rombuild.exe file, dependent upon whether he
or she is updating the OEM logo in DOS or in a Microsoft Windows environment.
4.8 OEM Binary
System customers can supply 16 KB of code and data for use during POST and at run-time.
Individual platforms may support a larger user binary. User binary code is executed at several
defined hook points during POST.
The user binary code is stored in the system flash. If no run-time code is added, the BIOS
temporarily allocates a code buffer according to [PMM]. If run-time code is present, the BIOS
shadows the entire block as though it were an option ROM. The BIOS leaves this region
writeable to allow the user binary to update any data structures it defines. System software can
locate a run-time user binary by searching for it like an option ROM, checking each 2 KB
boundary from C0000h to EFFFFh. The system vendor can place a signature within the user
binary to distinguish it from other option ROMs.
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Intel will provide the tools and reference code to help OEMs build a user binary. The user binary
must adhere to the following requirements:
• In order to be recognized by the BIOS and protected from runtime memory managers,
the user binary must have an option ROM header (55AA, size).
• The system BIOS performs a scan of the user binary area at predefined points during
POST. Mask bits must be set within the user binary to inform the BIOS if an entry point
exists for a given time during POST.
• The system state must be preserved by the user binary.
• User binary code must be relocatable. It will be located within the first Megabyte. The
user binary code should not make any assumptions about the value of the code segment.
• User binary code will always be executed from RAM and never from flash.
• The code in user binary should not hook critical interrupts, should not re-program the
chipset and should not take any action that affects the correct functioning of the system
BIOS.
The BIOS copies the user binary into system memory before the first scan point. If the user
binary reports that it does not contain runtime code, it is located in conventional memory (0 640 KB).
Reporting that the user binary is POSTed has only the advantage that it does not use up limited
option ROM space, and more option ROM space can be used for other devices. If user binary
code is required at run-time, it is copied to the option ROM space. At each scan-point during
POST, the system BIOS determines if the scan-point has a corresponding user binary entry
point to transfer control to.
To determine this, the bitmap at byte 4 of the header is tested against the current mask bit that
has been determined / defined by the scan point. If the bitmap has the appropriate bit set, the
mask is placed in AL and execution is passed to the address computed by (ADR(Byte
5)+5*scan sequence #).
During execution, the user binary may access 11 bytes of Extended BIOS Data Area RAM
(EBDA). The segment of the EBDA can be found at address 40:0e. Offset 18 to offset 21h is
available for the user binary. The BIOS also reserves eight CMOS bits for the user binary.
These bits are in a region of CMOS that does not have a checksum, with default values of zero,
and will always be located in the first bank of CMOS. These bits are contiguous, but are not in a
fixed location. Upon entry into the user binary, DX contains a ‘token’ that points to the reserved
bits.
4.9 Operating System Boot, Sleep, and Wake
4.9.1 Microsoft* Windows* Compatibility
Intel Corporation and Microsoft Corporation co-author design guides for system designers using
®
processors and Microsoft* operating systems. These documents are updated yearly to
Intel
address new requirements and current trends.
PC200x specifications are intended for systems that are designed to work with Windows 2000
and Windows XP class operating systems. The Hardware Design Guide (HDG) for the Windows
XP platform is intended for systems that are designed to work with Windows XP class operating
systems. Each specification classifies the systems further and has requirements based on the
intended usage for that system. For example, a server system that will be used in small
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home/office environments has different requirements than one used for enterprise applications.
The BIOS supports HDG 3.0.
4.9.2 Advanced Configuration and Power Interface (ACPI)
The BIOS is ACPI 2.0c compliant. The primary role of the BIOS is to provide ACPI tables.
During POST, the BIOS creates the ACPI tables and locates them in extended memory (above
1MB). The location of these tables is conveyed to the ACPI-aware operating system through a
series of tables located throughout memory. The format and location of these tables is
documented in the publicly available ACPI specification.
To prevent conflicts with a non-ACPI-aware operating system, the memory used for the ACPI
tables is marked as “reserved” in the INT 15h, function E820h.
As described in the ACPI specification, an ACPI-aware operating system generates an SMI to
request that the system be switched into ACPI mode. The BIOS responds by setting up all
system (chipset) specific configuration required to support ACPI, and sets the SCI_EN bit as
defined by the ACPI specification. The system automatically returns to legacy mode on hard
reset or power-on reset.
There are three runtime components to ACPI:
• ACPI Tables: These tables describe the interfaces to the hardware. ACPI tables can
make use of a p-code type of language, the interpretation of which is performed by the
operating system. The operating system contains and uses an ACPI Machine Language
(AML) interpreter that executes procedures encoded in AML and stored in the ACPI
tables. AML is a compact, tokenized, abstract machine language. The tables contain
information about power management capabilities of the system, APICs, and bus
structure. The tables also describe control methods that operating systems can use to
change PCI interrupt routing, control legacy devices in Super I/O, find out the cause of
wake events, and handle PCI hot plugging, if applicable.
• ACPI Registers: The constrained part of the hardware interface, described (at least in
location) by the ACPI tables.
• ACPI BIOS: This is the code that boots the machine and implements interfaces for
sleep, wake, and some restart operations. The ACPI Description Tables are also
provided by the ACPI BIOS.
The BIOS supports S0, S1, S4, and S5 states. S1 and S4 are considered sleep states. The
ACPI specification defines the sleep states and requires the system to support at least one of
them.
While entering the S4 state, the operating system saves the context to the disk and most of the
system is powered off. The system can wake on a power button press, or a signal received from
a wake-on-LAN compliant LAN card (or onboard LAN), modem ring, PCI power management
interrupt, or RTC alarm. The BIOS performs complete POST upon wake up from S4, and
initializes the platform.
The system can wake from the S1 state using a PS/2 keyboard, mouse, or USB device, in
addition to the sources described above.
The wake-up sources are enabled by the ACPI operating systems with cooperation from the
drivers; the BIOS has no direct control over the wakeup sources when an ACPI operating
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system is loaded. The role of the BIOS is limited to describing the wakeup sources to the
operating system and controlling secondary control/status bits via the DSDT table.
The S5 state is equivalent to operating system shutdown. No system context is saved.
4.9.3 Sleep and Wake Functionality
The BIOS supports a front panel power button. The power button is a request that is forwarded
by the mBMC to the ACPI power state machines in the chipset. It is monitored by the mBMC
and does not directly control power on the power supply.
The platform supports a front panel reset button. The reset button is a request that is forwarded
by the mBMC to the chipset. The BIOS does not affect the behavior of the reset button.
The BIOS supports a front panel NMI button. The NMI button may not be provided on all front
panel designs. The NMI button is a request that causes the mBMC to generate an NMI (nonmaskable interrupt). The NMI is captured by the BIOS during Boot Services time or the OS
during Runtime. The BIOS will simply halt the system upon detection of the NMI.
4.9.4 Power Switch Off to On
The chipset may be configured to generate wakeup events for several different system events:
Wake on LAN, PCI Power Management Interrupt (PMI), and Real Time Clock Alarm are
examples of these events. The operating system will program the wake sources before
shutdown. A transition from either source results in the mBMC starting the power-up sequence.
Since the processors are not executing, the BIOS does not participate in this sequence. The
hardware receives power good and reset from the mBMC and then transitions to an ON state.
4.9.5 On to Off (OS absent)
The SCI interrupt is masked. The firmware polls the power button status bit in the ACPI
hardware registers and sets the state of the machine in the chipset to the OFF state. The
mBMC monitors power state signals from the chipset and de-asserts PS_PWR_ON to the
power supply. As a safety mechanism, the mBMC automatically powers off the system in 4-5
seconds if the BIOS fails to service the request.
4.9.6 On to Off (OS present)
If an operating system is loaded, the power button switch generates a request (via SCI) to the
OS to shutdown the system. The OS retains control of the system and OS policy determines
what sleep state (if any) the system transitions into.
4.9.7 System Sleep States
The platform supports the following ACPI System Sleep States:
• ACPI S0 (working) state
• ACPI S1 (sleep) state
• ACPI S4 (suspend to disk) state
• ACPI S5 (soft-off) state
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The platform supports the following wake up sources in an ACPI environment. As noted above,
the OS controls the enabling and disabling of these wake sources.
• Devices that are connected to all USB ports, such as USB mice and keyboards can
wake the system up from the S1 sleep state.
• PS/2 keyboards and mice can wake up the system from the S1 sleep state.
• Both serial ports can be configured to wake up the system from the S1 sleep state.
• PCI cards, such as LAN cards, can wake up the system from the S1 or S4 sleep state.
Note that the PCI card must have the necessary hardware for this to work.
• As required by the ACPI Specification, the power button can always wake up the system
from the S1 or S4 state.
Additionally, if an ACPI operating system is loaded, the following can cause the system to wake
up: the PME, RTC, or Wake-On-LAN.
Table 44. Supported Wake Events
Wake Event Supported via ACPI (by sleep state) Supported
Via Legacy
Wake
Power Button Always wakes system.
Ring indicate from Serial A Wakes from S1 and S4. Yes
Ring indicate from Serial B
PME from PCI cards Wakes from S1 and S4. Yes
RTC Alarm Wakes from S1. Always wakes the system up from S4. No
Mouse Wakes from S1. No
Keyboard Wakes from S1. No
USB Wakes from S1. No
Wakes from S1 and S4. If Serial-B (COM2) is used for
Emergency Management Port, Serial-B wakeup is disabled.
Always wakes
system
Yes
4.10 Security
The BIOS provides a number of security features. This section describes the security features
and operating model.
The BIOS uses passwords to prevent unauthorized tampering with the system. Once secure
mode is entered, access to the system is allowed only after the correct password(s) has been
entered. Both user and administrator passwords are supported by the BIOS. To set a user
password, an administrator password must be entered during system configuration using the
BIOS setup menu. The maximum length of the password is seven characters. The password
cannot have characters other than alphanumeric (a-z, A-Z, 0-9).
Once set, a password can be cleared by entering the password change mode and pressing
enter twice without inputting a string. All setup fields can be modified when entering the
administrator password. The “user access level” setting in the BIOS setup Security menu
controls the user access level. The administrator can choose “No Access” to block the user from
accessing any setup features. “Limited Access” will allow only the date/time fields and the user
password to be changed. “View Only” allows the user to enter BIOS setup, but not change any
settings.
Revision 2.0
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