Intel SE7221BK1-E User Manual

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Intel® Server Board

SE7221BK1-E

Technical Product Specification

Intel order number C91860-001

Revision 1.3

February 2005

Enterprise Platforms and Services Marketing

 

 

 

SE7221BK1-E Technical Product Specification

 

 

 

 

 

 

 

Revision History

 

 

 

 

 

Date

Revision

Modifications

 

 

Number

 

 

July 2004

0.5

Preliminary Release; subject to change.

 

 

 

 

 

September 2004

0.8

Revised technical details of PCI subsystem, memory support and GMCH.

 

 

 

 

 

September 2004

0.9

Revised connectors section

 

 

 

 

 

October 2004

1.0

Released revision

 

 

 

 

 

November 2004

1.1

Corrected supported CPU matrix

 

 

 

 

 

January 2005

1.2

Added Diagnostic LED codes to error handling and reporting section

 

 

 

 

 

February 2005

1.3

Modified Diagnostic LED section. Correct supported CPU matrix.

 

 

 

 

This product specification applies to the Intel® Server Board SE7221BK1-E with BIOS identifier SE7221BK10.86B.

Changes to this specification will be published in the Intel® Server Board SE7221BK1-E Specification Update before being incorporated into a revision of this document.

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SE7221BK1-E Technical Product Specification

Disclaimers

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppels or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design.

Intel Corporation server baseboards contain a number of high-density VLSI and power delivery components which need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non-operating limits.

The Intel® Server Board SE7221BK1-E may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

This document and the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license. The information in this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document.

Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.

Intel® , Pentium® , Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.

*Other brands and names may be claimed as the property of others.

Copyright © Intel Corporation 2005.

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SE7221BK1-E Technical Product Specification

 

Table of contents

 

1.

Introduction ..........................................................................................................................

1

2.

Server Board Overview........................................................................................................

2

 

 

2.1

SE7221BK1-E Feature Set......................................................................................

2

3.

Functional Architecture .......................................................................................................

5

 

 

3.1

Processor Subsystem..............................................................................................

5

 

 

3.1.1

Processor VRD ........................................................................................................

5

 

 

3.1.2

Reset Configuration Logic .......................................................................................

5

 

 

3.1.3

Processor Module Presence Detection ...................................................................

5

 

 

3.1.4

Processor Support ...................................................................................................

5

 

 

3.1.5

Interrupts and APIC .................................................................................................

6

 

 

3.2

Memory Subsystem .................................................................................................

6

 

4. The Intel® E7221 Chipset .....................................................................................................

9

 

 

4.1.1

GMCH Memory Architecture Overview..................................................................

10

 

 

4.1.2

Graphics Memory Controller Hub (GMCH) ............................................................

10

 

 

4.1.3

ICH6R ....................................................................................................................

11

 

 

4.2

Super I/O ...............................................................................................................

13

 

 

4.2.1

Serial Ports ............................................................................................................

13

 

 

4.2.2

BIOS Flash ............................................................................................................

14

 

 

4.2.3

System Health Support..........................................................................................

14

5.

I/O Subsystem ....................................................................................................................

14

 

 

5.1

PCI Subsystem ......................................................................................................

14

 

 

5.1.1

P32-A: 32-bit/33-MHz PCI Subsystem...................................................................

14

 

 

5.1.2

P32-B 66-MHz PCI-X Subsystem (SE7221BK1LX sku only) .............................

15

 

 

5.1.3

P64-C 66/100-MHz PCI-X Subsystem...................................................................

16

 

 

5.1.4

PCI-E x8 ................................................................................................................

17

 

 

5.2

Video Controller .....................................................................................................

17

 

 

5.3

Network Interface Controller (NIC) ........................................................................

17

 

 

5.3.1

NIC Connector and Status LEDs ...........................................................................

17

 

 

5.4

Interrupt Routing ....................................................................................................

18

 

 

5.4.1

Legacy Interrupt Routing .......................................................................................

18

 

 

5.4.2

APIC Interrupt Routing...........................................................................................

18

 

 

5.4.3

Serialized IRQ Support ..........................................................................................

19

 

 

 

 

 

 

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SE7221BK1-E Technical Product Specification

 

 

5.5

PCI Error Handling.................................................................................................

19

6.

ACPI Implementation .........................................................................................................

23

 

6.1

ACPI ......................................................................................................................

23

 

6.1.1

Front Panel Switches.............................................................................................

23

 

6.1.2

Wake up Sources (ACPI and Legacy) ...................................................................

24

7.

Connectors .........................................................................................................................

25

 

7.1

Main Power Connector ..........................................................................................

25

 

7.2

I2C Header .............................................................................................................

26

 

7.3

Front Panel Connector...........................................................................................

26

 

7.4

VGA Connector......................................................................................................

27

 

7.5

NIC Connector .......................................................................................................

27

 

7.6

IDE Connector .......................................................................................................

28

 

7.7

SATA Connector....................................................................................................

29

 

7.8

USB Connector......................................................................................................

29

 

7.9

Floppy Connector ..................................................................................................

30

 

7.10

Serial Port Connector ............................................................................................

30

 

7.11

Keyboard and Mouse Connector ...........................................................................

31

 

7.12

Miscellaneous Headers .........................................................................................

31

 

7.12.1

Fan Header............................................................................................................

31

 

7.12.2

Intrusion Cable Connector .....................................................................................

32

 

7.12.3

HDD LED Header ..................................................................................................

32

 

7.12.4

Rolling BIOS selection header...............................................................................

33

8.

Configuration Jumpers......................................................................................................

33

 

8.1

System Recovery and Update Jumpers ................................................................

33

9.

BIOS Setup Utility...............................................................................................................

34

 

9.1

Localization............................................................................................................

34

 

9.2

Console Redirection ..............................................................................................

34

 

9.3

Configuration Reset ...............................................................................................

34

 

9.4

Keyboard Commands ............................................................................................

34

 

9.5

Entering BIOS Setup .............................................................................................

36

 

9.5.1

Main Menu .............................................................................................................

36

 

9.5.2

Advanced menu.....................................................................................................

37

 

9.5.3

Boot menu .............................................................................................................

43

 

9.5.4

Chipset Menu.........................................................................................................

45

 

9.5.5

Security menu........................................................................................................

47

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SE7221BK1-E Technical Product Specification

9.5.6

Server menu ..........................................................................................................

48

9.5.7

Exit menu...............................................................................................................

51

9.6

Upgrading the BIOS...............................................................................................

51

9.6.1

Preparing for the Upgrade .....................................................................................

51

9.6.2

Flash Architecture and Flash Update Utility...........................................................

53

9.6.3

Rolling BIOS and On-line updates.........................................................................

53

9.7

Error Handling and Reporting ................................................................................

56

9.7.1

POST Error Beep Codes .......................................................................................

56

9.7.2

BIOS Event Log .....................................................................................................

57

9.7.3

POST Progress Codes and Messages..................................................................

58

Table 70. POST Code Checkpoints .........................................................................................

58

Table 71. Bootblock Initialization Code Checkpoints............................................................

61

Table 72. Bootblock Recovery Code Checkpoints ................................................................

62

Table 73. DIM Code Checkpoints ............................................................................................

63

Table 74. ACPI Runtime Checkpoints .....................................................................................

63

9.8

Diagnostic LEDs ....................................................................................................

64

9.8.1

Diagnostic LED POST Progress Codes ................................................................

64

Table 76. Boot Block POST Progress Codes .........................................................................

64

Table 77. POST Progress Codes .............................................................................................

65

10. Power Information..............................................................................................................

68

10.1

Intel® Server Board SE7221BK1-E Power Budget ...............................................

68

10.2

Power Supply Specifications .................................................................................

69

10.2.1

Power Timing Requirements .................................................................................

69

10.2.2

Dynamic Loading ...................................................................................................

71

10.2.3

AC Line Transient Specification.............................................................................

72

10.2.4

AC Line Fast Transient (EFT) Specification ..........................................................

72

11. Absolute Maximum Ratings ..............................................................................................

72

11.1

Mean Time Between Failures (MTBF) Test Results..............................................

73

12. Hardware Monitoring .........................................................................................................

73

12.1

Monitored Components .........................................................................................

73

12.2

Fan Speed Control.................................................................................................

75

12.3

Chassis Intrusion ...................................................................................................

76

13. Product Regulatory Compliance.......................................................................................

76

13.1.1

Product Safety Compliance ...................................................................................

76

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13.1.2

Product EMC Compliance .....................................................................................

76

13.1.3

Product Regulatory Compliance Markings ............................................................

76

13.2

Electromagnetic Compatibility Notices ..................................................................

77

13.2.1

FCC (USA).............................................................................................................

77

13.2.2

INDUSTRY CANADA (ICES-003)..........................................................................

78

13.2.3

Europe (CE Declaration of Conformity) .................................................................

78

13.2.4

Taiwan Declaration of Conformity..........................................................................

78

13.2.5

Korean RRL Compliance .......................................................................................

78

13.2.6

Australia / New Zealand.........................................................................................

79

13.3

Replacing the Back-Up Battery..............................................................................

79

13.4

Calculated Mean Time Between Failures (MTBF).................................................

80

13.5

Mechanical Specifications .....................................................................................

80

Glossary........................................................................................................................................

 

I

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SE7221BK1-E Technical Product Specification

List of Tables

 

 

Table 1.

Processor Support Matrix ..............................................................................................

 

6

Table 2. Memory Bank Labels and DIMM Population Order........................................................

 

8

Table 3.

Characteristics of Dual/Single Channel Configuration with/without Dynamic Mode

...... 9

Table 4. Supported DDR2 modules ...........................................................................................

 

10

Table 5.

PCI Bus Segment Characteristics................................................................................

 

14

Table 6.

P32-A Configuration IDs ..............................................................................................

 

15

Table 7.

P32-A Arbitration Connections.....................................................................................

 

15

Table 8.

P32-B Configuration IDs ..............................................................................................

 

15

Table 9.

P32-B Arbitration Connections.....................................................................................

 

16

Table 10.

P64-C Configuration IDs ............................................................................................

 

16

Table 11.

P64-C Arbitration Connections ..................................................................................

 

16

Table 12. PCI-E x 8 Connections..............................................................................................

 

17

Table 13.

PCI AND PCI-X Interrupt Routing/Sharing.................................................................

 

18

Table 14.

Interrupt Definitions....................................................................................................

 

19

Table 15. Supported Wake Events ............................................................................................

 

24

Table 16. Power Connector Pin-out (CN4H1)............................................................................

 

25

Table 17. Auxiliary CPU Power Connector Pin-out (CN4B1).....................................................

 

25

Table 18. HSBP Header Pin-out (J1D1) ....................................................................................

 

26

Table 19. LCD Header Pin-out (J1C1).......................................................................................

 

26

Table 20. LEGEND SE_LINK Header Pin-out (J2B1)................................................................

 

26

Table 21.

Front Panel 34-Pin Header Pin-out (J1J1).................................................................

 

26

Table 22. VGA Connector Pin-out (J8A1)..................................................................................

 

27

Table 23.

NIC1-82541PI(10/100/1000) Connector Pin-out (J5A1) ............................................

 

27

Table 24.

NIC2-82541PI (10/100/1000) Connector Pin-out (J6A1) ...........................................

 

28

Table 25.

ATA 40-pin Connector Pin-out (J3J1) ........................................................................

 

28

Table 26. SATA Connector Pin-out (J1G1, J1G2, J1J2, J2J1)..................................................

 

29

Table 27. USB Connectors Pin-out (J5A1) ................................................................................

 

29

Table 28.

Optional USB Connection Header Pin-out (J4F1) .....................................................

 

29

Table 29.

Legacy 34-pin Floppy Connector Pin-out (JP3J1) .....................................................

 

30

Table 30.

External DB9 Serial A Port Pin-out (J8A1).................................................................

 

30

Table 31.

9-pin Header Serial B Port Pin-out (J1B1) .................................................................

 

31

Table 32. Keyboard and Mouse PS/2 Connectors Pin-out (KM9A1) .........................................

 

31

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SE7221BK1-E Technical Product Specification

 

Table 33.

Three-pin Fan Headers Pin-out (JP5J1, JP5J2, JP7A1, JP6A1)...............................

31

Table 34.

Eight-pin Fan Header Pin-out (J6J1, J6J2, J6J3, and J6J4)......................................

32

Table 35.

Intrusion Cable Connector (J1A1)Pin-Out .................................................................

32

Table 36. HDD LED Header (J1E1) Pin-Out..............................................................................

32

Table 37. HDD LED Header (J1E1) Pin-Out..............................................................................

33

Table 38. System Recovery and Update Jumper Options.........................................................

33

Table 39. BIOS Setup Keyboard Command Bar Options ..........................................................

34

Table 40. BIOS Setup, Main Menu Options...............................................................................

36

Table 41. BIOS Setup, Advanced Menu Options.......................................................................

37

Table 42.

BIOS Setup, Processor configuration sub-menu options...........................................

37

Table 43. BIOS Setup IDE Configuration Menu Options ............................................................

38

Table 44.

BIOS Setup, IDE Device Configuration Sub-menu Selections ..................................

39

Table 45.

BIOS Setup, Floppy Configuration Sub-menu Selections..........................................

40

Table 46. BIOS Setup, Super I/O Configuration Sub-menu.......................................................

40

Table 47. BIOS Setup, USB Configuration Sub-menu Selections ..............................................

41

Table 48. BIOS Setup, USB Mass Storage Device Configuration Sub-menu Selections..........

41

Table 49.

BIOS Setup, PCI Configuration Sub-menu Selections ..............................................

42

Table 50. BIOS Setup, Memory Configuration Sub-menu Selections........................................

43

Table 51. BIOS Setup, Boot Menu Selections ...........................................................................

43

Table 52.

BIOS Setup, Boot Settings Configuration Sub-menu Selections ...............................

44

Table 53.

BIOS Setup, Boot Device Priority Sub-menu Selections ...........................................

44

Table 54. BIOS Setup, Hard Disk Drive Sub-Menu Selections..................................................

44

Table 55. BIOS Setup, Removable Drives Sub-menu Selections..............................................

45

Table 56. BIOS Setup, ATAPI CDROM Drives Sub-menu Selections.......................................

45

Table 57. BIOS Setup, ATAPI CDROM Drives Sub-menu Selections.......................................

45

Table 58. BIOS Setup, ATAPI CDROM Drives Sub-menu Selections.......................................

45

Table 59. BIOS Setup, ATAPI CDROM Drives Sub-menu Selections.......................................

46

Table 60. BIOS Setup, ATAPI CDROM Drives Sub-menu Selections.......................................

47

Table 61. BIOS Setup, Security Menu Options..........................................................................

47

Table 62. BIOS Setup, Server Menu Selections........................................................................

48

Table 63. BIOS Setup, System Management Sub-menu Selections..........................................

49

Table 64.

BIOS Setup Serial Console Features Sub-menu Selections .....................................

50

Table 65.

BIOS Setup, Event Log Configuration Sub-menu Selections ....................................

50

Table 66.

BIOS Setup, Exit Menu Selections ............................................................................

51

Table 67. POST Error Beep Codes ...........................................................................................

56

 

 

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SE7221BK1-E Technical Product Specification

Table 68. BIOS Recovery Beep Codes .....................................................................................

57

Table 69. POST Error Messages and Handling.........................................................................

57

Table 70. POST Code Checkpoints............................................................................................

58

Table 71. Bootblock Initialization Code Checkpoints ..................................................................

61

Table 72. Bootblock Recovery Code Checkpoints......................................................................

62

Table 73. DIM Code Checkpoints ...............................................................................................

63

Table 74. ACPI Runtime Checkpoints ........................................................................................

63

Table 75. POST Progress Code LED Example ..........................................................................

64

Table 76. Boot Block POST Progress Codes .............................................................................

64

Table 77. POST Progress Codes ...............................................................................................

65

Table 78. The Board Power Budget...........................................................................................

68

Table 79.

The Board Power Supply Voltage Specification ........................................................

69

Table 80.

Output Voltage Timing ...............................................................................................

69

Table 81.

Turn On/Off Timing ....................................................................................................

70

Table 82.

Transient Load Requirements....................................................................................

71

Table 83. AC Line Sag Transient Performance .........................................................................

72

Table 84. AC Line Surge Transient Performance ......................................................................

72

Table 85. Absolute Maximum Ratings .......................................................................................

73

Table 86. Monitored Components..............................................................................................

73

Table 87. Product Certification Markings ....................................................................................

77

Table 88. MTBF Data.................................................................................................................

80

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List of Figures

 

Figure 1. Intel® Server Board SE7221BK1-E Diagram ..............................................................

4

Figure 2.

Memory Bank Label Definition......................................................................................

8

Figure 3.

Interrupt Routing Diagram ..........................................................................................

20

Figure 4.

ICH6R Interrupt Routing Diagram...............................................................................

21

Figure 5.

PXH Interrupt Routing Diagram ..................................................................................

22

Figure 6. System Recovery and Update Jumpers (J1F2)..........................................................

33

Figure 7. BIOS Recovery Jumper ..............................................................................................

56

Figure 8.

Output Voltage Timing ................................................................................................

70

Figure 9.

Turn On/Off Timing (Power Supply Signals)...............................................................

71

Figure 10. Fan Speed Control Block Diagram ...........................................................................

75

Figure 11. SE7221BK1-E Server Board Mechanical Drawing ....................................................

81

Figure 12. sku 1 Pedestal mount I/O shield mechanical drawing .............................................

82

Figure 13.

sku 2 Pedestal mount I/O shield mechanical drawing .............................................

83

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SE7221BK1-E Technical Product Specification

1.Introduction

This Intel® Server Board SE7221BK1-E Technical Product Specification (TPS) provides a highlevel technical description for the Intel® Server Board SE7221BK1-E. It details the architecture and feature set for all functional sub-systems that make up the server board.

This document is divided into the following main categories:

Chapter 2. Server Board Overview

Chapter 3. Functional Architecture

Chapter 4. The Intel® E7221 Chipset

Chapter 5. I/O Subsystem

Chapter 6. ACPI Implementation

Chapter 7. Connectors

Chapter 8. Configuration Jumpers

Chapter 9. BIOS Setup Utility

Chapter 10. Absolute Maximum Ratings

Chapter 11. Power Information

Chapter 12. Hardware Monitoring

Chapter 13. Product Regulatory Compliance

Chapter 14. Glossary

1

SE7221BK1-E Technical Product Specification

2.Server Board Overview

2.1SE7221BK1-E Feature Set

The Intel® Server Board SE7221BK1-E supports the following feature set:

Processor and Front Side Bus (FSB) support

-Supports single Intel® Pentium® 4 and Celeron® processors in an LGA775 package

-Capable of 800 MT/s on system bus

-Supports Hyper-Threading Technology

-Supports Intel® Extended Memory System 64 Technology (EM64T)

Intel® E7221 chipset components

-GMCH integrated graphics controller in GMCH component (Intel® GMA 900)

-ICH6R I/O controller

-PXH PCI-X Hub

-12-deep In-Order Queue

Memory System

-4 DIMM sockets supporting 400/533MHz DDR2 DIMMs

-Data bandwidth per channel of 4.2GB/s or 8.5GB/s in dual channel when using DDR2 533MHz

-Support for up to two DDR2 channels for a total of 4 DIMMs (2 DIMMs /Channel) providing up to 4GB max memory capacity.

-Support for 256MB, 512MB, 1GB and 2GB DRAM sizes -Supports Performance Acceleration Technology (PAT)

I/O Subsystem

Four independent PCI Buses:

Segment A: One PCI 32-bit/33-MHz, 5 V connector supporting full length PCI add-in cards and one embedded device(Supports PCI Specification, Rev 2.3)

One Intel® 10/100/1000 82541PI gigabit Ethernet Controller

Segment B: One PCI 32-bit/66-MHz embedded device (SE7221BK1LX sku only) One Intel® 10/100/1000 82541PI gigabit Ethernet Controller

Segment C: Two PCI-X 64-bit/66-MHz, 3.3 V slots supporting full length / full height PCI / PCI-X add-in cards or one 3.3V PCI-X 64-bit/100-MHz slot with riser card (SE7221BK1LX sku only)

Segment D: One x8 PCI Express* slot supporting x1/x2/x4/x8 PCI Express* add-in card or one x8 PCI Express* slot with riser card (SE7221BK1LX sku only)

Serial ATA host controller

- Four independent SATA ports supports data transfer rates up to 1.5 Gb/s (150MB/s) per port

IDE controller

- One IDE connector, supporting up to two ATA-100 compatible devices

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SE7221BK1-E Technical Product Specification

USB 2.0

Two external Universal Serial Bus (USB) ports with an additional internal header providing two optional USB ports for front panel support.

-Supports wake-up from sleeping states S1-S4

-Supports legacy Keyboard/Mouse connections when using PS2-USB dongle

LPC (Low Pin Count) bus segment with one embedded devices:

Super I/O (Super IO) controller chip, NS PC87427, providing all PC-compatible I/O (floppy, serial, keyboard, mouse, two serial com port ) and integrated hardware monitoring

SSI-compliant connectors for SSI interface support: front panel and power connectors.

Support for up to four system fans and one processor fan

3

SE7221BK1-E Technical Product Specification

A

B

C

D

E F

 

G

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

EE

 

 

 

 

 

 

 

 

 

 

J

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

 

 

CPU

 

 

 

 

K

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BB

 

 

 

 

 

Socket

 

 

 

 

 

AA

 

 

 

 

 

 

 

 

 

 

Z

 

 

 

 

 

 

 

1A Socket

2A Socket

1B Socket

2B Socket

Y

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIMM

DIMM

DIMM

DIMM

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

 

 

 

V

U T

S

R

QP

O

N

M

L

 

 

 

 

 

 

 

 

 

 

 

TP01326

 

 

Figure 1. Intel® Server Board SE7221BK1-E Diagram

 

 

A

Chassis Intrusion Header

L

DIMM Sockets (two – from left to

W 34-pin Front Panel Connector

 

 

 

right: DIMM 1B, DIMM 2B)

 

 

B

PCI Slot

M

DIMM Sockets (two – from left to

X Serial ATA (SATA) 2 Connector

 

 

 

right: DIMM 1A, DIMM 2A)

 

 

C PCI-X 100 SLOT

N

Front USB Header (optional)

Y

SATA 1 Connector

D

PCI-X 100 SLOT

O

System Fan Headers (for Intel®

Z

BIOS Control Jumper

 

 

 

Server Board SR1425BK1-E)

 

 

E PCI-Express* or Riser Connector

P

System Fan #4

AA BIOS Select Jumper

 

Slot

 

 

 

 

F

+12v CPU Power

Q

System Fan #3 (optional)

BB

HDD LED Header

G System Fan #1 (optional)

R

Main Power Connector

CC HSBP Header

H Back Panel I/O Connectors

S

Floppy Connector

DD Battery

I System Fan #2 (optional)

T

IDE Connector

EE

Serial B Header

J

CPU Fan (optional)

U

SATA 4 Connector

 

 

K

CPU Socket

V

SATA 3 Connector

 

 

4

Revision 1.3

SE7221BK1-E Technical Product Specification

3.Functional Architecture

This chapter provides a high-level description of the functionality distributed between the architectural blocks of the Intel® Server Board SE7221BK1-E.

3.1Processor Subsystem

The Intel® Server Board SE7221BK1-E supports Intel® Pentium® 4 and Celeron® D processors in the 775-land package, which is a follow on to Pentium® 4 and Celeron® D processors in the 478-pin package, with enhancements to the Intel® NetBurst® microarchitecture. Intel® Pentium® 4 and Celeron® D processors built on 90nm process technology in the 775-land package utilize Flip-Chip Land Grid Array (FC-LGA4) package technology, and plug into a 775-land LGA socket, referred to as the LGA775 socket. Pentium® 4 and Celeron® D processors in the 775-land package, like their predecessors in the 478-pin package, are based on the same Intel® 32-bit micro-architecture and maintain the tradition of compatibility with IA-32 software. Specific models of the Pentium® 4 Processor in the LGA775 package support Intel® EM64T (Extended Memory 64 Technology) for 64bit native mode operation with 64bit operating systems. The Intel® Celeron® Processor currently does not support EM64T.

3.1.1Processor VRD

The Intel® Server Board SE7221BK1-E has a VRD (Voltage Regulator Down) to support one processor. It is compliant with the VRM 10.1 DC-DC Converter Design Guide Line and provides a maximum of 120A, which is capable of supporting the requirements for Intel® Pentium® 4 and Intel® Celeron® D processors.

The board hardware must monitor the processor VTTEN (Output enable for VTT) pin before turning on the VRD. If the VTTEN pin of the processors is not identical the Power ON Logic will not turn on the VRD.

3.1.2Reset Configuration Logic

The BIOS determines the processor stepping, cache size, etc through the CPUID instruction. The requirements are as follows:

Processors run at a fixed speed, but can be programmed by BIOS to operate at a lower or higher speed.

The processor information is read at every system power-on.

Note: The processor speed is the processor power on reset default value. No manual processor speed setting options exist either in the form of a BIOS setup option or jumpers.

3.1.3Processor Module Presence Detection

SE7221BK1-E does not support this function.

3.1.4Processor Support

The Intel® Server Board SE7221BK1-E supports one processor in the LGA775 package. The support circuitry on the server board consists of the following:

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LGA775 processor socket supporting 800MHz FSB Intel® Pentium® 4 processor.

Processor host bus AGTL+ support circuitry.

Table 1. Processor Support Matrix

Processor Family

Package Type

Frequency

Cache Size

Front Side Bus

Pentium® 4

LGA775

3.0

- 3.8 GHz

2MB L2

800MHz

 

 

 

 

 

 

 

Pentium®

4

LGA775

2.8

- 3.8 GHz

1MB L2

800MHz

 

 

 

 

 

 

 

Celeron®

D

LGA775

2.26

- 2.93 GHz

256K L2

533MHz

 

 

 

 

 

 

 

Note: The Pentium® 4 Processor Extreme Edition IS NOT supported for use with the Intel® Server Board SE7221BK1-E.The board is designed to provide up to 120A of processor current. Processors with higher current requirements are not supported. For a complete list of all supported processors, please visit the Intel® Server Board SE7221BK1-E support site located at the following URL:

http://support.intel.com/support/motherboards/server/sb/CS-012690.htm

In addition to the circuitry described above, the processor subsystem contains the following:

Reset configuration logic

Server management registers and sensors

3.1.5Interrupts and APIC

Interrupt generation and notification to the processor is done by the APICs in the ICH6R using messages on the front side bus.

3.2Memory Subsystem

The baseboard supports up to four DIMM slots for a maximum memory capacity of 4 GB. The DIMM organization is x72, which includes eight ECC check bits. The memory interface runs at 400/533MT/s. The memory controller supports memory scrubbing, single-bit error correction and multiple-bit error detection and Intel® x4 SDDC support with x4 DIMMs. Memory can be implemented with either single sided (one row) or double-sided (two row) DIMMs.

3.2.1.1Memory DIMM Support

The board supports un-buffered (not registered) DDR2 400/533-compliant ECC or Non-ECC DIMMs operating at 400/533MT/s. Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported on this board. A list of qualified DIMMs is available at http://support.intel.com/support/motherboards/server/SE7221BK1E. Note that all DIMMs are supported by design, but only fully qualified DIMMs will be supported on the board.

The minimum supported DIMM size is 256 MB. Therefore, the minimum main memory configuration is 1 x 256 MB or 256 MB. The largest size DIMM supported is 2 GB however, the maximum main memory configuration is 4 GB implemented by 4 x 1 GB or 2 x 2 GB DIMMs.

Only un-buffered DDR2 400/533 compliant, ECC x8 and Non-ECC x8 or x16 memory DIMMs are supported

ECC single-bit errors (SBE) will be corrected and multiple-bit error (MBE) will be detected.

Intel® Server Board SE7221BK1-E also supports Intel® x4 SDDC with x4 DIMMs.

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The maximum memory capacity is 4 GB

Note* Although the Intel® Server Board SE7221BK1-E supports a maximum memory capacity of 4 GB, system resources consume roughly 750 MB of physical memory in the maximum memory configuration. As a result, when 4 GB of memory is used, the amount of memory made available to the operating system is significantly lower than 4 GB; roughly 3200 MB. THIS IS ONLY AN ISSUE WHEN 4 GB OF MEMORY IS USED. A memory configuration of less than 4 GB will not be susceptible to this issue. Please refer to Intel® Technical Advisory TA 719-01 on the support web site located at http://support.intel.com/support/motherboards/server/SE7221BK1E.

The minimum memory capacity is 256 MB via 1 x 256 MB DIMM module

3.2.1.2Memory Configuration

The memory interface between the GMCH and the DIMMs is 64-bit (non-ECC) or 72-bit (ECC) wide interface.

There are two banks of DIMMs, labeled 1 and 2. Bank 1 contains DIMM socket locations DIMM_1A and DIMM_2A. Bank 2 contains DIMM socket locations DIMM_1B and DIMM_2B. The sockets associated with each bank or “channel”, are located next to each other and the DIMM socket identifiers are marked on the baseboard silkscreen, near the DIMM socket. Bank 1 is associated with Memory Channel A while Bank 2 is associated with Memory Channel B. When only two DIMM modules are being used, the population order must be DIMM_1A, DIMM_1B to ensure dual channel operating mode.

To reiterate: In order to operate in Dual Channel Dynamic Paging Mode, the following conditions must be met:

2 identical DIMMs are installed, one each in DIMM_1A and DIMM_1B

4 identical DIMMs are installed (one in each socket location)

Installing only 3 DIMMs is not supported. Do not use DIMMs that are not “matched” (same type and speed). Use of identical memory parts is always the preferred method.

See Table 2 and Figure 2 on the following page for reference.

The system design is free to populate or not to populate any rank on either channel, including either degenerate single channel case.

DIMM and memory configurations must adhere to the following:

DDR2 400/533 , un-buffered, DDR2 DIMM modules

DIMM organization: x72 ECC or x 64 Non-ECC

Pin count: 240

DIMM capacity: 256 MB, 512 MB, 1 GB DIMMs

Serial PD: JEDEC Rev 2.0

Voltage options: 1.8 V

Interface: SSTL2

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Table 2. Memory Bank Labels and DIMM Population Order

Location

DIMM Label

Channel

Population Order

J8J1

(DIMM_1A)

A

1

J8J2

(DIMM_2A)

A

3

J9J2

(DIMM_1B)

B

2

J9J1

(DIMM_2B)

B

4

1

3

 

2

4

J8J1

 

J8J2

J9J2

J9J1

DIMM_1A

 

DIMM_2A DIMM_1B

DIMM_2B

Channel A

Channel B

(Bank 2)

(Bank 1)

 

Figure 2. Memory Bank Label Definition

Table 3 summarizes the characteristics of dual and single channel configurations with and without the use of Dynamic Mode.

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Table 3. Characteristics of Dual/Single Channel Configuration with/without Dynamic Mode

Throughput Level

Configuration

Characteristics

Highest

Dual Channel with Dynamic Paging Mode

All DIMMs matched

 

 

 

 

Dual Channel without Dynamic Paging Mode

DIMMs matched from Channel A to Channel B

 

 

DIMMs not matched within channels

 

 

 

 

Single Channel with Dynamic Paging Mode

Single DIMM or DIMMs matched with a

 

 

channel

 

 

 

Lowest

Single Channel without Dynamic Paging

DIMMs not matched

 

Mode

 

 

 

 

4.The Intel® E7221 Chipset

The Intel® Server Board SE7221BK1-E is designed around the Intel® E7221 chipset. The chipset provides an integrated I/O bridge and memory controller, and a flexible I/O subsystem core (PCI Express*). The chipset consists of three primary components:

GMCH: Graphics Memory Control Hub. The GMCH accepts access requests from the host (processor) bus and directs those accesses to memory or to one of the PCI buses. The GMCH monitors the host bus, examining addresses for each request. Accesses may be directed to a memory request queue for subsequent forwarding to the memory subsystem, or to an outbound request queue for subsequent forwarding to one of the PCI buses. The GMCH also accepts inbound requests from the ICH6R. The GMCH is responsible for generating the appropriate controls to control data transfer to and from memory.

The Intel® E7221 GMCH comes with an integrated high performance graphics media accelerator (Intel® GMA 900) and supports one x8 port configuration PCI-E interface. Maximum theoretical peak bandwidth on each x8 PCI Express* interface of 2.5 GB/s in each direction simultaneously, for 5 GB/s per port.

ICH6R: I/O Controller Hub 6R. The ICH6R controller has several components. It provides the interface for a 32-bit/33-MHz PCI bus. The ICH6R can be both a master and a target on that PCI bus. The ICH6R also includes a USB 2.0 controller and an IDE controller. The ICH6R is also responsible for much of the power management functions, with ACPI control registers built in. The ICH6R also provides a number of GPIO pins and has the LPC bus to support low speed legacy I/O.

The GMCH and ICH6R chips provide the pathway between processor and I/O systems. The GMCH is responsible for accepting access requests from the host (processor) bus, and directing all I/O accesses to one of the PCI buses or legacy I/O locations. If the cycle is directed to one of the PCI-E segments, the GMCH communicates with the PCI-E Devices (add-in card, on board devices) through the PCI-E interface. If the cycle is directed to the ICH6R, the cycle is output on the GMCH’s DMI bus. All I/O for the board, including PCI and PC-compatible I/O, is directed through the GMCH and then through the ICH6R provided PCI buses.

PXH: PCI-X Hub The PXH hub is peripheral chips that perform PCI bridging functions between the PCI Express* interface and the PCI bus. The PXH contains two PCI bus

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interfaces that can be independently configured to operate in PCI (33 or 66 MHz), PCI-X Mode1 (66,100,133), for either 32 or 64 bits.

4.1.1GMCH Memory Architecture Overview

The GMCH supports a 72-bit wide memory sub-system that can support a maximum of 4 GB of DDR2 memory using 1 GB DIMMs. This configuration needs external registers for buffering the memory address and control signals. The four chip selects are registered inside the GMCH and need no external registers for chip selects.

The memory interface runs at 400/533MT/s. The memory interface supports a 72-bit wide memory array. It uses seventeen address lines (BA [2:0] and MA [13:0]) and supports 256 Mb, 512 Mb, 1 Gb DRAM densities. The DDR DIMM interface supports memory scrubbing, single-bit error correction, and multiple bit error detection and Intel® x4 SDDC with x4 DIMMs.

4.1.1.1DDR2 Configurations

The DDR2 interface supports up to 4 GB of main memory and supports singleand doubledensity DIMMs. The DDR2 can be any industry-standard DDR2. The following table shows the DDR2 DIMM technology supported.

Table 4. Supported DDR2 modules

DDR2-400 and DDR2-533 Un-buffered

SDRAM Module Matrix

DIMM

DIMM

SDRAM

SDRAM

# SDRAM

# Address bits

Capacity

Organization

Density

Organization

Devices/rows/Banks

rows/Banks/column

 

 

 

 

 

 

256MB

32M x 72

256Mbit

32M x 8

9 /1 / 4

13 / 2 / 10

 

 

 

 

 

 

 

 

512MB

64M x 72

256Mbit

32M x 8

18

/ 2

/ 4

13 / 2 / 10

 

 

 

 

 

 

512MB

64M x 72

512Mbit

64M x 8

9 / 1 / 4

14 / 2 / 10

 

 

 

 

 

 

 

1GB

128M x 72

512Mbit

64M x 8

18

/ 2 / 4

14 / 2 / 10

 

 

 

 

 

 

1GB

128M x 72

1Gbit

128M x 8

9 / 1 / 8

14 / 3 / 10

 

 

 

 

 

 

 

 

4.1.2Graphics Memory Controller Hub (GMCH)

The GMCH is a 1210-ball FC-BGA device and uses the proven components of previous generations like the Intel® Pentium® 4 processor bus interface unit, the hub interface unit, and the DDR2 memory interface unit. In addition, the GMCH incorporates an integrated high performance graphics media accelerator and a PCI Express* interface. The PCI Express* interface allows the GMCH to directly interface with the PCI Express* devices (like PXH/PXHD). The GMCH also increases the main memory interface bandwidth and maximum memory configuration with a 72-bit wide memory interface.

The GMCH integrates the following main functions:

An integrated high performance main memory subsystem.

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A PCI Express* bus which provides an interface to the PCI-Express* devices( Fully compliant to the PCI Express* Base Specification, Rev 1.0a)

A DMI which provides an interface to the ICH6R

Other features provided by the GMCH include the following:

Full support of ECC on the processor bus

Full support of Intel® x4 SDDC on the memory interface with x4 DIMMs

Twelve deep in-order queue, two deep defer queue

Full support of un-buffered DDR2 ECC DIMMs.

Support for 1 GB DDR2 memory modules

Memory scrubbing

4.1.3ICH6R

The ICH6R is a multi-function device, housed in a 609-pin mBGA device, providing a DMI bus, a PCI 32-bit/33 MHz interface, a IDE interface, an integrated Serial ATA Host controller, a USB controller, a PCI-E x4 interface, and a power management controller. Each function within the ICH6R has its own set of configuration registers. Once configured, each appears to the system as a distinct hardware controller sharing the same PCI bus interface.

The primary role of the ICH6R is to provide the gateway to all PC-compatible I/O devices and features. The board uses the following the ICH6R features:

PCI 32-bit/33MHz interface

LPC bus interface

PCI Express* x4

DMI (Direct Media Interface)

IDE interface, with Ultra ATA 100/66/33 capability

Integrated Serial ATA Host controller

Universal Serial Bus (USB) 2.0 interface

PC-compatible timer/counter and DMA controllers

APIC and 82C59 interrupt controller

Power management

System RTC

Supports Smbus 2.0 Specification

General purpose I/O (GPIO)

The following are the descriptions of how each supported feature is used for ICH6R on the board.

4.1.3.1PCI Bus P32-A I/O Subsystem

The ICH6R provides a legacy 32-bit PCI subsystem and acts as the central resource on this PCI interface. P32-A supports the following embedded devices and connectors:

One Intel® ® 82541PI network controller

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One slots capable of supporting full length legacy PCI add-in cards operating at 33 MHz

4.1.3.2PCI Express* X4 Subsystem

The ICH6R supports one x4-lane PCI Express* interface that can also be configured as a single x1 or x4-lane port. The PCI Express* interface allows direct connection with the PXH/PXHD or PCI-E devices. (Fully compliant to the PCI Express* Base Specification, Rev 1.0a)

4.1.3.3PCI Bus Master IDE Interface

The ICH6R acts as a PCI-based Ultra ATA 100/66/33 IDE controller that supports programmed I/O transfers and bus master IDE transfers. The ICH6R supports one IDE channel, supporting two drives each (drives 0 and 1). The baseboard provides a 40-pin (2x20) IDE connector to access the IDE functionality.

The IDE interface supports Ultra ATA 100/66/33 Synchronous DMA Mode transfers on the 40pin connector.

4.1.3.4USB Interface

The ICH6R contains one EHCI USB 2.0 controller and four USB ports. The USB controller moves data between main memory and up to four USB connectors. All ports function identically and with the same bandwidth. The Intel® Server Board SE7221BK1-E implements four ports on the board.

The baseboard provides two external USB ports on the back of the server board. The dual-stack USB connector is located within the standard ATX I/O panel area. The Universal Serial Bus Specification, Revision 1.1, defines the external connectors.

The third/fourth USB port is optional and can be accessed by cabling from an internal 9-pin connector located on the baseboard to an external USB port located either in front or the rear of a given chassis.

4.1.3.5SATA interface

The ICH6R contains four SATA ports. The data transfer rates up to 150Mbyte/s.

4.1.3.6Compatibility Interrupt Controller

The ICH6R provides the functionality of two cascaded 82C59 with 15 interrupts handling. Support processor system bus interrupt.

4.1.3.7APIC

The ICH6R integrates an I/O APIC capability with 24 interrupts.

4.1.3.8Power Management

One of the embedded functions of the ICH6R is a power management controller. This is used to implement ACPI-compliant power management features. The baseboard does support sleep states S0, S1, S4, and S5.

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4.2Super I/O

National Semiconductor* PC87427Super IO device contains all of the necessary circuitry to control two serial ports, one parallel port, floppy disk, PS/2-compatible keyboard and mouse and hardware monitor controller. The baseboard implements the following features:

GPIOs

Two serial ports

Floppy

Keyboard and mouse

Local hardware monitoring

Wake up control

System Health Support

4.2.1Serial Ports

The board provides two serial ports, an external serial port, and an internal serial header. The following sections provide details on the use of the serial ports.

4.2.1.1Serial A

Serial A is a standard DB9 interface located at the rear I/O panel of the server board, below the video connector. Serial A is designated by as “Serial A” on the silkscreen. The reference designator is J8A1.

4.2.1.2Serial B

Serial B is an optional port, accessed through a 9-pin internal header (J1B1). A standard DH-10 to DB9 cable can be used to direct serial B to an external connector on any given chassis. The serial B interface follows the standard RS232 pin-out. The baseboard has a “Serial_B” silkscreen label next to the connector and is located beside the PCI32 5V connector.

4.2.1.3Floppy Disk Controller

The floppy disk controller (FDC) in the Super IO is functionally compatible with floppy disk controllers in the DP8473 and N844077. All FDC functions are integrated into the Super IO including analog data separator and 16-byte FIFO. The baseboard provides a standard 34-pin interface for the floppy disk controller.

4.2.1.4Keyboard and Mouse

Two external PS/2 ports, located on the back of the baseboard, are provided to access the keyboard or mouse functions.

4.2.1.5Fast X-Bus extension for boot flash, memory and I/O.

The fast X-bus Supports I/O and memory read/write operations and 8 bit data bus, 28-bit addressing.

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4.2.1.6Wake-up Control

The Super IO contains functionality that allows various events to control the power-on and power-off the system.

4.2.2BIOS Flash

The board incorporates an Intel® ® 28F320C3 flash memory component. The 28F320C3 is a high-performance 32-megabit memory component that provides 2096K x 16 of BIOS and nonvolatile storage space. The flash device is connected through the X Bus from Super IO.

4.2.3System Health Support

I2C interface to LM96000 sensors

Fan Monitor and Control (FMC)

One PWM-based fan controls

Software or local temperature feedback control Chassis intrusion detection

5.I/O Subsystem

5.1PCI Subsystem

The primary I/O buses for the SE7221BK1-E are 3 independent PCI bus segments (4 independent segments with SE7221BK1LX sku) with PCI, PCI-E and two PCI-X buses. The PCI buses comply with the PCI Local Bus Specification, Rev 2.3. The P32-A bus segment is directed through the ICH6R. The P32-B and P64-C bus segment are independently configured to PXH that is through ICH6R by PCI Express* x 4 interface. The PCI-E x8 bus is directed through the GMCH. The table below lists the characteristics of the three PCI bus segments.

Table 5. PCI Bus Segment Characteristics

PCI Bus Segment

Voltage

Width

Speed

Type

PCI I/O Card Slots

 

 

 

 

 

 

PCI

5V

32 bits

33MHz

P32-A

Slot 1

 

 

 

 

 

 

PCI-X

3.3V

64 bits

66/100MHz

P64-C

Slot 4; Slot 5, (Slot 6 through riser card)

 

 

 

 

 

 

PCI-E (x8)

3.3V

8 lanes

100MHz

 

Slot 6

 

 

 

 

 

 

5.1.1P32-A: 32-bit/33-MHz PCI Subsystem

All 32-bit/33-MHz PCI I/O for the board is directed through the ICH6R. The 32-bit/33-MHz PCI segment created by the ICH6R is known as the P32-A segment. The P32-A segment supports the following embedded devices and connectors:

One 10/100/1000-T Network Interface Controller: Intel® 82541PI Fast Ethernet Controller.

5.1.1.1Device IDs (IDSEL)

Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD [31:16], which acts as a chip select on the PCI bus segment in configuration cycles. This determines a

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unique PCI device ID value for use in configuration cycles. The following table shows the bit to which each IDSEL signal is attached for P32-A devices and the corresponding device description.

 

Table 6. P32-A Configuration IDs

 

 

IDSEL Value

Device

 

 

19

Intel® 82541PI LAN (NIC1)

 

 

18

PCI Slot 1 (32b/33MHz)

 

 

5.1.1.2P32-A Arbitration

P32-A supports two PCI devices: the ICH6R and one PCI bus masters (NIC). All PCI masters must arbitrate for PCI access, using resources supplied by the ICH6R. The host bridge PCI interface (ICH6R) arbitration lines REQx* and GNTx* are a special case in that they are internal to the host bridge. The following table defines the arbitration connections.

 

Table 7. P32-A Arbitration Connections

 

 

 

Baseboard Signals

 

Device

 

 

 

PCI REQ1_N/GNT_N1

 

Intel® 82541PI LAN (NIC1)

 

 

 

PCI REQ0_N/GNT_N0

 

PCI Slot 1 (32bit/33MHz)

 

 

 

5.1.2P32-B 66-MHz PCI-X Subsystem (SE7221BK1LX sku only)

One 32-bit PCI bus segment is directed through the PXH interface A. This PCI segment, P32-B, just has an embedded device, Intel® 82541PI LAN (NIC2) clocked at 66MHz. (SE7221BK1LX sku only)

5.1.2.1Device IDs (IDSEL)

Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD [31:16], which acts as a chip select on the PCI bus segment in configuration cycles. This determines a unique PCI device ID value for use in configuration cycles. The following table shows the bit to which each IDSEL signal is attached for P32-B devices and corresponding device description.

 

Table 8. P32-B Configuration IDs

 

 

IDSEL Value

Device

 

 

19

Intel® 82541PI LAN (NIC2)

 

 

5.1.2.2P32-B Arbitration

P32-B supports one PCI masters. All PCI masters must arbitrate for PCI access using resources supplied by the PXH. The host bridge PCI interface (PXH) arbitration lines REQx*

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and GNTx* are a special case in that they are internal to the host bridge. The following table defines the arbitration connections.

 

Table 9. P32-B Arbitration Connections

 

 

 

Baseboard Signals

 

Device

 

 

 

PCIX REQ_N0/GNT_N0

 

Intel® 82541PI LAN (NIC2)

 

 

 

5.1.3P64-C 66/100-MHz PCI-X Subsystem

One 64-bit PCI-X bus segment is directed through the PXH. This PCI-X segment, P64-C, provides two 3.3V 64-bit PCI-X slots or one 3.3V 64-bit PCI-X riser slot, (SE7221BK1LX sku only) capable of up to 100 MHz operation (with 1 adapter, either slot is capable of 100MHz, only speeds of 66MHz are supported with two adapters populated) and supports full-length PCI and PCI-X adapters.

5.1.3.1Device IDs (IDSEL)

Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD [31:16], which acts as a chip select on the PCI bus segment in configuration cycles. This determines a unique PCI device ID value for use in configuration cycles. The following table shows the bit to which each IDSEL signal is attached for P64-C devices and corresponding device description.

 

 

Table 10. P64-C Configuration IDs

 

 

 

IDSEL Value

Device

 

 

 

 

17

PCI Slot 4

(64bit/66-100MHz)/ PCI Slot 6 (64bit/100MHz) (Riser, SE7221BK1LX sku

only)

 

 

 

18

PCI Slot 5

(64bit/66-100MHz)

 

 

 

5.1.3.2P64-C Arbitration

P64-C supports two PCI masters: two PCI-X slots or one riser slot. All PCI masters must arbitrate for PCI access using resources supplied by the ICH6. The host bridge PCI interface (ICH6) arbitration lines REQx* and GNTx* are a special case in that they are internal to the host bridge. The following table defines the arbitration connections.

 

Table 11. P64-C Arbitration Connections

 

 

Baseboard Signals

Device

 

 

PCIX REQ_N0/GNT_N0

PCI Slot 4 (64bit/66M) / PCI Slot 6 (64bit/100M) (Riser, SE7221BK1LX sku

only)

 

 

PCIX REQ_N1/GNT_N1

PCI Slot 5(64bit/66M)

 

 

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5.1.4PCI-E x8

In this board, Lanes 0~7 are connected to a x8 PCI-E connector directly. It can support x1, x4, x 8 PCI-E add-in cards.

 

Table 12. PCI-E x 8 Connections

 

 

 

Lane

 

Device

 

 

 

Lane 0~7

 

Slot 6 (PCI Express* x 8)

 

 

 

5.2Video Controller

The Intel® E7221 GMCH includes an integrated graphics engine that supports standard SVGA drivers with analog display capabilities. 8 MB of memory is pre-allocated in the main memory to support the internal graphical device when less than 4 GB of physical memory is installed.

However, when the maximum of 4 GB of memory is installed, onboard system resources such as video consume a considerable amount of memory, leaving just above 3 GB of available memory for the operating system. Details of this issue have been communicated via the

Technical Advisory TA_719-01 which can be found at: http://support.intel.com/support/motherboards/server/SE7221BK1-E.

The baseboard provides a standard 15-pin VGA connector at the rear of the system, in the standard ATX I/O opening area. The video controller is disabled by default in BIOS Setup when an off-board video adapter is detected in either the PCI-E or PCI slots.

5.3Network Interface Controller (NIC)

The Intel® Server Board SE7221BK1-E supports two 10Base-T/100Base/1000Base-T (82541PI controller) network interfaces. One is through ICH6R directly, and another one is through PXH (SE7221BK1LX sku only).

The Intel® 82541PI Gigabit Ethernet is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the Intel® 82541PI allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs. The Intel® 82541PI integrates fourth generation gigabit MAC design with fully integrated, physical layer circuitry to provide a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASE_TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab). The controller is capable of transmitting and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps. In addition to managing MAC and PHY layer functions, the controller provides a 32-bit wide direct Peripheral Component Interconnect (PCI) 2.3 compliant interface capable of operating at 33 or 66MHz.

5.3.1NIC Connector and Status LEDs

The NICs drive two LEDs located on each network interface connector.

For the NIC 1 connector, the green LED indicates network connection when on, and Transmit/Receive activity when blinking. The yellow LED indicates 1000-Mbps operation when lit, the green LED indicates 100-Mbps operation when lit and 10-Mbps when off.

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SE7221BK1-E Technical Product Specification

For the NIC 2 connector (SE7221BK1LX sku only), the yellow LED indicates network connection when on, and Transmit/Receive activity when blinking. The orange LED indicates 1000-Mbps operation when lit, the green LED indicates 100-Mbps operation when lit and 10Mbps when off.

5.4Interrupt Routing

The board interrupt architecture accommodates both PC-compatible PIC mode and APIC mode interrupts through use of the integrated I/O APICs in the ICH6.

5.4.1Legacy Interrupt Routing

For PC-compatible mode, the ICH6 provides two 82C59-compatible interrupt controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary interrupt controller (standard PC configuration). A single interrupt signal is presented to the processors, to which only one processor will respond for servicing. The ICH6R contains configuration registers that define which interrupt source logically maps to I/O APIC INTx pins.

The ICH6 handles both PCI and IRQ interrupts. The ICH6R translates these to the APIC bus. The numbers in the table below indicate the ICH6R PCI interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD, INTE, INTF, INTG, INTH for PCI bus and PXIRQ0, PXIRQ1, PXIRQ2, PXIRQ3 for PCI-X bus) is connected. The ICH6R I/O APIC exists on the I/O APIC bus with the processors.

Table 13. PCI AND PCI-X Interrupt Routing/Sharing

Interrupt

 

 

INT A

INT B

INT C

INT D

 

 

 

 

 

 

Intel® 82541PI

 

PIRQC

 

PIRQE

 

 

 

 

 

 

PCI Slot 1

(PCI 32b/33M)

PIRQF

PIRQG

PIRQH

 

 

 

 

 

PXIRQ2

 

PCI Slot 4

(64b/66M)/

PCI Slot 6

PXIRQ0

PXIRQ1

PXIRQ3

(64bit/100MHz) (Riser,

 

 

 

 

SE7221BK1LX sku

only)

 

 

 

 

PCI Slot 5

(64b/66M

 

PXIRQ5

PXIRQ6

PXIRQ7

PXIRQ4

 

 

 

 

 

 

 

5.4.2APIC Interrupt Routing

For APIC mode, the baseboard interrupt architecture incorporates three Intel® I/O APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel® I/O APICs monitor each interrupt on each PCI device; including PCI slots in addition to the ISA compatibility interrupts IRQ (0-15).

When an interrupt occurs, a message corresponding to the interrupt is sent across a three-wire serial interface to the local APICs. The APIC bus minimizes interrupt latency time for compatibility interrupt sources. The I/O APICs can also supply greater than 16 interrupt levels to the processor(s). This APIC bus consists of an APIC clock and two bidirectional data lines.

5.4.2.1Legacy Interrupt Sources

The table below recommends the logical interrupt mapping of interrupt sources on the board. The actual interrupt map is defined using configuration registers in the ICH6.

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