Intel® Server Board S5500WB
Revision 1.9
February, 2012
Enterprise Platforms and Services Division
Technical Product Specification
Intel order number E53971-008
Revision History Intel® Server Board S5500WB TPS
ii
Date
Revision
Number
Modifications
03/30/2009
1.0
Initial Release.
04/29/2009
1.1
Formatting corrections.
05/20/2009
1.2
Updated heatsink installation steps.
Corrected processor fault table.
Added jumper location figure.
08/03/2009
1.3
Updated memory support.
Corrected PCIe slot speed.
Removed S4 support.
01/12/2010
1.4
Corrected USB header pin-out.
03/09/2010
1.5
Updated Power Supply communication bus requirements.
Increased maximum supported memory to 128GB.
Added support for 5600 series processors.
04/21/2010
1.6
Updated12V SKU board picture (Figure 1).
07/18/2010
1.7
Removed Rapid Boot Toolkit section.
Updated NIC LEDs.
Updated video resolution.
03/21/2010
1.8
Updated typo in board feature set.
02/16/2012
1.9
Updated typo in board feature set.
Revision History
Revision 1.9
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Intel® Server Board S5500WB TPS Disclaimers
iii
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express
or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel
assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular
purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining
applications. Intel may make changes to specifications and product descriptions at any time,
without notice.
Designers must not rely on the absence or characteristics of any features or instructions
marked "reserved" or "undefined." Intel reserves these for future definition and shall have no
responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
This document contains information on products in the design phase of development. Do not
finalize a design with this information. Revised information will be published when the product is
available. Verify with your local sales office that you have the latest datasheet before finalizing
a design.
This document may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available
on request.
This document and the software described in it are furnished under license and may only be
used or copied in accordance with the terms of the license. The information in this manual is
furnished for informational use only, is subject to change without notice, and should not be
construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or
liability for any errors or inaccuracies that may appear in this document or any software that
may be provided in association with this document.
Except as permitted by such license, no part of this document may be reproduced, stored in a
retrieval system, or transmitted in any form or by any means without the express written
consent of Intel Corporation.
Intel and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2011
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Table of Contents Intel® Server Board S5500WB TPS
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Table of Contents
1. Introduction ........................................................................................................................ 1
1.1 Section Outline ....................................................................................................... 1
1.2 Server Board Use Disclaimer ................................................................................. 1
2. Server Board Overview ...................................................................................................... 2
2.1 Intel® Server Board S5500WB Server Board .......................................................... 4
2.2 Server Board Connector and Component Layout ................................................... 6
2.2.1 Board Rear Connector Placement .......................................................................... 8
2.2.2 Server Board Mechanical Drawings ....................................................................... 8
3. Functional Architecture ................................................................................................... 13
3.1 High Level Product Features ................................................................................ 13
3.2 Functional Block Diagram .................................................................................... 14
3.3 Processor Subsystem .......................................................................................... 15
3.3.1 Processor Support ............................................................................................... 15
3.3.2 Processor Population Rules ................................................................................. 15
3.3.3 Installing or Replacing the Processor ................................................................... 17
3.3.4 Intel® QuickPath Interconnect (Intel® QPI) ............................................................ 20
3.4 Intel® QuickPath Memory Controller ..................................................................... 21
3.4.1 Supported Memory ............................................................................................... 21
3.4.2 Memory Subsystem Nomenclature....................................................................... 21
3.4.3 ECC Support ........................................................................................................ 22
3.4.4 Memory Reservation for Memory-mapped Functions ........................................... 22
3.4.5 High-Memory Reclaim .......................................................................................... 22
3.4.6 Memory Population Rules .................................................................................... 23
3.4.7 Installing and Removing Memory ......................................................................... 23
3.4.8 Channel-Independent Mode ................................................................................. 25
3.4.9 Memory RAS ........................................................................................................ 25
3.4.10 Memory Error LED ............................................................................................... 26
3.5 Intel® 5500 Chipset IOH ........................................................................................ 26
3.5.1 IOH24D PCI Express* .......................................................................................... 26
3.6 Management Engine ............................................................................................ 27
3.7 Intel® 82801Jx I/O Controller Hub (ICH10R) ......................................................... 28
3.7.1 Serial ATA Support .............................................................................................. 28
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3.7.2 USB 2.0 Support .................................................................................................. 29
3.8 Network Interface Controller (NIC) ....................................................................... 30
3.8.1 MAC Address Definition ....................................................................................... 31
3.8.2 LAN Connector Ordering ...................................................................................... 31
3.9 Integrated Baseboard Management Controller ..................................................... 31
3.9.1 Integrated BMC Embedded LAN Channel ............................................................ 33
3.9.2 RMM3 Advanced Management Board: ................................................................. 34
3.10 Serial Ports .......................................................................................................... 34
3.11 Wake-up Control .................................................................................................. 34
3.12 Integrated Video Support ..................................................................................... 34
3.12.1 Video Modes ........................................................................................................ 35
3.12.2 Dual Video ........................................................................................................... 35
3.12.3 Front Panel Video ................................................................................................ 35
3.13 I/O Slots ............................................................................................................... 36
3.13.1 X16 Riser Slot Definition ...................................................................................... 36
3.13.2 PE WIDTH Strapping ........................................................................................... 36
3.13.3 Slot 1 PCI Express* x8 Connector ........................................................................ 36
3.13.4 I/O Module Connector .......................................................................................... 37
4. Intel® I/O Expansion Modules .......................................................................................... 38
5. Platform Management Features ...................................................................................... 40
5.1 BIOS Feature Overview ....................................................................................... 40
5.1.1 EFI Support .......................................................................................................... 40
5.1.2 BIOS Recovery .................................................................................................... 40
5.2 BMC Feature Overview ........................................................................................ 40
5.2.1 Server Engines Pilot II Controller ......................................................................... 40
5.2.2 BMC Firmware ..................................................................................................... 41
5.2.3 BMC Basic Features ............................................................................................ 41
5.2.4 BMC Advanced Features ..................................................................................... 42
5.3 Management Engine (ME) ................................................................................... 42
5.3.1 Overview .............................................................................................................. 42
5.3.2 BMC - Management Engine Interaction ................................................................ 43
5.4 Data Center Manageability Interface .................................................................... 43
5.5 Other Platform Management ................................................................................ 43
5.5.1 Wake On LAN (WOL) .......................................................................................... 43
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5.5.2 PCI Express* Power management ....................................................................... 43
5.5.3 PMBus* ................................................................................................................ 43
5.6 I2C\SMBUS Architecture Block ............................................................................ 44
5.6.1 I2C\SMBUS Device Addresse .............................................................................. 44
6. Configuration Jumpers .................................................................................................... 46
6.1.1 Force IBMC Update (J1B5) .................................................................................. 47
6.1.2 Password Clear (J1C2) ........................................................................................ 48
6.1.3 BIOS Recovery Mode (J1C3) ............................................................................... 49
6.1.4 Reset BIOS Configuration (J1B4) ........................................................................ 50
6.1.5 Video Master (J6A3) ............................................................................................ 50
6.1.6 ME Firmware Force Update (J7A2) ...................................................................... 51
6.1.7 Serial Interface (J6A2) ......................................................................................... 51
7. Connector/Header Locations and Pin-out ...................................................................... 52
7.1 Power Connectors ................................................................................................ 52
7.2 System Management Headers ............................................................................. 54
7.2.1 Intel® Remote Management Module 3 (Intel® RMM3) Connector .......................... 54
7.2.2 BMC Power Cycle Header (12V Only) .................................................................. 54
7.2.3 Hard Drive Activity (Input) LED Header ................................................................ 55
7.2.4 IPMB Header........................................................................................................ 55
7.2.5 SGPIO Header ..................................................................................................... 55
7.3 SSI Control Panel Connector ............................................................................... 55
7.3.1 Power Button ....................................................................................................... 56
7.3.2 Reset Button ........................................................................................................ 56
7.3.3 NMI Button ................................................................ ........................................... 56
7.3.4 Chassis Identify Button ........................................................................................ 56
7.3.5 Power LED ........................................................................................................... 57
7.3.6 System Status LED .............................................................................................. 57
7.3.7 Chassis ID LED .................................................................................................... 59
7.4 I/O Connectors ..................................................................................................... 59
7.4.1 PCI Express* Connectors ..................................................................................... 59
7.4.2 VGA Connectors .................................................................................................. 61
7.4.3 NIC Connectors.................................................................................................... 62
7.4.4 SATA Connectors ................................................................................................ 64
7.4.5 Intel® I/O Expansion Module Connector ............................................................... 64
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7.4.6 Serial Port Connectors ......................................................................................... 66
7.4.7 USB Connectors .................................................................................................. 66
7.5 Fan Headers ........................................................................................................ 67
8. Intel® Light-Guided Diagnostics ...................................................................................... 68
8.1 5-V Standby LED ................................................................................................. 68
8.2 Fan Fault LEDs .................................................................................................... 69
8.3 System Status LED .............................................................................................. 69
8.4 DIMM Fault LEDs ................................................................................................. 73
8.5 POST Code Diagnostic LEDs .............................................................................. 74
8.6 Front Panel Support ............................................................................................. 75
9. Design and Environmental Specifications ..................................................................... 76
9.1 Fan Speed Control Thermal Management ........................................................... 76
9.2 Thermal Sensors .................................................................................................. 78
9.2.1 Processor PECI Temperature Sensor .................................................................. 78
9.2.2 Memory Temperature Sensor .............................................................................. 79
9.2.3 Board Temperature Sensor .................................................................................. 79
9.2.4 Thermals Sensor Placement ................................................................................ 79
9.3 Heatsinks ............................................................................................................. 80
9.3.1 Unified Retention System Support ....................................................................... 81
9.4 Errors ................................................................................................................... 82
9.4.1 PROCHOT# ......................................................................................................... 82
9.4.2 THERMTRIP# ...................................................................................................... 82
9.4.3 CATERR# ............................................................................................................ 82
10. Power Subsystem............................................................................................................. 83
10.1 Server Board Power Distribution .......................................................................... 83
10.2 Power Supply Compatibility .................................................................................. 83
10.3 Power Sequencing and Reset Distribution ........................................................... 84
11. Regulatory and Certification Information ....................................................................... 85
11.1 Product Regulation Requirements ........................................................................ 85
11.1.1 Product Safety Compliance .................................................................................. 85
11.1.2 Product EMC Compliance – Class A Compliance ................................................ 85
11.1.3 Certifications / Registrations / Declarations .......................................................... 85
11.2 Product Regulatory Compliance Markings ........................................................... 86
11.3 Electromagnetic Compatibility Notices ................................................................. 86
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11.3.1 FCC Verification Statement (USA) ....................................................................... 86
11.3.2 ICES-003 (Canada) .............................................................................................. 87
11.3.3 Europe (CE Declaration of Conformity) ................................................................ 88
11.3.4 BSMI (Taiwan) ..................................................................................................... 88
11.3.5 KCC (Korea) ........................................................................................................ 88
Appendix A: POST Code LED Decoder ................................................................................. 89
Appendix B: Video POST Code Errors .................................................................................. 96
Glossary ................................................................................................................................ 100
Reference Documents .......................................................................................................... 103
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List of Figures
Figure 1. Intel® Server Board S5500WB 12V .............................................................................. 4
Figure 2. Intel Server Board S5500WB SSI ................................................................................ 5
Figure 3. Intel® Server Board S5500WB Components (both SKUs are shown) ........................... 6
Figure 4. Rear Panel Connector Placement: ............................................................................... 8
Figure 5. Baseboard and Mounting holes .................................................................................... 9
Figure 6. Connector Locations .................................................................................................. 10
Figure 7. Primary Side Height Restrictions ................................................................................ 11
Figure 8. Secondary Side Height Restrictions ........................................................................... 12
Figure 9. Intel® Server Board S5500WB Functional Block Diagram .......................................... 14
Figure 10. Lifting the load lever of ILM cover ............................................................................ 17
Figure 11. Removing the socket cover ...................................................................................... 17
Figure 12. Installing processor .................................................................................................. 18
Figure 13. Package Installation/Remove Feature ..................................................................... 19
Figure 14. Installing/Removing Heatsink ................................................................................... 20
Figure 15. Intel® QPI Link.......................................................................................................... 20
Figure 16. Memory Channel Population .................................................................................... 23
Figure 17. Installing Memory ..................................................................................................... 24
Figure 18. Mirroring Memory Configuration ............................................................................... 26
Figure 19. Integrated BMC Hardware ....................................................................................... 33
Figure 20. S5500WB I2C\SMBUS Block Diagram .................................................................... 44
Figure 21: Jumper Blocks (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2, J7A2) ................................. 46
Figure 22: 5-V Standby Status LED Location ............................................................................ 68
Figure 23. Fan Fault LED Locations .......................................................................................... 69
Figure 24. System Status LED Location ................................................................................... 70
Figure 25. DIMM Fault LEDs Locations ..................................................................................... 73
Figure 26. Rear Panel Diagnostic LEDs .................................................................................... 74
Figure 27: Thermal Zones ......................................................................................................... 76
Figure 28: Location of Fan Connectors ..................................................................................... 77
Figure 29. Fans and Sensors Block Diagram ............................................................................ 78
Figure 30: Temp Sensor Location ............................................................................................. 80
Figure 31. Unified Retention System and Unified Backplate Assembly ..................................... 81
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Figure 32. Power Distribution Diagram ..................................................................................... 83
Figure 33. Diagnostic LED Placement Diagram ........................................................................ 89
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Intel® Server Board S5500WB TPS List of Tables
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List of Tables
Table 1. Intel® Server Board S5500WB Feature Set ................................................................... 2
Table 2. Intel® Server Board S5500WB System Interconnects ................................................... 7
Table 3. Intel® Server Board S5500WB Features ..................................................................... 13
Table 4. Mixed Processor Configurations .................................................................................. 16
Table 5. DIMM Nomenclature ................................................................................................ ... 22
Table 6. IOH24D PCI Express* Bus Segments ......................................................................... 27
Table 7. NIC 1 Status LED ........................................................................................................ 30
Table 8. RMM3 Features .......................................................................................................... 34
Table 9. Supported Video Modes .............................................................................................. 35
Table 10. Dual Video Options ................................................................ ................................... 35
Table 11. PEWIDTH Strapping Bits .......................................................................................... 36
Table 12. Intel® I/O Expansion Module Bus PEWIDTH Bits ...................................................... 37
Table 13. Intel® I/O Expansion Module Product Codes ............................................................. 38
Table 14: BMC Basic Features ................................................................................................. 41
Table 15. Advanced Features ................................................................................................... 42
Table 16. I2C/SMBus Device Address Assignment ................................................................... 44
Table 17: Server Board Jumpers (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2) ................................ 47
Table 18. Force IBMC Update Jumper ...................................................................................... 47
Table 19. Password Clear Jumper ................................................................ ............................ 48
Table 20. BIOS Recovery Mode Jumper ................................................................................... 49
Table 21. Reset BIOS Jumper .................................................................................................. 50
Table 22. Video Master Jumper ................................................................................................ 50
Table 23. SSI SKU 24-pin 2x12 Connector (J9B3) .................................................................... 52
Table 24. CPU 12V Power 2x4 Connector (J5K1) ..................................................................... 52
Table 25. SSI Power Control (J9D1) ......................................................................................... 52
Table 26. 12-V only 2x4 Connector (replaces EPSD12V 2x12 connector) (J9D2) .................... 53
Table 27. 12-V Only Power Control (replaces the 1x5 power control) (J9D1) (FOXCONN
ELECTRONICS INC HF1107V-P1 or TYCO ELECTRONICS CORPORATION 5-104809-6)53
Table 28. Peripheral Power (Only for 12-V only SKU) (J8K2) (iPN: C22293-003 MOLEX
CONNECTOR CORPORATION 43045-0627 ) ................................................................... 53
Table 29. Intel® RMM3 Connector Pin-out (J5B1) ..................................................................... 54
Table 30. BMC Power Cycle Header (J1D2) ............................................................................. 54
Table 31. IPMB Header 4-pin (J1B2) ........................................................................................ 55
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Table 32. SGPIO Header (J1B1) .............................................................................................. 55
Table 33. Front Panel SSI Standard 24-pin Connector Pin-out (J1E2) ...................................... 55
Table 34. Power LED Indicator States ...................................................................................... 57
Table 35. System Status LED ................................................................................................... 58
Table 36. Chassis ID LED Indicator States ............................................................................... 59
Table 37. Slot 6 Riser Connector (J4B1) ................................................................................... 59
Table 38. Slot 1 PCI Express* x8 Connector (J1B3) ................................................................. 60
Table 39. VGA External Video Connector (J6A1) ...................................................................... 61
Table 40. VGA Internal Video Connector (J1D1) ...................................................................... 62
Table 41. RJ-45 10/100/1000 NIC Connector Pin-out (J8A2, J9A1) .......................................... 63
Table 42. SATA Connectors ..................................................................................................... 64
Table 43. 50-pin Intel® I/O Expansion Module Connector Pin-out (J2B1, J3B1) ........................ 65
Table 44. External RJ-45 Serial Port A (COM1) (J7A1)............................................................. 66
Table 45. Internal 9-pin Serial B (COM2) (J1A2) ....................................................................... 66
Table 46. External USB Connector (J8A1, J9A1)) ..................................................................... 66
Table 47. Internal USB Connector (J1C1 and J9A2) ................................................................. 66
Table 48. Low-Profile Internal USB Connector (J1E3) .............................................................. 67
Table 49. SSI 4-pin Fan Connector (J2K2, J2K3, J3K1, J7K1, J8K4, J8K5) ............................. 67
Table 50. 8-pin Fan Connector (J2K1 & J8K3) (MOLEX CONNECTOR CORPORATION 53398-
0890 or 53398-0871 ) ......................................................................................................... 67
Table 51. System Status LED ................................................................................................... 71
Table 52. Standard Front Panel Functionality ................................................................ ........... 75
Table 53. Fan Connector Location & Detail ............................................................................... 77
Table 54. Fan Connector Location & Detail ............................................................................... 78
Table 55: Product Regulatory Compliance Markings ................................................................ 86
Table 56. POST Progress Code LED Example ......................................................................... 90
Table 57. Diagnostic LED POST Code Decoder ....................................................................... 91
Table 58. POST Error Messages and Handling ........................................................................ 96
Table 59: Glossary .................................................................................................................. 100
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Intel® Server Board S5500WB TPS Introduction
1
1. Introduction
The Intel® Server Board S5500WB is a dual socket server using the Intel® Xeon® Processor
5500 series and 5600 series processors, in combination with the IOH and ICH10R to provide a
balanced feature set between technology leadership and cost.
1.1 Section Outline
This document is divided into the following chapters:
Section 1 – Introduction
Section 2 – Server Board Overview
Section 3 – Functional Architecture
Section 4 – I/O Expansion Modules
Section 5 – Platform Management Features
Section 6 – Configuration Jumpers
Section 7 – Connector and Header Location and Pin-out
Section 8 – Intel® Light-Guided Diagnostics
Section 9 – Design and Environmental Specifications
Section 10 – Power Subsystem
Section 11 - Regulatory and Certification Information
Appendix A – POST Code LED Decoder
Appendix B – Video POST Code Errors
Glossary
Reference Documents
1.2 Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel ensures through its own chassis
development and testing that when Intel server building blocks are used together, the fully
integrated system will meet the intended thermal requirements of these components. It is the
responsibility of the system integrator who chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of air
flow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
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Server Board Overview Intel® Server Board S5500WB TPS
Feature
Description
Processors
Support for one or two Intel® Xeon® Processor 5500 and 5600 series processors in
FC-LGA 1366 Socket B package with up to 95 W Thermal Design Power (TDP)
Supports future processor compatibility guidelines
4.8 GT/s, 5.86 GT/s, and 6.4 GT/s Intel® QuickPath Interconnect (Intel® QPI)
Meets EVRD11.1
Memory
Support for 800/1066/1333 MT/s ECC registered (RDIMM) or unbuffered (UDIMM)
DDR3 memory.
8 DIMMs total across six memory channels (three channels per processor in a
2:1:1 configuration)
VRD optimized to support QR x8 DIMMs
No support for QR x4 DIMMs
Chipset
Intel® 5500 Chipset IOH
Intel® 82801Jx I/O Controller Hub (ICH10R)
I/O Control
External connections:
DB-15 Video connectors
RJ-45 serial Port A connector
RJ-45 connector for 10/100/1000 LAN
One 2x USB 2.0 connectors
One RJ-45 over USB for 10/100/1000 LAN
Internal connections:
Two USB 2x5 pin header, supporting four USB 2.0 ports
One low-profile USB 2x5 pin
One DH-10 Serial Port B header
One 2x8 pin VGA header with presence detection to switch from rear I/O video
connector
Six SATA II connectors
Intel® I/O Expansion Module Dual Connectors
One RMM3 connector to support optional Intel® Remote Management Module 3
SATA SW RAID 5 Activation Key Connector
One SSI-EEB compliant front panel header
Power Connections
SSI SKU
One SSI-EEB compliant 24-pin main power connector (SSI only SKU)
One SSI compliant 8-pin CPU power connector
One SSI compliant 5-pin power control Connector (SSI only SKU)
12-V Only SKU
One 8-pin power connector
One 6-pin Aux power connector for 3.3 V and 5 V
One 7-pin power control connector
2. Server Board Overview
The Intel® Server Board S5500WB is a monolithic printed circuit board (PCB) with features
designed to support the Internet Portal Data Center markets. The following table provides a
high-level product feature list.
Table 1. Intel® Server Board S5500WB Feature Set
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Feature
Description
System Fan Support
Two 8-pin fan headers for double rotor memory fans and six 4-pin fan headers
supporting two processor zones and two memory zones in a redundant fashion
Add-in Adapter Support
One riser slot supporting both full-height and low-profile 1U and 2U MD2 PCI
Express* x16 riser cards PCI gen2 Express* x8 w/ x16 connector.
One riser slot supporting PCI Express* x8 riser cards PCI gen2 Express* x4 w/ x8
connector.
Two Intel® I/O Expansion Module card connectors supporting double- and singlewide I/O modules.
Video
Onboard ServerEngines* LLC Pilot II Controller
Matrox* G200 2D Video Graphics controller
Uses 8 MB of the BMC 32 MB DDR2 Memory
Hard Drive
Support for six ICH10R SATA II ports
Optional support for SW RAID 5 with activation key
LAN
Two 10/100/1000 ports provided by Intel® 82576 PHYs with Intel® I/O Acceleration
Technology 2 support
Server Management
Onboard ServerEngines* LLC Pilot II Controller.
Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant
Basic
BMC Controller: ARM 926E-S microcontroller
Super IO: Serial Port logic, legacy interfaces, LPC interface, Port80
Hardware Monitoring: Fan speed control and voltage monitoring
Advanced
Video and USB compression and redirection
NC-SI port, a high-speed sideband management interface
Integrated Super I/O on LPC interface
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Server Board Overview Intel® Server Board S5500WB TPS
2.1 Intel
®
Server Board S5500WB Server Board
The Intel® Server Board S5500WB has two board SKUs, such as SSI-compliant and 12-V-onlySKU. The board layouts of the SKUs are shown.
Figure 1. Intel® Server Board S5500WB 12V
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5
Figure 2. Intel Server Board S5500WB SSI
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2.2 Server Board Connector and Component Layout
Figure 3. Intel® Server Board S5500WB Components (both SKUs are shown)
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Description
Description
A
Dual Intel® I/O Expansion Module
Connectors
V
Processor Socket 1
B
PCI Express x16 Gen2
W
8 Pin CPU Connector
C
Remote Management Module 3
X
Processor Socket 2
D
POST Code LEDs
Y
4-pin Fan Connector (CPU2)
E
External I/O
Z
4-pin Fan Connector (CPU2A)
F
USB Connector
AA
4-pin Fan Connector (MEM2)
G
Battery
BB
8-pin Fan Connector (MEM2R)
H
SATA Connectors
CC
DIMM Slot D2
I
24 Pin Connector (SSI only)
DD
DIMM Slot D1
J
8 Pin Connector (12V only)
EE
DIMM Slot E1
K
Aux Power (5-pin or 7-pin)
FF
DIMM Slot F1
L
RAID Key
GG
Front Panel Connector
M
DIMM Slot C1
HH
HDD LED Header
N
DIMM Slot B1
II
Low-Profile USB Connector
O
DIMM Slot A1
JJ
Internal VGA Connector
P
DIMM Slot A2
KK
BMC Power Cycle Header (12V Only)
Q
8-pin Fan Connector (MEM1R)
LL
USB Connector
R
4-pin Fan Connector (MEM1)
MM
Slot 1 PCI Express x8 Gen2
S
4-pin Fan Connector (CPU1A)
NN
SGPIO Connector
T
4-pin Fan Connector (CPU1)
OO
IMPB Connector
U
HDD Power Connector (12V only)
PP
Serial Port B
Table 2. Intel® Server Board S5500WB System Interconnects
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Description
Description
A
ID LED
E
RJ-45 GbE LAN connector
B
Status LED
F
RJ-45 Serial port connector
C
RJ-45 GbE/Dual USB connector
G
DB15 Video
D
Dual USB connector
H
Diagnostic LEDs
2.2.1 Board Rear Connector Placement
The Intel® Server Board S5500WB has the following board rear connector placement:
Figure 4. Rear Panel Connector Placement:
2.2.2 Server Board Mechanical Drawings
The following figures are mechanical drawings for the Intel® Server Board S5500WB.
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Figure 5. Baseboard and Mounting holes
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Figure 6. Connector Locations
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Figure 7. Primary Side Height Restrictions
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Figure 8. Secondary Side Height Restrictions
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Board
S5500WB 12V
S5500WB SSI
Form Factor
EATX 12‖ x 13‖
EATX 12‖ x 13‖
CPU Socket
B
B
Chipset
Intel® 5500 Chipset IOH
Intel® 82801Jx I/O Controller Hub (ICH10R)
Intel® 5500 Chipset IOH
Intel® 82801Jx I/O Controller Hub
(ICH10R)
Memory
8 RDIMMs or 8 UDIMMs DDR3
8 RDIMMs or 8 UDIMMs DDR3
Slots
1 PCI Express* x8 w/ x16 connector
1 PCI Express* x4 w/ x8 connector
1 PCI Express* x8 w/ x16 connector
1 PCI Express* x4 w/ x8 connector
Ethernet
Dual GbE, Intel® 82576 Gigabit Ethernet
Dual GbE, Intel® 82576 Gigabit Ethernet
Storage
Six SATA II ports (3Gb/s)
Six SATA II ports (3Gb/s)
SAS
One (1) 4-port SAS module on IOM
connector (optional)
One (1) 4-port SAS module on IOM
connector (optional)
I/O Module
Yes, single- and double-wide
Yes, single- and double-wide
SW RAID
LSI SW RAID 0,1,5,10
LSI SW RAID 0,1,5,10
Processor Support
95 W, optimized for 80 W
95 W, optimized for 80 W
Video
Integrated in BMC
Integrated in BMC
ISM
iBMC w/ IPMI 2.0 support
iBMC w/ IPMI 2.0 support
Chassis*
Reference
Reference
Power Supply
12 V and 5 VS/B PMBus*
12 V, 5 V, 3.3 V, 5 VSB, PMBus*
3. Functional Architecture
The Intel® Server Board S5500WB is a purpose build, power-optimized server used in a 1U
rack. Memory and processor socket placement is made to minimize the amount of fan power
required to cool these components. Voltage Regulators (VRDs) are optimized for a particular
range of memory and CPU power that suits the target Internet Portal Datacenter (IPDC)
segment of the market. The VRDs are also designed to be highly power-efficient, balancing the
needs of being small in size and also cost-effective. There are two SKUs: a 12-V only SKU and
an SSI-compliant SKU.
3.1 High Level Product Features
Table 3. Intel® Server Board S5500WB Features
Note:
*Referenced Chassis: Chenbro RM13204 Chassis and Intel® Server System SR1690WB.
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3.2 Functional Block Diagram
Figure 9. Intel® Server Board S5500WB Functional Block Diagram
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3.3 Processor Subsystem
The Intel
®
5500 series and the next generation Intel
following key technologies:
Intel
®
Integrated Memory Controller
Point-to-point link interface based on the Intel
which was formerly known as the Common System Interface (CSI).
The Intel
®
5500 series processor is a multi-core processor based on the 45 nm process
technology. Processor features vary by SKU and include up to two Intel
capable of up to 6.4 GT/s, up to 8 MB of shared cache, and an integrated memory controller.
The Intel
®
5600 series processor is the next generation of multi-core processors based on the
32 nm process technology. Processor features vary by SKU and include up to 6 cores and up to
12 MB of shared cache.
3.3.1 Processor Support
The Intel® Server Board S5500WB supports the following processors:
®
5600 series processors support the
®
QuickPath Interconnect (Intel® QPI),
®
QPI point-to-point links
One or two Intel® 5500 series or 5600 series processor(s) in FC-LGA 1366 socket B
package with 4.8 GT/s, 5.86 GT/s, or 6.4 GT/s Intel® QPI.
Up to 95 W Thermal Design Power (TDP).
Supports Low Voltage (LV) processors.
3.3.2 Processor Population Rules
For optimum performance, when two processors are installed, both must be the identical
revision and have the same core voltage and Intel
is installed, it must be in the socket labeled CPU1. The other socket must be empty. You must
populate processors in sequential order. Therefore, you must populate processor socket 1
(CPU1) before processor socket 2 (CPU2).
When a single processor is installed, no terminator is required in the second processor socket.
3.3.2.1 Mixed Processor Configurations
The following table describes mixed processor conditions and recommended actions for all
Intel® server boards and systems that use the Intel® 5500 Chipset. The errors fall into one of the
following two categories:
Fatal: If the system can boot, it goes directly to the error manager, regardless of
whether the Post Error Pause setup option is enabled or disabled.
®
QPI/core speed. When only one processor
Major: If the Post Error Pause setup option is enabled, the system goes directly to
the error manager. Otherwise, the system continues to boot and no prompt is given
for the error. The error is logged to the error manager.
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Error
Severity
System Action
Processor family not
identical
Fatal
The BIOS detects the error condition and responds as follows:
Logs the error into the system event log (SEL).
Alerts the Integrated BMC of the configuration error with an
IPMI command.
Does not disable the processor.
Displays ―0194: Processor family mismatch detected‖
message in the error manager.
Halts the system.
Processor cache not
identical
Fatal
The BIOS detects the error condition and responds as follows:
Logs the error into the SEL.
Alerts the Integrated BMC of the configuration error with an
IPMI command.
Does not disable the processor.
Displays ―0192: Cache size mismatch detected‖ message
in the error manager.
Halts the system.
Processor frequency (speed)
not identical
Major
The BIOS detects the error condition and responds as follows:
Adjusts all processor frequencies to the lowest common
denominator.
Continues to boot the system successfully.
If the frequencies for all processors cannot be adjusted to be the
same, then the BIOS:
Logs the error into the SEL.
Displays ―0197: Processor speeds mismatched‖ message
in the error manager.
Halts the system.
Processor microcode
missing
Minor
The BIOS detects the error condition and responds as follows:
Logs the error into the SEL.
Does not disable the processor.
Displays ―816x: Processor 0x unable to apply microcode
update‖ message in the error manager.
The system continues to boot in a degraded state,
regardless of the setting of POST Error Pause in the
Setup.
Processor Intel® QuickPath
Interconnect speeds not
identical
Halt
The BIOS detects the error condition and responds as follows:
Adjusts all processor interconnect frequencies to lowest
common denominator.
Logs the error into the SEL.
Alerts the Integrated BMC about the configuration error.
Does not disable the processor.
Displays ―0195: Processor 0x Intel(R) QPI speed
mismatch‖ message in the Error Manager.
If POST Error Pause is disabled in the Setup, continues to
boot in a degraded state.
If POST Error Pause is enabled in the Setup, pauses the
system, but can continue to boot if operator directs.
Table 4. Mixed Processor Configurations
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3.3.3 Installing or Replacing the Processor
3.3.3.1 Installing the Processor
To install a processor, follow these instructions:
1. Turn off all peripheral devices connected to the server.
2. Turn off the server.
3. Disconnect the AC power cord from the server.
4. Remove the server’s cover. See the document that came with your server chassis for
instructions on removing the server’s cover.
5. Locate the processor socket and raise the raise the load lever of the ILM cover
completely. (see letter ―A‖ in the figure below).
Figure 10. Lifting the load lever of ILM cover
6. Open the load plate (see letter ―B‖ in Figure 10 and letter ―C‖ in Figure 11).
.
Figure 11. Removing the socket cover
7. Remove the protective socket cover. (See letter ―D‖ in Figure 11)
8. Align the pins of the processor with the socket and insert the processor into the
socket.
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Figure 12. Installing processor
9. Lower the load plate and load lever of the ILM cover completely.
Note: Make sure the alignment triangle mark and the alignment triangle cutout align correctly.
To assist in package orientation and alignment with the socket:
A. The package Pin1 triangle and the socket Pin1 chamfer provide a visual reference for
proper orientation.
B. The package substrate has orientation notches along two opposing edges of the
package offset from the centerline. The socket has two corresponding orientation
posts to physically prevent mis-orientation of the package. These orientation features
also provide an initial rough alignment of the package to the socket.
C. The socket has alignment walls at the four corners to provide final alignment of the
package.
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Figure 13. Package Installation/Remove Feature
3.3.3.2 Installing the Processor Heatsink(s)
CAUTION: The heatsink has Thermal Interface Material (TIM) located on the bottom of it. Use caution
when you unpack the heatsink so you do not damage the TIM
To install the heatsink, follow these steps:
1. Remove the protective film on the TIM if present.
2. Orient the heatsink over the processor as shown in Figure 14. The heatsink fins must
be positioned as shown to provide correct airflow through the system.
3. Set the heatsink over the processor, lining up the four captive screws with the four
posts surrounding the processor.
4. Loosely screw in the captive screws on the heatsink corners in a diagonal manner
according to the numbers shown in as follows:
a) Starting with the screw at location 1, engage the screw threads by giving it two
rotations in the clockwise direction and stop. (IMPORTANT: Do not fully
tighten.)
b) Proceed to the screw at location 2 and engage the screw threads by giving it two
rotations and stop.
c) Engage screws at locations 3 and 4 by giving each screw two rotations and then
stop.
d) Repeat steps 4a through 4c by giving each screw two rotations each time until all
screws are lightly tightened up to a maximum of 8 inch-lbs torque.
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Figure 14. Installing/Removing Heatsink
3.3.3.3 Removing the Processor Heatsink
To remove the heatsink, follow these steps:
1. Loosen the four captive screws on the heatsink corners in a diagonal manner according
to the numbers shown in Figure 1 as follows:
a) Starting with the screw at location 1, loosen it by giving it two rotations in the
anticlockwise direction and stop. (IMPORTANT: Do not fully loosen.)
b) Proceed to the screw at location 2 and loosen it by giving it two rotations and
stop.
c) Loosen screws at locations 3 and 4 by giving each screw two rotations and then
stop.
d) Repeat steps 1a through 1c by giving each screw two rotations each time until all
screws are loosened.
2. Lift the heatsink from the board.
3.3.4 Intel
®
Intel
QPI is a cache-coherent, link-based interconnect specification for processor, chipset, and
I/O bridge components. You can use it in a wide variety of desktop, mobile, and server
platforms spanning IA-32 and Intel® Itanium
®
QuickPath Interconnect (Intel® QPI)
®
architectures. Intel® QPI also provides support for
high-performance I/O transfer between I/O nodes. It allows connection to standard I/O buses
such as PCI Express*, PCI-X*, PCI (including peer-to-peer communication support), AGP
(Accelerated Graphics Port), and so forth, through the appropriate bridges.
Each Intel
and receiver plus a differential forwarded clock. A full-width Intel
signals (20 differential pairs in each direction) plus a forwarded differential clock in each
direction. Each Intel
®
QPI link consists of 20 pairs of uni-directional differential lanes for the transmitter
®
5500 series and 5600 series processor supports two Intel® QPI links, one
®
QPI link pair consists of 84
going to the second processor and one going to the Intel® 5500 chipset IOH.
Figure 15. Intel® QPI Link
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In the current implementation, Intel
6.4 GT/s. Intel
quarter - 5 lanes) independently in each direction between a pair of devices communicating via
the Intel
®
QPI ports operate at multiple lane widths (full - 20 lanes, half - 10 lanes, and
®
QPI. The server boards support full-width communication only.
®
QPI ports are capable of operating at transfer rates of up to
For more information see the Intel® QPI Overview Rev 1.04 (Document#: 380531)
3.4 Intel
The Intel
package. Each processor produces up to three channels of DDR3 memory. The Intel
®
QuickPath Memory Controller
®
5500 series and 5600 series processors have an integrated memory controller on its
®
QPI
Memory Controller supports DDR3 800, DDR3 1066, and DDR3 1333 memory technologies.
The memory controller supports both Registered DIMMs (RDIMMs) and Unbuffered DIMMs
(UDIMMs).
Mixing of RDIMMs and UDIMMs is not supported.
3.4.1 Supported Memory
The Intel® Server Board S5500WB supports six DDR3 memory channels (three per processor
socket) with two DIMMs on the first channel and one DIMM on the second and third channels of
each processor. Therefore, the server board supports up to 8 DIMMs with dual-processor
sockets with a maximum memory capacity of 128 GB.
The server board supports DDR3 800, DDR3 1067, and DDR3 1333 memory technologies.
Memory modules of mixed speed are supported by automatic selection of the highest common
frequency of all memory modules.
The following configurations are not supported, validated or recommended:
Mixing of RDIMMs and UDIMMs is not supported
Mixing of memory type, size, speed and/or rank has not been validated and is
not supported
Mixing memory vendors has not been validated and is not recommended
Non-ECC memory has not been validated and is not supported in a server environment
Note: Mixed memory is not tested or supported. Non-ECC memory is not tested and is not
recommended for use in a server environment
The Intel® Server Board S5500WB uses a 2:1:1 memory DIMM layout. A 2:1:1 layout was
chosen for its lowest power for a particular bandwidth and because it allows the maximum
possible bandwidth when a 1:1:1 memory population is used.
3.4.2 Memory Subsystem Nomenclature
DIMMs are organized into physical slots on DDR3 memory channels that belong to processor
sockets.
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Processor Socket 1
Processor Socket 2
Channel A
Channel B
Channel C
Channel D
Channel E
Channel F
A1
A2
B1
C1
D1
D2
E1
F1
The memory channels from socket 1 are identified as Channels A, B, and C. The memory
channels from socket 2 are identified as Channels D, E, and F.
The DIMM identifiers on the silkscreen on the board provide information about the channel,
and, therefore the processor, to which they belong. For example, DIMM_A1 is the first slot on
Channel A on processor 1; DIMM_D1 is the first DIMM socket on Channel D on processor 2.
Table 5. DIMM Nomenclature
If the socket is not populated, the memory slots associated with a processor socket
are unavailable.
You can install a processor without populating the associated memory slots provided a second
processor is installed with associated memory. In this case, the memory is shared by the
processors. However, the platform suffers performance degradation and latency due to the
remote memory.
Sockets are self-contained and autonomous. However, all configurations in the BIOS setup
such as RAS, Error Management, and so forth, are applied commonly across sockets.
3.4.3 ECC Support
If at least one non-ECC DIMM is present in the system, the system reverts to non-ECC mode.
UDIMMs can be ECC or non-ECC; RDIMMs are always ECC enabled. Non-ECC DIMMs are not
validated and not recommended for server use.
3.4.4 Memory Reservation for Memory-mapped Functions
A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset,
processor, and BIOS (flash) memory-mapped I/O regions. This region displays as a loss of
memory to the operating system. In addition to this loss, the BIOS creates another reserved
region for memory-mapped PCI Express* functions, including a standard 64 MB or 256 MB of
standard PCI Express* Memory Mapped I/O (MMIO) configuration space. This is based on the
setup selection using the MAX_BUS_NUMBER feature offered by Intel® Tylersburg IOH chipset
and a variably sized MMIO region for the PCI Express* functions.
All these reserved regions are reclaimed by the operating system if Physical Address Extension
(PAE) is turned on in the operating system.
3.4.5 High-Memory Reclaim
When 4 GB or more of physical memory is installed (physical memory is the memory installed
as DDR3 DIMMs), the reserved memory is lost. However, the Intel
provides a feature called high-memory reclaim, which allows the BIOS and operating system to
remap the lost physical memory into system memory above 4 GB (the system memory is the
memory that can be seen by the processor).
®
5500 Series Chipset
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The BIOS will always enable high-memory reclaim if it discovers installed physical memory
equal to or greater than 4 GB. For the operating system, the reclaimed memory is recoverable
only when it supports and enables the PAE feature in the processor. Most operating systems
support this feature. For details, see the relevant operating system manuals.
3.4.6 Memory Population Rules
You should populate the memory slots of DDR3 channels furthest from the processor first.
Therefore, if A1 is empty, you cannot populate/use A2.
Figure 16. Memory Channel Population
3.4.7 Installing and Removing Memory
The silkscreen on the board next to CPU1 displays: DIMM_A2, DIMM_A1, DIMM_B1,
DIMM_C1, and next to CPU2 display: DIMM_D2, DIMM_D1, DIMM_E1, DIMM_F1 starting from
the inside of the board. DIMM_A1 is the blue socket closest to the CPU 1 socket. For memory
channel A, the server board requires DDR3 DIMMs within a channel to be populated starting
with the DIMM farthest from the processor. The DIMM farthest from the processor per channel
is blue on the board.
3.4.7.1 Installing DIMMs
To install DIMMs, follow these steps:
1. Turn off the server.
2. Disconnect the AC power cord from the server.
3. Remove the server’s cover and locate the DIMM sockets (see ― Installing Memory‖).
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Figure 17. Installing Memory
4. Make sure the clips at either end of the DIMM socket(s) are pushed outward to the open
position (see letter ―A‖ in the figure above).
5. Holding the DIMM by the edges, remove it from its anti-static package.
6. Position the DIMM above the socket. Align the two small notches in the bottom edge of
the DIMM with the keys in the socket (letter ―B‖ in Figure 16).
7. Insert the bottom edge of the DIMM into the socket (letter ―C‖ in Figure 16).
8. When the DIMM is inserted, push down on the top edge of the DIMM until the retaining
clips snap into place (letter ―D‖ in Figure 16). Make sure the clips are firmly in place
(letter ―E‖ in Figure 16).
9. Replace the server’s cover and reconnect the AC power cord.
3.4.7.2 Removing DIMMs
To remove a DIMM, follow these steps:
1. Turn off all peripheral devices connected to the server.
2. Turn off the server.
3. Remove the AC power cord from the server.
4. Remove the server’s cover.
5. Gently spread the retaining clips at each end of the socket. The DIMM lifts from the
socket.
6. Holding the DIMM by the edges, lift it from the socket and store it in an anti-static
package.
7. Reinstall and reconnect any parts you removed or disconnected to reach the DIMM
sockets.
8. Replace the server’s cover and reconnect the AC power cord.
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3.4.8 Channel-Independent Mode
In the Independent Channel mode, you can populate multiple channels in any order (for
example, you can populate channels B and C while channel A is empty). Also, DIMMs on
adjacent channels do not need to have identical parameters. Therefore, all DIMMs are enabled
and used in the Independent Channel mode.
Adjacent slots on channels A and D do not need matching size and organization. However, the
speed of the channel is configured to the maximum common speed of the DIMMs.
The single channel mode is established using the independent channel mode by populating
DIMM slots from channel A only.
3.4.9 Memory RAS
The memory RAS offered by the Intel® 5500 series and 5600 series processors is performed at
channel level (for example, during mirroring, channel B mirrors channel A). All DIMM matching
requirements are on a slot-to-slot basis on adjacent channels. For example, to enable mirroring,
corresponding slots on channels A and B must have DIMMS of identical parameters.
If one socket fails, the population requirements for RAS, the BIOS sets all six channels to the
Independent Channel mode. One exception to this rule is when all DIMM slots from a socket
are empty (for example, when only DIMM slots A1, B1, and C1 are populated, mirroring is
possible on the platform).
3.4.9.1 Memory Population for Channel Mirroring Mode
The mirrored configuration is a redundant image of the memory, and can continue to operate
despite the presence of sporadic uncorrectable errors.
Channel mirroring is a RAS feature in which two identical images of memory data are
maintained, thus providing maximum redundancy. On the Intel® 5500 series based Intel server
boards, mirroring is achieved across channels. Active channels hold the primary image and the
other channels hold the secondary image of the system memory. The integrated memory
controller in the processor alternates between both channels for read transactions. Under
normal circumstances, write transactions are issued to both channels.
Mirroring is only supported between Channels A & B and Channels D & E. The presence of a
DIMM on Channel C or F causes the BIOS to disable Mirroring and revert to the Independent
Channel mode.
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Figure 18. Mirroring Memory Configuration
3.4.10 Memory Error LED
Each DIMM is allocated an LED that, when lit, indicates a memory DIMM failure. It is the
function of the BIOS to identify bad DIMMs during the boot process. The BIOS sends a
message to the BMC to indicate which DIMM LED needs turn on.
3.5 Intel
The Intel
®
5500 Chipset IOH
®
5500 Chipset component is an I/O Hub (IOH). The Intel® 5500 Chipset provides a
connection point between various I/O components and Intel processors using the Intel® QPI
interface.
The Intel
®
5500 Chipset IOH is capable of interfacing with up to 24 PCI Express* lanes, which
can be configured in various combinations of x4, x8, x16 and limited x2 and x1 devices.
The Intel
the Intel
bridge and interfaces with other devices through SMBus, Controller Link, and RMII (Reduced
Media Independent Interface) manageability interfaces. The Intel
®
5500 Chipset IOH is responsible for providing a path to the legacy bridge. In addition,
®
5500 Chipset supports a x4 DMI (Direct Media Interface) link interface for the legacy
®
5500 Chipset supports the
following features and technologies:
Intel® QuickPath Interconnect (Intel® QPI)
PCI Express* Gen2
Intel® Virtualization Technology (Intel® VT) for Directed I/O 2 (Intel® VT-D2)
Manageability Engine (ME) subsystem
3.5.1 IOH24D PCI Express*
PCI Express* Gen1 and Gen2 are dual-simplex, point-to point serial differential low-voltage
interconnects. The signaling bit rate is 2.5 Gb/s one direction per lane for Gen1 and 5.0 Gb/s
one direction per lane for Gen2. Each port consists of a transmitter and receiver pair. A link
between the ports of two devices is a collection of lanes (x1, x2, x4, x8, x16, and so forth). All
lanes within a port must transmit data using the same frequency. The following table lists the
usage of the IOH24D PCI Express* bus segments.
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PCI Bus Segment
Width
Speed
Type
PCI I/O Card Slots
Port 0
ICH10R
x4
10 Gb/s
PCI Express*
Gen1
x4 PCI Express* Gen1 throughput to the ICH10R
southbridge
PE1, PE2
Intel® 5500 Chipset
IOH PCI Express*
x4
10 Gb/s
PCI Express*
Gen1
x4 PCI Express* Gen1 throughput to an onboard NIC.
PE3,
Intel® 5500 Chipset
IOH PCI Express*
X4
20 Gb/S
PCI Express*
Gen2
X4 PCI Express* Gen2 throughput to slot 1.
PE7, PE8
Intel® 5500 Chipset
IOH PCI Express*
x8
40 Gb/S
PCI Express*
Gen2
x8 PCI Express* Gen2 throughput to the slot 6 riser .
PE9, PE10
Intel® 5500 Chipset
IOH PCI Express*
x8
40 Gb/S
PCI Express*
Gen2
x4 PCI Express* Gen2 throughput to each of the two
Intel® I/O Expansion Module connectors.
Table 6. IOH24D PCI Express* Bus Segments
3.5.1.1 Direct Cache Access (DCA)
The DCA mechanism is a system-level protocol in a multi-processor system to improve I/O
network performance by providing higher system performance. It is designed to minimize cache
misses when a demand read is executed. This is accomplished by placing the data from the I/O
devices directly into the CPU cache through hints to the processor to perform a data pre-fetch
and install it in its local caches. The Intel® 5500 series and 5600 series processor supports
Direct Cache Access (DCA). You enable or disable DCA in the BIOS processor setup menu.
3.5.1.2 Intel
®
Virtualization Technology for Directed I/O (Intel® VT-d)
The Intel® Virtualization Technology is designed to support multiple software environments
sharing the same hardware resources. Each software environment may consist of an operating
system and applications. You can enable or disable the Intel® Virtualization Technology in the
BIOS setup. The default behavior is disabled.
Note: If the setup options are changed to enable or disable the Virtualization Technology
setting in the processor, the user must perform an AC power cycle for the changes to take
effect.
The Intel
®
5500 Chipset IOH supports DMA remapping from inbound PCI Express* memory
Guest Physical Address (GPA) to Host Physical Address (HPA). PCI Express* devices are
directly assigned to a virtual machine leading to a robust and efficient virtualization.
3.6 Management Engine
The Management Engine (ME) is an embedded ARC controller within the IOH. The IOH ME
performs manageability functions called Intel® Server Platform Services (SPS) for the discrete
Baseboard Management Controller (BMC).
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The functionality provided by the SPS firmware is different from Intel® Active Management
Technology (Intel® AMT or AT) provided by the ME on client platforms.
Server Platform Services are value-added platform management options that enhance the
value of Intel platforms and their component ingredients (CPUs, chipsets, and I/O components).
Each service is designed to function independently wherever possible, or grouped together with
one or more features in flexible combinations to allow OEMs (Original Equipment
Manufacturers) to differentiate platforms. The following is a high-level view of the Intel® Server
Board S5500WB SPS functions.
Node Management Features:
o NPTM Policy Manager
o Power Supply Monitoring Service
o Inlet Temperature Monitoring Service
o CPU Power Limiting Service
Provide Access to ICH10R Devices: The ME has control of ICH10R platform
instrumentation. SPS provides a mechanism for the BMC to access this instrumentation
through IPMI OEM commands. Use of this capability on Intel servers is
platform-/SKU-specific.
o ICH10 temperature monitoring
PECI 2.0 Proxy: SPS offers a means for a BMC without a PECI 2.0 interface to use the ME
as a PECI proxy. The BMC on Intel servers already has a PECI 2.0 interface, so this SPS
capability is not used.
3.7 Intel
The Intel® 82801Jx I/O Controller Hub (ICH10R) provides extensive I/O support and supports
the following features and specifications:
®
82801Jx I/O Controller Hub (ICH10R)
PCI Express* Base Specification, Revision 1.1 support
ACPI Power Management Logic Support, Revision 3.0a
Enhanced DMA controller, interrupt controller, and timer functions
Integrated Serial ATA host controllers with independent DMA operation on up to six
ports and AHCI support
USB host interface with support for up to 12 USB ports; six UHCI host controllers;
and two EHCI high-speed USB 2.0 host controllers
System Management Bus (SMBus) Specification, Version 2.0 with additional support
for I2C devices
Low Pin Count (LPC) interface support
Serial Peripheral Interface (SPI) support
3.7.1 Serial ATA Support
The ICH10R has an integrated Serial ATA (SATA) controller that supports independent DMA
operation on six ports and data transfer rates of up to 3.0 Gb/s. The six SATA ports on the
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server board are numbered SATA-1 through SATA-6. You can enable or disable the SATA
ports and/or configure them by accessing the BIOS setup utility during POST.
3.7.1.1 Intel
The onboard storage capability of these server boards includes support for Intel
Server RAID Technology II (Intel
®
Embedded Server RAID Technology II
®
ESRTII), which provides three standard software RAID levels:
®
Embedded
data stripping (RAID Level 0), data mirroring (RAID Level 1), and data stripping with mirroring
(RAID Level 10). For higher performance, you can use data stripping to alleviate disk
bottlenecks by taking advantage of the dual independent DMA engines that each SATA port
offers. Data mirroring is used for data security. If a disk fails, a mirrored copy of the failed disk
is brought online. There is no loss of either PCI resources (request/grant pair) or add-in card
slots.
With the addition of an optional Intel
®
RAID Activation Key, Intel® ESRTII is also capable of
providing fault tolerant data stripping (software RAID Level 5), such that if a SATA hard drive
fails, you can restore the lost data on a replacement drive from the other drives that make up
the RAID 5 pack.
®
Intel
Embedded Server RAID Technology functionality requires the following items:
ICH10R IO Controller Hub
Software RAID option is selected on BIOS menu for SATA controller
Intel
Intel
®
Embedded Server RAID Technology II Option ROM
®
Embedded Server RAID Technology II drivers, most recent revision
At least two SATA hard disk drives
3.7.1.2 Intel
The Intel
®
Embedded Server RAID Technology II for SATA Option ROM provides a pre-
operating system user interface for the Intel® Embedded Server RAID Technology II
implementation and provides the ability to use an Intel
volume as a boot disk as well as to detect any faults in the Intel
®
Embedded Server RAID Technology II Option ROM
®
Embedded Server RAID Technology II
®
Embedded Server RAID
Technology II volume(s).
3.7.2 USB 2.0 Support
The USB controller functionality integrated into ICH10R provides the server board with an
interface for up to 12 USB 2.0 ports. All ports are high-speed, full-speed, and low-speed
capable.
Four external connectors are located on the back edge of the server board.
Two internal 2x5 headers are provided, capable of supporting two optional USB 2.0
ports each, typically, one header supports Front panel USB and one supports an
internal third party management card.
One internal low-profile 2x5 header is provided
One Internal Type A USB vertical connector is provided for attaching standard
peripherals
The BMC consumes 2 ports, for a total of 12 Ports
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Functional Architecture Intel® Server Board S5500WB TPS
LED Color
LED State
NIC State
Green/Amber (Left)
Off
10 Mbps
Green
100 Mbps
Amber
1000 Mbps
Green (Right)
On
Active Connection
Blinking
Transmit / Receive activity
LED Color
LED State
NIC State
Green/Amber (Right)
Off
10 Mbps
Green
100 Mbps
Amber
1000 Mbps
Green (Left)
On
Active Connection
Blinking
Transmit / Receive activity
3.8 Network Interface Controller (NIC)
Network interface support is provided from the onboard Intel® 82576 NIC, which is a single,
compact component with two fully integrated GbE Media Access Control (MAC) and Physical
Layer (PHY) ports. The Intel® 82576 NIC provides the server board with support for dual LAN
ports designed for 10/100/1000 Mbps operation. Refer to the Intel® 82576 Gigabit Ethernet
Controller Datasheet (Document#: 82576) for full details of the NIC feature set.
The NIC device provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASETX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab) and is capable of transmitting
and receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps.
The Intel® 82576 NIC is powered off the main standby voltage rail via DC to DC Voltage
regulators for efficiency purposes. It is on standby power so the BMC can send out-of-band
management traffic over the RMII bus to the network during sleep state S5.
The NIC supports the normal RJ-45 LINK/Activity speed LEDs as well as the Proset ID function.
These LEDs are powered from a Standby voltage rail.
The link / activity LED (at the right of the connector) indicates network connection when on, and
transmit / receive activity when blinking. The speed LED (at the left of the connector) indicates
1000-Mbps operation when amber, 100-Mbps operation when green, and 10-Mbps when off.
The following table provides an overview of the LEDs.
Table 7. NIC 1 Status LED
Table 8. NIC 2 Status LED
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3.8.1 MAC Address Definition
The Intel® Server Board S5500WB has the following four MAC addresses assigned to it at the
Intel factory.
NIC 1 MAC address
NIC 2 MAC address – Assigned the NIC 1 MAC address +1
Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2
Intel® Remote Management Module 3 (Intel® RMM3) MAC address – Assigned the
NIC 1 MAC address +3
The Intel® Server Board S5500WB has a white MAC address sticker included with the board.
The sticker displays the NIC 1 MAC address in both bar code and alphanumeric formats.
3.8.2 LAN Connector Ordering
The Intel® 82576 NIC is connected to a stacked RJ-45 over USB mag-jack for NIC 1 and a RJ45 mag-jack for the second connection (NIC 2).
3.9 Integrated Baseboard Management Controller
The ServerEngines* LLC Pilot II Integrated BMC is provided by an embedded ARM9 controller
and associated peripheral functionality that is required for IPMI-based server management.
Firmware usage of these hardware features is platform-dependant.
The following is a summary of the Integrated BMC management hardware features used by the
ServerEngines* LLC Pilot II Integrated BMC:
IPMI 2.0 Compliant
Integrated 250 MHz 32-bit ARM9 processor
Six I2C SMBus modules with Master-Slave support
Two independent 10/100 Ethernet Controllers with RMII support
Six I2C interface
Memory Management Unit (MMU)
DDR2 16-bit up to 667 MHz memory interface
Up to 16 direct and 64 Serial GPIO ports
12 10-bit Analog to Digital Converters
Eight Fan Tachometers Inputs
Four Pulse Width Modulators (PWM)
Chassis Intrusion Logic with battery-backed general purpose register
JTAG Master interface
Watchdog timer
Additionally, the ServerEngines* Pilot II part integrates a super I/O module with the
following features:
Keyboard Style/BT Interface
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Two 16C550 compatible serial ports
Serial IRQ support
16 GPIO ports (shared with Integrated BMC)
LPC to SPI Bridge for system BIOS support
SMI and PME support
ACPI compliant
Wake-up control
The Pilot II contains an integrated KVMS subsystem and graphics controller with the
following features:
USB 2.0 for keyboard, mouse, and storage devices
Hardware Video Compression for text and graphics
Hardware encryption
2D Graphics Acceleration
DDR2 graphics memory interface
Matrox 2000 Graphics core with PCI Express* x1 host interface
Up to 1600x1200 pixel resolution
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Figure 19. Integrated BMC Hardware
3.9.1 Integrated BMC Embedded LAN Channel
The Integrated BMC hardware includes two dedicated 10/100 network interfaces. These
interfaces are not shared with the host system. At any time, you can enable only one dedicated
interface for management traffic. The default active interface is the NIC 1 port.
For these channels, you can enable support for IPMI-over-LAN and DHCP.
For security reasons, embedded LAN channels have the following default settings:
IP Address: Static
All users disabled.
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Manageability features
Description
Embedded Web U
Remote Power on\off, sensor status, system info,
System Event log, and OEM customization
KVM Redirection
High performance and multiple concurrent sessions
USB 2.0 Media Redirection
Boot over remote media
Security
SSL, SSH support
WS- MAN
Dedicated NIC
Shared NIC (Onboard NICs)
LDAP Support
3.9.2 RMM3 Advanced Management Board:
The RMM3 advanced management board serves two purposes. The first is to give the
customer the option to add a dedicated management 100-Mbit LAN interface to the product.
The second is to give additional flash space, enabling the Advanced Management functions to
support WS-MAN and CIMOM. The RMM3 comes with a third 10/100GbE NIC that connects to
the board. RMM3 management traffic can use the third NIC or NIC 1.
Table 8. RMM3 Features
3.10 Serial Ports
The server board provides two serial ports: an external RJ-45 serial port and an internal serial
header.
The rear RJ-45 serial A port is a fully-functional serial port that can support any standard
serial device.
The serial B port is an optional port that is accessed through a 9-pin internal DH-10 header.
You can use a standard DH-10 to DB9 cable to direct serial A port to the rear of a chassis.
Appendix A defines the serial B interface.
3.11 Wake-up Control
Wake from S1 is supported on LAN, USB, Serial port, and PCI Express* slots.
3.12 Integrated Video Support
The SVGA subsystem supports a variety of modes, up to 1280x1024@24bpp modes under 2D.
It also supports both CRT and LCD monitors up to a 200 Hz vertical refresh rate.
The video is accessed using a standard 15-pin VGA connector found in the I/O panel area of
the server board. You can disable the onboard video controller using the BIOS Setup utility or
when an add-in video card is detected. The system BIOS provides the option for dual-video
operation when an add-in video card is configured in the system.
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Onboard Video
Enabled
Disabled
Dual Monitor Video
Enabled
Disabled
Shaded if onboard video is set to "Disabled"
3.12.1 Video Modes
The integrated video controller supports all standard VGA modes. The following table shows
the 2D modes supported for both CRT and LCD.
Table 9. Supported Video Modes
3.12.2 Dual Video
The BIOS supports both single-video and dual-video modes. The dual-video mode is enabled
by default in the BIOS.
In the single mode (dual monitor video = disabled), the onboard video controller is disabled
when an add-in video card is detected.
In the dual mode (onboard video = enabled, dual monitor video = enabled), the onboard video
controller is enabled and is the primary video device. The external video card is allocated
resources and is considered the secondary video device. The BIOS Setup utility provides
options to configure the feature as follows.
Table 10. Dual Video Options
3.12.3 Front Panel Video
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Riser
Description
PEWIDTH0
pin A50
1U one x8
1 x8 PCI Express* Slot
0
2U two x4
2 X4 PCI Express* Slots
1
The Intel
®
Server Board S5500WB provides a mechanism to support video to the front panel
via the use of an internal header. When a monitor is plugged into the front panel video
connector, the rear panel video stream is disconnected.
There is a jumper option to change this default action. When the internal header is used by a
third-party Management card to do KVM over LAN and then when a monitor is plugged into the
rear panel video connector, the video stream to the internal header is cut off.
3.13 I/O Slots
3.13.1 X16 Riser Slot Definition
Slot 6 was defined to support riser cards. Slot 6 has a x16 physical connector with a PCI
Express* Gen II x8 electrical interface. Two clocks are provided so the bus can be bifurcated
into two x4 connectors.
Because of CPU placement, a 1U system supports only PCI Express* adapters that meet the
PCI SIG half card definition. Full-length boards are supported in a 2U system by using a taller
riser and extending the board over the 1U CPU heatsinks or if CPU2 is unpopulated.
Appendix A describes the pin assignments for this connector.
3.13.2 PE WIDTH Strapping
On the Intel® Server Board S5500WB, the IOH needs to be informed of the PCI Express* bus
width during power on. This is accomplished using the PEWIDTH input straps. The mechanism
used is the PEWIDTH bits, one bit is used to signify the width and number of PCI Express*
buses used by the riser. For slot 6, the PEWIDTH bit used is 0.
Table 11. PEWIDTH Strapping Bits
By using this mechanism for selecting PCI Express* port width, you can avoid a BIOS
rediscover and reboot.
The PEWIDTH is pulled up to 3.3 V Aux on the baseboard and grounded, if necessary, by the
riser. The baseboard provides an inverter and voltage level translator before passing this signal
to the IOH.
3.13.3 Slot 1 PCI Express* x8 Connector
Slot 1 provides a PCI Express* x4 bus on an x8 connector, if provided, for use in a 2U chassis
that uses LP boards without risers. Although it is feasible to use the IOM at the same time, it
would require 2U chassis back panel changes.
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Intel® I/O Expansion
Module
Description
PEWIDTH1 - Pin 2
one x8
1 x8 PCI Express* target device
0
two x4
2 x4 target devices
1
3.13.4 I/O Module Connector
Mezanine connectors are provided to support the various I/O modules, both the older Gen 1 I/O
modules supported by Intel® Server Board S5000PAL and newer, double-wide Gen 2 I/O
modules supported by the Intel® Server Board S5520UR are supported on the Intel® Server
Board S5500WB.
The Intel® I/O Expansion Module is also required to inform the IOH of the Intel® I/O Expansion
Module Bus usage, PEWIDTH bit 1 is to be used for this.
Table 12. Intel® I/O Expansion Module Bus PEWIDTH Bits
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Product Code
Description
AXX4SASMOD
Intel® SAS Entry RAID I/O Expansion Module: Provides 4port pass through SAS, entry-level RAID 0/1/1E, and
optional host RAID (4 internal ports).
AXXGBIOMOD
Dual Gigabit Ethernet I/O Expansion Module
AXXROMBSASMR
Intel® Integrated RAID I/O Expansion Module: Provides four
internal ports, full-featured SAS / SATA RAID 0,1,5,6 and
striping capability for spans 10, 50, 60. You must order the
optional backup battery AXXRSBBU3 separately.
AXXSASIOMOD
External 4-port SAS I/O Expansion Module.
AXX10GBIOMOD
Dual-port 10 Gigabit Ethernet I/O Expansion Module with
CX4 connectors.
4. Intel
®
I/O Expansion Modules
The Intel® Server Board S5500WB supports a variety of I/O Module options using 2x4 PCI
Express* Gen2 Intel® I/O Expansion Module connectors on the rear of the server board. Each
Intel® I/O Expansion Module connector is a 50-pin, surface mount, 0.8mm pitch, header. The
Intel® Server Board S5500WB accommodates both the double-wide I/O expansion modules and
the PCI Express* Gen 1 I/O modules (used on the S5000PAL rack server).
The Legacy modules are:
Dual Port GbE I/O Module
External 4 Port SAS I/O Module
The new modules consist of:
Internal 4-port Intel 82576EB GbE*
Dual Port Intel 10GbE I/O Module
Internal 4-port LSI* 1064e SAS I/O Module
Internal 4-port LSI* 1078e SAS I/O Module
Infiniband* I/O Expansion Module Single Port QDR
The second x4 Intel® I/O Expansion Module controller does not support a single-wide module; it
is only used to support a double-wide module. You must mount single-wide modules on
connector (J3B1) closest to Slot 6, marked Legacy Intel® I/O Expansion Module on the
silkscreen. When double-wide Intel® I/O Expansion Modules are installed, there might be
interference with some adapters installed in Slot 1.
The following table shows the product codes for each module.
Table 13. Intel® I/O Expansion Module Product Codes
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Product Code
Description
AXX4GBIOMOD2
Quad port Gigabit Ethernet I/O Expansion Module based on
the Intel® 82576EB Gigabit Ethernet Controller.
AXXIBQDRMOD
InfiniBand* I/O Expansion Module Single Port QDR.
For more information, refer to the I/O modules in the Intel® I/O Expansion Modules
Hardware Specification.
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5. Platform Management Features
This section explains BIOS and firmware (FW) requirements that drive specific hardware
implementations of the platform. To a large extent, this is background information.
5.1 BIOS Feature Overview
The Intel® Server Board S5500WB product uses the AMI Aptio v3.x code base.
5.1.1 EFI Support
The platform BIOS is compiled to support the 64-bit EFI environment, natively. This allows
operating systems that are EFI-aware to take advantage of the EFI-boot process in a native 64bit environment. It is expected this will reduce the time required to boot the platform to those
operating systems. Additionally, any utilities that make use of the EFI environment provided by
the platform BIOS need to support either the native 64-bit environment or make use of the EFI
byte code (EBC). Of course, to maintain compatibility with legacy operating environments, a
legacy boot option is provided.
5.1.2 BIOS Recovery
The platform BIOS supports a BIOS Recovery Mode Jumper. The BIOS samples this jumper
during POST through a GPIO and, if set, defaults to a recovery mode of operation that allows
restoration of the BIOS Flash to a full operational state.
The platform BIOS supports a Reset BIOS Configuration Jumper. The BIOS samples this
jumper during POST through a GPIO and, if set, resets its configuration information stored in
Flash memory.
5.2 BMC Feature Overview
The server management subsystem consists of multiple components including several
interconnected microcontrollers. The subsystem monitors platform sensors (temperatures,
voltages, fans, hard drives, and so forth); implements platform acoustics, power, and thermal
management policies; provides an intelligent LCD front-panel; and provides facilities for remote
and local management.
The server management subsystem is available when the system is connected to wall power
but not fully operational (S5 state); when the system is in a S1 sleep state or when the system
is fully operational (S0 state).
5.2.1 Server Engines Pilot II Controller
The center of the server management subsystem is the Server Engines Pilot II integrated
Baseboard Management Controller. This device provides support for many platform functions
including system video capabilities, legacy Super I/O functions, and also provides an ARM 926EJ microcontroller to host the embedded server management firmware stack.
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Feature
Description
IPMI 2.0
Compliance to IPMI 2.0 specification
Remote Management
Out-of-band access via either LAN or serial port for numerous features
Hardware Monitor
Monitor of fans, voltages, temperatures, chassis intrusions, memory errors,
power supplies, hard drives, and so forth
Event Management
System event filtering
Event Alerting
System events delivered via SNMP traps or email
System Event Log
Dedicated persistent storage for system events
Asset Inventory
Field replaceable unit (FRU) information
Console Redirection
Text-based console redirection via serial-over-LAN
The Server Engines Pilot II baseboard management controller across Intel’s server product line
with two different management feature set configurations: Basic and Advanced. The Intel
®
Server Board S5500WB supports both.
Basic features include IPMI 2.0 support, remote management, hardware monitoring, event
management, event alerting, system event log, asset inventory, console redirection, web
interface, and SMASH CLP (basic feature set).
Advanced features include the Basic features plus KVM redirection, USB Media redirection,
SMASH CLP (Advanced feature set), and WS-MAN. To enable the Advanced features, you
must install the Remote Management Module 3.
Note: The BMC consumes two USB ports; one runs at USB1.1 for keyboard mouse redirection
and one runs at USB2.0 for media redirection.
5.2.2 BMC Firmware
The BMC supports a Fast Firmware Update mode in addition to the standard KCS (Keyboard
Controller Style) SMS interface. This is a special AMI® proprietary protocol that goes over the
USB connection between the host and the BMC. Called ―IPMI over USB‖, it is implemented in
the LIBIPMI library on both host and BMC sides to transfer large blocks of data (up to 32 K)
much faster than KCS can. IPMI commands are embedded in data written/read to a virtual CDROM device.
The embedded server management firmware stack is based on a core stack from American
Megatrends Incorporated (AMI). The stack runs on an embedded version of the Linux operating
system and provides support for current industry standard management interfaces (IPMI 2.0)
and emerging industry standard advanced management interfaces (SMASH-CLP and WSMAN). The stack also includes support for keyboard, video, mouse (KVM), and USB media
redirection.
The server management subsystem provides remote connectivity through a single GbE NIC
with NC-SI support (RMII).
NPTM support is required; you must use the ME function in the IOH to accomplish this.
5.2.3 BMC Basic Features
Table 14: BMC Basic Features
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Feature
Description
SMASH CLP (Basic)
Command line SSH interface for basic server management operations
Node Manager
Power management by using P-state\C-State cycling method Requires
PMBus* power supply.
Manageability features
Description
Embedded Web UI
Remote Power on\off, sensor status, system info,
System Event log, OEM customization
KVM Redirection
high performance, multiple concurrent sessions
USB 2.0 Media Redirection
boot over remote media
Security
SSL, SSH support
WS- MAN
Dedicated NIC
Shared NIC (Onboard NICs)
LDAP support
5.2.4 BMC Advanced Features
The Intel® Server Board S5500WB product includes support for an upgrade module to support
the advanced server management functionality. The Remote Management Module 3 supports
an 8 MB SPI Flash, which connects to the integrated BMC SPI interface. This is in addition to
the local integrated BMC 8 MB SPI flash connected to the PILOT II IBMC down on the board.
The total 16 MB of Flash space is required to support advanced management features as
defined in the following table. The RMM3 advanced management board has a PHY device that
which interfaces with the secondary NC-SI port out of the Server Engines PILOT II integrated
BMC to offer a dedicated management Ethernet port.
Table 15. Advanced Features
5.3 Management Engine (ME)
5.3.1 Overview
The Intel® Server Platform Services (SPS) is a set of manageability services provided by the
firmware executing on an embedded ARC controller within the IOH. This management
controller is also commonly referred to as the Management Engine (ME). The functionality
provided by the SPS firmware is different from Intel® Active Management Technology (Intel®
AMT or AT) provided by the ME on client platforms.
Server Platform Services (SPS) are value-added platform management options that enhance
the value of Intel platforms and their component ingredients (CPUs, chipsets, and I/O
components). Each service is designed to function independently wherever possible, or
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grouped together with one or more features in flexible combinations to allow OEMs to
differentiate platforms.
5.3.2 BMC - Management Engine Interaction
Management Engine-Integrated BMC interactions include the following:
Integrated BMC stores sensor data records for ME-owned sensors.
Integrated BMC participates in ME firmware update.
Integrated BMC initializes ME-owned sensors based on SDRs.
Integrated BMC receives platform event messages sent by the ME.
Integrated BMC notifies ME of POST completion.
5.4 Data Center Manageability Interface
The DCMI specifications are derived from Intelligent Platform Management Interface (IPMI) 2.0.
The DCMI specifications define a uniform set of monitoring, control features and interfaces that
target the common and fundamental hardware management needs of server systems that are
used in large deployments within data centers, such as Internet Portal data centers. This
includes capabilities such as secure power and reset control, temperature monitoring, event
logging, and others. For more information refer to www.intel.com/go/dcmi.
5.5 Other Platform Management
The platform supports the following sleep states, S1 and S5. Within S0, the platform supports
additional lower power states, such as C1e and C6, for the CPU.
5.5.1 Wake On LAN (WOL)
Wake On LAN (WOL) is supported on both LAN ports and IOM LAN modules for all
supported Sleep states.
Wake on Ring is supported on the external Serial port only for all supported Sleep
states.
Wake on USB is supported on the rear and front panel USB ports for S1 only.
Wake on RTC is supported for all supported Sleep states.
Wake IPMI command is supported (BMC function no additional hardware requirement)
for all supported Sleep states.
5.5.2 PCI Express* Power management
L0 and L3 power management states are supported on all PCI Express* slots and embedded
end points.
5.5.3 PMBus*
Power supplies that have PMBus* 1.1 are supported and required to support Intel® Dynamic
Power Node Manager. Intel® Server Board S5500WB supports the features of Intel® Dynamic
Power Node Manager version 1.5 except the inlet temperature sensor.
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Main
Bus
Power
Rail
Sub
Bus
Power
Rail
Device
I2C\SMBus
Address
Note
Host
3V3SB
NA
NA
IBMC I2C\SMBus 3
No Connect
ICH10R SMBus
0x88
CK509B
0xD2
DB403
0xDC
Host
3V3
XDP
DB803
0xDC
CPU0 DIMM 1A
0xA0
CPU0 DIMM 2A
0xA2
CPU0 DIMM 1B
0xA4
CPU0 DIMM 1C
0xA6
CPU0 DIMM 1D
0xA8
CPU0 DIMM 2D
0xAA
CPU0 DIMM 1E
0xAC
CPU0 DIMM 1F
0xAE
Sensor
3V3SB
NA
NA
IBMC I2C\SMBus 1
Temp Sensor
0x9E
FP Temp Sensor
0x9A
FP FRU
0xAE
Baseboard FRU
0xA8
CPU IOH
0xE0
IPMI
3V3SB
NA
NA
IBMC I2C\SMBus 0
IPMI
5VSB
IPMI Connector
IPMI
5V
HSBP A
0xC0
5.6 I2C\SMBUS Architecture Block
Figure 20. S5500WB I2C\SMBUS Block Diagram
5.6.1 I2C\SMBUS Device Addresses
Table 21 lists the I2C\SMBus addresses of various devices by bus.
Table 16. I2C/SMBus Device Address Assignment
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Main
Bus
Power
Rail
Sub
Bus
Power
Rail
Device
I2C\SMBus
Address
Note
LAN
3V3SB
NA
NA
IBMC I2C\SMBus 5
NIC LAN
Link
3V3SB
NA
NA
IBMC I2C\SMBus 4
ICH10R SMLINK
0x88
PWR
5V
PS FRU
0xAC
PS I2C\PSMI
0xB0
Spare
3V3SB
NA
NA
IBMC I2C\SMBus 2
DDC
3V3SB
DDC
5V
IBMC GFX DDC
Video Monitor
0xA0
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6. Configuration Jumpers
The following table provides a summary and description of configuration, test, and debug
jumpers on the Intel® Server Board S5500WB. The server board has several 3-pin jumper
blocks that can be used.
Pin 1 on each jumper block can be identified by the following symbol on the silkscreen: ▼
Figure 21: Jumper Blocks (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2, J7A2)
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Jumper Name
Jumper Position
Mode of
Operation
Note
J1B5: BMC Force
Update jumper
1-2
Normal
IBMC GPIO[1] is pulled HIGH. Default position.
2-3
Update
IBMC GPIO[1] is pulled LOW.
J1C2: Password Clear
1-2
Normal
ICH10R INTRUDER# pin is pulled HIGH. Default
position.
2-3
Clear Password
ICH10R INTRUDER# pin is pulled LOW.
J1C3: BIOS Recovery
Mode
1-2
Normal
ICH10R GPIO [55] is pulled HIGH. Default
position.
2-3
Recovery
ICH10R GPIO [55] is pulled LOW.
J1B4: CMOS Clear
1-2
Normal
ICH10R RTCRST# pin is pulled HIGH. Default
position.
2-3
Clear CMOS
Settings
ICH10R RTCRST# pin is pulled LOW.
J6A3: Video Master
1-2
Internal
Internal connector will override if both connectors
are used.
2-3
External
External connector will override if both
connectors are used.
J7A2: ME Firmware
Force Update
1-2
Disabled
Default
2-3
Enabled
J6A2: Serial Interface
1 – 2
DCD to DTR
Data Carrier Detect
3 – 4
DSR to DTR
Data Set Ready
Jumper Position
Mode of
Operation
Note
1-2
Normal
IBMC GPIO[1] is pulled HIGH. Default position.
2-3
Update
IBMC GPIO[1] is pulled LOW.
Table 17: Server Board Jumpers (J1B5, J1C2, J1C3, J1B4, J6A3, J6A2)
6.1.1 Force IBMC Update (J1B5)
When performing a standard BMC firmware update procedure, the update utility places the
BMC into an update mode, allowing the firmware to load safely onto the flash device. In the
unlikely event the BMC firmware update process fails due to the BMC not being in the proper
update state, the server board provides a BMC Force Update jumper (J1B5) which will force the
BMC into the proper update state. The following procedure should be followed in the event the
standard BMC firmware update process fails.
Table 18. Force IBMC Update Jumper
1. Power down and remove the AC power cord.
2. Open the server chassis. See your server chassis documentation for instructions.
3. Move jumper from the default operating position, covering pins1 and 2, to the enabled
position, covering pins 2 and 3.
4. Close the server chassis.
5. Reconnect the AC cord and power up the server.
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Jumper
Position
Mode of Operation
Note
1-2
Normal
ICH10R INTRUDER# pin is pulled HIGH. Default position.
2-3
Clear Password
ICH10R INTRUDER# pin is pulled LOW.
6. Perform the BMC firmware update procedure as documented in the README.TXT file
included in the given BMC firmware update package. After successful completion of the
firmware update process, the firmware update utility may generate an error stating the
BMC is still in update mode.
7. Power down and remove the AC power cord.
8. Open the server chassis.
9. Move the jumper from the enabled position, covering pins 2 and 3 to the disabled
position, covering pins 1 and 2.
10. Close the server chassis.
11. Reconnect the AC cord and power up the server.
Note: Normal BMC functionality is disabled with the Force BMC Update jumper is set to the
enabled position. You should never run the server with the BMC Force Update jumper set in
this position. You should only use this jumper setting when the standard firmware update
process fails. This jumper should remain in the default / disabled position when the server is
running normally.
The server board has several 3-pin jumper blocks that can be used to configure, protect, or
recover specific features of the server board.
6.1.2 Password Clear (J1C2)
The user sets this 3-pin jumper to clear the password.
Table 19. Password Clear Jumper
6.1.2.1 Clearing the Password
1. Power down server. Do not unplug the power cord.
2. Open the chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1B6) from the default operating position, covering pins 1 and 2, to the
password clear position, covering pins 2 and 3.
4. Close the server chassis.
5. Power up the server, wait 10 seconds or POST completes.
6. Power down the server.
7. Open the chassis and move the jumper back to default position, covering pins 1 and 2.
8. Close the server chassis.
9. Power up the server.
The password is now cleared and you can reset it by going into the BIOS setup.
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Jumper
Position
Mode of
Operation
Note
1-2
Normal
ICH10R GPIO [55] is pulled HIGH. Default position.
2-3
Recovery
ICH10R GPIO [55] is pulled LOW.
6.1.3 BIOS Recovery Mode (J1C3)
The Intel
corruption in the main BIOS and Boot Block. This 3-pin jumper is used to reload the BIOS when
the image is suspected to be corrupted. For directions on how to recover the BIOS, refer to the
specific BIOS release notes.
You can accomplish a BIOS recovery from the SATA CD and USB Mass Storage device.
Please note that this platform does not support recovery from a USB floppy.
The recovery media must contain the following files under the root directory:
The BIOS starts the recovery process by first loading and booting to the recovery image file
(FVMAIN.FV) on the root directory of the recovery media (SATA CD or USB disk).This process
takes place before any video or console is available. Once the system boots to this recovery
image file (FVMAIN.FV), it boots automatically into the EFI Shell to invoke the Startup.nsh
script and start the flash update application (IFlash32.efi). IFlash32.efi requires the supporting
BIOS Capsule image file (*Rec.CAP). After the update is complete, a message displays, stating
the "BIOS has been updated successfully". This indicates the recovery process is finished. The
user should then switch the recovery jumper back to normal operation and restart the system by
performing a power cycle.
The following steps demonstrate this recovery process:
1. Power OFF the system.
2. Insert recovery media.
3. Switch the recovery jumper. Details regarding the jumper ID and location can be obtained
4. Power ON the system.
5. The BIOS POST screen will appear displaying the progress, and the system automatically
6. The Startup.nsh file executes, and initiates the flash update (IFlash32.efi) with a new
7. Power OFF the system, and revert the recovery jumper position to "normal operation".
8. Power ON the system.
9. Do NOT interrupt the BIOS POST during the first boot.
®
Server Board S5500WB uses BIOS recovery to repair the system BIOS from flash
Table 20. BIOS Recovery Mode Jumper
1. FVMAIN.FV
2. UEFI iFlash32 2.6 Build 9
3. *Rec.CAP
4. Startup.nsh (update accordingly to use proper *Rec.CAP file)
from the Board EPS for that Platform.
boots to the EFI SHELL.
capsule file (*Rec.CAP). The regular IFlash message displays at the end of the process—
once the flash update succeeds.
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Jumper Position
Mode of Operation
Note
1-2
Normal
ICH10R RTCRST# pin is pulled HIGH. Default position.
2-3
Reset BIOS Configuration
ICH10R RTCRST# pin is pulled LOW.
Jumper Position
Mode of
Operation
Notes
1-2
Internal
Internal connector will override if both connectors are used.
2-3
External
External connector will override if both connectors are used.
6.1.4 Reset BIOS Configuration (J1B4)
This jumper used to be the CMOS Clear jumper. Since the previous generation, the BIOS has
moved CMOS data to the NVRAM region of the BIOS flash. The BIOS checks during boot to
determine if the data in the NVRAM needs to be set to default.
Table 21. Reset BIOS Jumper
6.1.4.1 Clearing the CMOS
1. Power down server. Do not unplug the power cord.
2. Open the server chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1B4) from the default operating position, covering pins 1 and 2, to the
reset / clear position, covering pins 2 and 3.
4. Wait five seconds.
5. Remove AC power.
6. Move the jumper back to default position, covering pins 1 and 2.
7. Close the server chassis.
8. Power up the server.
The CMOS is now cleared and you can reset it by going into the BIOS setup.
Note: Removing AC Power before performing the CMOS Clear operation causes the system to
automatically power up and immediately power down, after the procedure is followed and AC
power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and reinstall the AC power cord. Power-up the system and proceed to the <F2> BIOS Setup Utility to
reset the desired settings.
6.1.5 Video Master (J6A3)
Table 22. Video Master Jumper
This jumper determines which video is the primary.
J6A3, 1-2 jumpered: Internal video connector is primary, but video can come out of external
video connector if you connect to it.
J6A3, 2-3 jumpered: External video connector is primary, but video can come out of internal
video connector if you connect to it.
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Pins
ME Firmware Update Mode
1-2
Disabled (Default)
2-3
Enabled
Pins
Mode
Description
1 – 2
DCD to DTR
Data Carrier Detect
3 – 4
DSR to DTR
Data Set Ready
6.1.6 ME Firmware Force Update (J7A2)
The ME firmware consists of two operational images and a recovery image. During boot, the
recovery loader is started first and it tries to load the active firmware image by running the
loader of this image. If it fails to boot, it tries to boot the other operational image. If both fail, the
recovery loader starts in recovery mode. The recovery mode can also be forced setting the
MGPIOx jumper on the board. Boot image verification and boot failure
6.1.7 Serial Interface (J6A2)
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Pin
Signal Name
Pin
Signal Name
1
+3.3V
13
+3.3V
2
+3.3V
14
-12V
3
GND
15
GND
4
+5V
16
PS_ON
5
GND
17
GND
6
+5V
18
GND
7
GND
19
GND
8
PWR_GD
20
NC 9 SB5V
21
+5V
10
+12V
22
+5V
11
+12V
23
+5V
12
+3.3V
24
GND
Pin
Signal Name
1
GND
2
GND
3
GND
4
GND
5
+12V
6
+12V
7
+12V
8
+12V
Pin
Signal Name
1
SMB_PWR_CLK
2
SMB_PWR_DAT
3
SMB_PWR_ALRT
4
GND
5
3.3V Remote Sense
7. Connector/Header Locations and Pin-out
7.1 Power Connectors
Table 23. SSI SKU 24-pin 2x12 Connector (J9B3)
Table 24. CPU 12V Power 2x4 Connector (J5K1)
Table 25. SSI Power Control (J9D1)
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Pin
Signal Name
1
GND
2
GND
3
GND
4
GND
5
+12V
6
+12V
7
+12V
8
+12V
Pin
Signal Name
1
SMB_PWR_CLK
2
SMB_PWR_DAT
3
SMB_PWR_ALRT
4
Remote Sense Return
5
12V Remote Sense
6
PS_ON
7
5V S/B
Pin
Signal Name
1
5V 2 5V 3 GND
4
Powergood
5
3.3V
6
GND
Table 26. 12-V only 2x4 Connector (replaces EPSD12V 2x12 connector) (J9D2)
Table 27. 12-V Only Power Control (replaces the 1x5 power control) (J9D1)
(FOXCONN ELECTRONICS INC HF1107V-P1 or TYCO ELECTRONICS CORPORATION 5-104809-6)
Table 28. Peripheral Power (Only for 12-V only SKU) (J8K2)
(iPN: C22293-003 MOLEX CONNECTOR CORPORATION 43045-0627)
Note: This connector is for output power only. The 5V is limited to 6.5A and the 3.3V is limited
to 2A. Pin 4 is a 3.3V output Power Good signal if needed for a backplane
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Pin
Description
Note
1
RST_BMC_PWR_CYC
When power is removed from the BMC.
2
GND
7.2 System Management Headers
7.2.1 Intel
®
Remote Management Module 3 (Intel® RMM3) Connector
A 34-pin Intel® RMM 3 connector (J5B1) is included on the server board to support the optional
Intel® Remote Management Module 3. There is no support for third-party management cards on
this server board.
Note: This connector is not compatible with the Intel
RMM) or the Intel
®
Remote Management Module 2 (Intel
Table 29. Intel® RMM3 Connector Pin-out (J5B1)
®
Remote Management Module (Intel
®
RMM2).
®
7.2.2 BMC Power Cycle Header (12V Only)
A header is provided so you can use an external switch to remove power from the BMC. In
effect, it causes a BMC Power on reset to occur.
Table 30. BMC Power Cycle Header (J1D2)
If this switch is used while the system power is still applied, then the main power rail regulators
is disabled first, then the main 3.3V S/B regulator is disabled, removing power from the BMC.
The usage of this header is to recover a non-responsive board, possibly caused by a
hung BMC.
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Pin
Description
1
LED_HD_ACTIVE_L
2
NC
Pin
Signal Name
Description
1
SMB_IPMB_5VSB_DAT
BMC IPMB 5V standby data line
2
GND
Ground
3
SMB_IPMB_5VSB_CLK
BMC IPMB 5V standby clock line
4
P5V_STBY
+5V standby power
Pin
Signal Name
Description
1
SCLOCK
SGPIO Clock Signal
2
SLOAD
SGPIO Load Signal
3
SDOUT0
SGPIO Data Out
4
SDOUT1
SGPIO Data In
Pin
Signal Name
Pin
Signal Name
1
P3V3_STBY (Power LED Anode)
2
P3V3_STBY (Front Panel Power)
3
Key 4 P5V_STBY (ID LED Anode)
5
FP_PWR_LED_N
6
FP_ID_LED_BUF_N
7
P3V3 (HDD Activity LED Anode)
8
FP_LED_STATUS_GREEN_N
9
LED_HDD_ACTIVITY_N
10
FP_LED_STATUS_A MBER_N
11
FP_PWR_BTN_N
12
NIC1_ACT_LED_N
13
GND (Power Button GND)
14
NIC1_LINK_LED_N
15
BMC_RST_BTN_N
16
SMB_SENSOR_3V3STB_DATA
17
GND (Reset GND)
18
SMB_SENSOR_3V3STB_CLK
19
FP_ID_BTN_N
20
FP_CHASSIS_INTRU
21
NC
22
NIC2_ACT_LED_N
23
FP_NMI_BTN_N
24
NIC2_LINK_LED_N
7.2.3 Hard Drive Activity (Input) LED Header
Table 47. SATA HDD Activity (Input) LED Header (J1D2)
7.2.4 IPMB Header
Table 31. IPMB Header 4-pin (J1B2)
7.2.5 SGPIO Header
Table 32. SGPIO Header (J1B1)
7.3 SSI Control Panel Connector
The server board provides a 24-pin SSI front panel connector (J1E2) for use with SSI compliant
third-party chassis. The following table provides the pin-out for this connector.
Table 33. Front Panel SSI Standard 24-pin Connector Pin-out (J1E2)
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Combined system BIOS and the Integrated BMC support provide the functionality of the various
supported control panel buttons and LEDs. The following sections describe the supported
functionality of each control panel feature.
7.3.1 Power Button
The BIOS supports a front control panel power button. Pressing the power button initiates a
request that the Integrated BMC forwards to the ACPI power state machines in the chipset. It is
monitored by the Integrated BMC and does not directly control power on the power supply.
Power Button — Off to On
The Integrated BMC monitors the power button and the wake-up event signals from the
chipset. A transition from either source results in the Integrated BMC starting the powerup sequence. Since the processors are not executing, the BIOS does not participate in
this sequence. The hardware receives the power good and reset signals from the
Integrated BMC and then transitions to an ON state.
Power Button — On to Off (operating system absent)
The System Control Interrupt (SCI) is masked. The BIOS sets up the power button
event to generate an SMI and checks the power button status bit in the ACPI hardware
registers when an SMI occurs. If the status bit is set, the BIOS sets the ACPI power
state of the machine in the chipset to the OFF state. The Integrated BMC monitors
power state signals from the chipset and de-asserts PS_PWR_ON to the power supply.
As a safety mechanism, if the BIOS fails to service the request, the Integrated BMC
automatically powers off the system in four to five seconds.
Power Button — On to Off (operating system present)
If an ACPI operating system is running, pressing the power button switch generates a
request via SCI to the operating system to shut down the system. The operating system
retains control of the system and the operating system policy determines the sleep state
into which the system transitions, if any. Otherwise, the BIOS turns off the system.
7.3.2 Reset Button
The platform supports a front control panel reset button. Pressing the reset button initiates a
request forwarded by the Integrated BMC to the chipset. The BIOS does not affect the behavior
of the reset button.
7.3.3 NMI Button
The BIOS supports a front control panel NMI button. The NMI button may not be provided on all
front panel designs. Pressing the NMI button initiates a request that causes the Integrated BMC
to generate an NMI (non-maskable interrupt). The NMI is captured by the BIOS during boot
services time and by the operating system during runtime. During boot services time, the BIOS
halts the system upon detection of the NMI.
7.3.4 Chassis Identify Button
The front panel Chassis Identify button toggles the state of the chassis ID LED. If the LED is
off, pushing the ID button lights the LED. It remains lit until the button is pushed again or until a
Chassis Identify or a Chassis Identify LED command is received to change the state of the
LED.
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State
ACPI
Power LED
Power off
No
Off
Power on
No
Solid on
S5
Yes
Off
S1 Sleep
Yes
~1 Hz blink
S0
Yes
Solid on
7.3.5 Power LED
The green power LED is active when the system DC power is on. The power LED is controlled
by the BIOS. The power LED reflects a combination of the state of system (DC) power and the
system ACPI state. The following table identifies the different states that the power LED can
assume.
Table 34. Power LED Indicator States
7.3.6 System Status LED
Note: The system status LED state shows the state for the current, most severe fault. For
example, if there was a critical fault due to one source and a non-critical fault due to another
source, the system status LED state would be solid on (the critical fault state).
The system status LED is a bicolor LED. Green (status) shows a normal operation state or a
degraded operation. Amber (fault) shows the system hardware state and overrides the
green status.
The Integrated BMC-detected state and the state from the other controllers, such as the SCSI /
SATA hot-swap controller state, are included in the LED state. For fault states monitored by the
Integrated BMC sensors, the contribution to the LED state follows the associated sensor state,
with the priority going to the most critical state currently asserted.
When the server is powered down (transitions to the DC-off state or S5), the Integrated BMC is
still on standby power and retains the sensor and front panel status LED state established prior
to the power-down event.
The following table maps the system state to the LED state.
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Color
State
System Status
Description
Green
Solid on
Ok
System ready
Green
~1 Hz blink
Degraded
BIOS detected
1. Unable to use all of the installed memory (more than one DIMM
installed).1
2. In a mirrored configuration, when memory mirroring takes place
and system loses memory redundancy. This is not covered by
(2). 1
3. PCI Express* correctable link errors.
Integrated BMC detected
1. Redundancy loss such as a power supply or fan. Applies only if
the associated platform subsystem has redundancy capabilities.
2. CPU disabled – if there are two CPUs and one CPU is disabled.
3. Fan alarm – Fan failure. Number of operational fans should be
more than minimum number needed to cool the system.
4. Non-critical threshold crossed – Temperature, voltage, power
nozzle, power gauge, and PROCHOT2 (Therm Ctrl) sensors.
5. Battery failure.
6. Predictive failure when the system has redundant power
supplies.
Amber
~1 Hz blink
Non-Fatal
Non-fatal alarm – system is likely to fail:
BIOS Detected
1. In non-mirroring mode, if the threshold of ten correctable errors
is crossed within the window.1
2. PCI Express* uncorrectable link errors.
Integrated BMC Detected
3. Critical threshold crossed – Voltage, temperature, power nozzle,
power gauge, and PROCHOT (therm Ctrl) sensors.
4. VRD Hot asserted.
5. Minimum number of fans to cool the system is not present or
have failed.
Amber
Solid on
Fatal
Fatal alarm – system has failed or shut down:
BIOS Detected
1. DIMM failure when there is one DIMM present and no good
memory is present.1
2. Run-time memory uncorrectable error in non-redundant mode.1
3. CPU configuration error (for instance, processor stepping
mismatch).
Integrated BMC Detected
1. CPU CATERR signal asserted.
2. CPU 1 is missing.
3. CPU THERMTRIP.
4. No power good – power fault.
5. Power Unit Redundancy sensor – Insufficient resources offset
(indicates not enough power supplies are present).
Off
N/A
Not ready
Main power off
Table 35. System Status LED
Notes:
1. The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide
the contribution to the system status LED.
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State
LED State
Identify active via button
Solid on
Identify active via command
~1 Hz blink
Off
Off
Pin
Side
B
PCI Express* Signal
PCI Express* Signal
Pin
Side
A
Pin
Side
B
PCI Express* Signal
PCI Express* Signal
Pin
Side
A
1
12V
PRSNT1#
1
41
PETxP6
GND
41
2
12V
12V
2
42
PETxN6
GND
42
3
RSVD
12V
3
43
GND
PERxP6
43
4
GND
GND
4
44
GND
PERxN6
44
5
SMCLK
JTAG2
5
45
PETxP7
GND
45
6
SMDATA
JTAG3
6
46
PETxN7
GND
46
7
GND
JTAG4
7
47
GND
PERxP7
47
8
3.3V
JTAG5
8
48
PRSNT2#
PERxN7
48
9
JTAG1
3.3V
9
49
GND
GND
49
10
3.3VAUX
3.3V
10
50
PETxP8
RSVD
50
11
WAKE#
PERST#
11
51
PETxN8
GND
51
KEY
KEY
KEY
KEY
52
GND
PERxP8
52
KEY
KEY
KEY
KEY
53
GND
PERxN8
53
12
RSVD
GND
12
54
PETxP9
GND
54
7.3.7 Chassis ID LED
The chassis ID LED provides a visual indication of a system being serviced. The state of the
chassis ID LED is affected by the following:
Toggled by the chassis ID button
Controlled by the Chassis Identify command (IPMI)
Controlled by the Chassis Identify LED command (OEM)
Table 36. Chassis ID LED Indicator States
There is no precedence or lock-out mechanism for the control sources. When a new request
arrives, all previous requests are terminated. For example, if the chassis ID LED is blinking and
the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is
pressed again with no intervening commands, the chassis ID LED turns off.
7.4 I/O Connectors
7.4.1 PCI Express* Connectors
The Intel® Server Board S5500WB has two PCI Express slots. The pin-outs for the slots are
shown in the following tables.
Table 37. Slot 6 Riser Connector (J4B1)
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Pin
Side
B
PCI Express* Signal
PCI Express* Signal
Pin
Side
A
Pin
Side
B
PCI Express* Signal
PCI Express* Signal
Pin
Side
A
13
GND
REFCLK+
13
55
PETxN9
GND
55
14
PETxP0
REFCLK-
14
56
GND
PERxP9
56
15
PETxN0
GND
15
57
GND
PERxN9
57
16
GND
PERxP0
16
58
PETxP10
GND
58
17
PRSNT2#
PERxN0
17
59
PETxN10
GND
59
18
GND
GND
18
60
GND
PERxP10
60
19
PETxP1
RSVD
19
61
GND
PERxN10
61
20
PETxN1
GND
20
62
PETxP11
GND
62
21
GND
PERxP1
21
63
PETxN11
GND
63
22
GND
PERxN1
22
64
GND
PERxP11
64
23
PETxP2
GND
23
65
GND
PERxN11
65
24
PETxN2
GND
24
66
PETxP12
GND
66
25
GND
PERxP2
25
67
PETxN12
GND
67
26
GND
PERxN2
26
68
GND
PERxP12
68
27
PETxP3
GND
27
69
GND
PERxN12
69
28
PETxN3
GND
28 70
PETxP13
GND
70
29
GND
PERxP3
29 71
PETxN13
GND
71
30
RSVD
PERxN3
30 72
GND
PERxP13
72
31
PRSNT2#
GND
31 73
GND
PERxN13
73
32
GND
RSVD
32 74
PETxP14
GND
74
33
PETxP4
RSVD
33 75
PETxN14
GND
75
34
PETxN4
GND
34 76
GND
PERxP14
76
35
GND
PERxP4
35 77
GND
PERxN14
77
36
GND
PERxN4
36
78
PETxP15
GND
78
37
PETxP5
GND
37
79
PETxN15
GND
79
38
PETxN5
GND
38
80
GND
PERxP15
80
39
GND
PERxP5
39
81
PRSNT2#
PERxN15
81
40
GND
PERxN5
40
82
RSVD
GND
82
Pin-Side B
PCI Express* Spec Signal
Description
Pin-Side A
PCI Express* Spec
Signal
Description
1
12V
1 Reserved 2
12V
2 12V 3
Reserved 3
12V 4
GND
4 GND
5
SMCLK 5
JTAG-TCK 6
SMDATA 6
JTAG-TDI 7
GND
7 JTAG-TDO 8
3.3V
8 JTAG-TMS 9
JTAG-TRST# 9
3.3V 10
3.3VAux 10
3.3V 11
Wake# 11
PERST#
KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY
12
Reserved 12
GND
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Table 38. Slot 1 PCI Express* x8 Connector (J1B3)
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Pin-Side B
PCI Express* Spec Signal
Description
Pin-Side A
PCI Express* Spec
Signal
Description
13
GND 13
REFCLK1+ 14
PETp(0) 14
REFCLK1+ 15
PETn(0) 15
GND 16
GND 16
PERp(0) 17
Reserved 17
PERn(0) 18
GND
1X end
18
GND 19
PETp(1) 19
Reserved 20
PETn(1) 20
GND 21
GND 21
PERp(1) 22
GND 22
PERn(1) 23
PETp(2) 23
GND 24
PETn(2) 24
GND 25
GND 25
PERp(2) 26
GND 26
PERn(2) 27
PETp(3) 27
GND 28
PETn(3) 28
GND 29
GND 29
PERp(3) 30
Reserved 30
PERn(3) 31
PRSNT2# 31
GND 32
GND
4X end
32
Reserved 33
33
Reserved 34
34
GND 35
GND 35
36
GND 36
37
37
GND 38
38
GND 39
GND 39
40
GND 40
41
41
GND 42
42
GND 43
GND 43
44
GND 44
45
45
GND 46
46
GND 47
GND 47
48
PRSNT2# 48
49
GND
8X end
49
GND
Pin
Signal Name
Description
1
V_IO_R_CONN
Red (analog color signal R)
2
V_IO_G_CONN
Green (analog color signal G)
3
V_IO_B_CONN
Blue (analog color signal B)
4
TP_VID_CONN_B4
No connection
5
GND
Ground
6
GND
Ground
7
GND
Ground
7.4.2 VGA Connectors
The following table details the pin-out definition of the external VGA connector (J6A1):
Revision 1.9
Table 39. VGA External Video Connector (J6A1)
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Pin
Signal Name
Description
8
GND
Ground
9
TP_VID_CONN_B9
No connection
10
GND
Ground
11
TP_VID_CONN_B11
No connection
12
V_IO_DDCDAT
DDCDAT
13
V_IO_HSYNC_CONN
HSYNC (horizontal sync)
14
V_IO_VSYNC_CONN
VSYNC (vertical sync)
15
V_IO_DDCCLK
DDCCLK
Pin
Signal Name
Pin
Signal Name
1
Red
2
R_RTN(Red Return)
3
Green
4
G_RTN(Green Return)
5
Blue
6
B_RTN(Blue Return)
7
Vsync 8 GND
9
Hsync GND
11
KEY
12
VIDEO_IN_USE signal
13
DDC_SDA
14
GND
15
DDC_SCL
16
+5V
The following table details the pin-out definition of the internal VGA connector (J1D1):
Table 40. VGA Internal Video Connector (J1D1)
7.4.3 NIC Connectors
The server board provides two stacked RJ-45 / 2xUSB connectors side-by-side on the back
edge of the board (J8A2, J9A1). The pin-out for NIC connectors are identical and are defined in
the following table.
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Table 41. RJ-45 10/100/1000 NIC Connector Pin-out (J8A2, J9A1)
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Pin
Signal Name
Description
1
GND
Ground
2
SATA_TX_P
Positive side of transmit differential pair
3
SATA_TX_N
Negative side of transmit differential pair
4
GND
Ground
5
SATA_RX_N
Negative side of receive differential pair
6
SATA_RX_P
Positive side of receive differential pair
7
GND
Ground
7.4.4 SATA Connectors
The server board provides up to six SATA / SAS connectors:
SATA-0 (J9B2)
SATA-1 (J9B3)
SATA-2 (J9C1)
SATA-3 (J9C2)
SATA-4 (J9B5)
SATA-5 (J9B4)
The pin configuration for each connector is identical and defined in the following table.
Table 42. SATA Connectors
7.4.5 Intel
®
I/O Expansion Module Connector
The server board provides 2x internal 50-pin Intel® I/O Expansion Module style connector
(J2B1, J3B1) to accommodate proprietary form factor Intel® I/O Expansion Modules, which
expand the I/O capabilities of the server board without sacrificing an add-in slot from the riser
cards. There are multiple Intel® I/O Expansion Modules for use on this server board. For more
information on the supported Intel® I/O Expansion Modules, refer to the Intel® Server Board IO
Module Hardware Specification. The following table details the pin-out of the Intel® I/O
Expansion Module connectors.
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Table 43. 50-pin Intel® I/O Expansion Module Connector Pin-out (J2B1, J3B1)
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Pin
Signal Name
Pin
Signal
1
SPA_RTS
5
SPA_RI
2
SPA_DTR
6
SPA_SIN
3
SPA_SOUT_N
7
SPA_DSR
4
GND
8
SPA_CTS
Pin
Signal Name
Pin
Signal Name
1
SPB_DCD
2
SPB_DSR
3
SPB_SIN_N
4
SPB_RTS
5
SPB_SOUT_N
6
SPB_CTS
7
SPB_DTR
8
SPB_RI
9
GND
Pin
Signal Name
Description
1
+5V
USB Power
2
USB_N
Differential data line paired with DATAH0
3
USB_P
Differential date line paired with DATAL0
4
GND
Ground
Pin
Signal Name
Pin
Signal Name
1
+5V 2 +5V 3 USB_N
4
USB_N
5
USB_P
6
USB_P
7
GND
8
GND
9
Key Pin
10
NC
7.4.6 Serial Port Connectors
The server board provides one external RJ-45 Serial A port (J7A1) and one internal 9-pin serial
B header (J1A2). The following tables define the pin-outs.
Table 44. External RJ-45 Serial Port A (COM1) (J7A1)
Table 45. Internal 9-pin Serial B (COM2) (J1A2)
7.4.7 USB Connectors
The following table details the pin-out of the external USB connectors (J7A1, J7A2) found on
the back edge of the server board and the internal connector (J9D3) centered on the right side
of the board.
Table 46. External USB Connector (J8A1, J9A1))
Two 2x5 connectors on the server board provide an option to support an additional four USB
ports. The pin-out is the same for both of the connectors and is detailed in the following table.
Table 47. Internal USB Connector (J1C1 and J9A2)
One low-profile 2x5 connectors (J1D4) on the server board provides an option to support lowprofile USB based embedded flash devices. The pin-out of the connector is detailed in the
following table.
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Pin
Signal Name
Pin
Signal Name
1
+5V 2 NC 3 USB_N
4
NC 5 USB_P
6
NC 7 GND
8
NC 9 Key Pin
10
LED#
Pin
Signal Name
Description
1
GND
Ground
2
12V
Power Supply 12V
3
TACH IN
FAN_TACH signal is connected to the BMC to monitor the fan speed
4
PWM OUT
FAN_PWM signal to control fan speed
Pin
Signal Name
1
GND
2
12V 3 Tach0
4
PWM0
5
GND
6
12V 7 Tach1
8
PWM1
Table 48. Low-Profile Internal USB Connector (J1E3)
7.5 Fan Headers
The server board provides six SSI-compliant 4-pin fan headers and two 8-pin fan headers to be
used for CPU, and IO cooling. The pin configuration for each of the 4-pin fan headers is
identical and defined in the following tables.
Table 49. SSI 4-pin Fan Connector (J2K2, J2K3, J3K1, J7K1, J8K4, J8K5)
Table 50. 8-pin Fan Connector (J2K1 & J8K3)
(MOLEX CONNECTOR CORPORATION 53398-0890 or 53398-0871 )
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8. Intel
The server boards have several onboard diagnostic LEDs to assist in troubleshooting boardlevel issues. This section provides a description the location and function of each LED on the
server board.
®
Light-Guided Diagnostics
8.1 5-V Standby LED
Several server management features of this server board require a 5-V stand-by voltage is
supplied from the power supply. Some of the features and components that require this voltage
must be present when the system is ―Off‖ include the Integrated BMC, onboard NICs, and
optional RMM3 connector with Intel
The LED is located in the lower-left corner of the server board and is labeled ―5VSB_LED‖ is
illuminated when AC power is applied to the platform and 5-V standby voltage is supplied to the
server board by the power supply.
®
RMM3 installed.
Figure 22: 5-V Standby Status LED Location
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A
FLTMEM2R
E
FLTCPU1
B
FLTMEM2
F
FLTCPU1A
C
FLTCPU2A
G
FLTMEM1
D
FLTCPU2
H
FLTMEM1R
8.2 Fan Fault LEDs
Fan fault LEDs are present for the six fans and are located near each CPU fan header.
Figure 23. Fan Fault LED Locations
8.3 System Status LED
The server board provides LED for system status. The following figure shows the LED location.
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Figure 24. System Status LED Location
The bi-color System Status LED operates as follows:
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Color
State
System Status
Description
Green
Solid on
Ok
System ready
Green
~1 Hz blink
Degraded
System degraded:
BIOS detected
1. Unable to use all of the installed memory (more than one
DIMM installed).1
2. In a mirrored configuration, when memory mirroring takes
place and system loses memory redundancy. This is not
covered by (2). 1
3. PCI Express* correctable link errors.
Integrated BMC detected
1. Redundancy loss such as a power supply or fan. Applies
only if the associated platform subsystem has redundancy
capabilities.
2. CPU disabled – if there are two CPUs and one CPU is
disabled.
3. Fan alarm – Fan failure. Number of operational fans should
be more than minimum number needed to cool the system.
4. Non-critical threshold crossed – Temperature, voltage,
power nozzle, power gauge, and PROCHOT2 (Therm Ctrl)
sensors.
5. Battery failure.
6. Predictive failure when the system has redundant power
supplies.
Amber
~1 Hz blink
Non-Fatal
Non-fatal alarm – system is likely to fail:
BIOS Detected
1. In non-mirroring mode, if the threshold of ten correctable errors
is crossed within the window.1
2. PCI Express* uncorrectable link errors.
Integrated BMC Detected
1. Critical threshold crossed – Voltage, temperature, power nozzle,
power gauge, and PROCHOT (therm Ctrl) sensors.
2. VRD Hot asserted.
3. The minimum number of fans required to cool the system are
not present or have failed.
Table 51. System Status LED
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Color
State
System Status
Description
Amber
Solid on
Fatal
Fatal alarm – system has failed or shut down:
BIOS Detected
1. DIMM failure when there is one DIMM present and no good
memory is present.1
2. Run-time memory uncorrectable error in non-redundant mode.1
3. CPU configuration error (for instance, processor stepping
mismatch).
Integrated BMC Detected
1. CPU IERR signal asserted.
2. CPU 1 is missing.
3. CPU THERMTRIP.
4. No power good – power fault.
5. Power Unit Redundancy sensor – Insufficient resources offset
(indicates not enough power supplies are present).
Off
N/A
Not ready
AC power off
Notes:
1. The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to
provide the contribution to the system status LED.
2. Support for an upper, non-critical threshold limit is not provided in default SDR configuration. However if a
user does enable this threshold in the SDR, then the system status LED should behave as described.
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A
FLT_F
E
FLT_A2
B
FLT_E
F
FLT_A1
C
FLT_D1
G
FLT_B
D
FLT_D2
H
FLT_C
8.4 DIMM Fault LEDs
Each DIMM slot has a DIMM Fault LED near the DIMM slot.
Figure 25. DIMM Fault LEDs Locations
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Description
Description
A
ID LED
E
RJ-45 GbE LAN connector
B
Status LED
F
RJ-45 Serial port connector
C
RJ-45 GbE/Dual USB connector
G
DB15 Video
D
Dual USB connector
H
Diagnostic LEDs
8.5 POST Code Diagnostic LEDs
Eight amber POST code diagnostic LEDs are located on the back edge of the server board in
the rear I/O area of the server board by the VGA connector.
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the given POST code to the POST code diagnostic LEDs
on the back edge of the server board. To assist in troubleshooting a system hang during the
POST process, you can use the Diagnostic LEDs to identify the last POST process executed.
For a complete description of how these LEDs are read and a list of all supported POST codes,
refer to Appendix A.
Figure 26. Rear Panel Diagnostic LEDs
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LED
Color
Condition
What It Means
Power/Sleep
Green
On
Power on or S0 sleep
Green
Blink
S1 sleep
Off
Off (also sleep S5 modes)
Status
Green
On
System ready/No alarm
Green
Blink
System ready, but degraded: redundancy lost such as power
supply or fan failure; non-critical temp/voltage threshold; battery
failure; or predictive PS failure.
Amber
On
Critical alarm: Voltage, thermal, or power fault; CPU1 missing;
insufficient power unit redundancy resource offset asserted
Amber
Blink
Non-Critical failure: Critical temp/voltage threshold; VDR hot
asserted; min number fans not present or failed
Off
AC power off: System unplugged
AC power on: System powered off and in standby, no prior
degraded\non-critical\critical state
HDD
Green
Blink
HDD access
Amber
Not Supported
HDD fault
Amber
Not Supported
Predictive failure, rebuild, identify
Off
No access
LAN #1 - Activity
Green
On
LAN link/ no access
Green
Blink
LAN access
Off
Idle
LAN #2 - Activity
Green
On
LAN link/ no access
Green
Blink
LAN access
Off
Idle
Identification
Blue
On
Front panel chassis ID button pressed
Blue
Blink
Unit selected for identification via software
Off
No identification
8.6 Front Panel Support
The Intel® Server Board S5500WB supports SSI standard front panel boards. The front panel
support is provided by a SSI compatible 2x12-pin signal connector. The front panel connector
supports the following diagnostic LEDs.
Table 52. Standard Front Panel Functionality
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9. Design and Environmental Specifications
9.1 Fan Speed Control Thermal Management
Fan speed control supports the following thermal sensors:
Discrete board level digital thermal sensor TMP75
Front panel Temp Sensor (if present)
CPU PECI DTS
DDR3 RDIMM TSOD
Eight front system fan headers for four individual thermal zones
Zone 4 (mem2 fans) responds to memory2 and CPU2 temperatures.
Zone 3 (CPU2 and MEM2 fans) responds to CPU2 and IOH temperatures.
Zone 2 (CPU1 and MEM1 fans) responds to CPU1 and IOH temperatures.
Zone 1 (mem1 fans) responds to memory1 and CPU1 temperatures.
Figure 27: Thermal Zones
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CPU 1
Memory 1
FAN_CPU1
FAN_CPU1A
FAN_MEM1
FAN_MEM1R
PWM_CPU1
PWM_CPU1
PWM_MEM1
PWM_MEM1
Tach 1
Tach 5
Tach 2
Tach 2 & 6
J8E1
J8J4
J8J3
J9E1
LED_Fan_Fault_CPU1
LED_Fan_Fault_CPU1A
LED_Fan_Fault_MEM1
LED_Fan_Fault_MEM1R
The following tables show a basic location of the fan connectors on the board. The first line is
the silk screen name of the connector; the second is the PWM signal name; the third is the
Tach #; and the forth is the reference description. The last is the signal name associated with
the fault LED signal.
Figure 28: Location of Fan Connectors
Table 53. Fan Connector Location & Detail
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CPU 2
Memory 2
FAN_CPU2
FAN_CPU2A
FAN_MEM2
FAN_MEM2R
PWM_CPU0
PWM_CPU0
PWM_MEM0
PWM_MEM0
Tach 3
Tach 7
Tach 4
Tach 4 & 8
J3E1
J2J2
J2J1
J1D5
LED_Fan_Fault_CPU0
LED_Fan_Fault_CPU0A
LED_Fan_Fault_MEM0
LED_Fan_Fault_MEM0R
Table 54. Fan Connector Location & Detail
9.2 Thermal Sensors
9.2.1 Processor PECI Temperature Sensor
The processor thermal control uses a CPU PECI thermal sensor, which is a relative
temperature off PROCHOT# trip point (a -20C reading means 20C below PROCHOT# trip point
temperature). The BMC can get the processor PECI Tcontrol values for each CPU installed to
use/follow the clamped algorithm for component thermal sensor. The following sample SDR
settings could be used:
Revision 1.9
Figure 29. Fans and Sensors Block Diagram
Use Tcontrol (byte 8, bit 0 = 1): Tcontrol value is provided by BIOS via the Set CPU
TControl command for the indicated CPU is used.
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Tcontrol offset Temperature = -2° C
Pos_hyst = 0° C
Neg_hyst = 3° C
Those parameters in turn set the following:
Upper = - CPU PECI Tcontrol + Tcontrol offset
Lower = - CPU PECI Tcontrol + Tcontrol offset – 3C
9.2.2 Memory Temperature Sensor
DDR3 cooling requires thermal throttling to protect memory from overheating. The Intel® Server
Board S5500WB supports both DDR3 UDIMM and DDR3 RDIMM. SPD temperature sensor on
DIMM is anticipated to be available on all DDR3 RDIMM but not for non-ECC UDIMM, so open
loop thermal throttling and closed loop thermal throttling are supported.
Static open loop thermal throttling: The system does not change any of the control
registers in the processor during runtime. OLTT control registers are configured by
BIOS MRC and remain fixed after post.
Static closed loop thermal throttling: The system does not change the control
registers for a closed loop in the processor during runtime. CLTT control registers are
configured by BIOS MRC.
For advanced implementation with dynamic OLTT and CLTT, refer to the VR_Hot Sensor
in VR11.1.
9.2.3 Board Temperature Sensor
For rack-based systems or those systems that do not have a front panel temp sensor, the
board is enabled to use a board-mounted, industry standard TMP75 type temp sensor. This
part is on the IBMC two-wire serial SENSOR bus. The use of digital parts removes calibration
and placement location issues imposed by the alternate analog type sensors.
9.2.4 Thermals Sensor Placement
The I2C\SMBUS based temp sensors are placed such that the ambient air temp can be
measured. Placement near hot components and or downstream of hot components (including
chassis-based hot spots) is avoided. The following figure shows the sensor placement on the
Intel® Server Board S5500WB.
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Location
Description
A
U4K3
Temp Sensor - TMP75
9.3 Heatsinks
The Intel® Server Board S5500WB system cooling solutions rely on heatsinks for CPU cooling.
Chipset and or voltage regulator heatsinks are compatible with the 1U usage.
Revision 1.9
Figure 30: Temp Sensor Location
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Note: The Intel® Thermal Solution STS100P – Passive 1U/2U heatsink was tested for
processors up to and including 95-W TDP (Thermal Design Power). Product order code:
BXSTS100P
9.3.1 Unified Retention System Support
The server board complies with the Intel® Unified Retention System (URS) and the Unified
Backplate Assembly. The server board ships with a made-up assembly of Independent Loading
Mechanism (ILM) and Unified Backplate at each processor socket.
The URS retention transfers load to the server board via the unified backplate assembly. The
URS spring, captive in the heatsink, provides the necessary compressive load for the thermal
interface material. All components of the URS heatsink solution are captive to the heatsink and
only require a Philips* screwdriver to attach to the unified backplate assembly. See the
following figure for the stacking order of the URS components.
The ILM and unified backplate are removable, allowing for the use of non-Intel heatsink
retention solutions.
Figure 31. Unified Retention System and Unified Backplate Assembly
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9.4 Errors
This section outlines how errors are routed in the hardware to ensure appropriate FW action
(logging, fan control, system management, and so forth) is taken when an event occurs.
9.4.1 PROCHOT#
PROCHOT# is a bi-directional signal. The CPU toggles PROCHOT# when it goes into throttling
mode. The duty cycle of PROCHOT# toggling indicates the amount of throttling initiated by the
CPU. FW does not monitor PROCHOT# to determine CPU throttling percentage. Instead, it
obtains outbound CPU throttling data via PECI. The path between the CPU’s and IBMC
(TTL_CPU_PROCHOT#) is there as a backup.
An external source can also toggle PROCHOT# to force the CPU to go into throttling mode.
This usually happens when the system reaches a certain thermal threshold. VRHOT is an
output of the CPU VR controller, which is capable of throttling the CPU via PROCHOT#. Some
simple masking circuitry is required to prevent the VRHOT from asserting the PROCHOT# to
the CPUs at the time of CPU_RST#. This keeps the VRHOT from unintentionally causing the
CPU to disable. FW monitors VRHOT and creates a SEL event if VRHOT is asserted. There is
no fan action as a result of the BMC seeing VRHOT.
9.4.2 THERMTRIP#
THERMTRIP# comes from the CPU. The THERMTRIP# signal is tied to a unique GPI on IBMC
for FW to monitor. The combined THERMTRIP#’s from both CPUs is also tied to the ICH10R
THERMTRIP input to cause an automatic Power Off condition when activated.
9.4.3 CATERR#
The CATERR# signal from the CPU signals a catastrophic error occurred. CATERR# may
signal two types of issues. One type is a warning and is indicated by a pulse on the signal. The
other is the static critical error, which is indicated by a continuously asserted level on the signal.
The BMC only logs the static Critical Error events and ignores the warnings indicated by the
pulse. An error on the CPU is immediately communicated to the ICH10R for notification.
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10. Power Subsystem
10.1 Server Board Power Distribution
Figure 32. Power Distribution Diagram
10.2 Power Supply Compatibility
The Intel® Server Board S5500WB is offered in two models:
SSI SKU: This version of the server board is designed to work with an ―off-the-shelf‖
multi-rail power supply that adheres to the SSI power specification: ―Power Supply
Design Guideline for 2008 Dual-Socket Servers and Workstations‖. You can view SSI
specifications at the following website http://ssiforum.org.
12V SKU: This version of the server board is designed to work with specially-designed
―single rail‖ power supplies that provide 12V and 5V standby current. The server board
has integrated, high-efficiency voltage regulators that produce other voltages required
(for example, 3.3 V, 5 V, and so forth) and can also supply 5 V power required by
hard drives.
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The SSI uses the standard 24-pin and 8-pin power headers along with the 5pin Control
connector. The 12-V only uses two 8-pin power headers, a 7-pin control header and a 6 pin
HDD power connector. For maximum rack server efficiency, a DC 12-V only power supply is
recommended. Appendix A shows connector pin outs.
PMbus communications between the power supply and server board must comply with both
SMBus and I2C Bus timing requirements.
10.3 Power Sequencing and Reset Distribution
The IBMC device is integrated into the power control and reset logic of the system. This design
reduces the discrete logic requirements of previous generations and at the same time permits
FW to manage certain features related to the power on/off control and the reset logic.
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11. Regulatory and Certification Information
11.1 Product Regulation Requirements
Intended Application – This product was evaluated as Information Technology Equipment
(ITE), which may be installed in offices, schools, computer rooms, and similar commercial type
locations. The suitability of this product for other product categories and environments (such as:
medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment),
other than an ITE application, may require further evaluation. This is an FCC Class A device.
Integration of it into a Class B chassis does not result in a Class B device.
11.1.1 Product Safety Compliance
The Intel® Server Board S5520UR complies with the following safety requirements:
UL60950 – CSA 60950(USA / Canada)
EN60950 (Europe)
IEC60950 (International)
CB Certificate & Report, IEC60950 (report to include all country national deviations)
GOST R 50377-92 – Listed on one System Certification (Russia)
Belarus Certification – Listed on System Certification (Belarus)
CE - Low Voltage Directive 73/23/EEE (Europe)
IRAM Certification (Argentina)
11.1.2 Product EMC Compliance – Class A Compliance
FCC /ICES-003 - Emissions (USA/Canada) Verification
CISPR 22 – Emissions (International)
EN55022 - Emissions (Europe)
EN55024 - Immunity (Europe)
CE – EMC Directive 89/336/EEC (Europe)
AS/NZS 3548 Emissions (Australia / New Zealand)
VCCI Emissions (Japan)
BSMI CNS13438 Emissions (Taiwan)
GOST R 29216-91 Emissions - Listed on one System Certification (Russia)
GOST R 50628-95 Immunity –Listed on one System Certification (Russia)
Belarus Certification – Listed on one System Certification (Belarus)
KCC (EMI) (Korea)
11.1.3 Certifications / Registrations / Declarations
NRTL Certification (US/Canada)
CE Declaration of Conformity (CENELEC Europe)
FCC/ICES-003 Class A Attestation (USA/Canada)
C-Tick Declaration of Conformity (Australia)
MED Declaration of Conformity (New Zealand)
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Regulatory Compliance
Country
Marking
UL Mark
USA/Canada
CE Mark
Europe
FCC Marking (Class A)
USA
EMC Marking (Class A)
Canada
CANADA ICES-003 CLASS A
CANADA NMB-003 CLASSE A
BSMI Marking (Class A)
Taiwan
KCC Mark
Korea
BSMI Certification (Taiwan)
GOST – Listed on one System Certification (Russia)
Belarus – Listed on one System Certification (Belarus)
KCC Certification (Korea)
Ecology Declaration (International)
11.2 Product Regulatory Compliance Markings
This Intel Server Board bears the following regulatory marks:
Table 55: Product Regulatory Compliance Markings
11.3 Electromagnetic Compatibility Notices
11.3.1 FCC Verification Statement (USA)
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two
conditions: (1) this device may not cause harmful interference, and (2) this device must accept
any interference received, including interference that may cause undesired operation.
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