Enterprise Platforms and Services Division – Marketing
Intel® Workstation Board S5000XVN TPS Revision History
Revision History
Date Revision Number Modifications
August 2006 1.0 First production S5000XVN Technical Product Specification.
March 2007 1.1 Updated Table 1, Figure 1, and Section 3.1.2.
Added Section 3.6.6.
Updated Section 6.1 and 6.2.
Updated Table 33, Appendix A and Table 44.
Added Section 8.2.
June 2007 1.2 Updated to reflect new processor support and new product codes whereever
applicable.
April 2009 1.3 Updated Section 6.3 BIOS Select Jumper.
Updated the Front Panel SSI Standard 24-pin Connector Pin-out (J1E4) table.
Updated Table 1 and Table 8.
Removed ‘dual-core’ from the processor definition.
April 2010 1.4 Removed section 9.3.7 CNCA (CCC-China).
August 2010 1.5 Added Table 6 for quad rank memory and corrected the title of Table 16.
Disclaimers
Information in this document is provided in connection with Intel® products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's
Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any
express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make
changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Intel
product to deviate from published specifications. Current characterized errata are available on request.
Intel Corporation server baseboards contain a number of high-density VLSI and power delivery components that need
adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of
these components when the fully integrated system is used together. It is the responsibility of the system integrator
that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters
to determine the amount of air flow required for their specific application and environmental conditions. Intel
Corporation cannot be held responsible if components fail or the server board does not operate correctly when used
outside any of their published operating or non-operating limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
®
Workstation Board S5000XVN may contain design defects or errors known as errata which may cause the
*Other brands and names may be claimed as the property of others.
This Technical Product Specification (TPS) provides board-specific information about the
features, functionality, and high-level architecture of the Intel
See the Intel
®
S5000 Server Board Family Datasheet for details about board subsystems,
®
Workstation Board S5000XVN.
including the chipset, BIOS, and server management.
In addition, design level information for specific subsystems can be obtained by ordering the
External Product Specifications (EPS) for a given subsystem. EPS documents are not publicly
available and must be ordered through your local Intel representative.
The Intel
which may cause the product to deviate from published specifications. Refer to the Intel
®
Workstation Board S5000XVN may contain design defects or errors known as errata
®
Server
Board S5000XVN Specification Update for published errata.
1.1 Chapter Outline
This document is divided into the following chapters
Chapter 1 – Introduction
Chapter 2 – Workstation Board Overview
Chapter 3 – Functional Architecture
Chapter 4 – Platform Management
Chapter 5 – Connector and Header Location and Pin-out
Chapter 6 – Configuration Jumpers
Chapter 7 – Light-Guided Diagnostics
Chapter 8 – Power and Environmental specifications
Chapter 9 – Regulatory and Certification Information
Appendix A – Integration and Usage Tips
Appendix B – BMC Sensor Tables
Appendix C – POST Code Diagnostic LED Decoder
Appendix D – POST Code Errors
Appendix E – Supported Intel
Glossary
Reference Documents
®
Server Chassis
1.2 Server Board Use Disclaimer
Intel Corporation server boards support add-in peripherals and contain a number of high-density
VLSI and power delivery components that need adequate airflow to cool. Intel ensures through
its own chassis development and testing that when Intel server building blocks are used
together, the fully integrated system will meet the intended thermal requirements of these
components. It is the responsibility of the system integrator who chooses not to use Inteldeveloped server building blocks to consult vendor datasheets and operating parameters to
determine the amount of air flow required for their specific application and environmental
conditions. Intel Corporation cannot be held responsible if components fail or the server board
does not operate correctly when used outside any of their published operating or non-operating
limits.
Revision 1.5
Intel order number: D66403-006
1
Overview Intel® Workstation Board S5000XVN TPS
2. Overview
The Intel® Workstation Board S5000XVN is a monolithic printed circuit board (PCB) with
features that support the pedestal workstation market.
2.1Workstation Board Feature Set
Table 1. Workstation Board Features
Feature Description
Processors Socket J (771-pin LGA sockets) supporting one or two Intel® Xeon® processors 5000
sequence, with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz.
One half-length/full-height PCI Express* x4 (x4 Throughput) slot
One full-length/full-height PCI Express* x16 (x16 throughput) slot
architecture (24-bit, 2-channel DAC, two stereo 20-bit ADCs)
Support for four SAS hard drives (order codes S5000XVNSASR and BB5000XVNSASR
only)
®
ESB2-E I/O Controller
(order codes S5000XVNSATAR & BB5000XVNSATAR only)
1, and 10 support (order codes S5000XVNSASR & BB5000XVNSASR only)
S5000XVNSASR and BB5000XVNSASR only)
the first 20 pins
one PCI-X slot is populated
with order codes S5000XVNSATAR & BB5000XVNSATAR only) slot
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Intel® Workstation Board S5000XVN TPS Overview
Feature Description
Fans Support for
Two processor fans
Four front hot-swap fans
Two rear system fans
Server Management Support for Intel® System Management Software
2.2Workstation Board Layout
Figure 1. Workstation Board Photograph
Revision 1.5
Intel order number: D66403-006
3
Overview Intel® Workstation Board S5000XVN TPS
2.2.1 Workstation Board Connector and Component Layout
The following figure shows the board layout of the workstation board. Each connector and major
component is identified by a letter. A component descriptions table follows the figure.
G
AB
DC
E
H
F
I
J
RR
QQ
K
L
M
PP
N
OO
NN
MM
O
LL
KK
JJ
II
P
Q
HH
GG
FF
R
S
EE
T
YXW
V
U
AF000499
2
SES I
C (order code
S5000XVNSASR only)
code S5000XVNSASR only)
order code S5000XVNSASR only)
order code S5000XVNSASR only)
DDZBB
AACC
A. PCI-X* 64-bit, 100-MHz fulllength/full-height slot 1
B. PCI-X 64-bit, 133-/100-MHz fulllength/full-height slot 2
C. PCI Express* x4
(S5000XVNSASR) or x8
(S5000XVNSATAR) full-length/fullheight slot 3 (x8 connector)
D. PCI Express* x4 half-length/fullheight slot 4 (x8 connector)
E. CMOS battery T. System fan 4 header II. SATA 2 or SAS 0 (SAS 0 on order
F. PCI Express x16 full-length/fullheight slot 6 (x16 connector)
G. CD-ROM line-in connector V. IPMB connector KK. SATA 4 or SAS 2 (SAS 2 on
P. Processor 1 socket EE. Enclosure management SAS
Q. Processor 2 socket FF. Hot-swap backplane A header
R. Processor 2 fan header GG. SATA 0
S. Processor 1 fan header HH. SATA 1
U. System fan 3 header JJ. SATA 3 or SAS 1 (SAS 1 on
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Intel order number: D66403-006
Intel® Workstation Board S5000XVN TPS Overview
H. P12V4 connector W. System fan 2 header LL. SATA 5 or SAS 3 (SAS 3 on
order code S5000XVNSASR only)
I. Back panel I/O ports X. System fan 1 header MM. USB port
J. Diagnostic and Identify LEDs Y. Processor power connector NN. Front control panel header
K. System fan 6 header Z. USB header OO. SATA software RAID 5 key
connector
L. System fan 5 header AA. IDE connector PP. SAS software RAID 5 key
connector (order code
S5000XVNSASR only)
M. Main power connector BB. Enclosure management SATA
SGPIO header
N. Auxilliary power signal connector CC. Hot-swap backplane B header RR. Chassis intrusion header
The architecture and design of the Intel® Workstation Board S5000XVN is based on the Intel®
S5000X chipset. This chipset is designed for systems that use the Intel
®
Xeon® processor with
system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz.
The chipset contains two main components: the Memory Controller Hub (MCH) for the host
bridge and the I/O controller hub for the I/O subsystem. The chipset uses the Enterprise South
Bridge (ESB2-E) for the I/O controller hub. This chapter provides a high-level description of the
functionality associated with each chipset component and the architectural blocks that make up
the server board.
For more information about the functional architecture blocks, see the Intel
The Memory Controller Hub (MCH) is a single 1432-pin FCBGA package, which includes the
following core platform functions:
System Bus Interface for the processor subsystem
Memory Controller
PCI-Express Ports including the Enterprise South Bridge Interface (ESI)
FBD Thermal Management
SMBUS Interface
This section provides a high-level overview of some of these core functions as they pertain to
this workstation board. You can obtain additional information from the Intel S5000 Server Board Family Datasheet and the Intel 5000 Series Chipset Memory Controller Hub Datasheet.
3.1.1 System Bus Interface
The MCH is configured for symmetric multi-processing across two independent front side bus
(FSB) interfaces that connect to the Intel
uses a 64-bit wide 667, 1066, or 1333 MHz data bus. The 1333-MHz data bus is capable of
transferring data at up to 10.66 GB/s. The MCH supports a 36-bit wide address bus, capable of
addressing up to 64 GB of memory. The MCH is the priority agent for both front side bus
interfaces, and is optimized for one processor on each bus.
®
Xeon® processors. Each front side bus on the MCH
3.1.2 Processor Support
The workstation board supports one or two Intel® Xeon® processors 5000 sequence with system
bus speeds of 667 MHz, 1066 MHz, and1333 MHz, and core frequencies starting at 2.66 GHz.
This workstation board does not support previous generations of the Intel
Note: Only Intel
®
Xeon® processors 5000 Sequence that support system bus speeds of 667
MHz, 1066 MHz, and 1333 MHz are supported on this workstation board. For a list of supported
processors, refer to the following table.
Table 2. Processor Support Matrix
Processor Family System Bus Speed Core Frequency Cache Watts Support
When two processors are installed, both must be of identical revision, core voltage, and
bus/core speed. When only one processor is installed, it must be in the socket labeled CPU1.
The other socket must be empty.
The board is designed to provide up to 130 A of current per processor. This board does not
support processors with higher current requirements.
No terminator is required in the second processor socket when using a single processor
configuration.
3.1.2.2 Common Enabling Kit (CEK) Design Support
The workstation board complies with Intel’s Common Enabling Kit (CEK) processor mounting
and heatsink retention solution. The workstation board ships with a CEK spring snapped onto
the underside of the workstation board beneath each processor socket. The heatsink attaches
to the CEK over the top of the processor and the thermal interface material (TIM). Refer to the
following figure for the stacking order of the chassis, CEK spring, workstation board, TIM, and
heatsink.
The CEK spring is removable, which allows for the use of non-Intel heatsink retention solutions.
Note: The processor heatsink and CEK spring shown in the following diagram are for reference
purposes only. The actual processor heatsink and CEK solutions compatible with this
generation server board may be of a different design.
The MCH supports four fully buffered DIMM (FBD) memory channels. FBD memory uses a
narrow, high–speed, frame-oriented interface referred to as a channel. The four FBD channels
are organized into two branches of two channels per branch. Each branch is supported by a
separate memory controller. The two channels on each branch operate in lock-step to increase
FBD bandwidth. The four channels are routed to eight DIMM sockets and are capable of
supporting registered DDR2-533 and DDR2-667 FBDIMM memory (stacked or unstacked).
Peak theoretical memory data bandwidth is 6.4GB/s with DDR2-533 and 8.0GB/s with DDR2-
667.
On the Intel
Branch 0 consists of channels A and B, and Branch 1 consists of channels C and D. FBD
memory channels are organized into two branches for support of RAID 1 (mirroring).
®
Workstation Board S5000XVN, a pair of channels becomes a branch where
To boot the system, the system BIOS on the workstation board uses a dedicated I2C bus to
retrieve DIMM information needed to program the MCH memory registers. The following table
provides the I
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability,
and Manageability) features. These features include the Intel
®
(Intel
x4 SDDC) for the following:
®
x4 Single Device Data Correction
Memory error detection and correction
Memory scrubbing
Retry on correctable errors
Memory built-in self-test
DIMM sparing
Memory mirroring
®
For more information about these features, refer to the Intel
S5000 Server Board Family
Datasheet.
3.1.3.2 Supported Memory
The workstation board supports up to eight DDR2-533 or DDR2-667 fully-buffered DIMMs (FBD
memory). The following tables show the maximum memory configurations supported with the
specified memory technology.
Table 4. Maximum Eight-DIMM System Memory Configruation – x8 Single Rank
DRAM Technology
x8 Single Rank
Maximum Capacity
Mirrored Mode
Maximum Capacity
Non-mirrored Mode
256 Mb 1 GB 2 GB
512 Mb 2 GB 4 GB
1024 Mb 4 GB 8 GB
2048 Mb 8 GB 16 GB
Table 5. Maximum Eight-DIMM System Memory Configuration – x4 Dual Rank
DRAM Technology
x4 Dual Rank
256 Mb 4 GB 8 GB
512 Mb 8 GB 16 GB
1024 Mb 16 GB 32 GB
2048 Mb 16 GB 32 GB
Maximum Capacity
Mirrored Mode
Maximum Capacity
Non-mirrored Mode
Table 6. Maximum Eight-DIMM System Memory Configuration – x2 Quad Rank
Note: This workstation board supports only fully buffered DDR2 DIMMs (FBDIMMs. See the
®
Intel
Workstation Board S5000XVN Tested Memory List for a list of supported memory for this
server board.
3.1.3.3 DIMM Population Rules and Supported DIMM Configurations
DIMM population rules depend on the operating mode of the memory controller, which is
determined by the number of DIMMs installed. You must populate DIMMs in pairs. DIMM pairs
are populated in the following DIMM socket order:
A1 and B1
C1 and D1
A2 and B2
C2 and D2
DIMMs within a given pair must be identical with respect to size, speed, and organization.
However, DIMM capacities can be different between different DIMM pairs. For example, a valid
mixed DIMM configuration may have 512 MB FBDIMMs installed in DIMM sockets A1 and B1,
and 1 GB FBDIMMs installed in DIMM sockets C1 and D1.
The workstation board is capable of supporting a minimum of one DIMM installed. However, for
system performance reasons, Intel’s recommendation is that at least two DIMMs are installed.
The following diagram shows the recommended minimum DIMM memory configuration.
Populated DIMM slots are shown in gray.
MCH
Branch 0
Channel B
Channel A
DIMM A1
DIMM A2
DIMM B1
DIMM B2
DIMM C1
DIMM C2
DIMM D1
DIMM D2
Branch 1
Figure 13. Minimum 2-DIMM Memory Configuration
Channel C
Channel D
TP02300
Note: The workstation board supports single DIMM mode operation. Intel will only validate and
support this configuration with a single 512 MB x8 FBDIMM installed in DIMM socket A1.
3.1.3.4 Non-mirrored Mode Memory Upgrades
The minimum memory upgrade increment is two DIMMs per branch. The DIMMs must cover the
same slot position on both channels. DIMMs pairs must be identical with respect to size, speed,
and organization. DIMMs that cover adjacent slot positions do not need to be identical.
When adding two DIMMs to the configuration shown in Figure 13 (above), you should populate
the DIMMs in DIMM sockets C1 and D1 as shown in the following diagram. Populated DIMM
sockets are shown in gray.
Revision 1.5
Intel order number: D66403-006
21
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