Intel iSBC 432/100 Hardware Reference Manual

inter

iSBC

432/100™

Processor

Board

Hardware

Reference

Manual

PN

171820-001

I I

11

11

I

iSBC

PROCESSOR

432/100™

BOARD

HARDWARE REFERENCE MANUAL

Manual Order Number:

171820-001

11

I

Intel Corporation,

Copyright©

3065

1981

Bowers Avenue, Santa Clara, California

Intel Corporation

95051

Additional copies

Literature Department
Intel Corporation
3065

Bowers Avenue

Santa

Clara, CA

of

this manual or other Intel literature may

95051

be

obtained from:

The information

Intel Corporation makes no warranty
to, the implied warranties
assume<,

-:ommitment to update nor to keep current the information contained

Intel Corporation assumes no responsibility for the use

in

this document

is

subject to change without notice.

of

of

merchantability and fitness for a particular purpose. lniel Corporation

any kind with regard to this material. including, but not limited

no responsibility for any errors that may appear

in

this document. Intel Corporation

in

this document.

of

any circuicry other than circuitry embodied

make~

no

in

an Intel product. No other circuit patent licenses are implied.

Intel software products are copyrighted
duplication or disclosure

is

subject to restrictions stated

by

and shall remain the property

in

Intel's software license, or as defined

of

Intel Corporation. Lse,

in

ASPR

7-104.9(a)(9).

No

part of this document may

written consent of

Intel Corporation.

The follo,,ing are trademarks of Intel Corporation and its affiliate' and may

be

copied or reproduced

in

any form or

by

any means without the prior

be

used only to identify Intel

products:

BXP

CRI

IC!:-

iCS

lrPt'i

inr

and the combination

DIT

el

of

ICE. iCS. iR\1X. iSBC. iSBX, l\1CS. or R\1X and a numerical suffix.

lntde1i,ion
Intel

le.:

iR~I\

iSHC
iSHX

I

ihrrir'.··

\h1naL~er

\1CS

\1egd~·ha\.."1i\

\licrnnwr

\luliihu'
\lultimoduk

Plu~-A.-Buhhlf

PRO\IPT

Prol1l\\arc

R\1\

~o

~htcn,

~non

LJl'I

~score

ii

This

manual
and principles
hardware/
available in the following documents:

•

iAPX

171860-001.

• Intel

Appiication

contains general information, installation, programming information,

of

operation

architectural information pertaining to the iSBC

for the Intel iSBC

432/

100 Processor Board. Additional

432 General Data Processor Architecture Reference Manual, Order No.

8251

Universal Synchronous/ Asynchronous Receiver/Transmitter,

Note

AP-i6.

• Intel Multibus Specification, Order No 9800683.

• Intel Multibus Interfacing, Application Note AP-28.

432/

PREFACE

100

board

is

Introductory
documents:

• The

• Introduction to the

• GettingStartedontheintellec432/JOO,

• Object Builder User's Guide,

iAPX

432 information, if required,

iAP

X 432 Object Primer, Order No. 171858-001.

iAPX

432 Architecture, Order No. 171821-001.

OrderNo.171819-001.

Order

No. 171859-001.

is

contained

in

the following

• Object Programming Language User's Manual, Order No. 171823-001.

iii

.

~

n

CHAPTER 1
GENERAL

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Equipment Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . l-2

Equipment Required . . . . . . . . . . . . . . . .

Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . !-2

CHAPTER2
PREPARATION

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-l

Unpacking and Inspection . . . . . . . . . . . . . . . . . . . . . .

Installation Considerations . . . . . . . . . . . . . . . . . . . . . 2-l

User Furnished Components . . . . . . . . . . . . . . . . . . . .

Power Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . .

Cooling Requirements . . . . . . . . . . . . . . . . . . . . . . . . .

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . .

Jumper Configuration . . . . . . . . . . . . . . . . . . . . . . . . .

1/0

Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multibus
Multibus

Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial Priority Resolution . . . . . . . . . . . . . . . . . . . . . . .

Parallel Priority Resolution
Serial

1/0

Board Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CHAPTER3

PROGRAMMING

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-l

Memory Addressing and Access . . . . . . . . . . . . . . . . .

1/0

Addressing and Access . . . . . . . . . . . . . . . . . . . . .

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-l

USART Programming . . . . . . . . . . . . . . . . . . .

8251A

Mode Instruction Format . . . . . . . . . . . . . . . . . . . . .

Sync Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Command Instruction Format . . . . . . . . . . . . . . . . .

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INFORMATION

..

. . . . . . . . . . l-2

FOR

USE

Bus

Access . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bus

Configuration . . . . . . . . . . . . . . . . . . . .

.....................

Cabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

INFORMATION

PAGE

l-1
l-l

2-1

2-2
2-2
2-2
2-2
2-2
2-3
2-4
2-4
2-4

2-4
2-l l
2-11
2-12

3-1
3-1

3-1
3-1
3-4
3-4
3-4
3-4
3-4

CONTENTS

PAGE

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Data Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . .

Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8253A PIT Programming . . . . . . . . . . . . . . . . . . . . . . .

Mode Control Word and Count . . . . . . . . . . . . . . .

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Counter Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Frequency/Divide Ratio Selection . . . . . . . .

Synchronous Mode
Asynchronous Mode

iSBC

432/

100

Control and Status Registers . . . . . . . .

........................

.......................

CHAPTER4
PRINCIPLES

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . 4-l

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . .

iAPX

432

Address Generation . . . . . . . . . . . . . . . . . . . . . . . . .

Data Transfer State Machine . . . . . . . . . . . . . . . . . .

Multibus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Serial

1/0
Parallel

Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . .

iAPX

432

Address Generation . . . . . . . . . . . . . . . . . . . . . . . . .

Data Transfer State Machine . . . . . . . . . . . . . . . . . .

Multibus Interface
1/0

Operation

OF

OPERATION

Processor . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1/0

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

General Data Processor . . . . . . . . . . . . .

...........................

..............................

CHAPTERS
REFERENCE

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Replaceable Parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Schematic and Parts Location Diagrams . . . . . . . . . .

Service and Repair Assistance . . . . . . . . . . . . . . . . . . .

INFORMATION

3-5
3-5
3-5
3-5
3-6
3-8
3-8
3-9
3-9
3-9
3-9
3-9

3-10

4-1

4-2
4-2
4-3
4-4
4-7
4-7
4-7
4-7

4-8
4-8
4-8
4-8
4-8
4-8

4-11
4-14

5-1
5-1
5-1
5-1

v

TABLES

TABLE

1-1
2-1
2-2
2-3
2-4
2-5
2-6

2-7

FIGURE

TITLE PAGE

iSBC

432/

100

Specifications . . . . . . . . . . . .

Connector Details . . . . . . . . . . . . . . . . . . . . .

Jumper Selectable Options . . . . . . . . . . . . . .

Multibus Connector P 1 Pin Assignments . .
Multibus Signal Functions
iSBC

432/

100

DC

Characteristics . . . . . . . .

iSBC

432/

100

AC

Characteristics

(Master Mode) . . . . . . . . . . . . . . . . . . . . . .

iSBC

432/

100

l/O

Access

AC

Characteristics . . . . . . . . . . . . . . . . . .

TITLE

-.

. . . . . . . . . . . . .

1-2
2-1
2-2
2-5
2-6
2-7

2-8

2-8

PAGE

TABLE

2-8
2-9

3-1
3-2

5-1

5-2

FIGURE

TITLE

Serial

l/O

Connector J 1 Pin Assignments

Connector J 1

Correspondence . . . . . . . . . . . . . . . . . . . . . 2-12

iSBC

432/

PIT Count Value vs. Rate Multiplier for

Each Baud Rate . . . . . . . . . . . . . . . . . . . . . 3-10

Replaceable

List of Manufacturers' Codes . . . . . . . . . . .

vs

RS-232-C Pin

100

l/O

Address Assignments . .

Parts . . . . . . . . . . . . . . . . . . . . .

PAGE

ILLUSTRATIONS

TITLE

PAGE

2-12

3-2

5-2
5-3

1-1
2-1
2-2
2-3
2-4
3-1

3-2

3-3

3-4

3-5

3-6

3-7
3-8

iSBC

432/

100

Processor Board

Bus

Exchange Timing (Master Mode)

I/O

Access Timing (Read/Write)

Priority Resolution Scheme

Serial

Parallel Priority Resolution Scheme

USART Synchronous Mode Instruction

Word Format

USART Synchronous Mode Transmission

Format

USART Asynchronous Mode Instruction

Word Format

USART Asynchronous Mode Transmission

Format

USART Command Instruction Word

Format

Typical

USART Status Read Format

PIT Mode Control Word Format

USART Initialization and Data

I/O

Sequence

......................

...........................

......................

...........................

...........................

......................

....

.......

.......

.....

.......

.
.
.
.

.

.

.

.

.

.

.

1-1

2-9
2-10
2-10
2-11

3-3

3-3

3-3

3-3

3-4

3-5

3-6

3-7

3-9
3-10

4-1

4-2

4-3
4-4

4-5

4-6
4-7
4-8
4-9

5-1

5-2

PIT Programming Sequence Examples
PIT Counter Register Latch Control Word

Format . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iSBC

432/

100

Processor Board Functional

Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iSBC 4321100 Processor Board Block

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .

Two-Phase Overlapped Processor Clock . .
24-Bit Processor Physical Address to 20-Bit

Multibus Address Conversion . . . . . . . . .

iSBC

432/

100

Data Transfer Routing

to/from

Typical Processor Write Cycle Timing . . . .

Typical Processor Read Cycle Timing . . . .

Eight--Bit Transfer Specification Opcode
Data Tran sf er State Machine State

Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .

iSBC

Schematic Diagram . . . . . . . . . . . . . . . . . . . . 5-7

the Multibus Bus . . . . . . . . . . . .

432/100 Parts Location Diagram . . .

..

3-8

3-9

4-2

4-3
4-3

4-4

4-5
4-9
4-9

4-10

4-12

5-5

vi

CHAPTER 1

1.1

INTRODUCTION

The

iSBC

432/100
compatible
mainframe,
board
Intellec
board
communications
Multibus
interfacing with

implementation

is

designed

microcomputer

contains

control

Processor

a 32-bit VLSI microprocessor. This

to

operate

systems.

an

iAPX

432 microprocessor, a serial

interface,

logic,

and

other

Multibus-compatible

1.2 DESCRIPTION

The iSBC
controlled by
(GDP).

43201

the
Instruction Execution Unit.
set supports a wide range
and
efficient
iSBC 432/100
bus for all

The

data

manipulation
and

memory

432/

100 Processor Board (figure 1-1)

an

iAPX

432 General

GDP

consists

Instruction

secure protection mechanisms.

board

and

of

Decode Unit

of

operations, as well as highly

accesses the Multibus system

1/0

Board

of

as a Multibus master in

programmable

bus expansion drivers for

two VLSI components:

The

data

operations.

is

a Multibus-

the

iAPX

432 Micro-

The

iSBC 432/100

boards.

Data

Processor

and

the 43202

GDP's

addressing modes

instruction

timers,

is

The

GENERAL

An

RS-232-C
by an Intel 8251A
Asynchronous Receiver
standard

19.2K
grammable for
asynchronous serial
(including IBM Bi-sync). In operation, most
transmission characteristics (e.g., character length,
parity,

In
the serial 110
double
addition,
for parity,
transmit
programmable
control lines, serial
are
upper right
or
connector).

CRT

bits/second.

and

both

the

buffered

USART

and

brought

round

baud

synchronous

overrun,

out

corner

cable

INFORMATION

compatible

USART

terminals

operation

rate) are

port

transmit

error

receive clocks are supplied by a
baud

to a 26-pin edge connector (in the

of

(through a standard

serial 110

(Universal

/Transmitter),

at

baud

The

USART

in many synchronous

data

programmable.

and

features half-

and

detection circuits can check

and

framing errors.

rate

generator.

data

lines,

the

board)

port,

Synchronous/

operates with

rates from 110 to

is

individually pro-

transmission

asynchronous

or

receive capability. In

The

The

and

signal

ground

that

mates with flat

controlled

formats

full-duplex,

USART

RS-232-C

board

and

modes,

lines

edge

Figure 1-1. iSBC

432/

1

OO'M

Processor Board

171820-1

1-1

General Information

Three

programmable

16-bit interval timers are pro-

vided by

an

Intel 8253

Programmable

Interval Timer

(PIT). All three timers are reserved for processor

time base generation

and

serial

I/O

baud

rate genera-

tion. Additional

on-board

l/O

registers, containing

processor control

and

status information, may be

accessed from the Multibus bus.

The

iSBC 432/100

board

provides full Multibus arbi-

tration

control

logic. This control logic allows up to
three bus masters to share the Multibus bus in serial
(daisy-chain) fashion

or

up

to

16

bus masters

to

share

the Multibus bus using

an

external parallel priority

resolution network.

The

Multibus

aribtration

logic

operates synchronously with the bus clock, which

is

derived from

another

Multibus master

or

generated

by customer supplied logic. (The

iSBC 432/100

board

does

not

generate the bus clock signal.)

Data

is

transferred by means

of

a handshake between the

controlling master

and

the addressed bus module.

This arrangement allows different speed controllers

to share resources

on

the same bus,

and

transfers via
the bus proceed asynchronously. The transfer speed
is

dependent

on

the transmitting

and

receiving

devices only. This design prevents slower master

modules from being handicapped in their attempts to

iSBC 432/100

gain control

of

the bus,

but

does not restrict the

speed

at

which faster modules can transfer

data

over

the same bus.

1.3 EQUIPMENT SUPPLIED

The following items are supplied with the iSBC
432/

100

Processor Board:

a.

Schematic diagram, drawing no. 171773

b. Assembly drawing, drawing no. 171826

1.4 EQUIPMENT REQUIRED

The iSBC

432/

100 Processor Board

is

designed to

operate in

an

Intellec 800, Intellec Series II, or

Intellec

Series III Microcomputer Development

System.

1.5

SPECIFICATIONS

Specifications

of

the iSBC

432/

100

Processor Board

are listed in table 1-1.

Table 1-1. iSBC 432/100™ Specifications

Word Size

Instruction:

Variable, 6 bits

to

271

bits.

Data:

8,

16,

32,

64,

or

80

bits.

Memory

Addressing

Physical:

1

Megabyte

RAM, ROM,

or

EPROM.

Virtual:

2

40

bytes

Serial

Cojllmunications

Synchronous:

5-,

6-,

7-,

or

8-bit characters. One

or

two

sync

characters.

Automatic sync

insertion.

Asynchronous:

5-,

6-,

7-,

or

8-bit characters. Break

character

generation.

1,

11/2,

or

2

stop

bits. False start bit

detection.

Sample Baud Rate:

Frequency

1

Baud Rate (Hz)

2

(kHz,

software

selectable)

Synchronous

Asynchronous

16

64

307.2

-

19200

4800

153.6

-

9600

2400

76.8

-

4800

1200

38.4

38400

2400

600

19.2

19200

1200

300

9.6

9600

600

150

4.8

4800

300

75

2.4

2400

150

-

1.76

1760

110

-

1-2

iSBC 432/100

General Information

Table 1-1. iSBC 432/100™ Specifications

Interval Timer and Baud Rate Generator

Output Frequencies:

1/0

Addressing

Interface Compatibility

Serial 1/0:

Interrupts:

(Cont'd.)

Notes.

1.

Frequency selected by 1/0 writes of appropriate 16-bit fre­quency factor into

2.

Baud rates shown here are only a sample subset
software programmable rates available. Any frequency from

37.5

to

crystal oscillator and 16-bit

1.228
Rate Generator:

Process

On-board
local accesses are translated to Multibus 1/0 accesses.

EIA

Clear to Send
Request to Send
Data Set Ready

The

INT5/, INT6/,

614.4

MHz±

0.1%

Clock:

1/0 devices recognize

standard

432

CPU

8253

PIT

registers.

of

possible

kHz may be generated utilizing the on-board

(.82

micmsecond nominai period).

37.5

Hz

3.25

microseconds to

timers)

RS-232-C

can generate a single interrupt on the Multibus

or INT7/ lines.

PIT.

to

614.4

kHz

58.25

minutes. (cascaded

an

8-bit 1/0 address. iSBC

signals provided and supported:

Transmitted Data

Received Data

Data Terminal Ready

432/100

Compatible

Environmental Requirements:

Relative Humidity:

Physical Characteristics

Width:

Height:

Thickness:

Weight:

Power Requirements

+
+12V

-12V

Connectors/Cables:

5V

5%

at

4.5

5%

at

40

5%

at

40

A

mA

mA

Refer to Table
paragraph

0°

to

To

90%

30.48

17.15

1.52

453.6

2-15

50° C (32°

without condensation.

cm

(12.00

cm

(6.75

cm

(0.6

inches)

gm

(16

ounces)

2-1

for compatible connector details. Refer to

for recommended types and lengths of 1/0 cables.

to

122°

F)

inches)

inches)

1-3

2.1

INTRODUCTION

This

chapter

provides instructions

for

configuring

the

iSBC

432/

100

Processor

Board

for

operation

in a

user-defined

environment.

It

is

advisable

that

the

contents

of

Chapters 1 and

3 be fully

understood

before

beginning the

configuration

and

installation

procedures described in this

chapter.

2.2

UNPACKING

AND

INSPECTION

Inspect the shipping

carton

immediately

upon

receipt

for evidence

of

mishandling

during

transit.

If

the

shipping

carton

is

severely

damaged

or

waterstained,

request

that

the

carrier's

agent

be present when the

carton

is

opened.

If

the

carrier's

agent

is

not

present

when the

carton

is

opened

and

the contents

of

the

carton

are

damaged,

keep the

carton

and

packing

material

for

the

agent's

inspection.

CHAPTER 2

PREPARATION

FOR

USE

For

repairs

to a product

damaged

in shipment, refer

to the

customer

letter

contained

in

the

shipping car-

ton.

It

is

suggested

that

salvageable shipping

cartons

and

packing

material

be

saved

for

future use in the

event the

product

must

be

reshipped.

2.3 INSTALLATION

CONSIDERATIONS

The

iSBC

432/

100

board

is

designed for use as a bus

master in

an

lntellec 800, Intellec Series II,

or

Intellec

Series III

Microcomputer

Development System.

Important

criteria

for

installing

and

interfacing the

iSBC

432/

100

board

in

this

configuration

are

presented in the following

paragraphs.

Table 2-1. Connector Details

No.

of

Pairs/

Centers

Connector

Intel®

Function

Pins

(inches)

Type

Vendor

Vendor

Part

No.

Part

No.

Serial 13/26

0.1

Flat

Crimp

3M

3462-0001

iSBC

955

1/0

AMP

88106-1

Cable

Connector

ANSLEY

609-2615

Set

SAE

SD6726 SERIES

Serial

13/26

0.1

Soldered

Tl

H312113

N/A

1/0

AMP 1-583485-5

Connector

Serial

13/26

0.1

Wirewrap1

Tl

H311113

N/A

1/0

Connector

Multibus

43/86

0.156

Soldered1

CDC3

VPB01E43DOOA1

N/A

Connector

MICRO PLASTICS

M P-0156-43-BW-4

ARCO

AE443WP1 LESS EARS

VIKING

2VH43/1AV5

Multibus

43/86

0.156

Wirewrap

1,2

CDC3

VFB01E43DOOA1

or

MDS 985*

Connector

CDC3

VP

801E43AOOA1

VIKING 2VH43/1AV5

NOTES:

1.

Connector heights are not guaranteed to conform to

OEM

packaging requirements.

2.

Wirewrap

pin

lengths

are

not

guaranteed

to

conform

to

OEM

packaging

requirements.

3.

CDC

VPB01

... , VPB02 ... , VP804 ... , etc. are

identical

connectors

with

different

electroplating

thickness

or

metal

surfaces.

*"MOS"

is an

ordering

code

only,

and is

not

used

as a

product

name

or

trademark.

MDS® is a

registered

trademark

of

Mohawk

Data

Sciences

Corp.

2-1

:Preparation for Use

2.4

USER

FURNISHED

COMPONENTS

2.7

PHYSICAL

iSBC 432/100

DIMENSIONS

A serial
cable
board

2.5

The

- l

1-1.

2.6

The iSBC 432/100
calories/minute

1/0

must

be installed to interface the processor

to a

CRT

.POWER

iSBC

432/

2V

power supplies

COOLING

connector (see ·table 2-1)

terminal.

REQUIREMENTS

100

board

requires +5V, + l 2V, and

at

the currents listed

REQUIREMENTS

board

(1.33

dissipates 336.5 gram-

BTU/minute),

and

and

RS-232-C

in

table

adequate
circulation must be provided to prevent a
temperature rise above

50° C (122° F). Intellec
systems include fans to provide adequate intake and
exhaust

of

ventilating air.

Table 2-2. Jumper Selectable Options

Fig.

Function

1/0

Base Address

5-1

Grid Ref. Grid Ref.

1B6

Fig.

2C5

5-2

Physical dimensions

of

the iSBC

432/

as follows:
a. Width:
b. Height:
c. Thickness: 1.52 cm

2.8

The iSBC
jumper-selectable options
configure the

30.48 cm (12.00 inches)
17

.15 cm (6.

JUMPER

CONFIGURATION

432/

100 design includes a variety

board

75

inches)

(0.6 inch)

for

his/her

that

allow the user to

particular applica-

tion. Table 2-2 summarizes these options

of

the

grid reference locations
figure

5-1

(parts location diagram)

jumpers

(schematic diagram).

Description

Selects the Multibus base address for on-board
default jumper
value of X is
to table

(79-80*)

determined

3-1

).

Other base addresses are selected as follows:

configures the

by the

address

110

1/0

addresses to

port to be addressed (refer

jumper

100

and

as shown

and

1/0

ports. The

board

are

of

lists the

in

figure 5-2

1X.

The

XACK/Timing

8/16-bit bus access

Bus Lock

I

Processor

Interrupt Signals

•Default jumper configured at the factory

ID

1B8

1B4

187

1C8

1

B7

J

3A6

7C2

2A6

2C4

4D1

7X
6X
5X
4X
3X
2X
1X

The factory default
delay to read and write on-board
not be modified.

Selects 8-or 16-bit Multibus transfer mode. The default
configuration
mode, all Multibus accesses are single-byte accesses. By
jumpering

Default jumper
data transfer. A
many as ten Multibus transfers in
other masters
this jumper and connect

Default jumpr
from
should not be removed.

A board generated interrupt may be routed to one of the
Multibus interrupt lines
86-87*
line is desired. remove this jumper and connect
90-91

45-46,

an

on-board register at

routes the interrupt signal to INT6/. If another

(INT51).

jumper

54-55*

(46-47*)

to

33-34*

selects the ·a-bit transfer mode.

the 16-bit Multibus mode is selected.

65-66*

locks the Multibus bus during each

GDP

initiated data transfer may require as

acquire the bus during GDP transfers, remove

64-65.

permits the

(INT5/, INT6/,

-~

67-68
69-70
71-72
73-74
75-76
77-78
79-80*

provides the

1/0

ports. This

the

GOP

to

1/0

address

or

correct

jumper

8-bit mode. To allow

read its

OOH.

INT?/). Default

88-89

XACK

should

jumper

In

GDP

processor

This

jumper

jumper

interrupt

(INT?/)

this

ID

or

2-2

iSBC 432/100

Preparation for

Use

Table 2-2.

Jumper

Selectable Options

(Cont'd.)

Function

Fig.

5-1

I Fig.

5-2

I

Grid Ref. Grid Ref.

Bus Arbitration

1B7

2A4

User Selectable Inputs

1B6

4C5

GDP

Initialization

1C5

4D6

Serial

1/0

Port

1C4

3C2

*Default

jumper

configured at the factory.

Study table 2-2 carefully while making reference to

figures

5-1

and

5-2.

If

the

default

(factory con-

figured)

jumper

configuration

is

appropriate

for a

particular function, no further action

is

required for

that

function.

If,

however, a different configuration

is

required, remove the default jumper(s)

and/

or

install optional jumper(s) as specified.

For

most

options, the

information

in table 2-2

is

sufficient for

proper

configuration. Additional information, where

necessary,

is

contained in the following paragraphs.

2.9

1/0

ACCESS

All

on-board

1/0

devices

are

accessible only from the

Multibus bus.

The

selection

of

an

1/0

base address

is

performed by the user as described in table 2-2.

By

moving the address selection

jumper,

the most

significant

four

1/0

address bits are fixed as:

Description

Default

jumper

81-82*

routes the Bus Priority Out signal BPRO/

to the Multibus bus. (Refer to table

2-4.)

This

jumper

should

always

be connected when the processor board is inserted in

an

lntellec system

or

used with a serial priority bus resolution

scheme.
The Common Bus Request

signal (CBRQ) from the Multibus

bus is not presently used.
Three user

selectable jumpers are available for system
confiQuration inputs. These three inputs are read throuqh the
processor status port. These inputs

·appear on the

three

most

significant data lines as follows:

Port Associated

Data Bit

Jumper

=0

=1

07

40-41

*

remove

jumper

install jumper*

06

38-39*

remove

jumper

install jumper*

05

36-37*

remove

jumper

install jumper*

In

normal operation (default

jumper

43-44*), the GDP is

initialized when a Multibus master writes

an

initialization

pattern to the processor control 1/0 port and also when the
Multibus INIT I signal is activated. The GDP is held in the
initialized state until the Multibus master subsequently
rewrites the

110

port.

The

serial 1/0 port has three

jumper

selectable options.

Jumper

31-32

provides 1/0 loopback for testing. This

jumper

should not be connected

in

normal operation;

27-28*

provides

an

automatic data set ready response when the data terminal

ready signal is asserted;

29-30*

provides an automatic clear-to­send response when the request-to-send signal is asserted.
User configuration

of

these jumpers is terminal dependent.

A7 A6

AS

A4

Hex

Jumper

0 0 0

1

1

79-80

0 0

1

0

2

77-78

0 0

1 1 3

75-76

0

1 0 0

4

73-74

0

1 0 1

5

71-72

0 1

1

0 6

69-70

0

1 1

1 7

67-68

The least significant four bits

of

the

1/0

address are

determined by the individual

1/0

port; a list

of

1/0

addresses

and

corresponding

I/O

ports

is

given

in

table 3-1.

The

processor ID register always resides

at

Multibus

1/0

address

OOH

and

cannot

be relocated.

Note

that

all Multibus

1/0

addresses generated by

the iSBC 432/

100

board

are even, i.e., the least-

significant address bit

is

always zero. In addition, all

Multibus addresses

(110

or

memory) are generated

using the

on-board

off

set register, as discussed

in

paragraph

4-5.

2-3

Preparation for Use

2.10 MULTIBUS BUS ACCESS

The iSBC

432/

100

board

contains no local memory.

All system memory resides

on

separate Multibus

modules. Both system

memory

and

all

1/0

ports

(including

1/0

ports contained

on

the processor
board) must be accessed via the Multibus bus. Each
GDP

access specifies either a local address

or

a

physical address (refer

to

the discussion in

Chapter

3). Local address requests are translated into
Multibus

1/0

commands; physical address requests

are translated into Multibus memory commands.

The

iSBC

432/

100

board

is

designed to operate with

either 8-bit

or

16-bit memory modules. A user-

selectable

jumper

(table 2-2)

is

provided to select the

8-bit

or

16-bit Multibus transfer mode. (The

board

is
factory-configured to operate in the 8-bit mode.)
GDP

memory accesses may require the transfer

of

one to ten

data

bytes over the Multibus bus. In the

8-

bit mode, all

GDP

memory requests initiate a series

of

single-byte read

or

write accesses. In the 16-bit

mode, all

GDP

multibyte memory requests that

originate

on

even byte boundaries are satisfied by a

series

of

double-byte (16-bit) read

or

write accesses.

All

other

accesses are

performed

in the same manner

as are accesses in the 8-bit mode.

When operating with

iSBC/MDS* 016

16K
RAM memory modules, the 8-bit mode must
be used. The 16-bit

mode

may be used with

iSBC/MDS

032/048/064

RAM memory

modules.

As mentioned earlier, a single

GDP

memory request

may require the transfer

of

ten

data

bytes over the

Multibus bus. In

order

to shorten the overall time

required for these

data

transfers, the bus may be

locked from the beginning

of

the first transfer until

the

GDP

memory transfer has been completed.

Locking the bus eliminates the time required

to·

acquire

and

release the bus for each byte

data

transfer. This

"bus

lock"

feature, which results in

higher processor

throughput,

is

user selectable as

described in table 2-2. The processor

board

is

shipped

with the

"bus

lock"

feature enabled.

The bus lock provision

cannot

be enabled in

systems

with

double-density

diskette
controllers and 8-bit memory if the diskette
controller will operate simultaneously with

· the iSBC 432/100

board.

*"lllDS" is

an

ordering code only, and is not used

as

a

product name or trademark.

MOS®

is

a registered

trademark of Mohawk Data Sciences Corp.

2-4

iSBC 432/100

2.11 MULTIBUS BUS CONFIGURATION

For

system applications, the iSBC

432/

100

board

is

designed for installation in a

standard

Multibus

backplane (e.g.,

an

Intellec Microcomputer Develop-

ment

System). Multibus signal characteristics and

methods

of

implementing a serial

or

parallel priority
resolution scheme for resolving bus contention in a
multiple bus master system are described in the
following paragraphs.

Always

turn

off

the system power supply

before installing

or

removing any

board
from the backplane. Failure to observe this
precaution can cause damage to the

board.

2.12 SIGNAL CHARACTERISTICS

As shown in figure 1-1, connector P 1 interfaces the
iSBC 432/100

board

to the Multibus bus. The pin

assignments for this 86-pin connector are listed in

table

2-3

and

descriptions

of

the signal functions are

provided in table 2-4.

The de characteristics

of

the iSBC

432/

100 bus inter-

face are provided in table 2-5. The ac characteristics

of

the iSBC

432/

100

board

when operating in the

master mode

and

slave mode are provided in tables

2-6

and 2-7, respectively. Bus exchange timing

diagrams are provided in figures

2-1

and 2-2.

2.13 SERIAL PRIORITY RESOLUTION

In a multiple bus master system, bus contention can
be resolved by implementing a serial priority resolu­tion scheme as shown in figure 2-3. Due to the prop­agation delay

of

the

BPRO/

signal path, this scheme

is

limited to a maximum

of

three bus masters capable

of

acquiring

and

controlling the Multibus bus. In the
configuration shown in figure 2-3, the bus master
installed in slot J2 has the highest priority

and

is

able

to acquire control

of

the bus

at

any time because its

BPRN/

input

is

always enabled (tied to ground).

If

the bus master in slot J2 desires control

of

the

Multibus bus, it drives its

BPRO/

output

high

and

inhibits the

BPRN/

input

to all lower-priority bus

masters. When finished using the bus, the J2 bus

master pulls its

BPRO/

output

low

and

gives the

J3

bus master the

opportunity

to

take control

of

the

bus.

If

the J3 bus master does

not

desire to control

the bus

at

this time, it pulls its

BPRO/

output

low
and gives the lowest priority bus master in slot J4 the
opportunity to assume control

of

the bus.

iSBC 4321100

Preparation for Use

Table 2-3. Multibus™ Connector

Pl

Pin

Assignments

Pin*

Signal Function Pin* Signal

Function

1

I

GND

\

AA

ADRF/

\

I

1

Ground

....

2

GND

45

ADRC/

3

+5V

46

ADRD/

4 +5V

47

ADRA/

5

+5V

48

ADRB/

6

+5V

Power

input

49

ADR8/

7 +12V

50

ADR9/

8

+12V

51

ADR6/

Address

bus

9

-5V

52

ADR7/

10

-5V

53

ADR4/

11

GND

l

Ground

54

ADR5/

1"1

I

GND

I

r::r::

ADR2/

1£.

,

.J.J

13

BCLK/

Bus

Clock

56

ADR3/

14

INIT/

System

Initialize

57

AORO/

15

BPRN/

Bus

Priority

In

58

ADR1i

16

BPRO/

Bus

Priority

Out

59

DATE/

17

BUSY/

Bus

Busy

60

DATF/

18

BREQ/

Bus

Request

61

DATC/

19

MRDC/

Memory

Read

Command

62

DATO/

20

MWTC/

Memory

Write

Command

63

DATA/

21

IORC/

1/0 Read

Command

64

DATB/

22

IOWC/

1/0

Write

Command

65

OATS/

23

XACK/

Transfer

Acknowledge

66

DAT9/

Data

Bus

24

INH1/

Inhibit

RAM

67

DAT6/

25

68

DAT?/

26

69

DAT4/

27

BHEN/

Byte

High

Enable

70

DAT5/

28

ADR10/

Address

bus

bit

10

71

DAT2/

29

CBRQ/

Common

Bus

Request

72

DAT3/

30

AOR11

/

Address

bus

bit

11

73

DATO/

31

CCLK/

Constant

Clock

74

DAT1/

32

ADR12/

Address

bus

bit

12

75

GND

}

Ground

33

INTA/

Interrupt

Acknowledge

76

GND

34

ADR13/

Address

bus

bit

13

77

35

INT6/

Interrupt

request

on

levern

78

36

INT?/

Interrupt

request

on

level 7

79

-12V

37

INT4/

Interrupt

request

on

level 4

80

-12V

38

INT5/

Interrupt

request

on

level 5

81

+5V

Power

input

39

INT2/

Interrupt

request

on

level 2

82

+5V

40

INT3/

Interrupt

request

on

level 3

83

+5V

41

INTO/

Interrupt

request

on level 0

84

+5V

42

INT1 I

Interrupt

request

on level 1

85

GND

}

Ground

43

ADRE/

86

GND

*All

odd-numbered

pins

(1,3,5 ...

85)

are

on

component

side

of

the

board. Pin 1 is

the

left-most

pin

when

viewed

from

the

component

side

of

the

board

with

the

extractors

at

the

top. All

unassigned

pins

are

reserved.

2-5

Preparation for Use

iSBC

432/lQO

Table 2-4. Multibus™ Signal Functions

Signal Functional Description

ADRO/ADRF/ Address. These

20

lines transmit the address of the memory location

or

1/0 port to be

AOR10/-ADR13/ accessed. For memory access,

ADRO/

(when active low) enables the even byte bank

(DATO/-DAT71) on the Multibus bus; i.e.,

ADRO/

is active low for all even addresses. ADR13/

is the most significant address bit.

BCLK/ Bus Clock. Used to synchronize the bus contention logic on all bus masters. BCLK/ is

approximately

10

MHz with a worst case 35/65 percent duty cycle.

BHENI

Byte High Enable. When active low, enables the odd byte bank (DAT8/-DATFI) onto the
Multibus bus.

BPRN/

Bus Priority In. Indicates to a particular bus master that no higher priority bus master is
requesting use of the bus. BPRN I is synchronized with BCLK/.

BPRO/

Bus Priority Out.

In

serial (daisy chain) priority resolution schemes,

BPRO/

must be

connected to the

BPRN

I input of the bus master with the next lower bus priority.

BREQ/

Bus Request.

In

parallel priority resolution schemes, BREQ/ indicates that a particular bus

master requires

control of the bus for one or more data transfers. BREQ/ is synchronized

with BCLK/.

BUSY/

Bus Busy. Indicates that the bus is in use and prevents all

other

bus masters from gaining

control of the bus. BUSY I is synchronized with BCLK/.

CBRQ/

Common Bus Request. Indicates that a bus master wishes control of the bus but does not
presently have

control. As soon

as

control of the bus is obtained, the requesting bus con-

troller raises the CBRQ/ signal.

CCLK/

Constant Clock. Provides a clock signal of constant frequency for use by other system
modules. CCLK/ is approximately

10

MHz with a worst case 35/65 percent duty cycle.

DATO/-DATF/

Data. These

16

bidirectional data lines transmit data to, and receive data from, the

addressed memory location

or

1/0 port. DATF/ is the most-significant bit. For data byte

operations, DATO/-DAT7/ is the even byte and DAT8/-DATF

I is the odd byte.

INH1/

Inhibit RAM. For system applications, allows

RAM

addresses to be overlaid by

ROM

I PROM

or memory mapped 1/0 devices.

INIT/

Initialize. Resets the entire system to known internal state.

INTA/

Interrupt Acknowledge. This signal is issued in response to

an

interrupt request.

INTO/-INT7 /

Interrupt Request. These eight lines transmit Interrupt Requests to the appropriate
interrupt handler.

INTO

has the highest priority.

IORC/

1/0 Read Command. Indicates that the address of

an

1/0 port is on the Multibus address

lines, and that the output of that port is to

be

read (placed) onto the Multibus data lines.

IOWC/

1/0 Write Command. Indicates that the address of

an

1/0 port is on the Multibus address
lines, and that the contents on the Multibus data lines are to be accepted by the addressed
port.

MRDC/

Memory Read Command. Indicates that the address of a memory location is on the
Multibus address

lines, and that the contents of that location are to be read (placed) on the

Multibus data

lines.

MWTC/

Memory Write Command. Indicates that the address of a

memory

location is on the

Multibus address

lines, and that the contents on the Multibus data lines are to be written

into that location.

XACK/

Transfer Acknowledge. Indicates that the address memory location has completed the

specified read

or

write operation. That is, data has been placed onto,

or

accepted from, the

Multibus data lines.

2-6

iSBC 432/100

Table 2-5. iSBC 432/100™ DC Characteristics

Preparation for

Use

r

Signals

XACK/

ADRO/-ADRF/

ADR10/-ADR13/

BHENi

BCLK/

CCLK

BPRN/

BPRO/ ,BREQ/

BUSY/

,CBRQ/,

(OPEN COLLECTOR)
DATO/-DATF/

INIT/
(SYSTEM RESET)

INT5/-INT7/
IORC/ ,IOWC/

MRDC/ ,MWTC/

l

I

Symbol

Vol
VoH
VIL
VIH
Ill
llH

Vol
VoH
VIL
VIH
Ill
llH
ILH

1

LL

VIL
VIH

1

1L

llH
VIL

VIH
1

1L

llH
VIL

VIH
Ill
llH

Vol
VoH

Vol

Vol
VoH
VIL
VIH
Ill
llH

VIL
VIH
Ill
llH

Vol
Vol

VoH
ILH
ILL
VIL
VIH
Ill
llH

Vol
VoH
ILH
ILL

Parameter

Description

Output

Low Voltage

Output

High Voltage t0H

Input

Low
Input High Voltage
Input
Input

Output
Output
input
Input High Voltage
Input
Input
Output
Output

Input
Input High Voltage
Input
Input

Input
Input High Voltage
Input
Input

Input Low Voltage
Input High Voltage
Input
Input

Output
Output

Output

Output
Output
Input
Input High Voltage
Input
Output

Input
Input High Voltage
Input
Input

Output
Output

Output
Output
Output
Input
Input
Input
Input

Output
Output
Output
Output

Voltage

Current

Current

Low Voltage

Current

Current

Low Voltage

Current

Current

Low Voltage

Current

Current

Current

Current

Low Voltage

Current

Low Voltage

Current

Current

Low Voltage

High Voltage

Current
Current

at Low V
at High V

Low

Voltage

High Voltage

at Low V

at High V
Leakage High
Leakage Low

at

Low

at High V

at Low V

at High V

at Low V

at High V
Low

Voltage

High Voltage
Low Voltage

Low Voltage
High Voltage

at Low V

Leakage High

at Low V

at High V

Low

Voltage

Low Voltage
High Voltage t0H
Leakage High
Leakage Low

at

Low

at High V

Low Voltage t0L
High Voltage
Leakage High
Leakage

Low

V

V

Conditions

l

t

0

VIN
VIN

t

0

loH

VIN

VIN

v
v 0 =0.45V

VIN
VIN

VIN
VIN

VIN
VIN

loL
loH

loL

loL
loH

VIN

v

VIN
VIN

loL
loL

V0=5.25V
Vo

VIN
VIN

loH

v
v

Test

L

=16

=-2.6

=0.4V
=2.7V

L

=32

=-5

=0.45V
=2.7V

=5.25V

0

=0.45V

=10

=20

=32

=5.25V

0

=16
=32

=0.4V

=.4V
=2.7V

=32

=5.25V

0

=.4V

0

mA

mA

mA

=0.45V
=5.5V

=0.4V
=2.7V

=5.5V

mA

=-0.4

mA

mA

=-5

mA

=0.45V

=0.4V
=2.4V

mA
mA

=-5

mA

mA

=-5

mA

mA

mA

Min. Max.

I

0.4

2.4

2.0

2.4

2.0

2.0

2.0

2.0

2.4

2.4

2.0

2.0

2.4

2.0

2.4

0.8

-0.4
20

0.45

0.8

-2.2

100

50

-50

0.8

-0.5
60

-0.4
20

0.8

-0.5
60

0.45

0.45

0.45

0.90

-0.80

200

0.8

-0.9
80

0.4

0.5

100

-100

-.4
20

0.5

100

-100

Units

l

v
v
v
v

mA
µA

v
v
v
v

mA
µA
µA
µA

v
v

mA
µA

.8

v
v

mA

µA

v
v

mA

µA

v
v

v
v

v
v
v

mA

µA

v
v

mA

µA

v
v

v

µA
µA

.8

v
v

mA
µA

I

v
v

µA
µA

2-7

Preparation for Use

iSBC 432/100

Table 2-6. iSBC 432/100™ AC Characteristics (Master Mode)

Minimum

Maximum

Parameter

(ns)

(ns) Description

Remarks

tAS

50

Address setup time to command

tAH

50

Address hold time from command

tos

50

Data setup to write

GMO

toHW

50

Data hold time from write CMD

tcv

198

202

CPU

cycle time

tcMDR

594

Read command width

tcMDW

594

Write command width

tcswR

396

Read-to-write command separation

In

override mode

tcsRR

396

'Read-to-read command separation

In

override mode

tcsww

594

Write-to-write command separation

In

override mode

tcsRw

594

Write-to-read command separation

In

override mode

tsAM

198

202

Time between XACK samples

to

HR

0

Read data hold time

toxL

-400

Read data setup to XACK

txAH

0

XACK hold time

tBs

23

BPRN

to BCLK setup time

to

BY

55

BCLK to BUSY delay

tNOD

30

BPRN

to

BPRO

delay

to

Bo

40

BCLK I to bus priority out

tBcv

100

Bus clock period (BCLK)

tBw

.35tBcv

.65tBcv

Bus clock low

or

high interval

Supplied by system

ti NIT

3000

Initialization width

After all voltages
have stabilized

Table 2-7. iSBC

432/

100™

1/0

Access

AC

Characteristics

Minimum Maximum

Parameter

(ns) (ns)

Description Remarks

tAs

50

Address setup to command From address to

command

tos

-100

Write data setup to command

tACK

4

tBcv

Command to XACK

tcMO

400

Command width

tAH

50

Address hold time

toHW

50

Write data hold time

toHR

25

125

Read data hold time

txAH

50

Acknowledge hold time

Acknowledge turn­off

delay

tACC

300

Read to data valid

toxL

100

Read data setup to XACK

2-8

iSBC 432/100

BCLK/

BREQ/

BPRN/

BUSY/

BPRO/

ADDRESS

WRITE

DATA

WRITE

COMMAND

WRITEXACK/

READ

COMMAND/

READ

DATA

READ

XACK/

1

acv---..j

I

'aw---1

H

r-

taw

Preparation for Use

I

tt~.J

--------------

~

tas

=7

_J

~1---------____,r(

___

_

l.--1DBY

~

l.:==1Dao

=7

\

STABLE

ADDRESS

~

(

=7

J

~TABLE

DATA

x T

IAS·

IDS

.____r-

____

--1____,i:==

'AH·

'DHW

\w

•

......_~~~~~tcMDw~~~~~-----4https://manualmachine.com/r-----------

\'--__

__;.

____________

--'7

IACKWT\

u

__J

k-

txAH

STABLE

DATA

IDXL~

r-

---1

I

L.DHR

*

CBRQ/

timing

not

shown

relative

to

other

bus signals

other

than

BCLK/.

Figure 2-1. Bus Exchange Timing (Master Mode)

171820-2

2-9

Preparation

for Use

ADDRESS

IORC/

or

IOWC/

XACK

1

READ DATA

WRITE DATA

I

x

HIGHEST
PRIORITY
MASTER

J2

15

BPRN/

r--

1

I

I B

I

I N

I

I

BPRO/

IAS

STABLE ADDRESS

IACK

IACC

tDs

STABLE DATA

Figure 2-2.

1/0

Access Timing (Read/Write)

J3

15

BPRN/

16 16

BPRO/

c

E

LOWEST
PRIORITY
MASTER

J4

15

BPRN/

BPRO/

16

H

iSBC432/100

IAH

IOHW

~

x=

BPRO/ AND BPRN/ PINS
NOT USED BY
NON-MASTERS

---,

I

I

: BACKPLANE

I

I

171820-3

L_

-------

- - -

---

- - -

------

-

-----

--

------

- - - -

_j

Figur 2-3. Serial Priority Resolution Scheme

171820-4

2-10

iSBC 432/100

NO.

2

PRIORITY

J2

(NOTE

1)

15

BPRN/

18

BREQ/

N0.1

PRIORITY

(HIGHEST)

J3

(NOTE

1)

15

BPRN/

BREQ/

15

18

BUS

PRIORITY

RESOLVER

(NOTE

2)

7 p

R

'-----------<116

I

p 0

R

I 1

0

BREO/INPUTS
FROM MASTERS
IN BACKPLANE

0

5 R

I

4 T

y

E

2 N

c

1 0

D

0 E

R 2

I

T 3

y

NOTE: REFER TO TEXT REGARDING THE

DISABLING OF

BPRO/

OUTPUT.

Preparation

for Use

NO.

8

NO.

7

PRIORITY

PRIORITY

(LOWEST)

J4

JS

(NOTE

1)
15

(NOTE

1)

BPRN/

BPRN/

BREQ/

Figure 2-4. Parallel

Priority

Resolution Scheme

171820-5

2.14 PARALLEL PRIORITY
RESOLUTION

A parallel priority resolution scheme allows up to

16

bus masters

to

acquire

and

control the Multibus bus.

Figure 2-4 illustrates one

method

of

implementing
such a scheme for resolving bus contention in a
system containing eight bus masters. Notice

that

the

two highest

and

two lowest priority bus masters are

shown installed in the system backplane.

In the scheme shown in figure 2-4, the priority

encoder is a 7 4148

and

the priority decoder

is

an· Intel

8205.

Input

connections

to

the priority encoder deter-

mine the bus priority, with

input

7 having the highest

priority

and

input

0 having the lowest priority (the

15

bus master has the lowest priority).

IMPORTANT:

In a parallel priority resolution

scheme, the

BPRO/

output

must be disabled

on

all

bus masters.

On

the iSBC

432/

100

board,

the

BPRO/

output

signal may be disabled by removing

jumper

40-41.

2.15 SERIAL

I/O

CABLING

Pin assignments

and

signal definitions for the

RS-232-C serial

1/0

interface are listed in table 2-8.

An Intel iSBC

955

cable set may

be

used for inter-

facing. The serial cable assembly consists

of

a
25-conductor flat cable with a 26-pin printed circuit
board

edge connector

at

one end and a 25-pin

RS-232-C interface connector

at

the other end.

2-11

Preparation

for Use

iSBC 432/100

Pin

10
12
13
14

2

4
6
8

Table 2-8. Serial

1

NOTES:

1.

All odd-numbered pins
right-most pin when viewed from the component side of the board with the extractors at the
top.

2.

For applications without

8251A

CTS

input.

3.

For applications without

8251

A

DSR

input.

Signal

PROTECTIVE

RXD
TXD

2

cTs

2

RTs

3

DTR

3

DSR
SIGGND

(1,

CTS

DSR

1/0

Connector

GND

3,

5,

... ,

25)

are

capability, connect jumper

capability, connect jumper

For applications where ,cables may be made by the
user for the iSBC
note

that

the mating connector for J 1 has

whereas the RS-232-C connector has

432/

100

board,

it

is

important to

25

pins. Conse-

26

pins

quently, when connecting the 26-pin mating connec­tor to 25-conductor flat cable, be sure
makes contact with pins 1 and 2
nector

correspondence between the

(JI)

cable to

and

and

not

with pin 26. Table 2-9 provides pin

board

an

RS-232-C connector. When attaching the

JI,

be sure

that

the

PC

connector

that

the cable

of

the mating con-

edge connector

is

oriented
properly with respect to pin 1 on the edge connector.
(Refer to the footnote in table 2-8.)

2.16 BOARD INSTALLATION

Always
supply before installing
iSBC
removing device interface cables. Failure to
take these precautions can result in damage
to the

turn

432/

100

board.

off

the computer system power

or

removing the

board

and before installing

or

JI

Pin

Assignments

Description

Protective Chassis Ground

8251A

receiver data input

8251A

transmitter data output

8251

A Clear-to-send input

8251A

Request-to-send output

8251

A Data Terminal Ready output

8251A

Data Set Ready input

Signal Ground

on

the component side of the board. Pin 1 is the

5-6.

This routes

3-4.

This routes

In

an

Intellec system, install the iSBC 432/100

8251A

8251A

RTS

DTR

(RXD)

(CTS)

(DSR)

output to

output to

in any odd-numbered slot except slot I
appropfiate serial
connector

JI

Table 2-9. Connector J 1

PC

Conn.

J1

1
2
3
4
5
6

7

8

9
10
11
12
13

1/0

.

Pin

Correspondence

RS232C

Conn.

14 14

1

15 16

2

16

3

17

4

18

5

19

6

20

cable assembly to the edge

Vs

PC

(TXD)

(RTS)

(DTR)

and

RS-232-C

Conn.

J1

15

17

18

19

20
21
22
23
24
25
26

board

attach the

RS232C

Conn.

7

21

8

22

9

23

10

24

11

25

12

N/C

13

2-12

3.1

INTRODUCTION

This chapter lists
the effects
programming information for the Intel
USART (Universal
Receiver/Transmitter), the Intel 8253
mabie intervai Timer),
status registers.

A complete description
General
programming,
found in the

Data

Architecture Reference Manual,

171860-00

I.

1/0

address assignments, describes

of

hardware initialization, and provides

Processor

and

protection

iAPX

432 General Data Processor

Synchronous/

and

the on-board controi and

of

the Intel iAPX 432

(GDP)-its

Asynchronous

PIT

(Program-

instruction set,

mechanisms-may

Order

CHAPTER 3

PROGRAMMING INFORMATION

3.3

1/0

ADDRESSING AND ACCESS

GDP

local address references are translated into

8251

No.

A

be

Multibus
accesses (including accesses to on-board devices)
occur via
located
logically situated
access the
address generation
as memory address generation (described in
paragraph 4-5).

3.4 INITIALIZATION

1/0

read/write

the Multibus bus.

on

the iSBC

board's

432/

on

the bus.

1/0

is

performed in the same manner

commands. All

1/0

ports physically

100 Processor Board are

Any

bus master may

ports (listed in table 3-1).

1/0

port

1/0

3.2

MEMORY

ADDRESSING

AND ACCESS

The iSBC
memory; all
over the Multibus architecture.
address references are translated into Multibus

memory
generated by the
off

set register
processor to share Multibus memory with the
432/

When the
bus) each
or
access mechanisms are described in detail beginning
in paragraph 4-4. Briefly, to perform Multibus

transfers, the iSBC
control
memory location

Memory Write

until a Transfer Acknowledge
from the addressed memory module. When the

transfer
releases the bus to permit
When a
data
one Multibus transfer, a

the processor

the complete sequence

feature eliminates the time required to release

regain bus control between
increasing

width requirements.

432/

100 Processor Board contains no local

GDP

memory accesses are processed

read/write

100

processor.

GDP

GDP

more 8/16-bit Multihus

of

the bus.

is

completed, the iSBC 432/100

GDP

transfer

that

throughput

commands. Physical addresses

GDP

are modified by an on-board

to

permit an Intellec

addresses memory (via the Multibus

access request

432/

100

After

and

issuing a Memory Read

command,

access request specifies a multibyte

must be translated into more

"bus

board

to

retain Multibus control for

of

and

GDP

or

is

implemented as one

data

transfers. Memory

board

must first gain

addressing the correct

the processor board waits

(XACK/)

other

masters

lock"

Multibus transfers. This

data

transfers, thereby

lowering Multibus band-

physical

iSBC system

iSBC

data

or

is

received

data

board

to

use it.

than

feature permits

and

The Multibus initialization signal line (INIT
activated, resets the
USART
Command

The

In addition to the
Multibus master may reset the
processor reset flag (contained within the processor
control

to

enter

Words to program the desired function.

8253

PIT

register-refer

is

3.5 8251A USART

The USART converts parallel
serial

output

half-

or

verts serial input

Prior

to the start

tion, the

words. These control words, which define the com-

plete functional operation

immediately follow a reset (internal

control words are either Mode instructions
Command

data

full-duplex operation. The USART also con-

USART

instructions.

GDP

and

causes the 8251A

an

"idle"

not

affected by the INIT I signal.

INIT

state waiting for a set

I reset sequence, another

GDP

to

table 3-1).

PROGRAMMING

output

format

data

of

data

must be loaded with a set

(e.g., IBM Bi-Sync) for

into parallel

transmission

data

of

the USART, must

or

/),

when

of

by writing the

data

into a

format.

or

data

recep-

of

control

external).

The

or

3.6 MODE INSTRUCTION FORMAT

The Mode instruction word defines the general
characteristics
operation.

of

the

Once the

USART

Mode

and

must follow a reset

instruction word has been

3-1

Programming

Information

iSBC 432/100

Table 3-1. iSBC

1/0

Address

00
XO

X2

X4

X6

X8

XA

xc

XE

XE

R/W

R

R/W

R/W

R/W

R/W

R/W

R/W

w

R

w

432/

100™

1/0

Address Assignments

Description

ID

Processor

8253

PIT

Process Clock Timer

Read:
Write:

Process

'Read: Counter 1

Write: Counter 1

Baud Rate Generator

Read: Counter 2
Write: Counter 2

Read:
Write:

8251A

Read: Data (J1)
Write: Data (J1)

Read:
Write: Mode

Memory Address Offset Register (contains
8-bit memory
operations)

Processor

bit#

0
1

2

3 stop command active

4

5-7

Processor Control

bit#

0 release
1 issue

2 issue
3 stop

4 issue

Register

Counter
Counter

Clock Timer

None
Control

USART

Status

offset

Status Register

description

processor
interrupt pending
GDP

accesses stopped

fatal error
user selectable

description

initialized state

Multibus
interprocessor

munication request

GDP

alarm signal

0
O (load count)

(load count)

(load count)

or

Command

for all memory addressing

initialization hold

jumpers

processor

accesses

from

interrupt

com-

an

Note:

Xis

jumper

written into the

mand

instructions

instruction

a.

For

Synchronous Mode:

(

1)

Character

(2)

Parity

(3)

Even/

(4) External sync detect

iSBC

(5) Single-

USART,

may

word

defines the following:

length

enable

odd

parity generation

432/100

board)

or

double-character sync

sync characters

be inserted.

(not

3-2

selectable

The

and

check

supported

or

Mode

by the

(1-7)

as described in table

com-

b.

Instruction
synchronous
figures

2-2.

For

Asynchronous
Baud

(1)
(2)

Character

(3)

Parity
Even/odd

(4)

Number

(5)

word

3-1

through

Mode:

rate factor

(Xl,

X16,

or

X64)

length

enable

parity generation

of

stop

bits

and

data

transmission formats for

and

asynchronous modes are shown in

and

check

3-4.

iSBC 432/100

CHARACTER

Lti'llGTH

0

1

0

1

0 0

1 1

5

6

7

a.

BITS

BITS

BITS

BITS

'----------

PARITY

ENABLE
11=ENABLEI
IO=DISABLEI

'------------

EVEN

PARITY

GENERATION/CHECK

1

=EVEN

0

=OOD

EXTERNAL

SYNC

DETECT

1 =

SYNDET

IS

AN

INPUT

O=SYNDET

IS AN

OUTPUT

SINGLE

CHARACTER

SYNC

l=SINGLE

SYNC

CHARACTER

O=

DOUBLE

SYNC

CHARACTER

NOTE IN

EXTERNAL

SYNC MODE.

PROGRAMMING

DOUBLE

CHARACTER

SYNC

WILL

AFFECT

ONLY

THE

Tx

Figure 3-1.

USART

Synchronous Mode

Instruction Word Format

111820-s

SYNC

CHAR

1

RECEIVE

FORMAT

SYNC

CHAR

1

CPU

BYTES

15 8 BITS'CHARI

DATA

CHARACH

RS

...._

____

..,.)

1--1

____

....

ASSEMBLED

SERIAL

DATA

OUTPUT

ITxDI

SYNC

CHAR

2

DAT

A c H

~JR~,_

A_c_T_E

_Rs

___

....

SERIAL

DATA

INPUT

iRxDI

SYNC

CHAR

2

DATA

CHARACTERS

CPU

BYTES

15

8 BITS

CHARI

DATA

CHl~l;ACTERS

Figure 3-2.

USART

Synchronous Mode

Transmission Format

111820-1

11

Programming Information

c

BAUD

RATE

FACTOR

0

1

0

1

0

0

1 1

SYNC

llXI

116XI

164XI

MODE

CHARACTER

LENGTH

0

1

0 1

0 0 1 1

s 6 7

8

BITS BITS

BITS

BITS

'----------

~~~l~~:L~ABLOE~

DISABLE

'------------

EVEN

PARITY

GENERATION.CHECK

1=EVEN

O•ODD

NUMBER

OF STOP BITS

0

1

0

1

0

0

1 1

INVALIO

1

,.

2

BIT

BITS

BITS

(ONLY EFFECTS

TX;

RX

NEVER
REQUIRES MORE THAN ONE
STOP BIT)

.Figure 3-3.

USART

Asynchronous Mode

Instruction Word Format

111820-8

GENERATED

TRANSMITTER

OUTPUT

Do

D1----Dx

BY

8251A

I

START

BIT

DATA

BITS

PARITY

BIT

ST~

BITS

L

RECEIVER

INPUT

DoD1----Dx

DOES NOT APPEAR
ON

THE

DATA

BUS

RXD

---i

STARTT

~

i t

B~IT_Si"'----P-A-Rl_T_Y--S"""'T6;1

~

BIT

BITS

L

-,-

PROGRAMMED

CHARACTER

LENGTH

TRANSMISSION

FORMAT

START

BIT

CPU

BYTE

15 8 BITS/CHARI

DATA

C~~RACTER

ASSEMBLED

SERIAL

DATA

OUTPUT

ITxDI

DATA

CHARACTER

PARITY

BIT

BITS

STOD

.....

____

...._

___

......

_-!

RECEIVE

FORMAT

SERIAL

DATA

INPUT

IRxDI

.._s_T_~_~_T__..

___

D_A_TA_c_H-4ARA~-CT_E_R

__

..._P_A_:_1~_y__...__s

......

~~~

CPU

BYTE

15 8 BITS/CHARI"

: I

DATA

CHA~ACTER

'NOTE

IF

CHARACTER

LENGTH

IS

DEFINED

AS

5.

6 OR 7

BITS

T+tE

UNUSH>BHS

ARE SET TO

"lEAO"

Figure 3-4.

USART

Asynchronous Mode

Transmission Format

111820-e

3-3

Programming Information

3.7 SYNC CHARACTERS

Sync characters are written to the USART in the
synchronous mode only.

The

USART can be pro-

grammed for either

one

or

two sync characters; the

format

of

the sync characters

is

at

the option

of

the

programmer.

3.8 COMMAND INSTRUCTION FORMAT

The

Command

instruction word shown in figure

3-5

controls the

operation

of

the addressed USART. A

Command

instruction

must

follow the mode

and/

or

sync words. Once the

Command

instruction has been

written,

data

can

be transmitted

or

received by the

USART.

~

EH J IR

I RTS l

ER

ISBRKI

RXEl

DTR

lTXEN

[

~

TRANSMIT

ENABLE

1 '

enable

0 ·

disable

DATA

TERMINAL
READY
..

high''

will

lorce

OTR

output

to

zero

RECEIVE

ENABLE

1

enable

0

disable

SEND

BREAK

CHARACTER

1 = forces

TXD

"low"

0 = normal

operation

ERROR

RESET

1 - reset

error

flags

PE. OE. FE

REQUEST

TO

SEND

-

"high"

will

force

ATS

output

to

lero

INTERNAL

RESET

''high"

returns

8251 A to

Mode

Instruction

Format

ENTER HUNT

MODE•

1 °

enable

..,arch

lor

Sync

Characters

"IHASNOEFFECT

IN

ASYNC MOOE I

Note: Error Reset must be performed whenever RxEnable

and Enter Hunt are programmed.

Figure 3-5. USART Command

Instruction Word Format

111s20-10

3-4

iSBC 432/100

It

is

not

necessary for a

Command

instruction to

precede all

data

transactions; only those trans-

missions

that

require a change in the

Command

instruction.

An

example

is

a change in the transmit

enable

or

receive enable flag.

Command

instructions

can be written

to

the

USART

at

any time

after

one

or

more

data

operations.

After initialization, always read the chip status

and

check for the

TXRDY

bit

prior

to writing either

data

or

command

words to the USART. This ensures

that

any prior

input

is

not

overwritten

and

lost. Note

that

issuing a

Command

instruction with bit 6 (IR) set will

return the

USART to the Mode instruction

format.

3.9 RESET

To

change the

Mode

instruction word, the USART

must receive a Reset

command.

The next word writ-

ten to the

USART

after

a Reset

command

is

assumed

to be a Mode instruction.

Similarly, for sync mode,

the next word

after a mode

instruction

is

assumed

to

be the first

of

one

or

more sync characters. All con-

trol words written

into

the USART after the Mode

instruction

(and/

or

the last sync character) are

assumed to be

Command

instructions.

3.10 ADDRESSING

The USART chip uses address X8 to read

and

write

110

data; address

XA

is

used to write mode

and

com-

mand words

and

read the USART status. (Refer to

table 3-1.)

3

.11

INITIALIZATION

A typical

USART

initialization and

1/0

data

sequence

is

presented in figure 3-6. The USART chip

is

initialized in four steps:

a. Reset the

USART

to the Mode instruction

format.

b. Write the Mode instruction word.

One function

of

the mode word

is

to specify synchronous

or

asynchronous operation.

c.

If

synchronous

mode

is

selected, write one

or

two

sync characters as required.

d. Write the

Command

instruction word.

First, reset the

USART chip by writing a

Command

instruction to location XA. The

Gommand

instruc-

tion must have bit 6 set (IR

=

1);

all other bits are

immaterial.

iSBC 432/100

ADDRESS

RESET

OOOA

MODE

INSTRUCTION

l

OOOA

SYNC

CHARACTER

1

I

SYNC

MODE

_f

ONLY*

OOOA

SYNC

CHARACTER

2

OOOA

COMMAND

INSTRUCTION

0008

.,r"

DATA

I/

0

-,...

OOOA

COMMAND

INSTRUCTION

0008

::~

110

DATA

~

OOOA

COMMAND

INSTRUCTION

*The second sync character

is

skipped

if

Mode instruction has

programmed

USART to single character internal sync mode.
Both sync characters are skipped if Mode instruction has
programmed

USART to async mode.

Figure

3-6.

Typical

USART

Initialization

and

Data

I/O

Sequence

rna20-11

NOTE

This reset

procedure

should be used only if

the

USART

has been completely initialized,

or

the initialization procedure has reached

the

point

that

the

USART

is

ready

to

receive

a

Command

word.

For

example, if the reset

command

is

written when the initialization
sequence calls for a sync character, then
subsequent

programming

will be in error.

Next write a

Mode

instruction word

to

the USART.

(See figures

3-1

through

3-4.)

If

the

USART

is

pro-

grammed for the synchronous mode, write one

or

two sync characters depending

on

the transmission

format.

Finally, write a

Command

instruction

word

to

the

USART. Refer to figure 3-5.

IMPORTANT:

During initialization, the 8251A

USART requires a

minimum

.recover-y time

of

2.4

microseconds

(6

clock cycles) between back-to-back

writes in

order

to set

up

its internal registers. This

precaution applies only

to

the

USART

initialization

and

does

not

apply

at

any

other

time.

Programming Information ·

3.12 OPERATION

Normal

operating

procedures use

data

read

and

write, status read,

and

Command

instruction write

operations.

Programming

and

addressing procedures

for the above

are

summarized in the following

paragraphs.

NOTE

After

the

USART

has been initialized,

always check the status

of

the

TXRDY

bit

prior

to

writing

data

or

writing a new com-

mand

word

to

the

USART.

The

TXRDY

bit

must

be

true

to

prevent overwriting

and

subsequent loss

of

command

or

data

words.

The

TXRDY

bit

is

inactive until initializa-

tion has been completed;

do

not

check

TXRDY

until

after

the

command

word,
which concludes the initialization procedure,
has been written.

Prior

to

any

operation

change, a new

command

word

must

be.

written with

command

bits changed as

appropriate.

(Refer

to

figure 3-5.)

3.13

DATAINPUT/OUTPUT

For

data

receive

or

transmit

operations,

perform

a

GDP

local read

or

write, respectively,

to

the

USART.

During

normal

transmit

operation,

the

USART

sets

the

Transmit

Ready (TXRDY) flag. This flag

indicates

that

the

USART

is

ready

to

accept a

data

character for transmission.

TXRDY

is automatically

reset when a

character

is

loaded into the

USART.

Similarly, during

normal

receive

operation,

the

USART

sets the Receive Ready (RXRDY) flag. This

flag indicates

that a character

has been received

and

is

ready

for

input

to

the processor. RXRDY

is

automatically reset when a character

is

read from the

USART.

TXRDY

and

RXRDY are available in the

status word. (Refer

to

paragraph

3-14.)

3.14 STATUS READ

Any Multibus

master

can determine the status

of

the

serial

1/0

port

by issuing

an

1/0

Read

Command

to

the upper address (XA)

of

the

USART

chip. The

format

of

the status

word

is

shown in figure 3-7.

3.15 8253 PIT

PROGRAMMING

A 14. 7456

MHz

crystal oscillator supplies the master

time base for

GDP

process timing

and

serial

I/0.

This basic frequency

is

divided by twelve

to

provide

the 1.2288

MHz

input

clock for

counter 0 and

counter 2.

The

output

of

counter 0 is

routed to the

3-5

Programming Information

clock

input

for

permits

the

microseconds
counter 2 is
and

receive

(RXC)

counter

generation

to

used

over

to

supply

clocks.

1.

This

cascaded

of

time· intervals from 3 .25

58 minutes.

the

8251 A

arrangement

The

output

transmit

3.16 MODE CONTROL WORD AND
COUNT

All three
use.
two steps:

a. A

b. A

counters

The

initialization

mode

control

down-count
counter;
or

two

word.

must

control

register

word

for

number

the

down-count

8-bit bytes as

be initialized

for

each

counter

(figure 3-8)

each individual

is

loaded

number

determined

by

prior

consists

is

written to the

counter.

into

consists

mode

of

(TXC)

to their

of

each

of

one

control

The

mode

control

following:
a. Selects the
b. Selects
c. Selects

read/load

(1)

(2)
(3)
(4)

counter

the

counter

one

functions:
Counter
Read

or

Read

or

Read

or

of

latch
load
load

load

most-significant byte.

d.

Sets

the

counter

The

mode

control

for any given

word

counter

ing sequence:
a.

Mode

control

word.
b. Least-significant
c. Most-significant

iSBC

432/100

word

(figure 3-8) does the

to

be

loaded.

operating

mode.

the following

(for

stable read

operation).

four

counter

most-significant byte only.
least-significant byte only.

least-significant byte first, then

for

either

binary

or

BCD

count.

and

the

count

register bytes

must

be entered in the follow-

count

register byte.

count

register byte.

l

DATA

DSR

DSR
used
Data

SET

is

to
Set

l

SYNDET

SYNC

When
cates
achieved

READY

general

test

modem

Ready.

I

FRAMING

DETECT

set

for

that

character

and

purpose.

conditions

FE

FE

flag
detected
is

reset
lion.

FE

8251.

internal

8251

Normally

OE

I

OVERRUN

The
not
one
the
OE
8251;
character

ERROR

is

set

when a valid

at

end

by

ER

bit

does

not

sync
sync

is

ready

such

as

PE

I

ERROR

OE

flag

is

set

read a character

becomes

available.

ER

bit

of

the

does

not

inhibit

however.

the

is

lost.

(ASYNC

ONLY)

stop

of

every

character.

of

Command

inhibit

operalon

detect,

indi-

has

been

for

data.

TXE

l

when

the

before

It

Command

operation

previously

bit

is

not

II

is

instruc-

of

l

RXRDY l TXRDY

l

CPU

does

the

next

is

reset

by

instruction.

of

the

overrun

]

L__

L..--

4

TRANSMITTER

Indicates
data

RECEIVER

Indicates
acter
lo

TRANSMITTER

Indicates

verier

PARITY

PE
detected.
mand
operation

character

on

transfer

in

ERROR

flag

is

instruction.

READY

USART

or

READY

USART

its

serial

it

to

EMPTY

that

parallel

transmitter

set

when a parity

II

is

reset

of

8251.

is

ready

command.

has

received a char-

input

the

CPU.

to

is

by

ER

PE

does

lo

and

serial

empty.

bit
not

accept

is

ready

error

of

inhibit

con-

Com-

a

is

Figure 3-7. USART Status Read Format

3-6

171820-12

iSBC 432/100

Programming Information

As long
counter,
venient sequence.
can

be

as

the

the

chip

loaded

above

can

For

first

procedure

be

programmed

example,

into

each

is

followed

in

mode

control

of

three counters,

for

any

each
con-

words

followed by the least-significant byte, etc. Figure 3-9
shows two possible

Since all

counters
the value
decremented.
results in a
numbers
count
the
control

or

register

number

word.

07 05

SC1

SCO

in

loaded

Loading

maximum

104 for

is

to

of

bytes

One

05

RL1

IL

programming

the

PIT

chip

in the

all zeroes into a

count

BCD

numbers.

be

loaded,

it

programmed

or

two bytes

04

03

ALO

M2

_JL

sequences.

are

downcounters,

count

count

16

of

2

When

must

be loaded with

in the

can

D2

D1

M1

MO

registers

register

for binary

a selected

mode

be loaded,

Do

BCD

_J

(BINARY/BCD)

is

0

1

depending
two bytes can

mode

the

of

bytes

The

count

counter

the
chip

mode

a.

b.

mode

c.

mode

d.

mode

e.

mode

f.

mode

Binary Counter (16-bits)

Binary Coded Decimal (BCD) Counter
(4 Decades)

on

the

appropriate

be

programmed

control

is

loaded

mode

selected in the

word,

in

output.

can

operate

in

any

0-Interrupt

I-Programmable

2-Rate

generator

3-Square

4-Software-triggered

5-Hardware-triggered

as long as the correct

order.

As shown in figure 3-8, the

of

six modes:

on

terminal

one-shot

wave

generator

down-count.

at

any

'time following

control

word controls

count

strobe

strobe

These

number

PIT

M1

MO

M2

0 0 0
0 0

x 1

(MODE)

Mode O

1 Mode 1

Mode 2

0

x 1 1 Mode 3

1

0 0

1

0

RL

1

RLO

0 0

1

0

1 1

SC1

0
0

1

1 1

Mode 4

1

Mode 5

(READ/LOAD)

Counter
to

paragraph

0 Read/Load most significant byte only.

1

Read/Load least significant byte only.
Read/Load least significant byte first,

then most significant byte.

SCO

(SELECT

0

1 Select Counter 1

0 Select Counter 2

~

Use Mode 3 for
Baud Rate Generator

Latching

3-19).

COUNTER)

Select Counter O

Illegal

operation

(refer

Figure 3-8. PIT Mode Control Word Format

171820-13

3-7

Programming Information

iSBC 4321100

PROGRAMMING

FORMAT

ALTERNATE

PROGRAMMING

FORMAT

Step

Step

1

Mode

Control Word

Counter n

1

Mode

Control Word

Counter

0

2 LSB

Count Register Byte

Counter n

2

Mode

Control Word

Counter 1

3

MSB

Count Register Byte

Counter n

3

Mode Control Word

Counter 2

4

LSB

Counter Register Byte

Counter 1

5 MSB

Count Register Byte

Counter 1

6

LSB

Count Register Byte

Counter 2

7

MSB

Count Register Byte

Counter 2

8

LSB

Count Register Byte

Counter

0

9

MSB

Count Register Byte

Counter

0

Figure 3-9.

PIT

Programming Sequence Examples

171820-14

Mode 3, the primary operating mode for

Counter

2,

is

used to generate Baud rate clock signals. In this

mode, the counter

output

remains high until one-half

of

the

count

value in the

count

register has been

decremented (for even numbers). The

output

then

goes low for the

other

half

of

the

count.

If

the value

in the

count

register

is

odd, the counter

output

is

high

for (N

+

1)/2

counts,

and

low for (N -

1)/2

counts.

Counter 0 and

counter 1 normally operate in mode 2.

In this mode, the

output

of

each

counter

will be low

for one period

of

the clock input.

The

period from

one

output

pulse to the next equals the

number

of

input counts in the

count

register.

If

the

count

register

is

reloaded between

output

pulses, the pres-

ent period will

not

be affected,

but

the subsequent

period will reflect the new value. When mode 2

is

set,

the

output

of

the counter will remain high until

after

the couTtt register

is

loaded.

3.17 ADDRESSING

As listed in table 3-1, the

PIT

uses four

I/

0

addresses. Addresses

XO,

X2,

and

X4, respectively,

are used in loading

and

reading the

count

in Counters

0,

1,

and

2. Address X6

is

used in writing the mode

control word to the desired counter.

3-8

3.18 INITIALIZATION

To

intialize the

PIT

chip,

perform

the following:

a. Write mode control word for

Counter

0 to

address X6.

Note

that

all mode control words are

written

to

X6, since the

mode

control word

specifies which

counter

is

being programmed.

(Refer to figure 3-8.)

b. Assuming the mode control word has selected a

2-byte load,

load

the least-significant byte

of

count

into

Counter 0 at

address

XO.

c.

Load

the most-significant byte

of

count

into

Counter 0 at

address

XO.

NOTE

Be

sure

to

enter the down-count in two bytes

if the

counter

was

programmed

for a two­byte entry in the mode control word.
Similarly, enter the

down

count

value in

BCD if the counter was so programmed.

d. Repeat steps b, c,

and

d for Counters 1

and

2.

iSBC 432/100

3.19

OPERATION

The following

paragraphs

describe operating pro-

cedures for counter reading, and for clock

frequency I divide ratio selection.

3.20

COUNTER

READ

Since the gates

of

all counters are constantly enabled,

the 8253 counters can only be read

"on

the

fly."

The

recommended

procedure

is

to

use a

mode

control

word

to

latch the contents

of

the

count

register; this

ensures

that

the

count

reading

is

accurate

and

stable.

The

latched value

of

the

count

can then be read.

NOTE

If a counter

is

read

during the down-count, it

is

mandatory

to

complete

the

read

procedure;

that

is, if two bytes were pr0--

grammed

to

the

counter,

then two bytes

must be read

before

any

other

operations are

performed

with

that

counter.

To

read the

count

of a particular

counter, proceed as

follows:
a. Write

counter

register latch

control

word (figure

3-10) to address X6. This

control

word specifies

the desired

counter

and

selects the

counter

latching

operation.

b.

Perform

a read

operation

of

the desired counter;

refer

to

table

3-1

for

counter

addresses.

NOTE

Be

sure

to

read

one

or

two bytes, as specified

in the initialization

mode

control

word.

For

two bytes, read in the

order

specified.

TL

I I

Loon't

Care

Selects Counter Latching

L

Operation

Specifies Counter

to

be

Latched

Figure 3-10.

PIT

Counter Register

Latch Control Word Format

1?1s20-15

Programming Information

3.21 CLOCK

FREQUENCY

/DIVIDE

RA

TIO

SELECTION

To

operate the 8251A serial

I/O

port,

counter 2 must

be loaded with a

down-count

value (N).

When

count

value N

is

loaded into a

counter,

it becomes the clock

divisor.

To

derive N for either synchronous

or

asyn-

chronous RS-232-C

operation,

use the procedures

described in following

paragraphs.

3.22 SYNCHRONOUS MODE

In the synchronous

mode,

the

TXC

and/or

RXC

rates equal the Baud rate.

Therefore,

the

count

value

is

determined by:

N=CB

where N

is

the

count

value,

B

is

the desired

Baud

rate,

and

C

is

1.2288

MHz,

the

input

clock frequency.

Thus, for a

4800 Baud rate, the required

count

value

(N) is:

N =

1.2288 X 10

6

=

256

4800

-·

If

the binary equivalent

of

count

value N = 256

is

loaded into

Counter

2, then the

output

frequency

is

4800 Hz, which

is

the desired clock rate for syn-

chronous

mode

operation.

3.23 ASYNCHRONOUS MODE

In the

asynchronous

mode,

the

TXC

and/or

RXC

rates equal the Baud

rate

times

one

of

the following

multipliers:

XI,

X16,

or

X64. Therefore, the

count

value

is

determined by:

N

=C/BM

where N

is

the

count

value,

B

is

the desired

Baud

rate,

M

is

the Baud

rate

multiplier (1, 16,

or

64),

and

C

is

1.2288

MHz,

the

input

clock frequency.

Thus, for a

4800 Baud rate, the required

count

value

(N) is:

N =

1.23 X 10

6

=

16

4800X18

_;

If

the binary equivalent

of

count

value N =

16

is

loaded into

Counter

2, then the

output

frequency

is

4800 X

16

Hz, which

is

the desired clock rate for

3-9

Programming Information

asynchronous mode operation.

Count

values (N) ver-

sus rate multiplier (M) for each Baud rate are listed

in

table 3-2.

NOTE

During initialization, be sure to load the
count

value (N) into counter 2

and

the Baud

rate multiplier (M) into the

825

lA

USART.

Table

3-2.

PIT

Count

Value vs.

Rate

Multiplier

for

Each

Baud

Rate

Baud Rate:

Count

Value (N)* For

(B) M = 1 M =

16

M=64

75

16384

1024

256

110

11171

698

175

150

8192

512

128

300

4096

256

64

600

2048

128

32

1200

1024

64

16

2400

512

32

8

4800

256

16

4

9600

128

8

2

19200

64

4

38400

32

*Count Values (N) assume clock is

1.2288

MHz. Count

Values (N) and Rate Multipliers (M) are in decimal.

3.24 iSBC 432/100 CONTROL AND
STATUS REGISTERS

In addition

to

the previously described

1/0

devices,

the processor

board

also contains a write-only con­trol register and a read-only status register as listed in
table 3-1.

The

status register contains iSBC

432/

100

operational information as follows when each bit

is

set:

Bit Number Description

3-10

0 Processor Initialization Hold. The

GDP

is
held in the initialized state. When this bit is
reset, the

GDP

is executing instructions.

Interrupt

Pending.

A GDP

interrupt

request has been issued.

2 Processor Access Stopped. The

iSBC

432/100

board has stopped Multibus

accesses.

The GDP may

continue

executing until the next Multibus access

i!:>
attempted.

3

Stop Request.

An

access stop request has

been issued. When the iSBC

432/100

board
acknowledges this request, the Processor
Access Stopped flag (bit 2 above) is set.

Bit Number

4

5-7

iSBC 432/100

Description

Fatal Error. The

GDP

has entered a state
from which it cannot continue executing.
For

example, a fatal error can be caused by

the corruption

of

system data structures.

User Selectable Jumpers. Three flags that
may be

individually selected by the user.

IMPORTANT: The Fatal Error signal is connected to a red
LED

in the upper left corner of the processor board. When

this

LED

is lit, a fatal

error

has occurred and the

GDP

has

suspended execution. The.

iSBC

432/100

processor must

be re-initialized to continue execution.

The processor control register contains five software

controlled

command

flags

that

control processor

initialization

and

interprocessor communication as

follows:

Bit Number Description

O Initialize Processor. When reset, this

command flag holds the

GDP

in the initial-

ized state. When the

flag is subsequently

set, the

GDP

begins execution.

Issue Multibus Interrupt. When set, this
flag sets the Interrupt Pending flag

in

the

status register and generates

an

interrupt

request on the appropriate Multibus

level

(see table

2-2).

2

Issue

Interprocessor

Communication
Request. Reserved for future implementa­tion. This flag should always be reset.

3

Stop Multibus Access Request. Setting
this flag causes the iSBC

432/100

board to

stop Multibus accesses. After stopping
Multibus activity, the Processor Access
Stopped flag (bit 2 in the status register) is

set. When this flag is reset, the processor
board continues with the next access. The
GDP may

continue

executing

while

Multibus accesses are stopped.

4

Issue Alarm Signal. Activation of this

signal causes a

GDP

ALARM condition.

This command

flag is automatically reset

(by the

iSBC

432/100

hardware) after the

ALARM condition is initiated.

NOTE

When interfacing the iSBC 432/100

Pro-

cessor Board

to

another

system processor

(e.g., in

an

Intellec Microcomputer Develop­ment System), the processor interrupt
capabilities should be fully utilized for

synchronization

and

communication. These
interrupt capabilities greatly enhance system
throughput

by eliminating Multibus polling

accesses

and

processor

"busy

wait"

operations.

I

• 0

n

CHAPTER 4

PRINCIPLES

OF

OPERATION

4.1

INTRODUCTION

The iSBC

432/

100 Processor Board

is

designed

to

incorporate the advanced processing features

of

the

iAPX

432 microprocessor into Multibus compatible

systems.

The

43201 Instruction Decode Unit

and

the

43202 Instruction Execution Unit comprise the

iAPX

432 General

Data

Processor (GDP). These LSI

devices form the

heart

of

the iSBC 432/100

board.

The

GDP

operates with a two-phase overlapped

clock

that

is

generated

on-board.

The

GDP

address space

is

divided into two com-

ponents: a local address space

and

a physical address

space.

On-board

logic converts local address space

references into Multibus

1/0

commands; physical
address space references are converted into Multibus
memory

commands.

To

perform

a memory

or

1/0

access, the

GDP

outputs

24

address bits

and

8 bits

of

control

information

(on the processor packet bus) in

two 16-bit cycles. This 24-bit address

is

converted to

a

20-bit Multibus address as described in

paragraph

4-5.

To

perform

this conversion,

an

address offset

register

is

used, permitting the iSBC 432/100

board

to share Intellec system memory with

another

pro-

cessor. All iSBC

432/

100 Multibus memory

references are translated

to

addresses in upper
memory (as specified by the offset value). In this
manner,

software

for

the system processor (e.g., the

Intellec

operating

system)

is

protected from iSBC

432/

100 accesses, allowing

both

processors

to

operate independently.

The iSBC

432/

100

board

is

designed to

operate

within 8-or

16-bit wide Multibus systems; a single

user selectable

jumper

option

configures the

board

for the

appropriate

operating

mode.

For

each

data

transfer, the

GDP

indicates the

number

of

bytes

to

be

transferred by means

of

a three-bit code embedded in

the eight

control

bits

(output

by the

GDP

at

the

start

of

each transfer). This code specifies a one to ten byte

transfer (1, 2, 4, 6, 8,

or

10

bytes). In the 8-bit

transfer mode,

data

reads

and

writes are

performed

one byte

at

a time over the Multibus bus. In the 16-bit

mode,

data

reads

and

writes are

performed

as

follows:

1.

When

a single byte

transfer

is

requested,

an

8-bit

Multibus read

or

write

is

performed.

2.

When

a multibyte transfer

is

requested

on

an

even byte

boundary,

the

appropriate

number

of

16-bit Multibus transfers

is

performed.

3.

When

a multi byte transfer

is

requested

on

an

odd

byte

boundary,

the

appropriate

number

of

8-bit

Multibus transfers

is

performed.

In the 8-bit

mode

a single 80-bit (10 byte) processor

requested read

or

write

operation

requires ten

Multibus accesses. A

jumper

option

is

provided

that

permits the iSBC

432/

I 00 processor

to

lock the bus

during a complete

data

transaction. Using this

"bus

lock"

provision results in faster overall processor

operation.

The

"bus

lock"

cannot

be used in systems

with double-density diskette controllers

and

8-bit

memory

if the disk controller

is

required

to

operate

simultaneously with the

iSBC

432/

100 Processor Board.

The actual

data

transfers in

both

the 8-and

the 16-bit

mode are controlled by a small

FPLA

state machine

in

conjunction

with a

memory

transfer counter. The

state machine determines whether the 8-

or

the 16-bit

transfer

mode

is

active

and

requests the correct

number

of

Multibus accesses. All Multibus accesses

are carried

out

by means

of

an

8288 bus controller

and

an

8289 bus arbiter.

The

iSBC

432/

100

board

also contains a serial 110

port

and

three timers.

One

timer provides the

baud

rate clock for the serial 110

port.

The

other

two

timers are cascaded

to

generate a process clock

(PCLK) for the 43202.

The

board

also contains a

number

of

miscellaneous

1/0

flags

that

can be read

or

written

(from

the bus)

to

control

processor opera-

tion

and

monitor

processor status. 110

port

address

assignments are detailed in

paragraph

3-3.

4.2

FUNCTIONAL

DESCRIPTION

The iSBC

432/

100 Processor

Board

may be func-

tionally subdivided into 6 units:

1.

CPU

and

110 Clock Generators

2.

iAPX

432

Processor

3. Address

Generator

4.

Data

Transfer

State

Machine

5.

Multibus Interface

6.

Input

and

Output

4-1

Principles

of

Operation

Figure

4-1

illustrates the approximate location

of

each functional unit

on

the iSBC

432/

100

Processor

Board; a block diagram

of

the

board

is

shown in
figure 4-2. The following paragraphs present a brief
description

of

each functional unit. A circuit analysis

of

each unit

is

also given (beginning with para-

graph 4-11).

4.3 CLOCK GENERATION

Two clocks are generated

on

the iSBC

432/

100

board.

One clock drives the

GDP

and all on-board

logic

that

is

synchronized with the processor. The

second clock drives

both

the 8253 Programmable

Interval Timer

(PIT)

and

the

825

lA

Universal Syn-

chronous/

Asynchronous

Receiver

/Transmitter

(USART).

GDP

operation requires two clock phases, CLKA

and CLKB,

that

differ by 90 degrees (ref er to figure
4-3). These clock phases are generated from the out­put

of

a crystal oscillator

and

both are buffered by

high-current line drivers

and

resistively terminated.

The second clock

is

derived from a

14.

7456

MHz

crystal attached to

an

8284 clock generator. The

divide-by-six

output

of

the 8284 (2.4576 MHz)

provides the 8251A master clock. This frequency

is

further divided by two, generating a 1.2288

MHz

clock for the 8253 timers. The 8253

is

programmed to

provide the

baud

rate for the

825

lA.

iSBC 432/100

4.4 iAPX 432 PROCESSOR

The

GDP

is

composed

of

two VLSI devices: the

43201

and the 43202. These devices are inter-

connected by means

of

a dedicated 16-bit bus and
three dedicated status signals. Both devices operate
with the same clock and are connected to a common

16-bit multiplexed

address/

data

bus. The two clock

phases (CLKA and CLKB) control the

43201/43202

timing. The

GDP

interfaces with external logic by

means

of

the 16-bit multiplexed

address/data

bus

(the packet bus

or

ACD

bus). All external logic tim­ing

is

synchronous with clock transitions. Most input
signals are sampled by the processor on the rising
edge

of

CLKA; inputs on the ACD bus are sampled

on the falling edge

of

CLKA. Most CPU outputs
may be sampled by external logic on the falling edge
of

CLKA.

Data

read and write addressing information

is

output

on the ACD bus by the

GDP

in two 16-bit informa-

tion cycles. The first double-byte

output

contains an

8-bit operation code

and

the least significant 8 bits

of
the address. The next double-byte contains the most
significant

16

bits

of

the address. The 8-bit operation

code contains

an

operation specifier

(1

bit), an access

specifier

(1

bit), and a length specifier

(3

bits). The

operation specifier indicates whether the procesor

is

executing a read

or

write operation. The access

specifier indicates the issuance

of

a local address

versus a physical memory address. Finally, the length

specifier indicates the number

of

data

bytes (1, 2, 4,

6,

8,

or

10)

affected by the

data

transfer. During pro-

cessor transfer requests, the external circuitry hand-

shakes with the

GDP

by means

of

the ISA

and

ISB

control signals.

SERIAL

1/0

CONNECTOR

CPU
CLOCK
GENERATOR

I I

8

43201

83202

i ? ! RS-232-C

I

!INTERFACE

I I

I I

I iAPX 432 CPU :

DATA-TRANSF~~~w~~

l

4-2

r----__

.1..

_____ ----

---

-,----------

-

_...1

__

------1

;------

: l

~

: I

I I c I :

: MULTIBUS™ ADDRESS :

LOCAL

1/0

:

1

GENERATION :

~

: :

I

1

1

TIMER

I : I : AND

------'-

--------------------.!.------

-

--------

-- - -

--

L

----

--T-

_..J

SERIAL

1/0

I

MULTIBUS™ INTERFACE

MULTIBUS™ INTERFACE

CONNECTOR

CLOCK

GENERATOR

Figure 4-1. iSBC

432/ 1 OO™

Processor

Board

Functional

Areas

171820-16

iSBC

432/

100

Principles

of

Operation

1,.._--------------'1.1

I\.----~

MULTIBUS

INTERFACE

CONTROLLER

ADDRESS

1/0

DECODE

DATA

BUS

BUS

PROCESSORDATA

TRANSCEIVERS

AND LATCHES

DATA TRANSFER

MACHINE

STATE

ADDRESS

GENERATOR

LATCHES

AND

11'---~I

en

:::>

"'

c

CJ

...

SYSTEM

CLOCK

GENERATOR

iAPX432

PROCESSOR

43201143202

11G-19.2K

RS-232-C

INTERFACE

BAUD

Figure 4-2. iSBC 432/100™ Processor Board Block Diagram

CLKA

CLKB

Figure 4-3. Two-Phase Overlapped Processor

data

output

from

111020-10

to and

as a

the

Clock

The ACD bus
from the processor for read and write accesses.
During a write access, the
sequence
immediately following the two initial addressing
specification cycles;

iriplifa the requifecrnumoer"of-aouble-bytes

ACD bus.
data element, it appears
of

the 16-bit ACD bus.

is

also used to transfer

data

is

of

up to five double-bytes (80 bits)

on

a read request, the processor

If

the read

or

write

data

is

a single 8-bit

on

the least significant bits

171820-17

The external circuitry may request

an

hold (stretch)
a write access)

access until the

or

until the

data
access) by the external component(s). The
is

used by the external circuitry to indicate this

that

the processor

data

is

accepted (for

is

supplied (for a read

ISB signal

request to the processor. The stretch function may be
requested

on

any double-byte

of

a read or write

data
transfer. After each double-byte transfer, the exter­nal circuitry must also indicate the success
of the tr an sf er cycle by means

of

the ISB signal.

or

failure

4.5 ADDRESS GENERATION

The 24-bit address issued by the iAPX 432 processor
is

converted into

follows (refer

L The

upper

20-bit address.

2. The lower twelve address bits are directly

loaded into three 4-bit counters.

an

initial 20-bit Multibus address as

to

figure 4-4):

four

bits are discarded, leaving a

4-3

Principles

of

Operation

iSBC 432/100

23

20

19

16 15 12

11

8 7 4 3

24-BIT PROCESSOR

-----------....-------

PHYSICAL ADDRESS

OFFSET

REGISTER

4 3 0

__

__..

__

...

FULL

ADDER

______

_.

20-BIT MULTIBUS

________

...._

_____

ADDRESS

Figure 4-4. 24-Bit Processor Physical Address to 20-Bit Multibus™ Address Conversion

171820-19

3.

The

remammg

eight bits are

added

to

an

address

offset

contained

in

an

8-bit offset

register.

The

result

of

this calculation

is

loaded into two

additional

4-bit counters.

The

offset register (an 8-bit

1/0

port

on

the

board)

may be loaded by a Multibus master

as discussed in

paragraph

4.18.

Once this initial address has been

computed

and

latched into the five address counters, the

data

transfer state machine controls the actual

data

transfers between the

bus

and

the

GDP.

As each 8-or

16-bit transfer

is

completed, the state machine
updates (increments) the 20-bit address (stored in the
counters) in

order

to

correctly cycle

through

multibyte transfer requests.

4.6

DAT A TRANSFER

ST A

TE

MACHINE

The

data

tr

an

sf er state machine

is

composed

of

a

programmable

logic

array

(PLA),

a state register, a

transfer

counter,

_and a command

decoder.

The

PLA,

which

is

the

heart

of

the

state

machine, generates the
signals required to synchronize Multibus operations
with processor

data

transfers.

The

state machine

operates in either

an

8-bit

or

16-bit Multibus mode. A

jumper

option

may

be

strapped

by the user

to

force

all

operations

to

be

performed

in the 8-bit mode.
Otherwise, in the 16-bit mode, all single byte
transfers

and

all multibyte transfers initiated

on

odd
addresses are forced into the 8-bit mode. The follow­ing descriptions

of

data

transfer

operations

are

graphically depicted in figure 4-5.

In the 8-bit mode, all Multibus operations are 8-bit
(byte) transfers.

If

a single-byte read

is

requested by

the processor, this byte

is

transferred from the least

significant eight Multibus

data

lines (DATO/-

DA

T7

/)

through a transparent

latch (A54) to the

4-4

least significant byte

of

the

ACD

bus

(ACDO-ACD7)

as illustrated in figure 4-5a.

When

more

than

one

byte

is

requested, two 8-bit Multibus

operations

are

combined into a single 16-bit processor transfer.

The

first Multibus read latches

DATO/-DAT7/

into

transparent

latch A54, driving ACDO-ACD7.

After

incrementing the

memory

address, the second

Multibus read

operation

transfers

data

from DATO/-

DAT7 I

onto

ACD8-ACDF

(through

transceiver

A52). A double-byte

read

transfer

is

illustrated in

figure 4-Sb.

During a single-byte write transfer,

data

on

ACDO-

ACD7 is transferred

to

the

DATO/-DAT7/

data

lines

of the Multibus bus

through

transceiver A53 (refer

to

figure 4-Sc). Multiple

data

byte transfers

perform

two Multibus write

operations

for each 16-bit

ACD

bus transfer.

The

first . Multibus write transfers

ACDO-ACD7

to

the

DATO/-DAT7/

data

lines

(through transceiver A53).

After

incrementing the
memory address, the second Multibus write opera­tion transfers

ACD8-ACDF

to

the

DATO/-DAT7/

Multibus

data

lines. This double-byte write transfer

is

shown in figure 4-5d.

In the 16-bit mode, a single byte read

is

performed

through A54 (if the address

is

odd)

or

through

A53

(if the address

is

even). A single-byte write transfers

data

through

transceiver A53. In

both

a single-byte

write

and

a single-byte read transfer, ACDO-ACD7

are connected

to

Multibus

data

lines

DATO/-DAT7/
(figure 4-Se to 4-5g). Multibyte transfers in the 16-bit
mode are

performed

as a sequence

of

double-byte

Multibus/processor

operations.

Each

double-byte

read transfers

16

bits

of

data

from the multibus bus

to the

ACD

bus by means

of

A53 (least significant

byte)

and

A5 l (most significant byte). Multibyte

write operations utilize the same

data

path

as used by

the multibyte read transfers,

but

in the opposite

direction. Multibyte transfers in the 16-bit mode

are

illustrated in figure 4-Sh.

iSBC

432/

I 00

Principles

of

Operation

DAT8-FI

DATo.7/

(A) SINGLE-BYTE READ TRANSFER, 8-BIT MODE

ACD8-F

---~--4

ACDo-7

ACDo-7

DAT8-FI

FIRST MULTIBUS

TRANSFER-

LOW BYTE IS LATCHED IN A54

DATo.7/

DAT8-FI

SECOND MULTIBUS

TRANSFER­HIGH BYTE FROM BUS, LOW BYTE
FROM LATCH

t--------

DATo.7/

(B) DOUBLE-BYTE READ TRANSFER, 8-BIT MODE

DAT8-FI

DATo.7/

(C) SINGLE-BYTE WRITE TRANSFER, 8-BIT MODE

Figure4-5. iSBC

432/lOOrM

Data

Transfer Routing

to/from

the Multibus™ Bus

171820-20

4-5

Principles

of

Operation

DAT5.F/

FIRST MULTIBUS

TRANSFER-

LOW BYTE

DATo.7/

DAT

a-Fl

SECOND MULTIBUS TRANSFER­HIGH

BYTE

(D)

DOUBLE-BYTE WRITE TRANSFER, 8-BIT MODE

(E)

SINGLE-BYTE READ TRANSFER (ODD ADDRESS), 16-BIT MODE

(F)

SINGLE-BYTE

READ

TRANSFER

(EVEN

ADDRESS),

16-BIT

MODE

iSBC 432/100

Figure 4-5. iSBC 432/100™

Data

Transfer Routing

to/from

the Multibus™ Bus

(Cont'd.)

111820-20

4-6

iSBC 432/100

Principles

of

Operation

(G) SINGLE-BYTE WRITE TRANSFER, 16-BIT MODE

DATs-FI

(H) DOUBLE-BYTE READ/WRITE TRANSFER, 16-BIT MODE

Figure 4-5. iSBC 432/100™

Data

Transfer

Routing

to/from

the

Multibus™ Bus

(Cont'd.)

rns20-~o

4.7 MULTIBUS INTERFACE

The iSBC 432/100 board

is

completely Multibus
compatible and supports both 8-bit and 16-bit opera­tions. The Multibus interface includes an 8288/8289
controller/arbiter pair that allows the

iSBC 432/100
board to function as a Multibus master. Also
included in the Multibus interface are address/data
bus transceivers and latches and an

1/0

command

decoder (discussed in paragraph 4-18). All

1/0

ports
are directly accessible from the Multibus by any
Multibus master.

4.8 INTERVAL TIMER

The

8253

PIT

provides three 16-bit timers used

on-board for serial

1/0

timing and for process

timing. Counters

0

and

1 are cascaded to provide the
process clock (PCLK) signal. Counter 2 generates a
programmable

baud

rate for the 8251A serial

1/0

port. Baud rates from

110

to

19

.2K are easily

generated as discussed in paragraph

3-20 and

table 3-2.

4.9 SERIAL

I/O

The 8251A USART provides an RS-232-C compat­ible serial synchronous

or

asynchronous data link for
CRT terminal operation. Character size, parity bits,
stop bits, and

baud

rates are all programmable as

discussed in paragraph

~-5.

4.10 PARALLEL

I/O

Four parallel

1/0

ports are contained on the iSBC

432/

100

board to support processor control and
status reporting functions. An 8-bit offset register
(write-only), used in addressing calculations (refer to
paragraphs

4-5

and

4-18), may be set from the

Multibus bus

to

translate processor addresses into

Multibus addresses. A second write-only

1/0

port
controls processor initialization and allows another
Multibus master

to

start, stop, and alarm the iSBC

432/100 processor (see paragraph 3-23).

4-7

Principles

of

Operation

iSBC 432/100

The third
by other Multibus masters
status (see
selectable inputs are user configurable
read by any Multibus master, including the
These inputs
configuration
The
with a unique processor ID. This processor ID
by the
cessor dependent parameters.

4.11

The schematic
is

given in figure 5-2.

of

7 sheets, each
Signals
assigned grid coordinates
and
coordinates
destination)

Both active-high

signal mnemonic

DA T7

(~

0.4V). Conversely, a signal mnemonic without a

virgule (e.g.,

active-high(~

1/0

port

(read-only) may be interrogated

to

fourth

GDP

paragraph

may

options

110

during initialization to determine pro-

3-23). In addition, three

be used

port

to

(such as

(read-only) supplies the

CIRCUIT ANALYSIS

diagram

that

traverse from one sheet to

the signal destination.

2Bl

on

sheet 2 in zone

/)

denotes

BYTOP) denotes

2.0V).

for the iSBC 432/100

The

schematic diagram consists

of

which includes grid coordinates.

at

locate a signal source (or signal

and

acitve-low signals are used. A

that

ends with a virgule (e.g.,

that

the signal

determine the processor

and

specify user-dependent

CRT

model selection).

another

both

the signal source

For

example, the grid

Bl.

is

active-low

that

the signal

4.12 INITIALIZATION

When the Multibus
iSBC 432/100 Processor
following state:

1.

The

GDP

is
state by pulling the
flip-flops A22

2.

The

data

transfer state machine
state zero (by the
4C4).

The

3.

4. The external

5.

6. The serial

bus

cleared.

is

(4C6),
The bus arbiter

cleared.

1/0

INIT

I signal

Board

initialized

PIN

and

A24

PINIT I input

interrupt

"stop"

port

flip-flop, A22 (4D6),

is

reset (outputs are 3-stated).

is

set to the

is

and

held in the initialized

IT I signal low (through

at

4D6

command

is

activated, the

forced into the

and

4D4).

is

initialized to

to

latch A25

flip-flop, A26

"idle"

mode.

4.13 CLOCKGENERATION

jumper

may be

GDP.

GDP

is

used

board

are

is

at

is

separate 50-ohm line driver (A3
controls the timing
transfer counter,

The

110 clock

generator (A41
MHz). This frequency
within the 8284 to provide a 2.4576
clock to the 8251A
is

also divided by two by flip-flop A23 (3D4) to
supply a 1.2288
at

3B4).

4.14

iAPX432GENERAL

of

the address counters, the

and

the

data

is

developed by

at

3D6) and crystal

is

internally divided by six

USART (A21

MHz

clock to the 8253

at

5C5).

CLKA/

transfer state machine.

an

8284 clock

Yl

(14.7456

MHz

master

at

3C4). This clock

PIT

(A36

DAT A PROCESSOR

As discussed previously, the

and

address
double-byte cycles
cycle, the write
double-byte addressing specification cycles.
ing

of
figure 4-6 while the timing
illustrated in figure 4-7.
within the 8-bit

4.1

S ADDRESS GENERATION

At

the

ment

of
up-counter (A57
type,

and
are clocked into latch A38 (7C3). Discrete logic gates
(A58
(from the
by the
the last
least significant address byte
on

ACDO-ACD7)

up-counters, A33

The second double-byte issued by the procesor
(upper

upper

The
bits are routed directly
(6B4).
4-bit adders
combined with the address offset from
The resulting address
up-counters (A3 l
generation

operation

a typical processor write cycle

operation

start

of a data

the

transfer

least-significant address

and

Al4

output

data

transfer state machine

data

byte

16

address bits)

four

The

remaining eight bits are

(AlS

of

a 20-bit Multibus address.

code

(paragraph

data

immediately follows these two

The

code

tr

an

sf er operation, the comple-

length

at

7C3).

The

at

7B2) generate the

of

the transfer counter)

is

transferred.

is

latched

and

A34 (6B4).

is

divided

bits are discarded.

to

and

Al6

is

and

A32

GDP

outputs

on

the

ACD

bus

in two

4-1). During a write

The

is

illustrated in

of

a typical read cycle

information

is

shown in figure 4-8.

is

latched into the transfer

access type,

bit

to

At

the same time, the

(output

into

into

a 4-bit up-counter,

at

6C6) where they are

latch~d

at

6C4)

contained

operation

(odd/even

CNTl

determine when

by the processor

three portions.

The

routed

into

to

complete the

signal

that

is

two 4-bit

lower four

to

Al8

(4A6).

two 4-bit

the

tim-

is

flag)

used

Al

two

7

The

CPU

clock

is

generated by two flip-flops (in

at

5C6)

from

a master oscillator
resulting overlapped
CLKB) are driven
50-ohm line drivers (A2
is

driven to v,arious positions on the

4-8

CPU

through

at

5C5).

(Al2

clock phases (CLKA

a resistive termination by

In

at

5D7). The

addition,

board

Al

and

CLKA/

by a

4.16

DATATRANSFERSTATE
MACHINE

The

heart

of

the

data

transfer state machine.

82Sl00

of

the

PLA

(A28

at

4C3).

PLA

are divided into three segments: a 4-bit

The

eight

output

is

an

signals

iSBC 432/100

Principles

of

Operation

CLKA

---'

I \

\

__

,

I

\

__

_

ACD ADDRs-23

ISA

ISB

____

s_T~·~~---E-RR

__

__,X~-----

BOUT

--------

*INTERPROCESSOR COMMUNICATION REQUEST WINDOW

Figure 4-6. Typical Processor Write Cycle Timing

171820-21

CLKA

ACD ADDRs-23

READ~

ISA

ISB

____

s_T~··~~---E-R_R

___

.J><~-----

BOUT

--------

*INTERPROCESSOR COMMUNICATION REQUEST WINDOW

Figure 4-7. Typical Processor Read Cycle Timing

171820-22

4-9

Principles

of

Operation

iSBC

432/100

15

14 13

12

10

9 8 7

0

ADDRo.7

.__-----1.-

TRANSFER LENGTH
000·

1 BYTE

001

• 2 BYTES

010·

4 BYTES

011

• 6 BYTES

100·

8 BYTES

101

• 10 BYTES

110

·RESERVED

111

·RESERVED

"------------.

OPERATION TYPE
0-READ

1-WRITE

"-------------

ACCESS TYPE
0

·PHYSICAL

MEMORY ACCESS

1

·LOCAL

ACCESS

Figure 4-8. Eight-Bit

Transfer

Specification Opcode.

171820-23

"next"

state (recorded in latch

A25

at 4C4), a 3-bit

command code, and the processor

ISB

signal. The

inputs to the

PLA

include the 4-bit current state

(from latch A25), the processor

ISA signal, the

CNT 1 signal from the transfer counter, the

odd/

even
address flag (least significant address bit), and the
operation type (read/write).

In addition, three synchronized signals are input to
the PLA: the Multibus transfer acknowledge signal
(XACK/), the interprocessor communication request
(from flip-flop

A23

at 4C6), and the processor

"access stop" request (from flip-flop

A26

at 4C6).

A transition from one

PLA

state to another state

occurs as the result

of

an input signal change. The

following twelve input signals

(16

bits) completely

control state transitions:

Input

Signal

STATE
ISA

IPCRQ

Description

4-bit current state number (from

A25

at

4C4)

Processor generated data transfer request
signal

Interprocessor

communication request

(from

A23

at

4C6)

BXACK Synchronized Muitibus

XACK

sigr1ai

STOPRQ

Processor "access

stop"

request (from

A26

at4C6)

PINIT I Processor initialization signal
CNT1

Last-byte transfer indicator

AO

Odd/even address flag (least significant
address bit)

WRITE

Processor write transfer indicator

4-10

During each state transition clock cycle, one

of

the

following eight commands (specified

by

the 3-bit

command code)

is

executed:

Command Command

Description

Code Name

0

2

3

4

5

6
7

COUNT

CLRIPC

LDLOW

LDHIGH

Increments

the

transfer

counter.
Clears pending interprocessor

communication requests.
Latches the least-significant 8

bits of the initial

Multibus

address

in

the

address

counters

(A33

and

A34).

Latches the most-significant

12

bits

of

the initial Multibus

address

into

the address

counters

(A17,

A31,

and

A32).

UNLOCK Unlocks the Multibus bus

(overrides the bus lock) at the
completion of a processor­requested data transfer.

STOPPED

Signals

that

processor
Multibus accesses have been
stopped.

NOOP

No operation.
Not used.

The state diagram for the data transfer state machine
is

given in figure 4-9.

To

illustrate actual state
machine operation, the following paragraphs
describe a four byte memory write operation on an
even byte boundary (in the 16-bit mode). While
reading the discussion, follow the state transitions as
depicted

in

figure 4-9.

iSBC 432/100

After initialization

and

before the

start

of

a transfer,

the state machine idles in state

0, maintaining ISB

high,

and

waiting for the processor

to

raise the ISA

signal (indicating the beginning

of a data

transfer

operation).

When

the state machine senses a high

ISA signal, it enables the

LDLOW

I signal and con-

tinues to maintain a high

ISB signal. The state

machine immediately enters state 8. Activation

of

the

LDLOW

I signal causes the least-significant address

byte

and

operation

code

information

to

be latched as

described in

paragraph

4.15. Shortly

after

the activa-

tion

of

the

LDLOW

I signal, the

CNTl

signal

and

AO

signal are

both

set low by the logic associated with

A57

and

A38 (7C3).

On

the subsequent clock cycle, the processor lowers

the

ISA signal as it

outputs

the upper

16

bits

of

the

address.

The

state machine recognizes this action

and

activates the

LDHIGH/

signal, latching the upper
address bits into the Multibus address latches. The
state machine enters state 2

and

waits until the

BXACK input

is

inactive (from previous transfers)

before proceeding with the actual

data

transfer).

Instead

of

lowering ISA, the processor may cancel

the

current

access by maintaining ISA high for

an

additional clock cycle.

As soon as BXACK

is

determined to be inactive, the

state machine enters state 7,

ISB

is

lowered (to begin

stretch),

and

the

ACCESS/

signal

is

enabled (A3

at

4C2) in

order

to

begin the first Multibus operation.

The state machine remains in state 7 until

XACK/
has been activated by the addressed device on the
Multibus (indicating

"write

data

accepted")

and

until the XACK signal has

propagated

through the

synchronizing flip-flops in A24 (4D4).

At

this point,

when BXACK

is

sensed active,

(CNTl

=O,

AO=O,

and

WRITE=

1 in this example), the state machine
increments the bus address (contained in the address
counters), increments the transfer counter, and
enters state 14.

State

14

inserts a delay to satisfy the

Multibus

data

hold time requirements.

On

the next

cycle, the state machine exits state

14

and

enters state

1,

raising the ISB signal to end stretch.

Since the

data

transfer in this example

is

not yet

complete (only two

of

the

four

bytes have been

transferred

and

CNTl

is

low), the Multibus address

is

again incremented. The state machine reenters

state 2

and

waits until BXACK has been removed

(after the previous transfer).

At

the same time, ISB

is

lowered

to

indicate

an

error-free

data

transfer.

Events for this second 16-bit

data

transfer proceed

from state 2 to state l in the same

manner

as . the
events proceeded for the first transfer. During this
second transfer,

CNTI

changes from low to high
immediately following the transfer counter incre­mentation (between state

14

and

state 1). Once in

Principles

of

Operation

state

1,

ISB

is

set to zero, indicating a second error

free transfer,

and

the state machine reenters the idle

state (state

0).

4.17 MULTIBUS INTERFACE

The Multibus interface consists

of

the 8288/8289 bus

controller/arbiter

pair (A45

and

A46

at

2C5),

bidirectional

data

bus transceivers (A5

l,

A52, and

A53

at

7B5

and

A55

at

3B6), a

data

latch (A54

at

7B5),

and

address buffers (A47, A48,

and

A49

at

6C2).

The falling edge

of

BCLK/

provides the bus timing

reference for the bus arbiter, which allows the

iSBC

4321100

board

to assume the role

of

a bus master.

When the

data

transfer state machine enters one

of

the predefined Multibus transfer states (state 7

or

state 15), the

ACCESS/

signal

is

activated. This

signal causes flip-flop

A30 (2B7) to enable bus arbi-

tration activity. Three

output

signals from the pro-

cessor request status latch (A38

at

7C3) are used to

indicate the type

of

Multibus activity required. The

READ

and

WRITE

signals specify

data

read

and

write cycles, respectively.

The

LOCAL/

signal

indicates

an

1/0

transfer when it

is

low (a local

address read

or

write),

and

a memory transfer when

the signal

is

high (a physical address read or write).

READ,

WRITE,

and

LOCAL/

are input to the

SO-S3

pins

of

the bus arbiter to control Multibus

activity.

When a Multibus transfer

is

initiated, the bus arbiter

drives

BREQ/

low

and

BPRO/

high. The

BREQ/

output

from each bus master in the system

is

used

when bus priority

is

resolved in a parallel priority

scheme as described in

paragraph

2.14. The

BPRO/

output

is

used when the bus priority

is

resolved in a

serial priority scheme as described in

paragraph

2.13.

The

iSBC

432/

l 00 gains control

of

the bus when the

BPRN/

input

to the bus arbiter

is

driven low

and

the

bus

is

not

busy (BUSY I inactive).

On

the next falling

edge

of

BCLK/,

the bus arbiter activates the BUSY I

and

AEN/

signals (driving them low). The BUSY I

output

indicates

that

the bus

is

in use

and

that

the

current bus master (in control

of

the bus) has total
bus control until the master releases the bus by deac­tivating its

BUSY I signal.

The

AEN/

output,

which

can be

thought

of

as a

"master

bus

control"

signal,

is

_applied

to

the bus addres.s buffers (A47, A48,

and

A49

at

6B2)

and

to the

input

of

gate Al4-5 (3A5).

With

AEN/

enabled, the

board

is

prepared to

recognize the ensuing acknowledge signal

(XACK/)

transmitted by the addressed system device.

4-11

Principles

of

Operation

4-12

[

CMD=NOOP]

ISB=O

[

CMD=NOOP]

ISB=O

Figure 4-9. Data Transfer State Machine State Diagram

iSBC 432/100

171820-24

iSBC 432/100

Principles

of

Operation

Data

Transfer State Machine Description

State

Activating

Next

Output

(Number)

lnput(s) State ISB

Command

Comments

IDLE(O) ISA=O

IDLE

1 UNLOCK

Wait

for

something

to

happen

IPCRQ=O

IDLE ISA=O

IDLE

0

CLRIPC

Issue

pending

IPC

if

no

access
IPCRQ=1
PINIT/=1

IDLE

ISA=1

ADDA 1 LDLOW

Access

start,

capture

low

address

ADDR(8) ISA=1 HOLD 1

NOOP

Access

cancelled

ADDA ISA=O

WAIT

1 LDHIGH Load

high

address;

stop

accesses

on

STOPRQ=1

stop

request

ADDA

ISA=O

XWAIT

1

LDHIGH Load high

address

STOPRQ=O

HOLD(4)

--

IDLE 1 NOOP

Prevent

an IPC

after a cancel

WAIT(12) STOPRQ=1

WAIT

0

STOPPED Set

stopped

status

and wait

for

the

stop

request

to

end

WAIT

STOPRQ=O

XWAIT

0

NOOP

Exit

wait

to

continue

access

XWAIT(2) BXACK=1 XWAIT

0

NOOP Wait

for

BXACK

inactive

to

start

access

XWAIT

BXACK=O

ACC

0 NOOP Start

the

access

ACC(7) BXACK=O ACC

0

NOOP Wait

for

access

complete

ACC

BXACK=1

RDONE 1 COUNT

_

Byte

read

access

complete
CNT1=1
WRITE=O

ACC

BXACK=1

WDONE

0

COUNT

Byte

write,

stretch

write

access

to

CNT1=1

satisfy

hold

time

WRITE=1

ACC

BXACK=1

DR

DONE 1 COUNT

Double-byte

read

access

complete
CNT1=0
AO=O
WRITE=O

ACC

BXACK=1

DWDONE

0

COUNT

Double-byte

write,

stretch

write

CNT1=0

access

to

satisfy

hold

time
AO=O
WRITE=1

ACC

BXACK=1

HWAIT

0

COUNT Odd

access

boundary,

perform

one

CNT1=0

byte

at a

time

A0=1

HWAIT(10)

BXACK=1 HWAIT

0

NOOP Wait

until

BXACK

done

HWAIT

BXACK=O

HGHBYT

0 NOOP

Start

high

byte

access

HGHBYT(15) BXACK=O

HGHBYT

0

NOOP

Wait

for

access

to

complete

HGHBYT

BXACK=1 XWAIT

1 COUNT

Start

next

double-byte
CNT1=0
WRITE=O

HGHBYT

BXACK=1

HGHWRT

0 COUNT

Stretch

write

data
CNT1=0
WRITE=1

HGHBYT

BXACK=1 RDONE

1 COUNT Read

access

complete

CNT1=1
WRITE=O

HGHBYT

BXACK=1 WDONE

0

COUNT

Stretch

write

data

CNT1:::::1

WRITE=1

HGHWRT(6)

--

XWAIT 1 NOOP

ComQ_lete

write

OQ_eration

DWDONE(14)

--

DRDONE 1 NOOP

Complete

write

operation

DRDONE(1) CNT1=0 XWAIT

0

COUNT

Get

next

double-byte

DRDONE

CNT1=1 IDLE

0 COUNT

Access

complete,

no

errors

WOONE(9)

-

ROONE

1

NOOP

Complete write operation

RDONE(5)

--

IDLE

0

COUNT

Access

complete,

no

errors

Figure 4-9.

Data

Transfer State Machine State Diagram (Cont'd.)

171820-24

4-13

Principles

of

Operation

When a Multibus transfer

is

initiated, the bus con-

troller (A46

at

2B5)

is

also enabled, The controller

decodes the

SO-S2

control signals

and

drives the

appropriate

Multibus

command

lines low when

AEN/

is

activated by the bus arbiter. The bus con-

troller also drives DEN high to selectively enable

data

bus drivers/receivers A51, A52, A53,

and/or

A54

(7B5) as described in

paragraph

4.6.

The

data

bus

drivers are switched

to

the

appropriate

"transmit"

or

"receive"

mode

depending

on

the state

of

the

READ,

WRITE,

and

processor generated BOUT

signals.

After the

command

is

acknowledged (signified by the

addressed device driving the Multibus

XACK/

line

low), the

data

transfer state machine terminates the

command.

The

bus arbiter

and

bus controller,

respectively, terminate

AEN/

and

DEN; the bus

arbiter also relinquishes control

of

the bus by driving

BREQ/

high

and

BPRO/

low

and

then raising

BUSY/.

When gaining control

of

the bus, the iSBC

432/

100

board

can invoke a

"bus

lock"

condition to prevent

loss

of

bus

control

during Multibyte transfers (see

paragraph

2.10

and

table 2-2). The

"bus

lock"

con-

dition

is

invoked by driving the bus arbiter LOCK pin

low. The

"bus

lock"

capability

is

enabled by a user-

selectable

jumper

option

(A30

at

2A6).

4-14

iSBC 432/100

4.18

1/0

OPERATION

The following paragraphs describe

on-board

1/0

operations. All

on-board

1/0

devices are accessible
only from the Multibus bus. The actual functions
performed by specific read and write commands to
on-board

1/0

devices are described in

Chapter

3.

Multibus address bits ADRO/ through ADR7 I are
applied to the

1/0

address decoder, which

is

com-

posed

of

A50, A37,

Al3,

and

A28 (2D5). The

board

1/0

base address

is

user-selected from the

jumper
matrix associated with the address decoder A50
(2C5). This address decoder decodes a portion

of

the

incoming address bits

(ADR3/

through

ADR7/)

from the bus. Addresses ADRO/ through

ADR2/

further qualify the

I/O

address

and

are decoded by

A37 to provide chip selects for the 8253

PIT,

the

8251A

USART,

and

the four parallel

110

ports:

Address* Chip Select

1/0

Device

00

PRID/

Processor

ID

Register

X2,X4,X6 53CS/

8253

PIT

XA

51CS/

8251A

USART

xc

OFFCS/

Address

Offset

Register

XE

STATCS/

Processor

Status/Control

Register

*X may be 1

through

7 as

selected

from

the

base

address

jumper

matrix.

·n ,

REFERENCE

CHAPTER

51

INFORMATION

5.1

INTRODUCTION

This

chapter
schematic
the iSBC

5.2 REPLACEABLE

Table

5-1

432/

iSBC

manufacturers

the
umn

in table 5-1. Intel

open

market

"COML";

these

parts

5.3 SCHEMATIC AND

provides a list

diagram,

432/100

provides a list

100

every

from

and a parts

Processor

board.

specified in the

are

listed in the

effort

a local (commercial)

of

Table

parts

should

of

replaceable

location

Board.

PARTS

replaceable
5-2 identifies

MFR

that

are available

MFR

CODE

be

made

distributor.

PARTS

diagram

parts

LOCATION DIAGRAMS

The

iSBC

432/

100

parts

location
schematic
5-2, respectively.
mnemonic
active low. Conversely, a signal mnemonic
virgule (e.g.,

5.4 SERVICE AND

diagram

that

are

provided

On

the schematic

ends with a virgule (e.g.,

BYTOP)

is

active high.

REPAIR

diagram

in figures

diagram,

ASSISTANCE

United States
repair assistance
Service
side the
source (Intel Sales
for service

Before calling

should have the following
a.
b.

Hotling

Date
Complete

dash
silk-screened
products,

Customers

by

in

Phoenix,

United

information

you received

number).

part

it

is

States

Office

the

number

On

onto

usually

can

contacting

Arizona.

should

or

Authorized

and

repair assistance.

Product

information

the

product.

of

boards,

the

board.

stamped

obtain

contact

Service Hotline, you

the

this

service

the Intel

Customers

Distributor)

available:

product

number
On

other

on

a label.

parts,

for

for

the

and

locates

CODE

to

IOWC/)

their sales

col-

on

the

column

procure

and

5-1

and

a signal

without

and

Product

out-

(including

is

usually

MCSD

as

is

c. Serial

a

a

number
other
usually

d. Shipping

If

e.

must

purposes.

f.

If

be sure
agreement.

Use the following
Product

All
Hawaii
Telephone:

All

TWX

Always
returning a
given a repair
instructions,
will help Intel

If

you are

sustained

warranty, a
can initiate the

In preparing
Center, use the original factory packing material, if
possible.
product
TH-240,
tion,
corrugated shipping
to ensure careful handling. Ship only to the address
specified by

number

is

MCSD

stamped

& billing addresses.

your

Intel

provide a

you have

to

Service Hotline:

U.S. locations, except Alaska,

[phone]

other

locations telephone:

[phone]

Number:

910-951-1330

contact

product

and

provide

returning

during

purchase

the

If

this

in a cushioning material such as Air

manufactured

Hawthorne,

Product

of

product.

usually

advise the

the

shipment

repair.

product

material

stamped

products,

on

product

purchase

an

extended

numbers

Product

to

authorization

other

important

you with fast, efficient service.

the

order

N .J.

Then

carton,

Service Hotline personnel.

the serial

a label.

warranty

order

warranty

Hotline

for

contacting the Intel

Service

Intel for repair. You will be

product

for shipment to the Repair

is

by the Sealed Air

because

or

if the

is

required

not

available, wrap the

enclose in a heavy

and

label

On

on

has expired, you

number

personnel

number,

information

product

boards,

the

board.
number

for

billing

agreement,

of

Arizona,

Hotline

"FRAGILE"

shipping

of

damage

is

before

Corpora-

before

whjch

out

this

On

is

this

&

of

Intel

Cap

duty

5-1

Reference Information

iSBC 432/100

Table 5-1. Replaceable Parts

Reference

Designation

A7,50 , IC,
A21
A36
A47,48,49,54
A41
A19,20,51,52,

53,55
A46
A45
A5
A6
A14
A9,35
A56,58
A22,23,26

A29

17

,31,32,33 IC, 74LS163,

A
34,57

A43

A38

A18,24,25

A15,16
A44

A4,39 IC,

A13
A28,40
A1,30
A37
A2,3
A11
A10
A8
A12
C52
C15
C1-3,12-14, Cap.,

16,20,22,
24-26,28,29,
31-51,53-68

C5,11,18,19 Cap.,
C6-9,21,23, Cap., cer, RDL, .1µF,

Intel

IC,

Intel

IC,

Intel

IC,

Intel

IC,

Intel

IC, Intel

IC,

Intel

8288,

IC,

Intel

IC,

Intel

IC,

Intel

43202,
IC, 74LS02, Quad
IC, 74LS04,
IC, 74LS10,
IC, 74LS74, Dual D
IC, 74LS125, Quad

IC, 74LS164, 8-Bit
IC, 74LS175, Quad D
IC, 74LS273, Octal D
IC, 74LS283, 4-Bit Full
IC, 74LS367,

74SOO,

IC,

74S08,
IC, 74S32, Quad 2-lnput
IC,

74S74,
IC,

74S139,
IC, 748140, Dual
IC,

75188,
IC, 75189A, Quad
IC, 82$100, FPLA
Oscillator,
Cap., mica, 10pF, 5%, 100V
Cap., cer, 330pF, 10%,

cer,

cer,

Description

8205,

3-to-8

8251

A, USART

8253,

P~ogrammable

8283,

Octal Latch

8284,

Clock

8287,

Octal

Bus

Controller

8289,

Bus

Arbiter

43201,

General
General

2-lnput

Hex

Inverters

Triple

3-lnput

Flip-Flops

Three-state

Binary

Shift

Hex

Bus
Quad 2-lnput NANO Gates
Quad 2-lnput AND

Dual D Flip-Flops

Dual 2-to-4

4-lnput

Quad

Line

Line

Crystal,

.01µF, +80

.1µF,

+80-20%,

27,30

C17
C70,71

C4,10
C69,72 Cap., tant,
DS1
R1,3

Cap., cer, 1µF,
Cap., tant, axial, 4.7µF, 20%,

Cap., tarit, axial,

Diode,
Res., fxd,

+80-20%,

22µF,

22µF,

10%, 15V

Red LED, 1.2 MCD

comp,

100

Decoder

Generator

Transceiver

Data

Processor

Data

Processor

NOR Gates

NANO Gates

4-Bit

Counter

Register

Flip-Flops

Flip-Flops

Adders

Drivers

Gates

OR

Gates

Decoder

Line

Driver

Driver

Receiver

20.000

MHz

50V

-20%,

50V

50V

+80-20%,

50V

15V

20%,

10V

ohm,

5%,

Interval

Bus

Buffers

50V

1/4W

Timer

Mfr.

Part

No.

8205
8251A
8253
8283
8284
8287

8288
8289

43201

43202

SN74LS02 Tl
SN74LS04 Tl
SN74LS10 Tl
SN74LS74
SN74LS125 Tl 1
SN74LS163 Tl

SN74LS164 Tl
SN74LS175
SN74LS273 Tl
SN74LS283
SN74LS367 Tl 1
SN74SOO
SN74S08 Tl
SN74S32 Tl
SN74S74
SN74S139 Tl 1
SN74S140
SN75188 Tl 1
SN75189A Tl 1
828100 SIG 1
K1100A
OBD
OBD
OBD

OBD
OBD

OBD
OBD

OBD
OBD
OBD
OBD

Mfr.

Code

COML
COML
COML
COML
COML
COML

COML 1
COML 1
COML 1
COML 1

Tl

Tl 1

Tl

Tl

Tl

Tl

MOT
COML
COML
COML

COML
COML

COML
COML

COML
COML
COML

COML

Qty

51

2
1
1
4

1

6

1
2
2
3

6

1

3
2

2
1
2
2

2

1
1
1

4
8

1
2

2
2
1
2

5-2

iSBC 432/100

Reference

Designation

R2
R4,5

RP1-3
XA12
XA36

XA8,21
XA5,6
Y1

Mfr.

Code

AMP
AUG
CAL
CRY
INT
MOT
SIG

Tl

08D

Table 5-1. Replaceable Parts

(Cont'd.)

Description

Res., fxd, comp,

220

ohm, 5%,

1/4WS

Res., fxd, comp, 1

Kohm,

5%,

1/4W

Res., pack, 8 pin, 1K ohm, 2%,

2W
Socket, 14-pin, DIP
Socket,

24-pin,

DIP

Socket, 28-pin,

DIP

Socket

Assembly, 64-pin Lead less

Crystal,

14.7456

MHz, Fundamental
Extractor, Card
Post, Wire Wrap
Plug, Shorting, 2-Position

Mfr. Part

No.

08D
08D
08D
514-AG19D
524-AG11D
528-AG11D
827-0067-00
CY148
105UL
89531-6
530153-2

Table 5-2. List

of

Manufacturers' Codes

Manufacturer

AMP, Inc.
Augat, Inc.
Calmark

Corporation
Crystek
Intel Corporation
Motorola

Semiconductor

Signetics

Texas

Instruments

Order

by Description; available from

any commerical

(COML) source

Reference Information

Mfr.

Qty

Code

COML

1

COML

2

COML

3

AUG

1

AUG

1

AUG

2

INT

2
CRY 1
CAL 2
AMP"

91

AMP

15

Address

Harrisburg,

PA

Attleboro,

MA
San Gabriel, CA
Fort Meyers, FL
Santa Clara, CA
Phoenix, AZ
Sunnyvale, CA
Dallas,

TX

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