Intel IQ80333 User Manual

Intel® IQ80333 I/O Processor

Customer Reference Board Manual

February 2005

Document Number: 306690001US

Intel Part Number: C90183-001

Intel® IQ80333 I/O Processor

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Intel® internal code names are subject to change.

THIS SPECIFICATION, THE Intel® IQ80333 I/O Processor IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.

Intel disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.

Copyright © Intel Corporation, 2005

AlertVIEW, i960, AnyPoint, AppChoice, BoardWatch, BunnyPeople, CablePort, Celeron, Chips, Commerce Cart, CT Connect, CT Media, Dialogic, DM3, EtherExpress, ETOX, FlashFile, GatherRound, i386, i486, iCat, iCOMP, Insight960, InstantIP, Intel, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel ChatPad, Intel Create&Share, Intel Dot.Station, Intel GigaBlade, Intel InBusiness, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetStructure, Intel Play, Intel Play logo, Intel Pocket Concert, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel TeamStation, Intel WebOutfitter, Intel Xeon, Intel XScale, Itanium, JobAnalyst, LANDesk, LanRover, MCS, MMX, MMX logo, NetPort, NetportExpress, Optimizer logo, OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

The ARM* and ARM Powered logo marks (the ARM marks) are trademarks of ARM, Ltd., and Intel uses these marks under license from ARM, Ltd.

*Other names and brands may be claimed as the property of others.

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					Contents
Contents
1	Introduction		....................................................................................................................................		9
	1.1	Document .............................................................................................Purpose and Scope			9
	1.2	Other Related ....................................................................................................Documents			9
	1.3	Electronic .........................................................................................................Information			10
	1.4	Component ......................................................................................................References			10
	1.5	Terms .........................................................................................................and Definitions			11
	1.6	Intel® 80333 .................................................................................................I/O Processor			12
	1.7	Intel® IQ80333 ...................................I/O Processor Evaluation Platform Board Features			14
2	Getting Started.............................................................................................................................				15
	2.1	Kit Content ..........................................................................................................................			15
	2.2	Hardware ..........................................................................................................Installation			15
		2.2.1 ..............................................................................	First - Time Installation and Test		15
		2.2.2 .............................................................................................	Power Requirements		16
	2.3	Factory ..................................................................................................................Settings			17
	2.4	Development ........................................................................................................Strategy			17
		2.4.1 ........................................................................................	Supported Tool Buckets		17
		2.4.2 .............................................................................................	Contents of the Flash		17
	2.5	Target ...................................................................................................................Monitors			18
		2.5.1 ....................................................................................................	RedHat RedBoot		18
	2.6	Host Communications ........................................................................................Examples			19
		2.6.1 .................................................................................	Serial - UART Communication		19
		2.6.2 ................................................................................	JTAG Debug Communication		19
		2.6.3 ........................................................................................	Network Communication		20
		2.6.4 .............................................................................................	GNUPro GDB/Insight		21
		................................................................	2.6.4.1	Communicating with RedBoot	21
		.............................................................................	2.6.4.2	Connecting with GDB	23
3	Hardware Reference ......................................................................................................Section				25
	3.1	Functional .............................................................................................................Diagram			25
	3.2	Board .........................................................................................Form-Factor/Connectivity			26
	3.3	Power..................................................................................................................................			27
	3.4	Memory ............................................................................................................Subsystem			28
		3.4.1 .........................................................................................................	DDR SDRAM		28
		.......................................................................................	3.4.1.1	Battery Backup	28
		3.4.2 .................................................................................	Flash Memory Requirements		29
	3.5	Interrupt .................................................................................................................Routing			30
	3.6	Intel® IQ80333 ..........................I/O Processor Evaluation Platform Board Peripheral Bus			31
		3.6.1 .............................................................................................................	Flash ROM		32
		3.6.2 .....................................................................................................................	UART		33
		3.6.3 ..................................................................................................	Non - Volatile RAM		33
		3.6.4 .........................................................................................................	Audio Buzzer		33
		3.6.5 ...........................................................................................................	HEX Display		33
		3.6.6 .........................................................................................................	Rotary Switch		33
		3.6.7 ........................................................................................................	Battery Status		34
	3.7	Debug ..................................................................................................................Interface			35

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		3.7.1	Console Serial Port ................................................................................................			35
		3.7.2	JTAG Debug ..........................................................................................................			36
			3.7.2.1	JTAG Port ..............................................................................................		36
	3.8	Board Reset Scheme..........................................................................................................				37
	3.9	Switches and Jumpers........................................................................................................				38
		3.9.1	Switch Summary ....................................................................................................			38
		3.9.2 Default Switch Settings of S7A1Visual ................................................................				38
		3.9.3	Jumper Summary ..................................................................................................			39
		3.9.4	Connector Summary ..............................................................................................			39
		3.9.5 General Purpose Input/Output Header ..................................................................				39
		3.9.6 Detail Descriptions of Switches/Jumpers...............................................................				40
			3.9.6.1 Switch S1C2: Intel ® 80333 I/O Processor Reset ...................................			40
			3.9.6.2 Switch S6A1: BPCI - X Reset ..................................................................			40
			3.9.6.3	Switch S8A1: Rotary ..............................................................................		40
			3.9.6.4	Switch S7A1...........................................................................................		40
				3.9.6.4.1	S7A1-1: PCI-X Bus A Speed Enable Corresponding to
					Signal Name PBI_AD3 .......................................................	40
				3.9.6.4.2	S7A1-2: Reset I/O Processor Core Corresponding to
					Signal Name PBI_AD5 .......................................................	40
				3.9.6.4.3	S7A1-3: Configration Cycle Enable Corresponding to
					Signal Name PBI_AD6 .......................................................	41
				3.9.6.4.4	S7A1-4: PCI-X Bus B Speed Enable Corresponding to
					Signal Name PBI_AD10 .....................................................	41
				3.9.6.4.5	S7A1-5: PCI-X Bus B Hot-Plug Reset Disable
					Corresponding to Signal Name PBI_AD11.........................	41
				3.9.6.4.6	Switch S7A1- 6: Hot Plug Capable Disabled Corresponding to
					Signal Name PBI_AD15 .....................................................	41
				3.9.6.4.7	Switch S7A1 - 7: SMBUS Manageability Address Bit 0
					Corresponding to Signal Name PBI_AD17.........................	42
				3.9.6.4.8	Switch S7A1 - 8: SMBUS Manageability Address Bit 3
					Corresponding to Signal Name PBI_AD18.........................	42
				3.9.6.4.9	Switch S7A1- 9:SMBUS Manageability Address Bit 2
					Corresponding to Signal Name PBI_AD17.........................	42
				3.9.6.4.10	Switch S7A110: SMBUS Manageability Address Bit 1
					Corresponding to Signal Name PBI_AD16.........................	42
			3.9.6.5	Jumper J7D1: Flash bit-width ................................................................		43
			3.9.6.6	Jumper J1C1: JTAG Chain ....................................................................		43
			3.9.6.7	Jumper J1D2: UART Control .................................................................		43
			3.9.6.8 Jumper J7B4: SMBus Header ...............................................................			44
			3.9.6.9 Jumper J9D3: Buzzer Volume Control ...................................................			44
4	Software Reference.....................................................................................................................					45
	4.1	DRAM	.................................................................................................................................			45
	4.2 Components on the Peripheral Bus....................................................................................					45
		4.2.1	Flash ROM .............................................................................................................			46
		4.2.2 .................................................................................Peripheral Bus Memory Map				47
	4.3 Board ..........................................................................Support Package (BSP) Examples					48
		4.3.1 ..............................................................Intel® 80333 I/O Processor Memory Map				48
		4.3.2 .............................................RedBoot* Intel® 80333 I/O Processor Memory Map				49
		4.3.3 ............................................................RedBoot Intel® 80333 I/O Processor Files				49
		4.3.4 RedBoot Intel® 80332 I/O Processor DDR
		.............................................................................	Memory Initialization Sequence			50

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					Contents
A	IQ80321 and IQ80333 Comparisons...........................................................................................				51
B	Getting Started and Debugger ...................................................................................................				53
	B.1	Introduction .........................................................................................................................			53
		B.1.1	Purpose .................................................................................................................		53
		B.1.2 Necessary Hardware and Software .......................................................................			53
		B.1.3	Related Documents ...............................................................................................		53
		B.1.4	Related Web Sites .................................................................................................		54
	B.2	Setup	..................................................................................................................................		55
		B.2.1 .....................................................................................................	Hardware Setup		55
		B.2.2 ......................................................................................................	Software Setup		56
	B.3	New Project ..............................................................................................................Setup			57
		B.3.1 ..........................................................................................	Creating a New Project		57
		B.3.2 .........................................................................................................	Configuration		58
	B.4	Flashing .............................................................................................................with JTAG			59
		B.4.1 ................................................................................................................	Overview		59
		B.4.2 .......................................................................................	Using Flash Programmer		60
	B.5	Debugging ......................................................................................................Out of Flash			61
	B.6	Building ..............................................................an Executable File From Example Code			61
	B.7	Running .......................................................................................the Code|Lab Debugger			62
		B.7.1 ...................................................................Launching and Configuring Debugger			62
		B.7.2 .....................................Manually Loading and Executing an Application Program			62
		B.7.3 ........................................................................................	Displaying Source Code		63
		B.7.4 ..................................................................................................	Using Breakpoints		63
		B.7.5 ...................................................................................Stepping Through the Code			64
		B.7.6 ..........................................................................Setting Code|Lab Debug Options			64
	B.8	Exploring ...........................................................................the Code|Lab Debug Windows			65
		B.8.1 .........................................................................................................	Toolbar Icons		65
		B.8.2 ...............................................................................................	Workspace Window		65
		B.8.3 ..........................................................................................................	Source Code		65
		B.8.4 ............................................................................4 Debug and Console Windows			65
		B.8.5 ....................................................................................................	Memory Window		65
		B.8.6 ..................................................................................................	Registers Window		66
		B.8.7 .......................................................................................................	Watch Window		66
		B.8.8 ..................................................................................................	Variables Window		66
	B.9	Debugging ...............................................................................................................Basics			67
		B.9.1 ................................................................................................................	Overview		67
		B.9.2 .....................................................................Hardware and Software Breakpoints			67
		.............................................................................	B.9.2.1	Software Breakpoints	67
		...........................................................................	B.9.2.2	Hardware Breakpoints	67
		B.9.3 ..............................................................................................	Exceptions/Trapping		68

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Contents
Figures
1	Intel® 80333 I/O Processor Block Diagram ................................................................................	13
2	Serial-UART Communication .....................................................................................................	19
3	JTAG Debug Communication .....................................................................................................	19
4	Network Communication Example .............................................................................................	20
5	Intel® 80333 I/O Processor Functional Block Diagram...............................................................	25
6	Board Form Factor .....................................................................................................................	26
7	Intel® IQ80333 I/O Processor Evaluation Platform Board Peripheral Bus Topology..................	31
8	Flash Connection on Peripheral Bus ..........................................................................................	32
9	JTAG Port Pin-out ......................................................................................................................	36
10	RESET Sources .........................................................................................................................	37
11	Default Switch Setting Switch S7A1 ...........................................................................................	38
12	Flash Connection to Peripheral Bus ...........................................................................................	46
13	Intel® 80333 I/O Processor Memory Map...................................................................................	48
14	Intel® 80333 I/O Processor Hardware Setup Flow Chart ...........................................................	55
15	Software Flow Diagram ..............................................................................................................	56

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	Intel® IQ80333 I/O Processor
		Contents
Tables
1	Intel® 80333 I/O Processor Related Documentation List..............................................................	9
2	Electronic Information .................................................................................................................	10
3	Component Reference................................................................................................................	10
4	Terms and Definitions.................................................................................................................	11
5	Summary of Features .................................................................................................................	14
6	Form-Factor/Connectivity Features ............................................................................................	26
7	Power Features ..........................................................................................................................	27
8	Flash Memory Requirements......................................................................................................	29
9	External Interrupt Routing to Intel® 80333 I/O Processor ...........................................................	30
10	Peripheral Bus Features .............................................................................................................	31
11	Flash ROM Features ..................................................................................................................	32
12	Rotary Switch Requirements ......................................................................................................	33
13	Battery Status Buffer Requirements ...........................................................................................	34
14	Reset Requirements/Schemes ...................................................................................................	37
15	Switch Summary.........................................................................................................................	38
16	Switch S7A1 ...............................................................................................................................	38
17	Jumper Summary .......................................................................................................................	39
18	Connector Summary...................................................................................................................	39
19	J2D2 GPIO Header Definition.....................................................................................................	39
20	Rotary Switch Settings................................................................................................................	40
21	S7A1-1: PCI-X Bus A Speed Enable ..........................................................................................	40
22	Switch S7A1-2: Reset IOP: Settings and Operation Mode.........................................................	41
23	Switch S7A1-3: RETRY: Settings and Operation Mode .............................................................	41
24	S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode .........................................	41
25	S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode ..........................	41
26	Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode .............................	41
27	Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode .............	42
28	Switch S7A1 - 8: SMBUS Manageability Address Bit 3: Settings and Operation Mode .............	42
29	Switch S7A1 - 9: SMBUS Manageability Address Bit 2: Settings and Operation Mode .............	42
30	Switch S7A1 - 10: SMBUS Slave Address 0: Settings and Operation Mode .............................	42
31	Jumper J7D1: Descriptions.........................................................................................................	43
32	Jumper J7D1: Settings and Operation Mode..............................................................................	43
33	Jumper J1C1: Descriptions.........................................................................................................	43
34	Jumper J1C1: Settings and Operation Mode..............................................................................	43
35	Jumper J1D2: Descriptions.........................................................................................................	43
36	Jumper J1D2: Settings and Operation Mode..............................................................................	43
37	Jumper J7B4: Descriptions.........................................................................................................	44
38	Jumper J7B4: Settings and Operation Mode..............................................................................	44
39	Jumper J9D3: Descriptions.........................................................................................................	44
40	Jumper J9D3: Settings and Operation Mode..............................................................................	44
41	Peripheral Bus Memory Map ......................................................................................................	47
42	Intel® IQ80321 Evaluation Platform Board and
	Intel® IQ80333 I/O Processor Evaluation Platform Board Comparisons ....................................	51
43	Related Documents ....................................................................................................................	53

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Contents

Revision History

	Date	Revision	Description
	March 2005	001	Initial Intel® Developer Web Site Release
			(http://developer.intel.com/design/iio/).

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Introduction

1

1.1Document Purpose and Scope

This document describes the Intel® IQ80333 I/O processor evaluation platform board (IQ80333) using DDR-II 400 MHz SDRAM. The Intel®80333 I/O processor (80333) is intended for rapid, intelligent I/O development. The 80333 is a multi-function device that integrates the Intel XScale® core (ARM* architecture compliant) with intelligent peripherals including a PCI Express bus application bridge.

1.2Other Related Documents

Table 1.	Intel® 80333 I/O Processor Related Documentation List
	Document	Number
Intel®80333 I/O Processor Developer’s Manual		305432
Intel®80333 I/O Processor Datasheet		305433
Intel®80333 I/O Processor Design Guide		305434
Intel®80333 I/O Processor Specification Update		305435
Intel® Flash Recovery Utility (FRU) Reference Manual		274071
IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE JTAG-1149.1-1990)		http://www.ieee.org
PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group
PCI Express Specification, Revision 1.0a - PCI Special Interest Group
PCI Express Base Specification 1.0a - PCI Special Interest Group
PCI Express Card Electromechanical Specification 1.0a - PCI Special Interest Group		http://www.pcisig.com
PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group		/specifications
PCI-X Specification, Revision 1.0b - PCI Special Interest Group
PCI Bus Power Management Interface Specification, Revision 1.1 - PCI Special Interest Group
PCI Bus Hot-Plug Specification, Revision 1.1 - PCI Special Interest Group

Intel documentation is available from the local Intel Sales Representative or Intel Literature Sales.

To obtain Intel literature write to or call:

Intel Corporation

Literature Sales

P.O. Box 5937

Denver, CO 80217-9808

(1-800-548-4725) or visit the Intel website at http://www.intel.com

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Introduction

1.3Electronic Information

Table 2.	Electronic Information
	Support Type	Location/Contact
The Intel World-Wide Web (WWW) Location:		http://www.intel.com
Customer Support (US and Canada):		1-916-377-7000

1.4Component References

Table 3 provides additional information on the major components of 80333.

	Table 3.	Component Reference
	Component	Part Number		Additional Information
	Intel		•	Manufacturer: Intel Corporation
	StrataFlash®	28F640J3C
			•	URL: http://developer.intel.com/design/flcomp/prodbref/298044.htm
	Memory
	Intel(R)		•	Manufacturer: Intel Corporation
	Gigabit	82545EM
	Ethernet		•	URL: http://developer.intel.com/design/network/products/lan/controllers/82545.htm
	Controller
			•	Manufacturer: Grayhill*
	Rotary Switch	DR FC 16	•	URL:
				http://embrace.grayhill.com/embrace/Item/ASP/Item-Detail.asp?PartNo=94HAB16W&Catalog
				GroupID=Series94HBinaryCoded&GroupDisplayLabel=&RestSes=No
	Hex Display	HDSP-A103	•	Manufacturer: Agilent Technologies*
			•	URL: http://www.semiconductor.agilent.com/cgi-bin/morpheus/home/home.jsp?pSection=LED
	AudioBuzzer	DMT 1206	•	Manufacturer: RDI*
		SMT	•	URL: http://www.rdi-electronics.com/products/Audio/DMT-1206-SMT.html
	NVSRAM	STK14C88-3	•	Manufacturer: SIMTEK*
		N 35	•	URL: http://www.simtek.com/product-information/datasheets/256K-PDF/STK14C88-3.pdf
	CPLD	XC9572XL -	•	Manufacturer: XILINK*
		10TQ100C	•	URL: http://www.xilinx.com/bvdocs/publications/ds057.pdf
	Temperature	LM75CIMX-3	•	Manufacturer: National*
	Sensor		•	URL: http://www.national.com/pf/LM/LM75.html
	Program-	MAX6306UK	•	Manufacturer: Maxim*
	mable Reset
		29D3	•	URL: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1524
	IC
	Registered	IDT74SSTU3	•	Manufacturer: IDT* (Integrated Device Technology)
	Buffer	2864BF	•	URL: http://www1.idt.com/pcms/products.taf?catID=97&genID=74SSTU32864
	Program-	IDTCSPU877	•	Manufacturer: IDT* (Integrated Device Technology
	mable PLL	BV	•	URL: http://www1.idt.com/pcms/products.taf?catID=112&genID=CSPU877
	256 bit 1-wire	DS2430A_TS	•	Manufacturer: Maxim*
	EEPROM	OC	•	URL: http://www.maxim-ic.com/quick_view2.cfm?qv_pk=2913
	3.3V	MAX561	•	Manufacturer: Maxim*
	Transceiver		•	URL: http://www.maxim-ic.com/quick_view2.cfm?qv_pk=1544
	Battery	ADP3801	•	Manufacturer: Analog Devices*
	Charger		•	URL: http://www.analog.com/UploadedFiles/Data_Sheets/308746738ADP3801_2_0.pdf

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Introduction

1.5Terms and Definitions

Table 4.	Terms and Definitions
	Acronym/Term	Definition
	ARM	Refers to both the microprocessor architecture and the company that licenses it.
	CRB	Customer Reference Board
	ICE	In-Circuit Emulator – A piece of hardware used to mimic all the functions of a
		microprocessor.
	IOP	I/O processor
	JTAG	Joint Test Action Group – A hardware port supplied on Intel XScale® microarchitecture
		evaluation boards used for in-depth testing and debugging.
	PPCI-X	Primary PCI-X.
	PSU	Power Supply Unit
	SPCI-X	Secondary PCI-X.

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Introduction

1.6Intel® 80333 I/O Processor

The 80333 is a follow-on product to the Intel® 80332 I/O processor (80332). It is a multi-function device that combines the Intel XScale® core with intelligent peripherals, and integrates two

PCI Express to PCI-X Bridges. The 80333 consolidates into a single system:

•Intel XScale® core with an internal bus operating at 333 MHz.

•x8 PCI Express Upstream Link.

•Two PCI Express-to-PCI Bridges supporting PCI-X interface on both segments.

•PCI Standard Hot Plug Controller (segment B).

•Address Translation Unit (ATU): PCI-to-Internal Bus Application Bridge, interfaced to the segment A.

•High-Performance Memory Controller.

•Interrupt Controller with 17 external interrupt inputs.

•Two Direct Memory Access (DMA) Controller.

•Peripheral Bus Interface (PBI) Unit.

•Enhanced Application Accelerator Unit (AAU) which supports RAID 6 functionality.

•Two I2C Bus Interface Units (BIU).

•Two 16550 Compatible UARTs with flow control (4 pins).

•Eight General Purpose Input Output (GPIO) Ports.

The 80333 is an integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs.

PCI Express is an industry standard, high performance, low latency system interconnect. The 80333 PCI Express upstream link is capable of x8 lane widths at 2.5 GHz operation as defined by the PCI Express Specification, Revision 1.0a. The addition of the Intel XScale® core brings intelligence to the PCI Express-to-PCI Bridges.

The 80333 integrates dual PCI Express-to-PCI-X Bridges with the ATU as an integrated secondary PCI device. The Upstream PCI Express port implements the PCI-to-PCI Bridge programming model according to the PCI Express Specification, Revision 1.0. The Primary Address Translation Unit is compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a definitions of an ‘application bridge’.

For more in depth information in regards to the 80333, please see the Intel®80333 I/O Processor Developer’s Manual.

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Introduction

Figure 1. Intel® 80333 I/O Processor Block Diagram

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Intel® IQ80333 I/O Processor

Introduction

1.7Intel® IQ80333 I/O Processor Evaluation Platform Board Features

Table 5.	Summary of Features
	Feature		Definition
	Battery Backup Unit:	Battery back up circuit for SDRAM.
	Ethernet	Intel(R) 82545EM Gigabit Ethernet Controller
	Flash ROM:	8 MB Flash ROM 3.3 V – 16-bit Flash I/F.
	Form Factor:	PCI-Express card (312 X 107 mm)
	General Purpose I/O:	GPIO Pins are used as described in the appropriate section in this document
	Hex Display:	Two 7-segment Hex LED displays.
	JTAG Port:	ARM compliant JTAG Header.
	Logic Analyzer:	Logic analyzer connectors on the DDRII SDRAM interface.
		Interposer Card may be used for the memory bus – Information supplied separately.
		• 256 MB (512 Mb x 16) DDRII SDRAM 400 MHz DIMM.
	Memory:	•	ECC
		•	Registered
		Board sources +1.25 V, +2.5 V, +3.3 V, +5 V, +12 V, and -12 V from primary PCI
	Onboard Power:	connector.
		• All core voltages are derived from 3.3 V supply.
		• Auxiliary power for the Secondary PCI slot.
	Power LED:	Power on (green).
	Primary PCI:	PCI Express - x8 lane
		Support for “RAID” 6 functionality– Ability to make the devices plugged in the
	RAID Support	secondary expansion slots “Private”.
		Integrated XOR engine and two iSCSI CRC32C off-load engines.
		• 1 64-bit PCI-X connector - 133 MHz.
	Secondary PCI:	• 1 64 bit 100 MHz PCI-X
		• Intel(R) 82545EM Gigabit Ethernet Controller also on the 100 MHz PCI.
	Serial Port:	Dual RJ11 serial port connectors. The 80333 has two integrated UART serial ports
		which are 16550 compatible.

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The 80333 is a software development environment for IQ80333. Software updates and additional offerings from vendors can change frequently. To keep up-to-date, please visit http://www.intel-ioprocessortools.com/kshowcase/view for the latest updates.

2.1Kit Content

The 80333 Kit contains the following items:

•IQ80333 with 400 MHz DDRII SDRAM DIMMs

•Code|Lab* Development Environment from Accelerated Technology Incorporated*

•JTAG Emulation unit

•Serial Cable and RJ11 Adapter

2.2Hardware Installation

Warning: Static charges can severely damage the boards. Be sure you are properly grounded before removing the board from the anti-static bag.

2.2.1First-Time Installation and Test

For first-time installation, visually inspect the 80333 for any damage made during shipment. Follow the host system manufacturer’s instructions for installing a PCI Express adapter card. The board is a full-length host bus adapter card that requires a PCI Express slot free from obstructions. The IQ80333 has a x8 (read as ‘by eight’) edge connector.

Note: Please note, at this time the IQ80333 does NOT work in a passive backplane. This is due to the nature of the PCI Express linking protocol. For the I/O processor to successfully come out of reset, a link must be established on the PCI Express bus. Without another device on a passive backplane to ‘talk to’, a link is not established.

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Intel® IQ80333 I/O Processor

Getting Started

2.2.2Power Requirements

The 80333 requires a 3.3 V supply coming through the PCI Express primary connector. Plug the board into a desktop with a PCI Express slot.

The 80333 has an auxiliary power receptacle (J1A1, see Section 3.9.4, “Connector Summary”) that is used to power the secondary PCI-X slot. This connector is compatible with a standard ATX hard drive power connector.

Caution: Before connecting power to the entire system, verify that the auxiliary system power to the secondary PCI-X slot and the main power to the 80333 are both connected. Both power rails should come up at the same time. When there is not a card plugged into the secondary PCI-X slot, then the auxiliary power can be left unconnected.

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Getting Started

2.3Factory Settings

Make sure that the switch/jumper settings are set to proper positions as explained in Section 3.9, “Switches and Jumpers” on page 38.

2.4Development Strategy

2.4.1Supported Tool Buckets

For developing and debugging software application, the production version of the 80333 kit includes the Code|Lab Development Environment. Support for the Code|Lab development environment is available from MGC*. Please refer to the enclosed package.

The following tools are available for evaluation purposes (please contact appropriate vendor). These tools are for evaluation purposes and do not include any support. Please contact the vendor directly for additional information and support. They include, but are not limited to:

•RedHat* GNUPro tools

•ARM RealView Developer Suite

•WindRiver* VxWorks* RTOS and Tornado* Development Tools

•Wasabi Systems NetBSD* OS

•TimeSys* Linux* RTOS

•Accelerated Technology Inc.*, Nucleus Plus* RTOS and Development Tools

Please contact your Intel representative for the latest updates or visit

http://www.intel-ioprocessortools.com/kshowcase/view.

2.4.2Contents of the Flash

The production version of the board contains an image for RedHat RedBoot* target monitor.

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