3 Using the USB Download Cable........................................................................................ 9
3.1 Installing the USB Download Cable Driver on Windows................................................ 9
3.2 Installing the USB Download Cable Driver on Linux..................................................... 9
3.2.1 Installing on Red Hat Enterprise 4 or Earlier Versions..................................... 10
3.2.2 Installing on Red Hat Enterprise 5............................................................... 10
3.3 Setting up the USB Download Cable Hardware in the Quartus Prime Software............... 10
3.4 Connecting the USB Download Cable to the Board..................................................... 11
4 Revision History for USB Download Cable User Guide.................................................... 13
Intel FPGA USB Download Cable User Guide
2
1 Introduction to USB Download Cable
1 Introduction to USB Download Cable
The USB Download Cable interfaces a USB port on a host computer to an FPGA
mounted on a printed circuit board. The cable sends configuration data from the host
computer to a standard 10-pin header connected to the FPGA. You can use the USB
Download Cable to iteratively download configuration data to a system during
prototyping or to program data into the system during production.
1.1 USB Download Cable Revision
Table 1.USB Download Cable Revision
RevisionIndicatorDescriptionRoHS Compliant
Rev. ARibbon cable. No revision
marking on the casing.
Rev. B"Rev. B" on the casing.10-pin female connector that is connected to the
Rev. C"Rev. C" on the casing.10-pin female connector that is connected to the
10-pin female connector that is connected to the
USB Download Cable through a ribbon cable.
USB Download Cable through a flexible PCB cable.
USB Download Cable through a flexible PCB cable.
No
No
Yes
1.2 Supported Devices and Host Systems
You can use the USB Download Cable with supported Intel® FPGAs, serial
configuration devices, and host systems.
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX,
Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or
other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance
of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Intel assumes
no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
EPCS devices
EPCQ devices
EPCQ-L devices
Windows
Linux
ISO
9001:2008
Registered
USBInterface
Chip
EPM7064AETC44
I/Os
I/Os
V
CC (TRGT)
Pin 1
V
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
USBVCC
USB
Receptacle
10-Pin
Female Plug
Voltage Translator
Circuitry
0.5 (1)
7.5 (1)
2.5
1.0
2.0
(1) Applies to Rev. B and Rev. C.
All Dimensions are in inches.
2 Specifications for USB Download Cable
2 Specifications for USB Download Cable
The USB Download Cable has a universal USB connector that plugs into the PC USB
port, and a female connector that plugs into a male header on the device board. This
section shows the hardware components, their dimensions, and lists the pins,
operating conditions and power requirements.
2.1 Block Diagram and Dimension
Figure 1.Block Diagram of the USB Download Cable
Figure 2.Dimension of the USB Download Cable
2.2 Cable-to-Board Connection
TheUSB Download Cable has a 10-pin female connector, which plugs into a 10-pin
male header on the device board. The male header consists of two rows of five pins,
which are connected to the programming or configuration pins of the device.
2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX,
Megacore, NIOS, Quartus and Stratix words and logos are trademarks of Intel Corporation in the US and/or
other countries. Other marks and brands may be claimed as the property of others. Intel warrants performance
of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Intel assumes
no responsibility or liability arising out of the application or use of any information, product, or service
described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the
latest version of device specifications before relying on any published information and before placing orders for
products or services.
ISO
9001:2008
Registered
0.023 Sq .
0.235
0.100
Side View
0.100
Top View
Dimensions are in inches
10-pin Male Header
0.250 Typ.
0.700 Typ.
0.425 Typ.
0.100 Sq.
1098765432
1
0.025 Sq.
Spacing between pin centers is 0.1 inches.
10-pin Female Connector
(Device Board)
2 Specifications for USB Download Cable
A 10-pin surface mount header can be used for the JTAG, AS, or PS download cable.
However, Intel recommends using a through-hole connector because of the repeated
insertion and removal force needed.
Figure 3.Connectors and Dimensions
2.3 Pin Description
The following table lists the pins of the USB Download Cable female plug and describes
their functions in the JTAG, active serial and passive serial modes.
Table 3.Signal Names of the USB Download Cable Female Plug
PinAS ModePS ModeJTAG Mode
Signal NameDescriptionSignal NameDescriptionSignal NameDescription
10
1
2
3
4
5
6
7
8
9
DCLK
GND
CONF_DONE
V
CC(TRGT)
nCONFIG
nCE
DATAOUT
nCS
ASDI
GND
Clock signal.
Signal ground.
Configuration
done.
Target power
supplied by the
device board.
Configuration
control.
Cyclone chip
enable.
Active serial data
out.
Serial
configuration
device chip
select.
Active serial data
in.
Signal ground.
DCLK
GND
CONF_DONE
V
CC(TRGT)
nCONFIG
————
nSTATUS
————
DATA0
GND
Clock signal.
Signal ground.
Configuration
Target power
supplied by the
device board.
Configuration
Configuration
Data to device.
Signal ground.
done.
control.
status.
TCK
GND
TDO
V
CC(TRGT)
TMS
——
TDI
GND
Clock signal.
Signal ground.
Data from
device.
Target power
supplied by the
device board.
JTAG state
machine control.
Data to device.
Signal ground.
Intel FPGA USB Download Cable User Guide
5
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