Intel Xeon, E7500, E7501 Design Manual

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset

Compatible Platform

Design Guide Addendum for Embedded Applications

July 2003

Order Number: 273707-004

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Xeon™ Processor with 512 KB L2 Cache, the Intel®E7500 chipset and the Intel® 7501 chipset may contain design defects or errors known

2 Platform Design Guide Addendum

Contents

1.0 Introduction......................................................................................................................................7

1.1 Reference Documentation ....................................................................................................7

2.0 Uni-processor System Bus Routing Guidelines...............................................................................9

2.1 Routing Guidelines for the 2X and 4X Signal Groups.........................................................11

2.1.1 Design Recommendations.....................................................................................12

2.2 Routing Guidelines for Common Clock Signals..................................................................13

2.2.1 Wired-OR Signals..................................................................................................13

2.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals...........................14

2.3.1 Asynchronous GTL+ Signals Driven by the Processor..........................................15

2.3.1.1 Voltage Translation for FERR#..............................................................15

2.3.1.2 Proper THERMTRIP# Usage.................................................................16

2.3.2 Asynchronous GTL+ Signals Driven by the Chipset..............................................17

2.3.2.1 Voltage Translation for INIT#.................................................................17

2.3.3 BR[3:0] Routing Guidelines for Uni-processor Designs.........................................18

3.0 Memory Interface Routing Guidelines ...........................................................................................21

3.1 DIMM Types .......................................................................................................................22

3.2 Dual Channel DDR Overview .............................................................................................22

3.2.1 Dual Channel Source Synchronous Signal Group Routing ...................................23

3.2.2 Dual Channel Command Clock Routing................................................................25

3.2.3 Dual Channel Source Clocked Signal Group Routin g ...........................................26

3.2.4 Dual Channel Chip Select Routing ........................................................................27

3.2.5 Dual Channel Clock Enable Routing .....................................................................28

3.2.6 2.5 Volt Decoupling Requirements ........................................................................28

3.3 Single Channel DDR Overview...........................................................................................30

3.3.1 Unused Channel B.................................................................................................31

3.3.2 Single Channel Source Synchronous Signal Group Routing.................................32

3.3.3 Single Channel Command Clock Routing..............................................................36

3.3.4 Single Channel Source Clocked Signal Group Routing.........................................37

3.3.5 Single Channel Chip Select Routing......................................................................38

3.3.6 Single Channel Clock Enable Routing...................................................................39

3.3.7 Single Channel DC Biasing Signals.......................................................................40

3.3.7.1 Single Channel Receive Enable Signal (RCVEN#) ...............................40

3.3.7.2 Single Channel DDRCOMP...................................................................41

3.3.7.3 Single Channel DDRVREF and ODTCOMP..........................................41

3.3.7.4 Single Channel DDRCVO......................................................................41

3.3.8 Single Channel DDR Signal Termination and Decoupling.....................................42

3.3.9 2.5 V Decoupling Requirements ............................................................................42

Platform Design Guide Addendum 3

Contents

Figures

1 Uni-processor System Bus Topology .........................................................................................10

2 Topology for Asynchronous GTL+ Signals Driven by the Processor..........................................15

3 FERR# Routing Topology for Low Voltage Intel

1 Recommended THERMTRIP# Circuit .......................................... ...... ....... ...... ...........................16

4 Topology for Asynchronous GTL+ Signals Driven by the Chipset..............................................17

5 INIT# Routing Topology for a Uni-processor System .................................................................18

6 Voltage Translator Circuit...........................................................................................................18

7 BR[3:0]# Connection for UP Configuration.................................................................................19

8 DIMM Connector Styles Supported............................................................................................22

9 1-DIMM per Channel Implementation.........................................................................................23

10 2-DIMMs per Channel Implementation.......................................................................................23

11 Dual Channel 2-DIMM Command Clock Topology.....................................................................26

12 1-DIMM Per Channel Decoupling...............................................................................................29

13 2-DIMMs Per Channel Decoupling.............................................................................................30

14 Single Channel 2-DIMM Implementation....................................................................................31

15 Single Channel 4-DIMM Implementation....................................................................................31

16 Single Channel Source Synchronous Topology DIMM Solution ................................................35

17 Trace Length Matching Requirements for Single Channel Source Synchronous Routing.........35

18 Single Channel 2-DIMM Command Clock Topology ..................................................................36

19 SIngle Channel Source Clocked Signal Topology......................................................................37

20 Single Channel Chip Select Topology........................................................................................38

21 Single Channel CKE Topology...................................................................................................39

22 Single Channel Receive Enable Signal Routing Guidelines.......................................................40

23 Single Channel DDRCOMP Resistive Compensation................................................................41

24 Single Channel DDRCVO Single Channel Routing Guidelines..................................................42

25 Single Channel 2-DIMM Decoupling ..........................................................................................43

26 Single Channel 4-DIMM Decoupling ..........................................................................................44

Xeon™ Processors.......................................16

Tables

1 Reference Documents..................................................................................................................7

2 System Bus Signal Groups...........................................................................................................9

3 Uni-processor System Bus Routing Summary ...........................................................................10

4 2X and 4X Signal Groups...........................................................................................................11

5 Source Synchronous Signals and Associated Strobes ..............................................................11

6 Common Clock Signals ..............................................................................................................13

7 Asynchronous GTL+ and Miscellaneous Signals .......................................................................14

8 Dual Channel Source Synchronous Signal Group Routing Guidelines......................................24

9 Dual Channel Command Clock Pair Routing Guidelines ...........................................................25

10 Dual Channel Source Clocked Signal Group Routing Guidelines..............................................26

11 Dual Channel Chip Select Routing Guidelines ...........................................................................27

12 Dual Channel Clock Enable Routing Guidelines ........................................................................28

13 Channel B Signal Terminations..................................................................................................32

14 Single Channel DQ/CB to DQS Mapping ...................................................................................32

15 Single Channel Source Synchronous Signal Group Routing Guidelines ...................................34

16 Single Channel Command Clock Pair Routing Guidelines.........................................................36

4 Platform Design Guide Addendum

Contents

17 Single Channel Source Clocked Signal Group Routing Guidelines............................................37

18 Single Channel Chip Select Routing Guidelines.........................................................................38

19 Single Channel Clock Enable Routing Guidelines......................................................................39

20 Single Channel Receive Enable Routing Guidelines..................................................................40

21 DDRCOMP Routing Guidelines..................................................................................................41

22 DDRCVO Routing Guidelines.................... ...... ....... ...... ...... .............................................. ...... ... .42

Revision History

Date Revision Description

July 2003 -004

January 2003 -003

June 2002 -002 Document Update

January 2002 -001 Initial Release

Updated memory interface routing information and added Low Voltage Intel

Updated and expanded memory interface routing information. Added E7501 chipset information.

XeonTM processor information.

Platform Design Guide Addendum 5

Contents

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6 Platform Design Guide Addendum

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

1.0 Introduction

This document is an addendum to the Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform Design Guide. It contains applied computing-specific guidelines, such as uni-

processor design guidelines, angl ed Double Data Rate (DDR) guidelines and single channel DDR guidelines.

Carefully follow the design information and recommendations provided in this document. These design guidelines have been developed to ensure maximum flexibility for system designers while reducing the risk of board-related issues.

Note that the guidelines recommended in this document are based on experience and preliminary simulation work done at Intel.

1.1 Reference Documentati on

T a ble 1. Reference Documents (Sheet 1 of 2)

Document Location

Intel

E7501 Chipset Memory Controller Hub (MCH)

Datasheet Intel® Xeon™ Processor and Intel® E7500/E7501

Chipset Compatible Platform Design Guide Intel® Xeon™ Processor with 512 KB L2 Cache and

Intel E7500 Chipset Platform Design Guide Intel® Xeon™ Processor with 512 KB L2 Cache at

1.80 GHz to 2.40 GHz Datasheet Intel® E7500 Chipset Memory Controller Hub (MCH)

Datasheet Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2)

Datasheet Intel 82801CA I/O Controller Hub 3 (ICH-3) Datasheet

Intel® 82870P2 PCI/PCI-X 64-bit Hub 2 (P64H2) Specification Update

Intel® 82801CA I/O Controller Hub 3 (ICH3-S) Specification Update

603-Pin Socket Design Guidelines

VRM 9.1 DC-DC Converter Design Guidelines

Intel® Xeon™ Processor Voltage Regulator Down (VRD) Design Guidelines

Intel® Xeon™ Processor with 512 KB L2 Cache System Compatibility Guidelines

Intel® Xeon™ Processor Thermal Design Guidelines

Intel® E7500 Chipset Thermal and Mechanical Design Guidelines

http://developer.intel.com/design/chipsets/datashts/

251927.htm http://developer.intel.com/design/chipsets/designex/

251929.htm http://developer.intel.com/design/chipsets/e7500/

guides/298649.htm http://developer.intel.com/design/Xeon/datashts/

298642.htm http://developer.intel.com/design/chipsets/e7500/

datashts/290730.htm http://developer.intel.com/design/chipsets/e7500/

datashts/290732.htm http://developer.intel.com/design/chipsets/e7500/

datashts/290733.htm http://www.intel.com/design/chipsets/e7500/

specupdt/290735.htm http://www.intel.com/design/chipsets/e7500/

specupdt/290739.htm http://developer.intel.com/design/Xeon/guides/

249672.htm http://developer.intel.com/design/Xeon/guides/

298646.htm http://developer.intel.com/design/Xeon/guides/

298644.htm http://developer.intel.com/design/Xeon/guides/

298645.htm http://developer.intel.com/design/Xeon/guides/

298348.htm http://developer.intel.com/design/chipsets/e7500/

guides/298647.htm

Platform Design Guide Addendum 7

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

T able 1. Reference Documents (Sheet 2 of 2)

Document Location

Intel® Xeon™ Processor Thermal Solution Functional Specifications

Intel® Xeon™ Processor with 512 KB L2 Cache Thermal Models

Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Model in IGES

Intel® Xeon™ Processor with 512 KB L2 Cache Mechanical Model in ProE* Format

AP-728 Intel ® ICH Family Real Time Clock (RTC) Accuracy and Considerations Under Test Conditions

ITP700 Debug Port Design Guide Intel® Xeon™ Processor with 512 KB L2 Cache Signal

Integrity Models PCI Bus Power Management Interface Specification,

Revision 1.1

PCI Hot Plug Specification, Revision 1.1

PCI Local Bus Specification, Revision 2.2 PCI-PCI Bridge Architecture Specification, Revision

1.1 PCI Standard Hot-Plug Controller and Subsystem

Specification, Revision 1.0 PCI-X Specification, Revision 1.0a http://www.pcisig.com/specifications/pcix_20/pci_x/ System Management Bus Specification (SMBus),

Revision 1.1 Universal Serial Bus Specification, Revision 1.1 http://www.usb.org/developers/docs/ Low Voltage Intel® XeonTM processor at 1.6 GHz and

2.0 GHz Datasheet Intel® XeonTM processor with 533 MHz System Bus at

2.0 GHz to 2.8 GHz Datasheet Low Voltage Intel® XeonTM processor for Embedded

Applications Thermal Design Guidelines

http://developer.intel.com/design/Xeon/applnots/

249673.htm

http://developer.intel.com/design/Xeon/devtools/

http://developer.intel.com/design/Xeon/devtools/ http://developer.intel.com/design/chipsets/applnots/

292276.htm http://developer.intel.com/design/Xeon/guides/

249679.htm

http://developer.intel.com/design/Xeon/devtools http://www.pcisig.com/specifications/conventional/

pci_bus_power_management_interface http://www.pcisig.com/specifications/conventional/

pci_hot_plug http://www.pcisig.com/specifications/conventional/

conventional_pci http://www.pcisig.com/specifications/conventional/

pci_to_pci_bridge_architecture http://www.pcisig.com/specifications/conventional/

pci_hot_plug

http://www.sbs-forum.org/

http://www.intel.com/design/intarch/datashts/

273766.htm http://www.intel.com/design/xeon/datashts/

252135.htm http://www.intel.com/design/intarch/designgd/

273764.htm

8 Platform Design Guide Addendum

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

2.0 Uni-processor System Bus Routing Guidelines

This section covers the system bus source synchronous (data, address, and associated strobes) and common clock signal routing for Intel FSB)/Low Voltage Intel

Xeon™ processor (400 MHz FSB) and Intel® E7500/E7501 chipsetbased systems, in a uni-processor (UP) configuration. Table 2 lists the signals and their corresponding signal types .

Figure 1 describes the uni-processor system bus topology.

T a ble 2. System Bus Signal Groups

Signal Group Type Signals

AGTL+ Common Clock Input Synchronous to BCLK

AGTL+ Common Clock I/O Synchronous to BCLK

AGTL+ Source Synchronous I/O: 4X Group

AGTL+ Source Synchronous I/O: 2X Group

AGTL+ Strobes

Async GTL+ Input

Async GTL+ Output System Bus Clock Clock BCLK0, BCLK1

TAP Input TAP Output

SMBus Interface

Power/Other Power/Other

NOTES:

1. These signals do not have on-die termination on the processor. They must be terminated properly on the system board. If the signal is not connected, it must be pulled to the appropriate voltage level t hrough a 1 kΩ ± 5% resistor.

2. Xeon processors use only BR0# and BR1#.

3. These signals are ‘wired-OR’ signals and may be driven simultaneously by multiple agents. For further details on how to implement wired-OR signals, refer to the routing guidelines in Section 2.2.1.

4. The value of these pins driving the active edge of RESET# determine processor configuration options.

5. SM_V

6. Terminations and routing for TAP signals and all debug port signals are found in the ITP700 Debug Port Design Guide.

7. PROCHOT # is input/output on Low Voltage Intel® Xeon™ processor D-stepping and beyond.

has critical power sequencing requirements.

Xeon™ processor with 512 KB L2 cache (400/533 MHz

BPRI#, BR[3:1]#

1,2

, DEFER#, RESET#1,

RS[2:0]#, RSP#, TRDY#

, BNR#3,

, LINT0/INT R,

Synchronous to associated strobe

Synchronous to BCLK [1:0]

Asynchronous

ADS#, AP[1:0]#, BINIT# BPM[5:0]# DRDY#, HIT# MCERR#

, BR0#1, DBSY#, DP[3:0]#,

, HITM#3, LOCK#,

D[63:0]#, DBI[3:0]#

A[35:3]#

, REQ[4:0]#

ADSTB[1:0]#, DSTBN[3:0]#, DSTBP[3:0]# A20M#, IGNNE#, INIT#

LINT1/ NMI, PWRGOOD, SMI# STPCLK#

Asynchronous

FERR#, IERR#, THERMTRIP#, PROCHOT#

Synchronous to TCK TCK, TDI, TMS, TRST# Synchronous to TCK TDO

Synchronous to SM_CLK

SM_EP_A[2:0], SM_TS_A[1:0], SM_DA T, SM_CLK, SM_ALERT#, SM_WP

GTLREF[3:0], COMP[1:0], OTDEN , RESERVED, SKTOCC#, TESTHI[6:0], VID[4:0], VCC_CPU, SM_V V

SSA

SSSENSE

, V

CCIOPLL

, VSS, V

CCSENSE

, SLP#,

, V

CCA

Platform Design Guide Addendum 9

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

Figure 1. Uni-processor System Bus Topology

Note:

Package trace Motherboard PCB trace

Processor MCH

Pad

Length L1 = 3.5 - 10"

Refer to Table 3 for a summary of the uni-processor system bus routing recommendations. Use this as a quick reference only. The following sections provide more information for each parameter. Intel strongly recommends simulation of all signals to ensure that setup and hold times are met.

T a ble 3. Uni-processor System Bus Routing Summary

Parameter Platform Routing Guidelines

Trace width/spacing 5/15 mils

3.5“– 10“pin-to-pin

4X signal group line lengths

DSTBn/p[3:0]# line lengths

2X signal group line lengths Address signals should follow the same routing rules as the data signals. ADSTB[1:0]# line lengths ADSTB# signals should follow the same routing rules as the DSTB# signals. Common clock signal line

lengths Topology The processor must have on-die termination enabled.

Routing priorities

Reference plane requirements

System board Impedance 50 Ω ± 10%

Length must be added to the system board trace between agents to compensate for the stub created by the processor package

DSTB# signals should follow the same routing rules as the data signals A 25 mil spacing should be maintained around each strobe signal (between

DSTBp# and DSTBn#, and any other signal.)

Common clock signals should follow the same routing rules as the data signals, however no length compensation is necessary.

All signals within the same strobe group must be routed on same layer for the entire length of the bus.

Ground reference only. Avoid changing layers when routing system bus signals. If a layer change must occur, use vias connecting the two reference planes to

provide a low impedance path for the return current. Vias should be as close as possible to the signal via.

Pad

A9044-01

10 Platform Design Guide Addendum

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

2.1 Routing Guidelines fo r the 2X and 4X Signal Groups

The 4X group of signals uses four times the frequency of the base clock, or 400 MHz. The 2X group uses twice the frequency of t h e bas e cloc k, o r 20 0 MHz. The 2 X and 4 X si gn als are l i st ed i n

Table 4. Table 5 lists the 2X and 4X signals with their associated strobes.

Table 4. 2X and 4X Signal Groups

2X Group 4X Group

HA[35:3]#

REQ[4:0]#

Table 5. Source Synchronous Signals and Associated Strobes

Signals Associated Strobe

REQ[4:0]#, HA[16:3]# ADSTB0# HA[35:17]# ADSTB1# HD[15:0]#, DBI0# DSTBP0#, DSTBN0# HD[31:16]#, DBI1# DSTBP1#, DSTBN1# HD[47:32]#, DBI2# DSTBP2#, DSTBN2# HD[63:48]#, DBI3# DSTBP3#, DSTBN3#

HD[63:0]#

DBI[3:0]#

Routing guidelines for the 2X and 4X signal groups are given below:

• Trace impedance = 50 Ω ± 10%

• Route traces using 5/15 mil spacing

• Route all traces at least 25 mils away from the strobes

• Route all traces with at least 50% of the trace width directly over the reference plane for short

distances only when needed in the interposer socket region.

• Route signals and their associated strobes on the same layer for the entire length of the bus.

• A strobe and its complement must be routed within 25 mils of the same length over the entire

length of the buses.

• All 2X and 4X signals of the same group (refer to Table 5) m ust be routed within ±25 mils of

the same length between the agents and within ±50 mils of the entire length of the bus.

• Total bus length must not exceed 10”.

• Trace length matching is required. Please contact your Intel field representative for a length

matching spreadsheet.

Trace length matching is required within each source synchronous group to compensate for the package trace length differences between data signals and the associated strobe. This will balance the strobe- t o-signal skew in the middle of the setup and hold window. Figure 1 shows how t o implement trace length matching. An example of trace length matching is given in Equation 1.

Platform Design Guide Addendum 11

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

2.1.1 Design Recommendations

Below are the design recommendations for the data, address, strobes, and common clock signals. For the following discussion, the pad is defined as the attach point of the silicon pad to the package substrate.

DATA:

• The pin to pin distance from the processor to the chipset should be between 3.5" to 10" (i.e.,

3.5" < L1 < 10"). Data signals of the same source synchronous group should be routed to the same pad to pad length within ± 100 mils of the associated strobes. As a result, additional traces will be added to some data nets on the system board in order for all trace lengths within the same data group to be the same length (± 100 mils) from the pad of the processor to the pad of the chipset. This length compensation will result in minimizing the source sync hro nou s skew that exists on the system bus. Without the length compensation the flight times between a data signal and its strobe is different, which results in an inequity between the s etup and ho ld times.

Equation 1. Calculating Package Delta Addition to System Board Length for UP Systems

delta

net,strobe

ADDRESS:

= (cpu_pkglen

† Strobe package length is the average of the strobe pair.

- cpu_pkglen

net

) + (chipset_pkglen

strobe†

- chipset_pkglen

net

strobe

• Address signals follow the same rules as data signals except they should be routed to the same

pad to pad length within ±200 mils of the associated strobes. Address signals may change layers if the reference plane remains Vss and as long as the layers for a given group are all of the same configuration (all stripline or all microstrip).

STROBE:

• A strobe and its complement should be routed to a length equal to their corresponding data

group's median pad-to-pad length ±25 mils. This causes the strobe to be received closer to the center of the data pulse, which results in reasonably comparable setup and hold times. A strobe and its complement (xSTBp/n#) should be routed to ±25 mils of the same length. It is recommended to simulate skew in order to determine the length that best centers the strobe for a given system.

COMMON CL OCK:

• Common clock signals should be routed to a minimum pin-to-pin system board length of 6"

and a maximum motherboard length of 10".

)

12 Platform Design Guide Addendum

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

2.2 Routing Guidelines for Common Clock Signals

Table 6 lists the common clock signals.

Table 6. Common Clock Signals

Signal Type Signals

BPRI# BR[3:1]# DEFER#

AGTL+ Common Clock Input

AGTL+ Common Clock I/O

RESET# RS[2:0]# RSP# TRDY#

ADS# AP[1:0]# BINIT# BNR# BPM[5:0]# BR0# DBSY# DP[3:0]# DRDY# HIT# HITM# LOCK# MCERR#

Routing guidelines for the source synchronous signal group are given below:

• Trace impedance = 50 Ω ±10%

• Route traces using 5/15 mil spacing

• Keep signals on the same layer for the entire length of the bus

• Route traces with at least 50% of the trace width directly over a reference plane

• Total bus length must not exceed 10"

2.2.1 Wired-OR Signals

There are five wired-OR signals on the system bus. These signals are HIT#, HITM#, MCERR#, BINIT#, and BNR#. These signals differ from the other fr ont-side bus signals in that more than one agent can be driving the signal at the same time. Timing and signal integrity must be met for the case where one agent is driving, all agents are driving, or any combination of agents are driving.

The wired-OR signals should follow the same routing rules as the common clock signals. Intel recommends that simulations for these signals be performed for a given system.

Platform Design Guide Addendum 13

Intel® Xeon™ Processor and Intel® E7500/E7501 Chipset Compatible Platform

2.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals

This section provides routing guidelines for the sign als listed in Table 7.

Table 7. Asynchronous GTL+ and Miscellaneous Signals

Signal Name Type CPU I/O Type Driven by Received by

A20M# Async GTL+ I ICH3-S Processor BINIT# AGTL+ I/O Processor Processor BR[3:1]# AGTL+ I Processor Processor BR0# AGTL+ I/O Processor/MCH Processor/Chipset COMP[1:0] Analog I Pull-down Proc e ssor FERR# Async GTL+ O Processor Chipset IERR# Async GTL+ O P rocessor External Logic IGNNE# Async GTL+ I ICH3-S Processor INIT# Async GTL+ I ICH3-S Processor LINT[1:0] Async GTL+ I ICH3-S Processor ODTEN Other I Pull-up/Pull-down Processor PROCHOT# Async GTL+ O Processor External Logic PWRGOOD Async GTL+ I External Logic Processor SLP# Async GTL+ I ICH3-S Processor SM_ALERT# SMBUS (3.3 V) O Processor/Controller Controller SM_CLK SMBUS (3.3 V) I/O Processor/Controller Processor/Controller SM_DAT SMBUS (3.3 V) I/O Processor/Controller Processor/Controller SM_EP_A[2:0] SMB US (3.3 V) I Pull-up/Pull-down Processor SM_TS_A[1:0] SMBUS (3.3 V) I Pull-up/Pull-down Processor SM_WP SMB US (3.3 V) I External Logic Processor SMI# Async GTL+ I ICH3-S Processor STPCLK# Async GTL+ I ICH3-S Processor THERMTRIP# Async GTL+ O Processor External Logic VCCA Power I Pull-up/Pull-down Processor VCCIOPLL Power I Pull-up/Pull-down Processor VCCSENSE Other O Processor Voltage Regulator VID[4:0] Other O Processor Voltage Regulator GTLREF Po wer I Pu ll-up/Pull-down Processor VSSA Power I Pull-up/Pull-down Processor

14 Platform Design Guide Addendum

+ 30 hidden pages

Intel Xeon, E7500, E7501 Design Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Contents

Figures

Tables

Revision History

1.0 Introduction

1.1 Reference Documentati on

T a ble 1. Reference Documents (Sheet 1 of 2)

2.0 Uni-processor System Bus Routing Guidelines

T a ble 2. System Bus Signal Groups

Figure 1. Uni-processor System Bus Topology

T a ble 3. Uni-processor System Bus Routing Summary

2.1 Routing Guidelines fo r the 2X and 4X Signal Groups

Table 4. 2X and 4X Signal Groups

Table 5. Source Synchronous Signals and Associated Strobes

2.1.1 Design Recommendations

2.2 Routing Guidelines for Common Clock Signals

Table 6. Common Clock Signals

2.2.1 Wired-OR Signals

2.3 Routing Guidelines for Asynchronous GTL+ and Miscellaneous Signals

Table 7. Asynchronous GTL+ and Miscellaneous Signals