Intel DP35DPM Schematics Rev3.03

CR-1 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE1

8 2

PAGE #

COMPONENT/FUNCTION

[1. INDEX]
[2. BLOCK DIAGRAM]
[3. RESET MAP]
[4. CLOCK DISTRIBUTION]

D

[5. GPIO, IRQ, IDSEL MAP]
[6. CPU-SOCKET 1 OF 2]
[7. CPU SOCKET 2 OF 2]
[8. CPU TERMINATION & MISC P/U P/D]
[9. CPU PLL FILTERED SUPPLY]
[10. MCH SECTIONS PAGE 1 OF 6]
[11. MCH SECTIONS PAGE 2 OF 6]
[12. MCH SECTIONS PAGE 3 OF 6]
[13. MCH SECTIONS PAGE 4 OF 6]
[14. MCH SECTIONS PAGE 5 OF 6]
[15. MCH SECTIONS PAGE 6 OF 6]

C

[16. PLL & CRT FILTERS]
[17. MCH DECOUPLING AND COMP]
[18. MCH DCPL & VGA TERMINATION]
[19. MCH VREFS & TERMINATION]
[20. VGA CONNECTOR]
[21. PCI EXPRESS X16]
[22. PCI EXPRESS X16]
[23. PCI EXPRESS X16 COUPLING]
[24. 240P CONN DDR2, CH A]
[25. 240P CONN DDR2, CH B]
[26. DDR VTT TERMINATION]
[27. DDR VTT DECOUPLING]

B

[28. CK505 PAGE 1 OF 2]
[29. CK505 PAGE 2 OF 2]
[30. ICH9 1 0F 6 CONTROL]
[31. ICH9 2 OF 6 CONTROL]
[32. ICH9 3 OF 6 CONTROL]
[33. ICH9 4 OF 6 - CONTROL]
[34. ICH 5 OF 6 - CONTROL]
[35. ICH 6 OF 6 - GROUND BODY]
[36. GPIO TERMINATION & RST STRAPS]
[37. ICH PIN STRAPS]
[38. ICH DECOUPLING]
[39. ME & CONTROL BUFFERS/ICH CIRCUITS]
[40. SERIAL FLASH PRIMARY]
[41. SATA CONNECTORS]
[42. USB FP HDR 1]
[43. USB FP HDR 2]
[44. USB FP HDR 2]
[45. BACK PANEL USB]
[46. BACK PANEL USB WITH ESATA]
[47. PCI EXPRESS X1 #1]

[48. PCI CONN 1]
[49. PCI CONN 2]

8

7

PAGE #

6

COMPONENT/FUNCTION

[50. PCI TERMINATION]
[51. STD FRONT PANEL HDR]
[52. USB_FP_HEADER_POWER]
[53. 1394 CONTROLLER]
[54. 1394 BP REV1]
[55. 1394 PWR/DCPL]
[56. LAN NINEVEH]
[57. LAN NINEVEH]
[58. LAN NINEVEH]
[59. AUDIO CODEC]
[60. AUDIO DECOUPLING & JACK SENSE]
[61. AUDIO SPDIF]
[62. AUDIO JACK (BLUE GREEEN PINK]

45

PAGE #

COMPONENT/FUNCTION

[97. PRIMARY XDP-LITE]
[98. PATA]

[99. PATA]
[100. TEST SITE CAPS]
[101. PCI EXPRESS X1 #2]
[102. PCI EXPRESS X1 #3]
[103. PCI CONN 3]
[104. AUX FAN CONFIGURATION]
[105. HARDWARE MANAGEMENT: HECETA]
[106. ITE IT8211F 1 OF 2]
[107. PATA 2ND CONNECTOR]

3

REVISIONS

REV

REV

2.02

DESCRIPTION

DESCRIPTION

DESIGN

REVISIONS

DFT

DATE

DFT

DATE

2006

CHK APVD

CHK

1

DATE DATE

DATE

APVD

DATE

D

[63. AUDIO JACK (BLACK ORANGE]
[64. AUDIO FP HEADERS & HDA HEADER]
[65. AUDIO MIC BIAS]
[66. AUDIO VREG]
[67. SPDIF HEADER]
[68. TPM 1.2]
[69. PORT ANGELES 1 OF 2]
[70. PORT ANGELES 2 OF 2]
[71. FDD CONN]

BEARLAKE-B ATX

CLASSIC SKU

FROSTBURG

DRAGONTAIL PEAK

FAB C

C

[72. PS/2 CONNECTOR]
[72. LPT SIGNALS]
[73. LPT SIGNALS]
[74. SERIAL PORT A]
[75. STUDIES PURPOSE]
[76. SST SENSOR]
[77. FAN CONFIGURATION]
[78. MTG HOLES/LABELS]
[79. CORE VREG]
[80. CORE VREG]

TAPE-OUT: WWXX-2006
FAB A

REV

CONROE, BEARLAKE, DDR?, ICH9,
2-CHANNEL DDR2, PCIEXPRESS GFX, ATX
CUSTOMER REFERENCE BOARD

POWER SYMBOLS USED:
VCC3

VCC
+12V

-12V

3.03

B

[81. VREG_SM_VTT]
[82. VREG_1P25_CORE MCH]
[83. MCH DCPL]
[84. CORE VREG]
[85. VREG_FSB VTT & SFR]
[86. VREG 1.25 MCH CL]
[87. CORE VREG]
[88. CORE VREG]
[89. CORE VREG]
[90. NO PAGE TITLE FOUND!!!]
[91. WAKE CONTROL SWITCH PS2/USB (BP RIGHT)]
[92. VREG: DECOUPLING AND STITCHING]
[93. VCCP VREG]
[94. VCCP VREG]
[95. VCCP VREG]

[96. VREG: VCCP DECOUPLING / 2X2 CONN]

7

65

[PAGE_TITLE=INDEX]

BPAGE DRAWING

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4 2

NOTES:

1. THIS SCHEMATIC DOCUMENTS THE GENERIC PRODUCT WITH
ALL POSSIBLE CONFIGURATIONS.
PLEASE REFER TO SPECIFIC PRODUCT PBA EPL FOR
ITEMS SHOWN AS OPTIONAL IN THE SCHEMATIC.

2. RESISTORS ARE IN OHMS UNLESS OTHERWISE SPECIFIED.

3. VCC = +5V UNLESS OTHERWISE SPECIFIED.

4. * SUFFIX INDICATES ACTIVE LOW SIGNAL.

5. \I SUFFIX INDICATES SIGNAL EXITS HIERARCHICAL BLOCK.

6. THIS DOCUMENT ALSO EXISTS ON ELECTRONIC MEDIA.

BOM_RELEASE_DATE

SIGNATURE

?

DRN_BY

?

CHK_BY
ENGR_APVD

CUSTOM TEXT B-PAGE

3

?

?

PB_NUMBER

?

inte

TITLE

?

?

?

CONFIDENTIAL

INTEL

?

DOCUMENT_NUMBER

xxxxxx

S

3065 BOWERS AVEDATE
SANTA CLARA, CA

PAGE REV

1/107

1

95051

3.01

AA

POWER
SUPPLY CONN

XDP SSA

D

FRONT PANEL

USB PORT 1

C

USB PORT 2

FRONT PANEL

USB PORT 3

USB PORT 4

BACK PANEL

USB PORT 1

USB PORT 2

USB PORT 3

USB PORT 4

B

USB PORT 5

USB PORT 6

CR-2 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE2

8

7

VREG

(BACKSIDE)

PECI

SM BUS S3

SATA CONN

PCIE SLOT 1

E

PCI 1X16

GRFX CONN

VGA CONN

SPI FLASH

1&2

3&4

5&6

SM BUS S3

LPC BUS

6

SPI

PCIE X1

LAND GRID ARRAY (LGA) CONNECTOR

LGA775

PROCESSOR SOCKET

FSB

GMCH:

GRAPHICS MEMORY

CONTROLLER HUB

DMI

ICH9: I/O

CONTROLLER HUB

45

CHANNEL A DDR2 667/800

CHANNEL B DDR2 667/800

GLCI

LCI

(LAN CONNECT INTERFACE)

PCI (33MHZ)

PCI (33MHZ)

SST_CTL

3

CORE

DUAL DATA RATE SDRAM

(2-DDR SDRAM DIMMS)

DUAL DATA RATE SDRAM

(2-DDR SDRAM DIMMS)

NINEVEH
OR EKRON

SM BUS S3

THERMAL SENSOR

THERMAL SENSOR

LAN

SM BUS S0

SM BUS S3

SM BUS S0

1394

2

CK_505 CLOCK

DIMM 0:1

DIMM 0:1

RJ45

PCI SLOT 1

PCI SLOT 2

1

MODULE REV DETAILS

MODULE NAME

FP HDR

2 PER

BACK PANEL

REV

DATE

D

C

B

BROADWATER

HIGH DEF AUDIO LINK

HD AUDIO

2X8 HDR

CHIPSET

SM BUS S3

A

SM BUS S0

PS2 MOUSE &
KEYBOARD

BLOCK DIAGRM UPDATED: 09/06/2005

8

PORT
ANGELES

SIO

PARALLEL (1)

SERIAL HEADER (2)

7

FLOPPY DISK
DRIVE CONN

SM BUS S3 = RESUME WELL

SM BUS S0 = MAIN POWER WELL

6

TPM: SECURITY

MIC IN

LINE IN

CD IN (ATAPI, BLACK)

SP/DIF IN

5

HD 10 CH

AUDIO CODEC

FRONT PANEL
LINE OUT
SP/DIF OUT
LINE OUT (SURR)
LINE OUT (SURR)
LINE OUT (LFE/CENTER)

BPAGE DRAWING

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3

PC_SPKR

[PAGE_TITLE=BLOCK DIAGRAM]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

2

1

A

3.01

CR-3 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE3

8

D

7

6

AFTER P_PCIRST*, HANDSHAKE (ON HL BUS) BETWEEN ICH/MCH MUST
HAPPEN BEFORE H_CPURST* WILL BE ASSERTED/DE-ASSERTED

MCH: MEMORY

CONTROLLER HUB

P_PCIRST*
PWRGD_3V

H_CPURST*

DB_RESET*

45

ICH

FP_RST*

SIO

RES:H_CPURST

3

XDP T_RST

XDP-SSA 30-PIN

2

MODULE REV DETAILS

MODULE NAME

TRST*

H_CPURST*

LGA775 SOCKET

H_PWRGD

CPU\DBR*

1

REV

DATE

FP_RST*

D

PORT ANGELES

PCIRST_OUT*

RES: PA_PLTRST*

C

RES:5V_STBY - PS ON

RES: PS_ON_ HEADER*

POWER (2X12)

SUPPLY CONN

PS_ON*

PWRGD_PS

PCI_RST*
SLP_S4/S5*
SLP_S3*
FP_RST*

PWRGD_PS

PWRGD_3V

RSMRST*

KBRST*
PS_ON*

RES:PLTRST - PCIE

E

PCI GRAPHICS

PWRGD

1X16 CONN

X1-PORT (2)

E

PCI CONN

X1-PORT (1)

PWRGD

TPM (SECURITY)

LRESET*

PCI SLOT 2

PCI SLOT 1

C

P_PCIRST*

B

RESET*

FRONT PANEL CONN

2X8 HEADER

PWR ON SWITCH

A

H_CPURST*

XDP-SSA 31-PIN

DBR*

RESET SWITCH

FP_RST*

FP_RST*

SW_ON*

SW_ON*

JUMPER-STRAP-GND

PULL-UP TERMINATION

PWRGD_3V
RSMRST*

RCIN*
SYS_RESET*

RTC_RST*

SW_ON*

CKT: G_RST*

P_PCIRST*

JRSTSYNC

ICH9: I/O

CONTROLLER HUB

H_PWRGD

ACZ_RST*

S4_STATE

SLP_S4*
SLP_S3*

1394

PLTRST*

RES: SLP_S3*

RES: 1394_PCI_RST*

CKT: G_RST*

RES:JRSTSYNC

RES: CDC_DOWN_RST*

RES: AUD_LINK_RST_HDR*

P_PCIRST*

G_RST*

1394

LAN

JRSTSYNC

AC04 AUDIO CODEC

RESET*

2X8 HDR

AUD_LINK_RST_HDR*

B

A

RESET MAP UPDATED: 09/06/2005

8

7

BPAGE DRAWING

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6

5

4 2

3

[PAGE_TITLE=RESET MAP]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

3

1

3.01

CR-4 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE4

8

7

14.318MHZ

RES: 14MHZ

6

JORDAN

LAN

33MHZ

D

3.3 VOLT

33MHZ
33MHZ
33MHZ
33MHZ

RES: 33MHZ

LPC BUS 2X10 (TPM)

PCI SLOT 1

RES: 33MHZ

1394

32.7KHZ

TPM

CLK14

PCICLK

RTCCLK
USBCLK

DMICLK
SATACLK
AUD_BCLK

45

ICH

SUSCLK

SMBUS CLK

32.7KHZLANCLK

SCLK

3

SCLK

2

MODULE REV DETAILS

MODULE NAME

CLK14
SUSCLK

PORT
ANGELES

KBCLK

MCLK

REV

1

DATE

D

MS/KB

AUDIO

CODEC

AUD_BCLK

3.3 VOLT

C

CK505

48MHZ

25MHZ

CRYSTAL

LAN

JORDAN

ICH

12.288 MHZ

33M

C

SRC CLOCK PAIRS

B

A

14.318MHZ

SRC CLOCK PAIR

HOST CLOCK PAIRS

CLOCK DISTRIBUTION UPDATED: 09/07/2005

8

100MHZ
100MHZ
100MHZ

100MHZ
100MHZ
100MHZ
100MHZ
100MHZ
100MHZ

SCLK

96MHZ

100/133/167/200 MHZ CPU_CK

100/133/167/200 MHZ CPU_CK

100/133/167/200 MHZ CPU_CK

7

X1 PCI-EXPRESS #1

X1 PCI-EXPRESS #2

SPARE

SPARE

SPARE

XDP PORT

CPU

CORE

6

XDP

CLK-OUT

XDP CLK-OUT OPTION

5

X16 PCI-EXPRESS

GCLKIN
REFCLKIN
HOST

PCI - GRAPHICS

MCH

DUAL CHANNEL

DDR
2X200/266/333 MHZ

E

BPAGE DRAWING

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4 2

3

CHAN A

DIMM0

DIMM1

CHAN B

DIMM0

DIMM1

[PAGE_TITLE=CLOCK DISTRIBU T I ON]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

1

B

A

4

3.01

CR-5 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE5

ICH

D

C

B

PORT ANGELES

GPXX
GPXX
GPXX
GPXX
GPXX
GPXX
GPXX
GPXX

A

GPXX
GPXX
GPXX
GPXX
GPXX
GPXX
GPXX

8

PIN NAME

GP[0]
GP[1]
GP[2]
GP[3]
GP[4]
GP[5]
GP[6]
GP[7]
GP[8]
GP[9]
GP[10]
GP[11]
GP[12]
GP[13]
GP[14]
GP[15]
GP[16]
GP[17]
GP[18]
GP[19]
GP[20]
GP[21]
GP[22]
GP[23]
GP[24]
GP[25]
GP[26]
GP[27]
GP[28]
GP[29]
GP[30]
GP[31]
GP[32]
GP[33]
GP[34]
GP[35]
GP[36]
GP[37]
GP[38]
GP[39]
GP[48]
GP[49]

(PIN 103/118)
(PIN 104/119)
(PIN 105/120)
(PIN 106/121)
(PIN 108/124)
(PIN 109/126)
(PIN 111/127)
(PIN 112/128)
(PIN 116)
(PIN 114)
(PIN 74/115/122)
(PIN 75/113/125)
(PIN 101)
(PIN 100)
(PIN 102)

7

POWER
WELL

MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
RESUME (STBY)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)
MAIN (CORE)

CPU

(BASED ON NATIONAL PA3.0, MAY 2004, REV 1.1; MULTI-PLEXED/PROGRAMMABLE GPIO PINS)

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY/VCC3

STBY

STBY

STBY/STBY/VCC3

STBY/STBY/VCC3

STBY

STBY

N/C (P A30)

USAGE

FP AUD DETECT
FRONT FAN TACH
P_INTE
P_INTF
P_INTG
P_INTH
REAR FAN TACH
EV FAN TACH
SATA/HOT-SWAP
WOL
NOT USED (RVP)
PORT 80 LED
BOARD ID 3
LPC_SIO_PME
NOT USED (RVP)
LAN DISABLE
BOARD ID 1
CPU FAN TACH
BOARD ID 2
SATA1GP

NOT USED (TP): SATA HOTSWAP CTL

SATA0GP
NOT USED
LDRQ1
V_SM LED CONTROL
BOARD ID 4
S4_STATE
NOT USED (TP)
NOT USED (TP)
OC5
OC6
OC7
BOARD ID 0
MFG_MODE (RVP)
ICH CFG JUMPER
NOT USED (TP)
SATA2GP
SATA3GP
NOT USED
NOT USED
NOT USED
CPUPWRGD

NOT USED (TP)
1394 ENABLE
NOT USED (TP)
1 WATT VREG CONTROL
1 WATT VREG CONTROL+

MEM. OVERVOLTAGECONTROL1

MEM. OVERVOLTAGE CONTROL2 (TP)

BOARD ID 5

5V_DDCSDA 2.2K P/U TO VCC
5V_DDCSCL
3V_DDCSDA
3V_DDCSCL
2X12 HDR DETECT
NOT USED (TP)
NOT USED (PA30)

AFTER
PLTRST

IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT

OUT(ALERT)

IN
IN
IN
OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
OUT
LOW
LOW
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

N/C (PA30)

6

GPIO SIGNALS NOT USED: GP40-47

S3/S5

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

NOTES

10K P/U TO VCC3

3.3K P/U TO +12V (THRU 15K)

8.2K P/U TO VCC

8.2K P/U TO VCC

8.2K P/U TO VCC

8.2K P/U TO VCC

3.3K P/U TO +12V (THRU 15K)

3.3K P/U TO +12V (THRU 15K),10K VCC3
10K P/U TO V_3P3_STBY
100K P/D TO GND
10K P/U TO V_3P3_STBY
10K P/U TO V_3P3_STBY
10K P/U TO V_3P3_STBY, 10K P/D
10K P/U TO V_3P3_STBY

10K P/U TO VCC3, 10K P/D

3.3K P/U TO +12V (THRU 15K)
10K P/U TO VCC3, 10K P/D
10K P/U TO VCC3

10K P/U TO VCC3
10K P/U TO VCC3
10K P/U TO VCC3
1K P/U TO V_SM (THRU EMPTY 0 OHM RES)
10K P/U TO V_3P3_STBY, 10K P/D
10K P/U TO V_3P3_STBY (EV DESIGN ONLY)
ENERGY LAKE STATUS LED: GREEN
ENERGY LAKE STATUS LED: YELLOW
NOA SHARED WITH OVER-CURRENT
NOA SHARED WITH OVER-CURRENT
NOA SHARED WITH OVER-CURRENT
10K P/U TO VCC3, 10K P/D

4.7K P/U TO VCC3
1K P/U TO VCC3 (SUITCASE JMPR); 4.7K P/D TO GND: BIOS NORMAL, RECOVER, CONFIGURE

10K P/U TO VCC3
10K P/U TO VCC3
10K P/U TO VCC3
10K P/D TO GND
10K P/U TO VCC3
EMPTY 100 OHM P/U (VTT)

1K P/D TO GND

10K EMPTY P/U TO V_3P3_STBY (1.8/1.9 VREG CTL)

2.2K P/U TO VCC

2.2K P/U TO VCC3

2.2K P/U TO VCC3

AUDIO

A

LAN

2

MODULE REV DETAILS

MODULE NAME

PCI X1

USB2

USB1

2.0

2.0

#2

#1

B

A

C

A

A

2420

45

3

IRQ ROUTING TABLE (EXCERPT FROM ICH BIOS BKM REV 0.72)

SLOT2
P_INTA*
P_INTB*
P_INTC*
P_INTD*
P_INTE*
P_INTF*
P_INTG*
P_INTH*
REQ/GNT
IDSEL

SLOT1

IRQD
IRQA
IRQB
IRQC

16

SLOT4

SLOT3
IRQD
IRQC
IRQA

IRQB IRQA

IRQB

IRQC
IRQB
IRQA
IRQD

1

0

IRQA

IRQC
IRQD

3

2

19

1817

SLOT5

IRQC

IRQD

IRQB

SLOT6

IRQA

IRQB
IRQD
IRQC

21

SMBUS ADDRESS LINES SA [2-0] SMBUS ADDRESS
MEMORYSLOT-0 (CHANNEL-A: SLOT-0) 0000A1H0A0H
MEMORYSLOT-1 (CHANNEL-A: SLOT-1) 0010A3H0A2H
MEMORYSLOT-2 (CHANNEL-B: SLOT-0) 0100A5H0A4H
MEMORYSLOT-3 (CHANNEL-B: SLOT-1) 0110A7H0 A6H
CK410 - - - 0D3H 0D2H

DB800/DB400 - - - 0DDH 0DCH

SMBUS DATA (EXCERPT FROM ICH BIOS BKM REV 0.72)

#3

C

1

REV

PCI X16

#1

A

DATE

D

SMBUS

#2

C

C

B

A

MULTI-PLEXED GPIO PINS ON PORT ANGELES WHICH ARE USED FOR SPECIFIC FUNCTIONS (NOT AS GPIO) ARE NOT IDENTIFIED HERE
UN-USED GPIO PINS ON PORT ANGELES ARE NOT IDENTIFIED HERE
TOTAL OF (33) POSSIBLE GPIO PINS ON PORT ANGELES (POWER WELL: STBY OR V_3P3_STBY = RESUME, VCC3 = MAIN).
NOTE: (0-4) GP'S FROM THE FWH WERE NOT USED (POWER WELL = CORE, INPUT ONLY)

8

7

6

5

4 2

BPAGE DRAWING

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3

[PAGE_TITLE=GPIO, IRQ, IDSEL MAP]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

5

1

3.01

CR-6 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE6

8

BI

BI

BI
BI

BI

H_ADSTB1_N

H_A_N<16..3>

H_REQ_N<4..0>

H_ADSTB0_N
H_A_N<35..17>

TP_CPU_AC4
TP_CPU_AE4

3
4
5
6
7
8
9
10
11
12
13
14
15
16

TP_RSVD_N4
TP_RSVD_P5

0
1
2
3
4

17
18
19
20
21
22
23
24
25
26
27
28
29
30

31

32
33
34
35

10

D

10

10

10

C

10

B

105

1

VTT_OUT_RIGHT

6

7

IN

89397

2

R128PR

51
5%

CH

402

VTT_OUT_RIGHT

7893

97

105

A

6

IN

1

C1PR

.1UF
20%
25V

2

EMPTY
603

DESIGN NOTE:

INTERNAL PU AVAILABLE

R1BU

ATX DESIGN ONLY

1K
5%

EMPTY
402

CPU_BOOT

1

DESIGN NOTE:

STUFF R128PR TO PREVENT

2

PSC,SMF,CDM & PSL CPU
FROM BOOTING

R7PR

1

49.9
1%

2

CH
402

8

1

2

AB6

AA4
AD6
AA5
AB5
AC5
AB4
AF5
AF4
AG6
AG4
AG5
AH4
AH5
AJ5
AJ6
AC4
AE4
AD5

L5
P6
M5
L4
M4
R4
T5
U6
T4
U5
U4
V5
V4
W5
N4
P5
K4
J5
M6
K6
J6
R6

W6
Y6
Y4

R16PR

49.9
1%

CH
402

A<3>*
A<4>*
A<5>*
A<6>*
A<7>*
A<8>*
A<9>*
A<10>*
A<11>*
A<12>*
A<13>*
A<14>*
A<15>*

RSVD
RSVD
REQ<0>*
REQ<1>*
REQ<2>*
REQ<3>*
REQ<4>*
ADSTB<0>*

A<17>*
A<18>*
A<19>*
A<20>*
A<21>*
A<22>*
A<23>*
A<24>*
A<25>*
A<26>*
A<27>*
A<28>*
A<29>*
A<30>*
A<31>*
A<32>*
A<33>*
A<34>*
A<35>*
RSVD
RSVD
ADSTB<1>*

OUT

7

6

1

R8PR

130
1%

EMPTY
402

2

H_COMP6
H_COMP7

7

J1PR

LGA775_C

REV=1.8

H_FORCEPH_N

ADS*
BNR*
HIT*

RSP*
BPRI*
DBSY*
DRDY*
HITM*
IERR*
INIT*
LOCK*
TRDY*

BINIT*
DEFER*A<16>*

MCERR*
AP<0>*

AP<1>*

BR<0>*
TESTHI_8
TESTHI_9

TESTHI_10

DP<0>*

DP<1>*

DP<2>*

DP<3>*

GTLREF0
GTLREF1
GTLREF2

GTLREF_SEL

RESET*

RS<0>*

RS<1>*

RS<2>*

1of 4

IC

OUT
OUT
OUT

6

H_ADS_N

D2
C2
D4
H4
G8
B2
C1
E4
AB2
P3
C3
E3
AD3
G7

AB3
U2

U3
F3

G3
G4
H5

J16
H15
H16
J17

H1
H2
E24
H29

G23
B3

F5
A3

TP_RSP_N

TP_BINIT_N

TP_MCERR_N

TP_AP<0>
TP_AP<1>

TP_CPU_J16
TP_CPU_H15
TP_CPU_H16
TP_CPU_J17

0

1

2

H_BNR_N
H_HIT_N

H_BPRI_N
H_DBSY_N
H_DRDY_N
H_HITM_N
H_IERR_N
H_INIT_N
H_LOCK_N
H_TRDY_N

H_DEFER_N

H_BR_N<0>
H_BPM3_2
H_BPM2_2
H_TESTHI_10

CPU_GTLREF0
CPU_GTLREF1

CPU_MCH_GTLREF

TP_GTL_DET

H_CPURST_N

H_RS_N<2..0>

OUT

BI
BI
BI

IN
BI
BI
BI

IN
BI
IN

IN

BI
BI
BI
BI

IN
IN

OUT

IN

IN

10
10
10

10

10
10

10
8
32

10

10

10

8

10
97
97
8

8
8

17

8

10 97

10

R19PR

PRECISION FSB COMPENSATION RESISTORS

69

16

6

95
6
6

6

7897

IN

IN

VTT_OUT_LEFT

1

C2PR

.1UF
20%
25V

2

EMPTY
603

H_VCCPLL

1

2

C18PR

10UF
20%

6.3V
EMPTY
805

1

2

5

C3PR

.01UF
20%
50V
X7R
603

32

16

93

70

949596105

H_CPU_PD_F6

1

51
5%

2

CH

402

1

R14PR

49.9
1%

CH
402

2

32
32

8
32
32
32
33

9
9
9
69

93

8

29
29

33

76

76

93
93
93
93

76

DESIGN NOTE:

50OHM ON 1080
TP ON 2116

45

ICH_H_SMI_N H_TESTHI_0

IN

H_A20M_N

IN

H_FERR_N

OUT

H_INTR

IN

H_NMI

IN

H_IGNNE_N

IN

H_STPCLK_N

IN

H_VCCA

IN

H_VSSA

IN

H_VCCIOPLL

IN

H_VCCPLL

IN

H_VID<7..0>

2

1

OUT

OUT

IN
IN

OUT

IN

OUT

OUT
OUT
OUT
OUT

IN

105

R18PR

49.9
1%

CH
402

VRD_VIDSEL
CK_H_CPU_DP

CK_H_CPU_DN
H_SKTOCC_N

H_TEMP_SRC_DP
H_TEMP_RET_DN

VCC_SENSE
VSS_SENSE
VCC_PKGSENSE
VSS_PKGSENSE

TP_VTT_PKGSENSE

TP_SLEW_CTRL

H_PECI

BI

TP_MPG_NOBOOT

1

R17PR

49.9
1%

CH
402

2

2

1

VCCP

R20PR

49.9
1%

CH
402

0
1
2
3
4
5

6

7

6

IN

6

IN

1

1

R12PR

49.9
1%

CH
402

2

2

Sun Mar 18 18:42:58 2007

4 2

3

J1PR

LGA775_C

P2
K3
R3
K1
L1
N2
M3

A23
B23
C23
D23

AM2
AL5
AM3
AL6
AK4
AL4
AM5
AM7
AN7

F28
G28

AE8
AL1

AK1
AJ7
AH7

AN3
AN4
AN5
AN6
AL8
AL7
F29

F6
G6
G5

AL3

DESIGN NOTE:

STUFF R15PR FOR 95W YORKFIELD

DESIGN NOTE:

STUFF R13PR FOR 65W CPU:CNR/WOLFDALE

1

R22PR

49.9
1%

2

CH
402

BPAGE DRAWING

frostburg_fabc.sch_1.6

REV=1.8

SMI*
A20M*
FERR*/PBE*

LINT0
LINT1
IGNNE*

STPCLK*
VCCA

VSSA
VCCIOPLL
VCC_PLL

VID<0>
VID<1>
VID<2>
VID<3>
VID<4>
VID<5>
VID<6>
VID<7>
VID_SELECT

BCLK<0>
BCLK<1>

SKTOCC*
THERMDA

THERMDC
RSVD
RSVD

VCC_SENSE
VSS_SENSE
VCC_MB_REGULATION
VSS_MB_REGULATION
VCC
VSS
RSVD

IMPSEL
RSVD
PECI

NC

105

H_MSID0
H_MSID1

R21PR

24.9
1%

CH
402

H_COMP8
H_COMP0
H_COMP1
H_COMP2
H_COMP3
H_COMP4
H_COMP5

0

402

R13PR

1

EMPTY

3of 4

6789397

5%

3

TESTHI_0
TESTHI_1
TESTHI_2
TESTHI_3
TESTHI_4
TESTHI_5
TESTHI_6

TESTHI_7
TESTHI_11
TESTHI_12
TESTHI_13

FORCEPR*

PWRGOOD

PROCHOT*

THERMTRIP*

COMP<0>
COMP<1>
COMP<2>
COMP<3>
COMP<4>
COMP<5>
COMP<6>
COMP<7>
COMP<8>

MSID<1>
MSID<0>

BOOTSELECT

LL_ID<0>

LL_ID<1>

IN

R15PR

0

2

402

OUT
OUT
OUT
OUT
OUT
OUT
OUT

2

MODULE REV DETAILS

MODULE NAME

F26

H_TESTHI_1

W3

H_TESTHI_2_7

F25
G25
G27
G26
G24
F24

H_TESTHI_11

P1

H_TESTHI_M

W2

H_TESTHI_13

L2

H_FORCEPH_N

AK6

H_PWRGD

N1

H_PROCHOT_N

AL2

H_THERMTRIP_N

RSVD
RSVD
RSVD
RSVD

FC5

RSVD
RSVD

M2
A13

T1
G2
R1
J2
T2
Y3
AE3
B13

G1
U1
A24
E29

F2
G10

AH2
V1

W1

Y1
V2
AA2

H_COMP0
H_COMP1
H_COMP2
H_COMP3
H_COMP4
H_COMP5
H_COMP6
H_COMP7
H_COMP8

H_BPM0_2
H_TESTHI_M
H_DCKLPH2
TP_SFRANAD2

CPU_GTLREF2
CPU_GTLREF3

TP_CPU_AH2

H_MSID1
H_MSID0

CPU_BOOT

TP_V2
TP_LL_ID1

BI

OUT

OUT

97
6

8

8

IN

8

IN

OUT
OUT

IC

VTT_OUT_RIGHT

R131PR

1

R130PR

1

1K
5%

2

EMPTY

1

2

5%

EMPTY

DESIGN NOTE:

EMPTY Q1PR FOR VTT TOOL TEST

6
6
6
6
6
6
6

[PAGE_TITLE=CPU-SOCKET 1 OF 2]

CONFIDENTIAL

CUSTOM TEXT BPAGE

402

H_MSID_XSTR_BASE_1

INTEL

680
5%

CH

2

VRD_ENABLE

402

3

Q1PR

1

MMBT3904
EMPTY

2

DOCUMENT_NUMBER

xxxxxx

REV

IN
IN
IN

IN
IN
IN
IN

IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN

IN

402

1

R112PR

1

1K

8
8
8

8
68
8
6

8
837
8

6
6
6
6
6
6
6
6
6

6
6

6

1

DATE

95

33

95

32

2

5%

EMPTY

OUT

PAGE REV

6

D

C

B

93

A

3.01

CR-7 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE7

8

R124PR

2

VR_READY

8

39

IN

93

0CH5%

402

1

D

CAD NOTE:

H_VR_READY

7

7

OUT

6

97
97
97

97
97

97

PLACE CLOSE TO VR CONTROLLER

333651

7097

C

R33PR

1

1K
5%

2

EMPTY

402

DESIGN NOTE:

FOR DEBUG ONLY

J1PR

H_D_N<15..0>

10

BI

B

H_DBI_N<0>

10

BI

H_STBN_N<0>

10

BI

H_STBP_N<0>

10

BI

H_D_N<31..16> H_D_N<63..48>

10 10

BI

A

H_DBI_N<1>

10

BI

H_STBN_N<1> H_STBN_N<3>

10 10

BI

H_STBP_N<1> H_STBP_N<3>

10 10

BI

B4

0

C5

1

A4

2

C6

3

A5

4

B6

5
6

B7
A7

7

A10

8

A11

9

B10

10

C11

11

D8

12
13

B12

14

C12
D11

15

A8
C8
B9

G9

16

F8

17
18

F9

19

E9

20

D7

E10

21

D10

22

F11

23

F12

24

D13

25

E13

26

G13

27

F14

28

G14

29

F15

30

G15

31

G11
G12
E12

D<0>*
D<1>*
D<2>*
D<3>*
D<4>*
D<5>*
D<6>*
D<7>*
D<8>*
D<9>*
D<10>*
D<11>*
D<12>*
D<13>*
D<14>*
D<15>*
DBI<0>*

DSTBN<0>*
DSTBP<0>*

D<16>*
D<17>*
D<18>*
D<19>*
D<20>*
D<21>*
D<22>*
D<23>*
D<24>*
D<25>*
D<26>*
D<27>*
D<28>*
D<29>*
D<30>*
D<31>*
DBI<1>*

DSTBN<1>*
DSTBP<1>*

LGA775_C

REV=1.8

D<32>*
D<33>*
D<34>*
D<35>*
D<36>*
D<37>*
D<38>*
D<39>*
D<40>*
D<41>*
D<42>*
D<43>*
D<44>*
D<45>*
D<46>*
D<47>*

DBI<2>*
DSTBN<2>*
DSTBP<2>*

D<48>*
D<49>*
D<50>*
D<51>*
D<52>*
D<53>*
D<54>*
D<55>*
D<56>*
D<57>*
D<58>*
D<59>*
D<60>*
D<61>*
D<62>*
D<63>*

DBI<3>*
DSTBN<3>*
DSTBP<3>*

G16
E15
E16
G18
G17
F17
F18
E18
E19
F20
E21
F21
G21
E22
D22
G22
D19
G20
G19

D20
D17
A14
C15
C14
B15
C18
B16
A17
B18
C21
B21
B19
A19
A22
B22
C20
A16
C17

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

H_D_N<47..32>

H_DBI_N<2>
H_STBN_N<2>
H_STBP_N<2>

H_DBI_N<3>

2of 4

IC

8

7

6

OUT

81328
81328
81328

IN
IN

OUT

IN
IN

BI

OUT
OUT
OUT

97
97

H_TCK
H_TDI
H_TDO
H_TMS
H_TRST_N

H_BPM_N<5..0>

FP_RST_N

XDP_CLKOUT_DP

OUT

XDP_CLKOUT_DN

OUT

H_FSBSEL0
H_FSBSEL1
H_FSBSEL2

97

891417 34 38

IN

2

MODULE REV DETAILS

MODULE NAME

85

7

IN

689397

105

68

97

85

DESIGN NOTE:

ENG FEATURE: 1K RES (EMPTY)

R32PR

2

5%

EMPTY

R31PR

2

5%

EMPTY

OUT
OUT
OUT

1

1K

402

1

1K

402

45

J1PR

LGA775_C

TCK
TDI
TDO
TMS
TRST*

BPM<0>*
BPM<1>*
BPM<2>*
BPM<3>*
BPM<4>*
BPM<5>*

DBR*
ITPCLK<0>

ITPCLK<1>
BSEL<0>

BSEL<1>
BSEL<2>

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD

RSVD

REV=1.8

VTT_OUT_RIGHT

VTT_OUT_LEFT

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VTT_PWRGD

VTT_SEL

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

4of 4

AE1
AD1
AF1
AC1
AG1

AJ2

0

AJ1

1

AD2

2

AG2

3

AF2

4

AG3

5

AC2
AK3

AJ3
G29

H30
G30

N5

CPU_N5

H_BPM1_2

BI

TP_CPU_E7
TP_CPU_AE6

TP_CPU_D16
TP_ACLKPH2

TP_SFRANAC2

10

BI

10

BI

10

BI

10

BI
BI

C9
E7

AE6
D16

A20
E23

VCCP=AG22,K29,AM26,AE12,AE11
VCCP=W23,W24,W25,T25,Y28,AL18,AC25,W30,Y30,AN14,AD28,Y26,AC29,M29,U24,J23,AC27,AM18,AM19,AB8
VCCP=AC26,J8,J28,T30,AM9,AF15,AC8,AE14,N23,W29,U29,AC24,AC23,Y23,AN26,AN25,AN11,AN18,Y27,Y25
VCCP=U27,AD24,AE23,AE22,AN19,V8,K8,AE21,AM30,AE19,AC30,AE15,M30,K27,M24,AN21,T8,AC28,N25,AE18,W26
VCCP=AD25,M8,N30,AD26,AJ26,AM29,M25,M26,L8,U25,Y8,AJ12,AD27,U23,M23,AG29,N27,AM22,U28,K28
VCCP=U8,AK18,AD8,K24,AH28,AH21,AK12,AH22,T29,AM14,AM25,AE9,Y29,AK25,AK19,AG15,J22,T24,AG21,AM21
VCCP=J25,U30,AL21,AG25,AJ18,J19,AH30,J15,AG12,AJ22,J20,AH18,AH26,W27,AL25,AN8,AH14,T23,R8
VCCP=AK22,AN29,AG11,AK26,J10,AJ15,AG26,AN9,AH15,AF18,AL15,J26,J18,J21,AG27,AK15,AF11,AD23,AM15,AF8
VCCP=AK21,AG30,AJ21,AM11,AL11,AJ11,K30,AL14,AN30,AH25,AL12,AJ9,AK11,AG14,N29,AL30,AJ25,AH9,J29,J11
VCCP=K25,P8,K23,AL19,AM8,T26,N28,AH12,AL22,AN15,AJ8,U26,AJ19,T27,AK8,AN12,AG9,N26,AF9,AF22
VCCP=AH11,AJ14,AH19,AH29,AH27,AG28,AL26,AM12,J24,J13,T28,W28,J12,J27,AG19,AL9,AD30,AF21,Y24,AK14
VCCP=J9,M27,AF14,J30,AG18,AA8,AG8,AL29,AD29,W8,AH8,N24,AN22,J14,K26,AF19,N8,AF12,M28,AK9
GND=C10,D12,C24,K2,C22,AN1,B14,K7,AE16,B11,AL10,AK23,H12,AF7,AK7
GND=H7,E14,L28,Y5,E11,AL16,AL24,AK13,D21,AL20,D18,AN2,AK16,AK20,AM27,AM1,AL13,AL17,C19
GND=E28,AK30,D24,AL23,A12,L25,J7,AE28,AE29,K5,J4,AE30,AN20,AF10,AE24,AM24,AN23,H9,H8
GND=H13,AC6,AC7,AH6,C16,AM16,AE25,AE27,AJ28,F19,AH13,AD7,AH16,AK17,E17,AH17,AH20,AE5,AH23
GND=AE7,AM13,AH24,AJ30,AJ10,AF3,AK5,AJ16,AF6,AK29,AJ17,F22,AH3,AK10,AM10,F16,AJ23,F13,AG7,F10
GND=L26,AD4,H11,L24,L23,AM23,A15,AH10,B24,L3,H27,A21,AE2,AJ29,AK27,AK28,B20,AM20
GND=H26,B17,H25,H24,AA3,AA7,H23,AA6,H10,H22,H21,H20,H19,H18,AB7,H17,AJ24,AM17,AC3,H14
GND=P28,V6,AK2,P27,P26,AM28,AJ13,W4,P25,AJ20,W7,P23,C7,L30,L29,D15,AL27,Y7,L27
GND=AA29,N6,N7,AA28,AN13,AA27,AA26,P4,AA25,AA24,P7,E26,V30,R2,V29,V28,R5,V27,R7,E20
GND=AN10,V25,T3,V24,V23,T6,E25,R29,R28,R27,R26,R25,U7,R24,R23,P30,V3,P29
GND=AF16,AE10,AF13,H6,A18,A2,E2,D9,C4,A6,D6,D5,A9,D3,B1,B5,B8,AJ4,AE26,AH1
GND=V7,C13,AK24,AB30,L6,L7,AB29,M1,AB28,AN17,AB27,AB26,AN16,M7,AB25,AB24,AB23,N3,AA30
GND=F4,AG10,AE13,AF30,H28,F7,AF29,AF28,AF27,AF26,AF25,AN28,AN27,AF24,AF23,AG24,AF17,AN24,H3
GND=Y2,P24,AE20,AE17,E27,T7,R30,AJ27,AB1,AM4,V26,AA23,AL28,AF20,AG23,AG20,E8,AG17,AG16,AG13

3

A29
B25
B29
B30
C29
A26
B27
C28
A25
A28
A27
C30
A30
C25
C26
C27
B26
D27
D28
D25
D26
B28
D29
D30
AM6

VTT_OUT_RIGHT

AA1

VTT_OUT_LEFT

J1

VTT_SEL

F27

TP_EXTBGREF

F23
D14

TP_SFRANAD
TP_SFRANAC

E6

H_DCLKPH

E5

H_ACLKPH

J3

TP_HFPLL

D1

CAD NOTE:

PLACE A GND VIA

IC

NEAR TP ON
PIN D1

V_FSB_VTT

H_VR_READY

1

REV

DATE

D

1

1

C4PR

2

X7R
603

.1UF
10%
16V

C5PR

C

.1UF
10%
16V

2

X7R
603

B

A

10

BI
BI
BI

BPAGE DRAWING

frostburg_fabc.sch_1.7

Sun Mar 18 18:42:59 2007

5

4 2

3

[PAGE_TITLE=CPU SOCKET 2 OF 2]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

7

1

3.01

D

C

B

A

CR-8 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE8

8

105

VTT_OUT_RIGHT

678

IN

93

97

97
8
6

IN

7
93

105

9

DESIGN NOTE:

PRODUCT MAY
TIE GTLREFS
TOGETHER

6

IN

8

97

678

97

9

IN

VTT_OUT_RIGHT

IN

CPU_GTLREF1

678

IN

IN

DESIGN NOTE:

PRODUCT MAY
TIE GTLREFS
TOGETHER

1

2

1

2

VTT_OUT_LEFT

VTT_OUT_LEFT

1

R59PR

115
1%

CH
402

2

CPU_GTLREF0_DIVIDER

1

R65PR

200

1%

CH
402

2

R60PR

115
1%

CH
402

CPU_GTLREF1_DIVIDER

R56PR

200
1%

CH
402

1

0

402

1

2

1

2

1

R117PR

115
1%

CH
402

2

CPU_GTLREF3_DIVIDER

1

R118PR

200
1%

CH
402

2

R62PR

R114PR

115
1%

CH
402

CPU_GTLREF2_DIVIDER

R115PR

200
1%

CH
402

8

7

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200 OHM RESISTORS

R63PR

1

5%

10

CH

1

C9PR

1.0UF
20%
10V

2

Y5V
603

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200

1

C10PR

1.0UF
20%
10V

2

Y5V
603

2

CPU_GTLREF0

5%

EMPTY

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200 OHM RESISTORS

1

C14PR

1.0UF
20%
10V

2

Y5V
603

DESIGN NOTE:

GTLREF VOLTAGE SHOULD BE 0.67*VTT

(67% OF 1.2V) = 0.80V
<FOR THIS DESIGN>
100OHM OVER 200

402

OHM RESISTORS

R57PR

2

1

5%

10

CH

402

OUT

R116PR

1

10

402

OHM RESISTORS

R119PR

1

402

1

C16PR

1.0UF
20%
10V

2

Y5V
603

DESIGN NOTE:

KF CPU GTLREF: DEFAULT EMPTY

7

6

CPU GTLREF

CPU_GTLREF0

2

1

C8PR
220PF

50V

2

EMPTY
402

CPU_GTLREF1

1

C7PR
220PF
10%
50V

2

EMPTY
402

68

2

5%
CH

2

CPU_GTLREF3

5%10
CH

6

10%

CPU_GTLREF2

1

2

1

2

C15PR

220PF
10%
50V
EMPTY
402

C17PR

220PF
10%
50V
EMPTY
402

OUT

OUT

68

68

OUT

OUT

45

V_FSB_VTT

7

89141734

IN

38

85

R67PR

2

470
4025%CH

R69PR

2

470
402

105

7

8

6

93

97

678

97

1

R55PR

62
5%

CH
402

2

1

1

5%
CH

IN
IN

R68PR

2

470
4025%CH

VTT_OUT_RIGHT
VTT_OUT_LEFT

1

R52PR

100

5%
EMPTY

402

2

H_FSBSEL0

1

H_FSBSEL1

H_FSBSEL2

FSB SELECTS

R51PR

62
5%

CH
402

1

2

1

2

OUT

OUT

OUT

R75PR

680
5%

CH
402

CPU SIGNAL TERMINATION

3

71328

71328

71328

CAD NOTE:

PLACE AT CPU END OF

1

R76PR

330
5%

CH
402

2

ROUTE

1

2

R66PR

130
1%

EMPTY
402

2

MODULE REV DETAILS

MODULE NAME

CAD NOTE:

3438

85

17

V_FSB_VTT

7

89

IN

14

PLACE AT ICH END OF
ROUTE

1

1

R71PR

R72PR

62

62

5%

5%

CH

CH

402

2

402

2

H_THERMTRIP_N

H_FERR_N

H_PROCHOT_N
VR_READY
VRD_VIDSEL
H_CPURST_N
H_PWRGD
H_BR_N<0>

1

REV

DATE

D

C

32

6

OUT

32

6

OUT

6

37

IN

OUT
OUT

73993

6

93

6

10 97

6

33

6

10

95

OUT

OUT
OUT

B

V_FSB_VTT

7

89

1

2

105

R54PR

51
5%

CH
402

14173438

9397

VTT_OUT_LEFT

1

R49PR

51
5%

CH
402

2

1

2

IN

678

IN

R53PR

51
5%

CH
402

VTT_OUT_RIGHT

1

R64PR

51
5%

CH
402

2

1

2

R50PR

51
5%

CH
402

1

2

R48PR

62
5%

CH
402

1

2

R70PR

51
5%

CH
402

85

6

7

6

IN

8

97

TESTHI PULLUPS

[PAGE_TITLE=CPU TERMINATION & MISC P/U P/D]

BPAGE DRAWING

frostburg_fabc.sch_1.8

Sun Mar 18 18:43:01 2007

5

4 2

3

CONFIDENTIAL

CUSTOM TEXT BPAGE

TESTHI PIN NAME MAPPING
TESTHI[0]

TESTHI[1]
TESTHI[5:2]
TESTHI[7:6]

1

TESTHI[10:8]

R35PR

TESTHI[11]

51
5%

TESTHI[12]

CH

TESTHI[13]

402

2

H_TESTHI_0
H_TESTHI_2_7
H_IERR_N
H_TESTHI_1

H_TESTHI_10
H_TESTHI_11
H_TESTHI_M

H_TESTHI_13

INTEL

BYPASSEN
ODT
MCLK[3:0]
MCLKIO[1:0]
BR#[3:1]
DPSLP#
DT_SVR#
SLP#

DESIGN NOTE:

CHANGE TO H_TESTHI_2-7

6

OUT
OUT
OUT
OUT

OUT
OUT
OUT

OUT

FOR CRB

6
6
6

6
6
6

66

DOCUMENT_NUMBER

xxxxxx

PAGE REV

8

1

A

3.01

CR-9 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE9

8

D

C

105
9092

101

848586
596469
39

47

48

333436

V_3P3_STBY\G

92122

IN

28

32

3738
4953
70

82

87

88

102103

B

SIO_PIN_108

69

IN

DESIGN NOTE:

PULL UP FOR PIN 106 IS AVAILABLE ON SIO PAGE

1

2

7

VCCPLL SUPPLY

V_SFR_OUT

87

IN

V_1P5_ICH

3438

829298

IN

R146PR

10K

5%
EMPTY

402

R137PR

SIO_PIN_108_R SIO_PIN_106_R

1

2

5%

1K

EMPTY

402

MBT3904DUAL

Q4PR

5

R90PR

1

0

603

DESIGN NOTE:

DO NOT STUFF
BOTH R90PR, R87PR

DESIGN NOTE:

COST REDUCTION EXP

R87PR

1

0

603

VCC3

R139PR

1

1K

1

5%
EMPTY

2

402

2

3

4

1A

CH

1A

EMPTY

R140PR

1K

5%
EMPTY

402

6

EMPTY

1

2

H_VCCPLL

2

GTLREF_FET0
GTLREF_FET1

2

R138PR

1

1K

402

6

OUT
OUT

EMPTY

OUT

5%

45

3

PLL SUPPLY FILTER

V_FSB_VTT

7

85

6

16

7

IN

8914173438

IN

DESIGN NOTE:

L3PR: DUAL CORE SUPPORT

47

CAD NOTE:

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET

69

TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12 MIL

85

105

921222832 33

IN

34 36 37 38 39
64 697082 84 85
92

SIO_PIN_106

868788 90
484953 59

101

102 103

V_3P3_STBY\G

R145PR

1

10K

5%
EMPTY

2

402

9

9

2

8914173438

V_FSB_VTT

10UH

1

L3PR
EMPTY

721891-026

2

IN

1

2

1

2

693286-014
FB1PR

EMPTY

693286-014

FB2PR
EMPTY

10UH

1

L1PR
EMPTY

721891-026

2

DESIGN NOTE:

INDUCTOR: 125 MA
0805 PACKAGE

DESIGN NOTE:

COST REDUX EXPERIMENT
EMPTY ONE INDUCTOR
TO EVALUATE

10UH

1

L2PR
EMPTY

721891-026

2

DESIGN NOTE:

INDUCTOR: 125 MA
0805 PACKAGE

1

C13PR

2

1

2

33UF
20%
25V
EMPTY
RDL

R86PR

0
5%

EMPTY
402

1

C11PR

1.0UF
20%
10V

2

EMPTY
603

1

C12PR

1.0UF
20%
10V

2

EMPTY
603

2

H_VSSA

MODULE REV DETAILS

MODULE NAME

H_VCCIOPLL

H_VCCA

OUT

OUT

6

OUT

6

1

REV

DATE

D

6

C

B

3

CPU_GTLREF0_DIVIDER_R CPU_GTLREF1_DIVIDER_R

Q3PR

D

BSS138N

GTLREF_FET0

9

A

1

EMPTY

S

G

2

GTLREF_FET0_Q

R143PR

1

1.3K
1%

2

EMPTY
402

8

R142PR

2

1

CPU_GTLREF0_DIVIDER

0

5%

EMPTY

402

CAD NOTE:

PLACE CLOSE TO THE GTLREF DIVIDER

7

8 8

GTLREF_FET1

9

ININ

6

3

Q2PR

D

BSS138N

1

EMPTY

S

G

2

GTLREF_FET1_Q

R144PR

1

576

1%

EMPTY

2

402

5

R141PR

1

2

CPU_GTLREF1_DIVIDER

5%

0

EMPTY

402

CAD NOTE:

PLACE CLOSE TO THE GTLREF DIVIDER

BPAGE DRAWING

frostburg_fabc.sch_1.9

Sun Mar 18 18:43:02 2007

4 2

OUTOUT

[PAGE_TITLE=CPU PLL FILTERED SUPPLY]

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

INTEL

DOCUMENT_NUMBER

xxxxxx

PAGE REV

9

1

A

3.01

CR-10 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE10

8

EXP_A_RX_0_DP EXP_A_TX_0_DP

21

22 23

IN

EXP_A_RX_0_DN

21

22

IN

EXP_A_RX_1_DP

21

22

D

C

IN

EXP_A_RX_1_DN

21

22

IN

EXP_A_RX_2_DP

21

22

IN

EXP_A_RX_2_DN

21

22

IN

EXP_A_RX_3_DP

21

22

IN

EXP_A_RX_3_DN

21

22

IN

EXP_A_RX_4_DP

21

22

IN

EXP_A_RX_4_DN

21

22

IN

EXP_A_RX_5_DP

21

22

IN

EXP_A_RX_5_DN

21

22

IN

EXP_A_RX_6_DP

21

22

IN

EXP_A_RX_6_DN

21

22

IN

EXP_A_RX_7_DP

21

22

IN

EXP_A_RX_7_DN

21

22

IN

EXP_A_RX_8_DP

21

22

IN

EXP_A_RX_8_DN

21

22

IN

EXP_A_RX_9_DP

21

22

IN

EXP_A_RX_9_DN

21

22

IN

EXP_A_RX_10_DP

21

22

IN

EXP_A_RX_10_DN

21

22

IN

EXP_A_RX_11_DP

21

22

IN

EXP_A_RX_11_DN

21

22

IN

EXP_A_RX_12_DP

21

22

IN

EXP_A_RX_12_DN

21

22

IN

EXP_A_RX_13_DP

21

22

IN

EXP_A_RX_13_DN

21

22

IN

EXP_A_RX_14_DP

21

22

IN

EXP_A_RX_14_DN

21

22

IN

EXP_A_RX_15_DP

21

22

IN

EXP_A_RX_15_DN

21

22

IN

29
29

DMI_IT_MR_0_DP

BI

DMI_IT_MR_0_DN

BI

DMI_IT_MR_1_DP

BI

DMI_IT_MR_1_DN

BI

DMI_IT_MR_2_DP

BI

DMI_IT_MR_2_DN

BI

DMI_IT_MR_3_DP

BI

DMI_IT_MR_3_DN

BI

CK_PE_100M_MCH_DP

IN

CK_PE_100M_MCH_DN

IN

SDVO_CTRL_DATA

BI

SDVO_CTRL_CLK

BI

31
31
31
31
31
31
31
31

21

22

21

22

B

SIGNAL NAMING CONVENTION

EXP: PCI EXPRESS
DMI: DIRECT MEDIA INTERFACE
ITP: ICH TRANSMIT POSITIVE
ITN: ICH TRANSMIT NEGATIVE
IRP: ICH RECEIVE POSITIVE
IRN: ICH RECEIVE NEGATIVE
MTP: MCH TRANSMIT POSITIVE
MTN: MCH TRANSMIT NEGATIVE
MRP: MCH RECEIVE POSITIVE

A

MRN: MCH RECEIVE NEGATIVE

8

7

F13
E13
K15
J15
F12
E12
J12
H12
J11
H11

F7
E7
E5
F6
C2
D2
G6
G5
L9
L8
M8
M9
M4
L4
M5
M6
R9

R10

T4
R4
R6
R7

W2
V1
Y8

Y9
AA7
AA6
AB3
AA4

B12
B13

G17
E17

J3UB

1

NC NC

HDR

C85376-001

7

6

U1UB

BRLK_B

REV=1
PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7
PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3

EXP_CLKINP
EXP_CLKINN

SDVO_CTRLDATA
SDVO_CTRLCLK

PEG_TXP_0
PEG_TXN_0
PEG_TXP_1
PEG_TXN_1
PEG_TXP_2
PEG_TXN_2
PEG_TXP_3
PEG_TXN_3
PEG_TXP_4
PEG_TXN_4
PEG_TXP_5
PEG_TXN_5
PEG_TXP_6
PEG_TXN_6
PEG_TXP_7

PCIE

PEG_TXN_7
PEG_TXP_8
PEG_TXN_8
PEG_TXP_9

PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15

DMI_TXP_0

DMI_TXN_0

DMI_TXP_1

DMI_TXN_1

DMI_TXP_2

DMI_TXN_2

DMI

DMI_TXP_3

DMI_TXN_3

EXP_COMPO

EXP_COMPI

2OF8

SDVO CTRL DATA

1 SDVO CARD PRESENT, PEG DISABLED

0 SDVO DISABLED (DEFAULT)

1

J2UB

1

HDR

J9UB

NC

1

HDR

J7UB

NC

HDR

6

D11
D12

EXP_A_TX_0_DN

B11

EXP_A_TX_1_DP

A10

EXP_A_TX_1_DN

C10

EXP_A_TX_2_DP

D9

EXP_A_TX_2_DN

B9

EXP_A_TX_3_DP

B7

EXP_A_TX_3_DN
EXP_A_TX_4_DP

D7
D6

EXP_A_TX_4_DN
EXP_A_TX_5_DP

B5
B6

EXP_A_TX_5_DN
EXP_A_TX_6_DP

B3
B4

EXP_A_TX_6_DN

F2

EXP_A_TX_7_DP

E2

EXP_A_TX_7_DN
EXP_A_TX_8_DP

F4
G4

EXP_A_TX_8_DN
EXP_A_TX_9_DP

J4
K3

EXP_A_TX_9_DN

L2

EXP_A_TX_10_DP
EXP_A_TX_10_DN

K1
N2

EXP_A_TX_11_DP
EXP_A_TX_11_DN

M2

EXP_A_TX_12_DP

P3

EXP_A_TX_12_DN

N4

EXP_A_TX_13_DP

R2

EXP_A_TX_13_DN

P1

EXP_A_TX_14_DP

U2
T2

EXP_A_TX_14_DN
EXP_A_TX_15_DP

V3

EXP_A_TX_15_DN

U4
V7

DMI_MT_IR_0_DP

V6

DMI_MT_IR_0_DN

W4

DMI_MT_IR_1_DP

Y4

DMI_MT_IR_1_DN

AC8

DMI_MT_IR_2_DP

AC9

DMI_MT_IR_2_DN

Y2

DMI_MT_IR_3_DP

AA2

DMI_MT_IR_3_DN

AC11

GRCOMP

AC12

CAD NOTE:

MCH COMP0/1 SIGNALS:
TIE TOGETHER AT PINS.

IC

HS1UB

BRDWTR_ATX_HS

1

NC_3

NC_1

2

NC_4

NC_2

8

NC_8

NC_5

7

NC_7

NC_6

5

3
4

5
6

HEATSINK

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

45

23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

31

BI

17

IN

H_A_N<35..3>

6

BI

H_REQ_N<4..0>

6

BI

H_ADSTB0_N

6

BI

H_ADSTB1_N

6

BI

H_STBP_N<0>

7

BI

H_STBN_N<0>

7

BI

H_DBI_N<0>

7

BI

H_STBP_N<1>

7

BI

H_STBN_N<1>

7

BI

H_DBI_N<1>

7

BI

H_STBP_N<2>

7

BI

H_STBN_N<2>

7

BI

H_DBI_N<2>

7

BI

H_STBP_N<3>

7

BI

H_STBN_N<3>

7

BI

H_DBI_N<3>

7

BI

H_ADS_N

6

BI

H_TRDY_N

6

OUT

H_DRDY_N

6

OUT

H_DEFER_N

6

OUT

H_HITM_N

6

OUT

H_HIT_N

6

OUT

H_LOCK_N

6

IN

H_BR_N<0>

68

OUT

H_BNR_N

6

BI

H_BPRI_N

6

OUT

H_DBSY_N

6

BI

H_RS_N<2..0>

6

BI

H_CPURST_N

68

97

OUT

3

U1UB
BRLK_B

3

J42

FSB_AB_3

L39

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

32
33
34
35

0
1
2
3
4

0
1
2

AA37

AA42

AA41

J40
L37
L36
K42
N32
N34
M38
N37
M36
R34
N35
N38
U37
N39
R37
P42
R39
V36
R38
U36
U33
R35
V33
V35
Y34
V42
V38
Y36
Y38
Y39

F40
L35
L38
G43
J37

M34
U34

M42
M43
M40
G35
H33
J33
G27
H27
G29
B38
C38
E33

W40
Y40
W41
T43
Y43
U42
V41

W42
G39
U40
U41

U39
C31

FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35

FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4

FSB_ADSTBB_0
FSB_ADSTBB_1

FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DINVB_0
FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DINVB_1
FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DINVB_2
FSB_DSTBPB_3
FSB_DSTBNB_3
FSB_DINVB_3

FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_CPURSTB

REV=1

1OF8

BPAGE DRAWING

frostburg_fabc.sch_1.10

Sun Mar 18 18:43:03 2007

4 2

3

[PAGE_TITLE=MCH SECTIONS PAGE 1 OF 6]

2

MODULE REV DETAILS

MODULE NAME

H_D_N<63..0>

0

INTEL

R40
P41
R41
N40
R42
M39
N41
N42
L41
J39
L42
J41
K41
G40
F41
F42
C42
D41
F38
G37
E42
E39
E37
C39
B39
G33
A37
F33
E35
K32
H32
B34
J31
F32
M31
E31
K31
G31
K29
F31
J29
F29
L27
K27
H26
L26
J26
M26
C33
D35
E41
B41
D42
C40
C35
B40
D38
D37
B33
D33
C34
B35
A32
D32

B25
D23
C25
D25

D24
B24

R32
U32

IC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

HXSWING
HXRCOMP
HXSCOMP

HXSCOMPB

MCH_GTLREF

CK_H_MCH_DP
CK_H_MCH_DN

DOCUMENT_NUMBER

xxxxxx

FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7

FSB

FSB_DB_8

FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63

FSB_SWING
FSB_RCOMP
FSB_SCOMP

FSB_SCOMPB

FSB_DVREF

FSB_ACCVREF

HPL_CLKINP
HPL_CLKINN

DESIGN NOTE:

MCH GTLREF0/1: SEPARATE SIGNALS ON EV ONLY;
TIE TOGETHER AT PINS ON CRB.

CONFIDENTIAL

CUSTOM TEXT BPAGE

REV

1

BI

17

IN

17

IN

17

IN

17

IN

17

IN

29

IN

29

IN

PAGE REV

10

1

DATE

7

D

C

B

A

3.01

CR-11 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE11

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

M_DQS_A_DP<7..0>
M_DQS_A_DN<7..0>

M_DQM_A<7..0>

M_DATA_A<63..0>

111

101112

13

8

AV4

DDR_A_DQ_8

DDR_A_WEB

BA33

9

AV3

DDR_A_DQ_9

DDR_A_CASB

AW35

BA4

DDR_A_DQ_10

DDR_A_RASB

AY33

BB3

DDR_A_DQ_11

AU1

AU2

DDR_A_DQ_12

DDR_A_BS_0

BA31

AY31

1

0

DDR_A_DQ_13

DDR_A_BS_1

14

AY2

DDR_A_DQ_14

DDR_A_BS_2

AY20

2

AN3

DDR_A_DQ_1

DDR_A_MA_5

BB22

AR2

DDR_A_DQ_2

DDR_A_MA_6

BA22

AR3

AL3

DDR_A_DQ_3

DDR_A_MA_7

BB21

AW21

7

8

DDR_A_DQ_4

DDR_A_MA_8

AM2

AR5

DDR_A_DQ_5

DDR_A_DQ_6

DDR_A_MA_10

DDR_A_MA_9

BA21

BB31

101113

9

7

AR4

DDR_A_DQ_7

DDR_A_MA_11

BC20

AY21

DDR_A_MA_12

12

AW2

AY38

DDR_A_DQS_1

DDR_A_MA_13

AW1

DDR_A_DQSB_1

DDR_A_MA_14

BA19

14

AW3

DDR_A_DM_1

000

0123456

C

AM1

AP2

AP3

AN2

DDR_A_DQ_0

DDR_A_DM_0

DDR_A_DQS_0

DDR_A_DQSB_0

BRLK_B

U1UB

REV=1

B

DDR_A_MA_4

DDR_A_MA_3

DDR_A_MA_2

DDR_A_MA_1

DDR_A_MA_0

BA23

BB23

AY23

AY25

BB30

1

05923456

A

15

2

AY3

AY7

DDR_A_DQ_15

BA34

01230

161718

2

2

BA6

BB6

BB5

AY6

BA9

DDR_A_DM_2

DDR_A_DQ_18

DDR_A_DQ_17

DDR_A_DQ_16

DDR_A_DQS_2

DDR_A_DQSB_2

DDR_A_CKE_1

DDR_A_CKE_0

DDR_A_CSB_3

DDR_A_CSB_2

DDR_A_CSB_1

DDR_A_CSB_0

AY35

BB33

BB38

AY19

AW18

1

19

BB9

DDR_A_DQ_19

DDR_A_CKE_2

BB19

2

202122

BA5

BB4

DDR_A_DQ_21

DDR_A_DQ_20

DDR_A_CKE_3

BA18

3

BC7

DDR_A_DQ_22

DDR_A_ODT_0

BB35

0

23

AY9

DDR_A_DQ_23

DDR_A_ODT_1

BA38

1

333

2425262728

AT20

AU18

AN18

AT18

DDR_A_DM_3

DDR_A_DQ_24

DDR_A_DQS_3

DDR_A_DQSB_3

DDR_A_ODT_3

DDR_A_ODT_2

BA35

BA39

3

2

AR18

AU21

DDR_A_DQ_26

DDR_A_DQ_25

DDR_A_CKB_0

DDR_A_CK_0

AU31

AR31

AP17

AT21

DDR_A_DQ_27

DDR_A_CK_1

AP27

AN27

DDR_A_DQ_28

DDR_A_CKB_1

29

AN17

DDR_A_DQ_29

DDR_A_CK_2

AV33

30

AP20

DDR_A_DQ_30

DDR_A_CKB_2

AW33

31

AV20

AP29

DDR_A_DQ_31

DDR_A_CK_3

444

AR41

DDR_A_DQS_4

DDR_A_CKB_3

DDR_A_CK_4

AM26

AP31

32333435363738

AR40

AU43

AV42

DDR_A_DM_4

DDR_A_DQSB_4

DDR_A_CK_5

DDR_A_CKB_5

DDR_A_CKB_4

AM27

AU33

AT33

AU40

AP42

AN39

AV40

AV41

DDR_A_DQ_37

DDR_A_DQ_36

DDR_A_DQ_35

DDR_A_DQ_34

DDR_A_DQ_33

DDR_A_DQ_32

CK_M_DDR0_A_DP
CK_M_DDR0_A_DN
CK_M_DDR1_A_DP
CK_M_DDR1_A_DN
CK_M_DDR2_A_DP
CK_M_DDR2_A_DN
CK_M_DDR3_A_DP
CK_M_DDR3_A_DN
CK_M_DDR4_A_DP
CK_M_DDR4_A_DN
CK_M_DDR5_A_DP
CK_M_DDR5_A_DN

AR42

DDR_A_DQ_38

39

AP41

DDR_A_DQ_39

555

AL40

AL41

DDR_A_DQS_5

DDR_A_DQSB_5

40414243444546

AM43

AM39

AN41

DDR_A_DM_5

DDR_A_DQ_41

DDR_A_DQ_40

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

AK42

DDR_A_DQ_42

AN40

AK41

DDR_A_DQ_44

DDR_A_DQ_43

24
24
24
24
24
24
24
24
24
24
24
24

AN42

DDR_A_DQ_45

AL42

DDR_A_DQ_46

47

AL39

DDR_A_DQ_47

666

AG42

AG41

DDR_A_DQS_6

DDR_A_DQSB_6

AG40

DDR_A_DM_6

48495051525354755

AJ40

AH43

AF39

AE40

AJ42

AJ41

AF41

DDR_A_DQ_54

DDR_A_DQ_53

DDR_A_DQ_52

DDR_A_DQ_51

DDR_A_DQ_50

DDR_A_DQ_49

DDR_A_DQ_48

DDR_A

AF42

DDR_A_DQ_55

7

AC42

AC41

DDR_A_DQS_7

DDR_A_DQSB_7

RSVD

AN21

7

AC40

DDR_A_DM_7

565758

AD40

AD43

DDR_A_DQ_57

DDR_A_DQ_56

AB41

DDR_A_DQ_58

AA40

DDR_A_DQ_59

60

AE42

DDR_A_DQ_60

61

AC39

AE41

DDR_A_DQ_61

62

DDR_A_DQ_62

63

AB42

DDR_A_DQ_63

3OF8

IC

OUT
OUT
OUT

BI

24
24
24
24

D

C

B

A

M_ODT_A<3..0>

M_SCKE_A<3..0>

M_SCS_A_N<3..0>

M_SBS_A<2..0>

M_RAS_A_N
M_CAS_A_N

M_WE_A_N

M_MAA_A<14..0>

8

7

6

5

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

24 26
24 26
24 26
24 26
24 26
24 26
24 26

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.11

Sun Mar 18 18:43:04 2007

3

[PAGE_TITLE=MCH SECTIONS PAGE 2 OF 6]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

11

1

3.01

TP_A_RCVEN_N

CR-12 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE12

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

D

M_DQS_B_DP<7..0>
M_DQS_B_DN<7..0>

M_DQM_B<7..0>

M_DATA_B<63..0>

31

2524262728

AV24

AT23

30

29

AT26

AP26

AU23

AW23

AR24

AN26

10111213146115

111

AN8

7

AW7

AU7

AW5

AN5

AN6

AN9

9

8

AT11

AU11

AR12

AP12

AR11

AW9

AP13

AR13

AU9

AV12

AU12

059000123456

C

AR7

AN7

AV6

AU5

18

17

16

222

AP15

AR15

AW13

AU15

AV13

AU17

333

19

20

222123

AT17

AU13

AM13

AV15

AW17

AT24

AU26

AP23

444

AW39

AU39

AU37

AW37

33323435363738539

AV38

AN36

AN37

AU35

AR35

AN35

7

7

41

5

5

4042434446

AR37

AL35

AL34

AM37

AM35

AM38

AJ34

AL38

AR39

45647

AM34

AL37

AL32

6

AG35

AG36

6

48495051525354

AG39

AG38

AJ38

AF35

AF33

AJ37

7

55

56

58

60

62

63

AJ35

AG33

AF34

AC36

AC37

AD38

AD36

AC33

AA34

AA36

AD34

AF38

AC34

AA33

OUT
OUT
OUT

BI

25
25
25
25

D

C

IC

DDR_B_DQ_0

DDR_B_DM_0

DDR_B_DQ_1

DDR_B_DQ_4

DDR_B_DQ_3

DDR_B_DQ_2

DDR_B_DQS_0

U1UB

B

DDR_B_DQSB_0

BRLK_B

REV=1

DDR_B_MA_8

DDR_B_MA_7

DDR_B_MA_6

DDR_B_MA_5

DDR_B_MA_4

DDR_B_MA_3

DDR_B_MA_2

DDR_B_MA_1

DDR_B_MA_0

AW15

BB15

BA15

AY15

BA14

BB14

AW12

BA13

BB13

01234575

679

8

DDR_B_DM_1

DDR_B_DQ_7

DDR_B_DQ_6

DDR_B_DQ_5

DDR_B_DQ_9

DDR_B_DQ_8

DDR_B_DQS_1

DDR_B_DQSB_1

DDR_B_DQ_10

DDR_B_DQ_11

DDR_B_DQ_12

DDR_B_DQ_13

DDR_B_DQ_14

DDR_B_DQ_15

DDR_B_DM_2

DDR_B_DQ_20

DDR_B_DQ_19

DDR_B_DQ_18

DDR_B_DQ_17

DDR_B_DQ_16

DDR_B_DQS_2

DDR_B_DQSB_2

DDR_B_DQ_21

DDR_B_DQ_22

DDR_B_DQ_23

DDR_B_DM_3

DDR_B_DQ_28

DDR_B_DQ_27

DDR_B_DQ_26

DDR_B_DQ_25

DDR_B_DQ_24

DDR_B_DQS_3

DDR_B_DQSB_3

DDR_B_DQ_29

DDR_B_DQ_30

DDR_B_DQ_31

DDR_B_DM_4

DDR_B_DQ_36

DDR_B_DQ_35

DDR_B_DQ_34

DDR_B_DQ_33

DDR_B_DQ_32

DDR_B_DQS_4

DDR_B_DQSB_4

DDR_B_DQ_37

DDR_B_DQ_38

DDR_B_DQ_39

DDR_B_DM_5

DDR_B_DQ_44

DDR_B_DQ_43

DDR_B_DQ_42

DDR_B_DQ_41

DDR_B_DQ_40

DDR_B_DQS_5

DDR_B_DQSB_5

DDR_B_DQ_45

DDR_B_DQ_46

DDR_B_DQ_47

DDR_B_DM_6

DDR_B_DQ_52

DDR_B_DQ_51

DDR_B_DQ_50

DDR_B_DQ_49

DDR_B_DQ_48

DDR_B_DQS_6

DDR_B_DQSB_6

DDR_B_DQ_53

DDR_B_DQ_54

DDR_B_DQ_55

DDR_B_DM_7

DDR_B_DQ_56

DDR_B_DQS_7

DDR_B_DQSB_7

DDR_B_DQ_57

DDR_B_DQ_58

DDR_B_DQ_59

DDR_B_DQ_60

DDR_B_DQ_61

DDR_B_DQ_62

DDR_B_DQ_63

4OF8

B

RSVD

RSVD

AA39

AP21

DDR_B

RSVD

AM21

DDR_RCOMPVOH

DDR_RCOMPVOL

DDR_RCOMPYPU

DDR_RCOMPYPD

DDR_RCOMPXPU

DDR_RCOMPXPD

DDR_VREF

AM6

AM8

AL4

AL2

BB40

BA40

AM10

RSVD

RSVD

RSVD

RSVD

RSVD

DDR_B_MA_9

AY13

BA17

AY12

AY27

BB25

AW26

AY24

BB17

BA11

BB11

14

10

13

12

11

AY17

012

AY11

DDR_B_CSB_1

DDR_B_CSB_0

BA25

BA29

1

0

DDR_B_CSB_3

BA26

BA30

AW11

23012

BC12

DDR_B_ODT_3

DDR_B_CKE_2

BA10

BB10

BB27

AW29

BA27

AY29

3

1

032

AW31

AV31

AT27

AV32

AU27

DDR_B_CKB_5

AT32

AR29

AU29

AV29

AP32

AN33

AW27

DDR_B_CK_5

DDR_B_CKB_4

DDR_B_CK_4

DDR_B_CKB_3

DDR_B_CK_3

DDR_B_CKB_2

DDR_B_CK_2

DDR_B_CKB_1

DDR_B_CK_1

DDR_B_CKB_0

DDR_B_CK_0

DDR_B_ODT_2

DDR_B_ODT_1

DDR_B_ODT_0

DDR_B_CKE_3

DDR_B_CKE_1

DDR_B_CKE_0

DDR_B_CSB_2

DDR_B_BS_2

DDR_B_BS_1

DDR_B_BS_0

DDR_B_RASB

DDR_B_CASB

DDR_B_WEB

DDR_B_MA_14

DDR_B_MA_13

DDR_B_MA_12

DDR_B_MA_11

DDR_B_MA_10

RSVD

BA2

AW42

AN32

AG32

AM31

AF32

TP_DDR_OBSERV_1

TP_DDR_OBSERV_0

TP_DDR_ANALOG_1

TP_DDR_ANALOG_0

TP_DDR_RCOMPYPAD

CK_M_DDR0_B_DP
CK_M_DDR0_B_DN
CK_M_DDR1_B_DP
CK_M_DDR1_B_DN

A

M_ODT_B<3..0>

M_SCKE_B<3..0>

M_SCS_B_N<3..0>

M_SBS_B<2..0>

M_RAS_B_N
M_CAS_B_N

M_WE_B_N

M_MAA_B<14..0>

8

7

6

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

5

CK_M_DDR2_B_DP
CK_M_DDR2_B_DN
CK_M_DDR3_B_DP
CK_M_DDR3_B_DN
CK_M_DDR4_B_DP
CK_M_DDR4_B_DN
CK_M_DDR5_B_DP
CK_M_DDR5_B_DN

26

25
25

26

25

26

25

26

25

26

25

26

25

26

4 2

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

TP_DDR_RCOMPXPAD

25
25
25
25
25
25
25
25
25
25
25
25

TP_DDR_SLEWYDB

TP_DDR_SLEWXDB

MCH_VREF

19

IN

MCH_DDR_RCOMPXPD

19

IN

MCH_DDR_RCOMPXPU

19

IN

MCH_DDR_RCOMPYPD

19

IN

MCH_DDR_RCOMPYPU

19

IN

MCH_DDR_RCOMPVOL

19

IN

MCH_DDR_RCOMPVOH

19

IN

CAD NOTE:

BTX SPECIFIC: TESTPOINT ON DDR_RCOMPY_PAD (U1UB)
ATX SPECIFIC: DO NOT TESTPOINT (U1UB_PIN AW42)

BPAGE DRAWING

frostburg_fabc.sch_1.12

Sun Mar 18 18:43:05 2007

3

TP_B_RCVEN_N

[PAGE_TITLE=MCH SECTIONS PAGE 3 OF 6]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

12

1

A

3.01

CR-13 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE13

8

13

33

53

70

IN

PWRGD_3V

7

R10UB

1

2

5%

0

CH

402

D

DESIGN NOTE:

0 OHM ISOLATION RESISTOR (R10UB) ON PWRGD_3V TO PWRGD_3V_R

DESIGN NOTE:

FAB A/B ONLY: DEFAULT STUFF (R12UB) FOR BOTH AMT AND NON-AMT
AND FOR NON-AMT ADD 0 OHM SOLDER BLOB ACROSS R11UB

C

53

70

CAD NOTE:

86

DEFAULT STUFF (R10UB): DEFENSIVE DESIGN (ENG. EXP)

BOM NO TE:

STUFF R12UB FOR AMT

R12UB

2

39

1333

IN

IN

MCH_CLPWROK

PWRGD_3V

1

5%

0

EMPTY

402

1

2

R11UB

0

5%
CH

402

BOM NO TE:

STUFF R11UB FOR NON AMT

OVERLAP PADS ON R11UB, R12UB

B

NOA H L DESCRIPTION

0 SEE BSEL TABLE BSEL0
1 SEE BSEL TABLE BSEL1
2 SEE BSEL TABLE BSEL2

4:3 SEE DFT MODE TABLE DFT MODE

5 DDR2 DDR3 MEMORY TYPE

A

6 NORM REVERSE PCI-EXPRESS LANE REVERSAL
7 DISABLE ENABLE FSB HARDWARE STRAPS
8 CONCURRENT NON-CONCURRENT PCI-E / SDVO CO-EXISTENCE
9 DISABLE ENABLE ITPM HOST INTERFACE
11 ENABLE DISABLE ME CRYPTO

3,4,5,6,7,8,9 ALL HAVE INTERNAL PULL-UPS

8

7

1

2

MCH_CLPWROK_R

6

PWRGD_3V_R

C147UB
220PF

10%
50V
X7R
402

13

OUT

32

6

OUT

45

13

13

13

32
32
19
32
13

32

13

IN

13

IN

13

IN

13

IN

13

IN

13

IN

OUT

BI

BI
BI

IN

BI

IN

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2
TP_MCH_K20
TP_MCH_F20
MCH_PIN_G18
MCH_EXP_SLR
TP_MCH_K17
MCH_EXP_EN
MCH_RFU_G15

TP_MCH_L17
MCH_RFU_E20
TP_MCH_N18
TP_MCH_N15
TP_MCH_N17
TP_MCH_L15
TP_MCH_L18
TP_MCH_M18

CL_N_DATA
CL_N_CLK
CL_N_VREF_MCH
CL_RST
MCH_CLPWROK_R

TP_MCH_JTAG_TDI
TP_MCH_JTAG_TDO
TP_MCH_JTAG_TCK
TP_MCH_JTAG_TMS

TP_HPLLMON1_DP
TP_HPLLMON1_DN
TP_HPLLMON2_DP
TP_HPLLMON2_DN

TP_DPLLMON1_DN
TP_DPLLMON1_DP
TP_DPLLMON2_DN
TP_DPLLMON2_DP

G20
J20
J18
K20
F20
G18
E18
K17
J17
G15

L17
E20
N18
N15
N17
L15
L18
M18

AD12
AD13

AM5
AA12
AM15

AA10

AA9
AA11

Y12

U30

U31

R29

R30

U12

U11

R12

R13

BSEL0
BSEL1
BSEL2
ALLZTEST
XORTEST
MTYPE
EXP_SLR
RSVD
EXP_EN
RFU_G15

RSVD
RFU_E20
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

CL_DATA
CL_CLK
CL_VREF
CL_RSTB
CL_PWROK

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

RSVD
RSVD
RSVD
RSVD

3

U1UB

BRLK_B

REV=1

VGA

CRT_DDC_DATA

DPL_REFCLKINP
DPL_REFCLKINN

MISC

5OF8

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE
CRT_REDB

CRT_GREENB

CRT_BLUEB

CRT_DDC_CLK

CRT_IREF

RSVD
RSVD
RSVD

RSTINB

PWROK

ICH_SYNCB

RSVD

DESIGN NOTE:

7828

IN

7828

IN

7828

IN

VCC
VSS

NC

IC

ENG FEATURE: NOA STRAPS AND FSBSEL ISOLATION

H_FSBSEL0

H_FSBSEL1

H_FSBSEL2

BSEL TABLE

2 1 0 PSB FREQUENCY

0 0 0 267 MHZ (1067)
0 0 1 133 MHZ (533)
0 1 0 200 MHZ (800)
0 1 1 167 MHZ (133)
1 0 0 333 MHZ (1333)
1 0 1 100 MHZ (133)
110400 MHZ (RSVD)
1 1 1 533 MHZ (133)

5

21

22

BPAGE DRAWING

frostburg_fabc.sch_1.13

Sun Mar 18 18:43:08 2007

4 2

[PAGE_TITLE=MCH SECTIONS PAGE 4 OF 6]

3

EXP_PRSNT_N

IN

2

C15

VGA_HSYNC

E15

VGA_VSYNC

B18
C19
B20
C18
D19
D20

L13
M13

A20
C14

D13
L12
M11

H18
F17
A14
AM18
AM17
J13

A42
R20

CUSTOM TEXT BPAGE

VGA_RED

VGA_GREEN

TPEV_PM_EXTTS_N

TP_PM_BMBUSY_N

TPEV_XDP_TESTIN_N

PLTRST_N
PWRGD_3V_R
ICH_SYNC_N

TPEV_MCH_DET_N

INTEL

CONFIDENTIAL

MODULE REV DETAILS

MODULE NAME

VGA_BLUE

VGA_MCH_DDCSDA
VGA_MCH_DDCSCL

VGA_DACREFSET
CK_96M_DREF_DP

CK_96M_DREF_DN

V_1P25_CORE

TP_FSB_OBS

1

R23BC

0

2

5%
CH

2

CH

2

2

5%

EMPTY

2

5%

2

5%

EMPTY

2

5%

EMPTY

2

4025%EMPTY

MCH_BSEL0

MCH_BSEL1

MCH_BSEL2

MCH_RFU_G15

MCH_RFU_E20

MCH_PIN_G18

MCH_EXP_SLR

MCH_EXP_EN

DESIGN NOTE:

DEBUG PURPOSE, ALWAYS EMPTY

R13UB

1

10K
402

R15UB

1

10K 5%
402

R14UB

1

10KCH5%
402

R101UB

1

1K

402

R102UB

1

1K

EMPTY

402

R17UB

1

1K

402

R18UB

1

1K

402

R16UB

1

0CH5%

402

DOCUMENT_NUMBER

xxxxxx

OUT
OUT

OUT
OUT
OUT

BI
BI

IN
IN

IN

IN

IN
IN

OUT

REV

2

OUT

OUT

OUT

1

17
17

20

17 19
17 19

20

17 19

20

17

20

17

20

17

17

29

17

29

105
14 161718
387682 83 86

33

68 69 98

13

33

13

13

13

13

OUT

13

OUT

13

OUT

13

OUT

13

OUT

PAGE REV

13

1

DATE

21 34

3.01

D

98

C

B

A

98105
7682
18

21

13

14

16

17

3438

83

86

D

C

B

14

16

1986

DESIGN NOTE:

A

ENG FEATURE: R22BC

16
16

16
16
16

CR-14 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE14

8

VCC3

IN

IN
IN

IN
IN
IN

V_1P25_CORE

V_1P25_CL_MCH

ETCH

R22BC

0OHM

VCCA_GPLL
VCCA_HPLL

TP_MCH_VCCA_HPLL

VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB

1

SM

2

V_1P25_HPL

AJ12
AJ11
AJ10

AJ9
AJ8
AJ7
AJ6
AJ5
AH4
AH2

AH1
AG14
AG13
AG12
AG11
AG10

AG9

AG8

AG7

AG6

AG5

AG4

AG3

AG2
AF14
AF13
AF12
AF11

AF3

AF2

AF1
AE25
AE23
AE21
AE19
AD24
AD22
AD20
AD14
AC25
AC23
AC21
AC19
AC14
AC13

AC6
AB24
AB22
AB20
AA25
AA23
AA21
AA19
AA14
AA13

AA3

Y24

Y22

Y20

Y14

Y13

W25

W23

W21

W19

V14

V13

V12

V10

U14

U13

U10

P20

Y11

Y32

B15

C23

V31

A24

A22

C22

B17

Y6

V9

U9
U6
U3

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC_CL_PLL
VCCAPLL_EXP
VCCA_HPL
RSVD
VCCA_MPL
VCCA_DPL_A
VCCA_DPL_B

VCC3_3

8

7

6OF8

7

U1UB

BRLK_B

REV=1

POWER

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

AG24
AG23
AG22
AG21
AG20
AG19
AG18
AG17
AG15
AF26
AF25
AF24
AF22
AF20
AF18
AF17
AF15
AE27
AE26
AE17
AD27
AD26
AD18
AD15
AC26
AC15
AB26
AB17
AA26
AA15
Y26
Y17
W27
W18
V27
V25
V23
V21
V19
V17
U26
U24
U22
U20
U18
U15
R17
AD17
AC27
AC17
AB27
AB18
AA27
AA17
Y27
Y18
Y15
W26
W17
V26
V24
V22
V20
V18
V15
U25
U23
U21
U19
U17
R18
R15

R14
P15
P14
N12
N11
N9
N8
N6
N3
L6
J6
J3
J2
G2
F11
F9
D4
C13
C9

IC

6

6

V_1P25_CORE

89

173438

85

2425

27

81

8286

18

BOM NO TE:

DEFAULT (M22UB): 1 OHM 0402 5%
OPTION (M22UB): 600 OHM FB (A51464-006)

DESIGN NOTE:

EMPTY M22UB FOR NON-GRAPHIC SKU'S

V_3P3_DAC_FB

14

IN

16

DESIGN NOTE:

STUFF R92UB FOR NON-GRAPHIC SKU'S

BOM NO TE:

DEFAULT (M24UB): 1 OHM 0402 5%
OPTION (M24UB): 600 OHM FB (A51464-006)

V_3P3_DAC_FB

14

IN

16

ININ

7

IN

141819

IN

80
17

IN

16

IN

16

IN

13 14
38

V_SM

V_1P25_PCIEXPRESS

1

CH1402

1

CH

VCCD_CRT
VCCDQ_CRT

5

16 171821 34

76 82

83 86 98 105

V_FSB_VTT

M22UB

MULTI

R92UB

2

1

0

5%

EMPTY

402

M24UB

MULTI

402

1

2

2

V_3P3_VCCABG_EXP

V_3P3_DAC_FILTERED

45

BRLK_B

P29

VTT_FSB

P27

VTT_FSB

P26

VTT_FSB

P24

VTT_FSB

P23

VTT_FSB

N29

VTT_FSB

N26

VTT_FSB

N24

VTT_FSB

N23

VTT_FSB

M29

VTT_FSB

M24

VTT_FSB

M23

VTT_FSB

L24

VTT_FSB

L23

VTT_FSB

K24

VTT_FSB

K23

VTT_FSB

J24

VTT_FSB

J23

VTT_FSB

H24

VTT_FSB

H23

VTT_FSB

G26

VTT_FSB

G24

VTT_FSB

G23

VTT_FSB

F26

VTT_FSB

F24

VTT_FSB

F23

VTT_FSB

E29

VTT_FSB

E27

VTT_FSB

E26

VTT_FSB

E23

VTT_FSB

D29

VTT_FSB

D28

VTT_FSB

D27

VTT_FSB

C30

VTT_FSB

C29

VTT_FSB

C27

VTT_FSB

B30

VTT_FSB

B29

VTT_FSB

B28

VTT_FSB

B27

VTT_FSB

A30

VTT_FSB

A28

VTT_FSB

R27

VTT_FSB

R26

VTT_FSB

R24

VTT_FSB

R23

VTT_FSB

BC39

VCC_DDR

BC34

VCC_DDR

BC30

VCC_DDR

BC26

VCC_DDR

BC22

VCC_DDR

BC18

VCC_DDR

BC14

VCC_DDR

BB39

VCC_DDR

BB37
BB32
BB28
BB26
BB24
BB20
BB18
BB16
BB12
AY32
AW24
AW20
AV26
AV18

AC3
AC4
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11

AC2

AD1

AD2

C17

B16

A16

C21

B21

D16

VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR

VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP

VCC_EXP
VCC_EXP
VCC_EXP

VCCA_DAC
VCCA_DAC
VCCA_EXP
VCCD_CRT
VCCDQ_CRT
VSS

POWER

VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR
VCC_CKDDR

Sun Mar 18 18:43:09 2007

4 2

3

VSS

AL26
AL24
AL23
AL21
AL20
AL18
AL17
AL15
AK30
AK29
AK27
AJ31
AJ30
AG31
AG30
AF31
AF30
AD32
AD30
AC32
AA32
AJ29
AJ27
AG29
AG27
AG26
AF29
AF27
AD29
AC30
AC29

AL12
AL11
AL10
AL9
AL8
AL7
AL6
AL5
AK26
AK24
AK23
AK21
AK20
AK18
AK17
AK15
AK3
AK2
AK1
AJ14
AJ13
AJ4
AJ3
AJ2
AD31
AC31
AA31
AA30
Y31
Y30
AJ26
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AJ15
AG25
AA29
Y29

V30
AL13

AK14
AL29

AL27
BB41

BA42
AY42
BB42
BA43

VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL

VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL
VCC_CL

VCC_CL
VCC_CL

VCC_CL
VCC_CL

BPAGE DRAWING

frostburg_fabc.sch_1.14

3

V_1P25_CL_MCH

2

MODULE REV DETAILS

MODULE NAME

19
14

IN

16
86

CAD NOTE:

PLACE BACKSIDE RESISTOR R19BC CLOSE TO MCH BALL/PIN

R19BC

1

0

DESIGN NOTE:

1A

EMPTY

2

ENG FEATURE: 0 OHM RES R19BC (EMPTY)

603

1

C7BC

.1UF
10%
16V

2

EMPTY
603

CAD NOTE:

PLACE CAPS AND MULTI-SITE
CLOSE TO MCH BALLS FOR V_CKDDR

V_CKDDR

1

C3UB

.1UF
20%
25V

2

Y5V
603

BOM NO TE:

DEFAULT: MULTI SITE M1UB TO USE 721891-022 (1UH INDUCTOR)

DESIGN NOTE:

FOR CRB, TIE THIS PIN TO VSS
EV: CONNECT TO EVMC OR VREG ( TBD )

[PAGE_TITLE=MCH SECTIONS PAGE 5 OF 6]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

27

80

81

MCH_V_CKDDR_R

1

C2UB

22UF
20%

6.3V

2

X5R
805

DOCUMENT_NUMBER

402

402

R94UB

1

1

R95UB

1

1

xxxxxx

1

REV

V_SM

14

1819

2425

2

5%
CH

2

5%
CH

86

82

1

IN

M1UB

MULTI

SMIND

PAGE REV

14

1

DATE

D

C

B

2

A

3.01

CR-15 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE15

8

BC37
BC32
BC28
BC24

D

C

B

A

BC10

BC5
BB7

AY41

AY4
AW43
AW41
AV37
AV35
AV27
AV23
AV21
AV17
AV11

AV9

AV7

AV2
AU42
AU38
AU32
AU24
AU20

AU6

AU4
AT31
AT29
AT15
AT13
AT12
AR38
AR33
AR32
AR27
AR26
AR23
AR21
AR20
AR17

AR9

AR6
AP43
AP24
AP18

AP1
AN38
AN31
AN29
AN24
AN23
AN20
AN13
AN12
AN11

AN4
AM42
AM40
AM36
AM33
AM29
AM24
AM23
AM20
AM11

AM9

AM7

AM4
AL36
AL33
AL31
AK43
AJ39
AJ36
AJ33
AJ32
AH42
AG37
AG34
AF43
AF37
AF36
AF10

AF9

AF8

AF7

AF6

AF5

8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

7

U1UB

BRLK_B

REV=1

7OF8

7

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE24
AE22
AE20
AE4
AE3
AE2
AD42
AD39
AD37
AD35
AD33
AD25
AD23
AD21
AD19
AC38
AC35
AC24
AC22
AC20
AC10
AC7
AC5
AB43
AB25
AB23
AB21
AB19
AB2
AB1
AA38
AA35
AA24
AA22
AA20
AA8
AA5
Y42
Y37
Y35
Y33
Y25
Y23
Y21
Y19
Y10
Y7
Y5
Y1
W24
W22
W20
W3
V43
V39
V37
V34
V32
V11
V8
V5
V2
U38
U35
U8
U7
U5
T42
T1
R36
R33
R31
R11
R8
R5
R3
P43
P30
P21
P18
P17
P2
N36
N33
N31
N27
N21
N13
N10
N7

6

BRLK_B

M37
M35
M33
M27
M21
M20
M17
M15
M10

L40
L33
L32
L31
L29
L21
L20
L11

K43
K26
K21
K18
K13
K12

J38
J35
J32
J27
J21

H31
H29
H21
H20
H17
H15
H13
G42
G38
G32
G21
G13
G12
G11

F37
F35
F27
F21
F18
F15

E43
E32
E24
E21
E11

D40
D31
D21
D17
D15

C26
C11

B37
B32
B31
B26
B23
B22
B19
B14

N5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

M7

VSS

M1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

L7

VSS

L5

VSS

L3

VSS
VSS
VSS
VSS
VSS
VSS
VSS

K2

VSS
VSS
VSS
VSS
VSS
VSS

J9

VSS

J7

VSS

J5

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

G9

VSS

G7

VSS

G1

VSS
VSS
VSS
VSS
VSS
VSS
VSS

F3

VSS
VSS
VSS
VSS
VSS
VSS

E9

VSS

E3

VSS
VSS
VSS
VSS
VSS
VSS

D3

VSS
VSS
VSS

C6

VSS

C5

VSS

C4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

B10
A39
A34
A26
A18
A12
A7
BC41
BC3
BA1
AY40
AF23
AF21
AF19
AE18
AC18
AA18
V29
U29
U27
R21
E1
C43
C1
A41
A5
A3

IC

6

5

45

U1UB

BRLK_B

REV=1

DDR3_DRAMRSTB

DDR3_DRAM_PWROK

DDR3_A_CSB1

DDR3_A_MA0
DDR3_A_WEB

DDR3_B_ODT3

DDR3

NC

8OF8

4 2

TEST0
TEST1
TEST2

BC16
AN15

AY37
BB29
BB34
AW32

BC43
BC1
A43

N20

NC

BC42

NC

BC2

NC

BB43

NC

BB2

NC

BB1

NC

B43

NC

B42

NC

B2

NC

IC

Sun Mar 18 18:43:10 2007

3

TP_DDR_DRAMRST

DRAM_PWROK_DDR3

DDR3_SCS_A_N1
DDR3_MAA_A0
DDR3_WE_A_N
DDR3_B_ODT_B3

DESIGN NOTE:

NO TESTPOINT NEEDED ON DDR2 SKEW

TP_CGC_NCTF_BC43
TP_CGC_NCTF_BC1
TP_CGC_NCTF_A43

[PAGE_TITLE=MCH SECTIONS PAGE 6 OF 6]

BPAGE DRAWING

frostburg_fabc.sch_1.15

3

2

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

1

MODULE REV DETAILS

MODULE NAME

1

2

DESIGN NOTE:

DDR2 BOARDS,STUFF R109UB= 0OHM

R109UB

0
5%

CH
402

REV

DOCUMENT_NUMBER

xxxxxx

1

DATE

PAGE REV

15

3.01

D

C

B

A

D

C

B

A

CR-16 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE16

8

R127PR

2

1A
CH

IV_3P3_DAC

R31UB

1

32.4K
1%

2

EMPTY
402

R30UB

1

102K
1%

2

EMPTY
402

BOM NO TE:

STUFF FOR FAB A VALIDATION

1

0

603

DESIGN NOTE:

24 OHM 805 1/8W
USE A93555-010

69

IN

H_VCCPLL

BOM NO TE:

DEFAULT (H_VCCPLL, R127PR): USE 0 OHM,
NON-GRAHPHIC SKU:EMPTY

1

VCC

R29UB

1

24
5%

2

EMPTY
805

2

Q1UB

MMBT3904
EMPTY

3

V_3P3_DAC_FILTERED_FB

7

VCC3

M19UB

1

MULTI

M18UB

1

1

C12UB

4.7UF
20%

10V

BOM NO TE:

2

EMPTY
805

DEFAULT (M18UB): FB 0603 (693286-015)
OPTION: STUFF FB 0603 (693286-015)

BOM NO TE:

DEFAULT (H_VCCPLL, M3UB): FB 0603 (693286-015)
OPTION (M3UB) TBD

M3UB

1

MULTI

FB

MULTI

2

EMPTY

2

VCCDQ_CRT_PN1

BOM NO TE:

DEFAULT (VCCDQ, M16UB) GRAPHIC SKU: MULTI SITE TO USE 1 UF (602433-052)
OPTION (VCCDQ, M16UB) NON-GRAPHIC SKU: MULTI SITE TO US E 0 OHM

M16UB

1

MULTI

603

6

BOM NO TE:

DEFAULT (M19UB)STUFF FB 0603 (693286-015)

2

FB

V_3P3_DAC_FB

1

C25UB

220UF

20.0%
25V
ELEC

2

RDL

213438

76

82838698105

DEFAULT (M23UB): 1 OHM 0402 5%

BOM NO TE:

OPTION (M23UB): 600 OHM FB (A51464-006)

M23UB

1

CH

DEFENSIVE OPTION (VCCDQ, M16UB): USE 600 OHM FB (A51464-006)

2

X5R

MULTI

1

2

VCCDQ_CRT

402

2

MODULE REV DETAILS

MODULE NAME

VCCA_HPLL

C16UB

1

2

603

X5R

10%

2.2UF

6.3V

VCCA_MPLL

VCCA_MPLL_R_PAIR

1

2

2

1

C20UB

10UF

20%

2

6.3V

2

X5R
805

C10UB

10UF

20%

6.3V
X5R
805

R96UB

1

1

402

R97UB

1

1

402

VCCA_GPLL

1

C17UB

.1UF
10%
16V

2

X7R
603

2

5%
CH

2

5%
CH

VCCA_DPLLA

1

C21UB

1

C23UB

220UF
20%

6.3V
ALUM

2

RDL

.1UF
10%
16V

2

X7R
603

VCCA_DPLLB

1

C19UB

1

C18UB

220UF
20%

6.3V
ALUM

2

RDL

.1UF
10%
16V

2

X7R
603

M6UB

M8UB

M9UB

3

M2UB

1

EMPTY

1

1

EMPTY

1

IND SM

2

VCCA_GPLL_PN1

2

2

SMIND

2

MULTI

SM

M10UB

2

MULTI

SMIND

M4UB

2

MULTI

SM

M11UB

2

MULTI

R37UB

1

1

5%
CH

402

R28UB

1

5%

1

CH

402

BOM NO TE:

C21UB, C19UB: 220 UF CAN BE EMPTY
IF USING RT9199 OR FOR NON-GRPHICS
SKUS W/SERIES RES

45

14

16

19

86

CAD NOTE:

14

16

19

86

14

OUT

1

C22UB

1.0UF
20%
10V

2

Y5V
603

V_1P25_CORE

131417

18

OUT

IN

14

CAD NOTE:

BOM NO TE:

DEFAULT (VCCA_GPLL, M6UB): USE 1 UH 721891-022
OPTION: MULTI SITE TO USE 0 OHM A93552-002
CHANGE TO OPTIONAL PART IF RT9199 I S ENABLED AND
SOURCING PWR.

BOM NO TE:

DEFAULT (VCCA_DPLLA, M8UB): USE 10 UH 721891-026
OPTION: MULTI SITE TO USE 0 OHM A93552-002
CHANGE TO OPTIONAL PART IF RT9199 I S ENABLED AND SOURCING PWR
CHANGE TO 0 OHM RESISTOR FO R NON-GRAPHICS SKU.

BOM NO TE:

DEFAULT (VCCA_DPLLB, M9UB): USE 10 UH 721891-026
OPTION: MULTI SITE TO USE 0 OHM A93552-002
CHANGE TO OPTIONAL PART IF RT9199 I S ENABLED AND SOURCING PWR
CHANGE TO 0 OHM RESISTOR FO R NON-GRAPHICS SKU.

V_1P25_CL_MCH

IN

PLACE MULTI-SITES M2UB AND
M10UB IN OVERLAP PATTERN

V_1P25_CL_MCH

IN

PLACE MULTI-SITES M4UB AND
M11UB IN OVERLAP PATTERN

1

MULTI

IND SM

1

MULTI

IND SM

1

MULTI

OUT

OUT

OUT

OUT

OUT

1

REV

DATE

D

14

14

C

14

14

B

14

A

VCCD_CRT

1

C4UB

4.7UF
10%

6.3V

2

X5R
603

8

7

M17UB

1

MULTI

603

BOM NO TE:

2

DEFAULT (VCCD, M17UB) GRAPHIC SKU: MULTI SITE TO USE 0.1UF (602433-056)

X7R

OPTION (VCCD, M17UB) NON-GRAPHIC SKU: MULTI SITE TO USE 0 OHM

6

5

OUT

14

BPAGE DRAWING

frostburg_fabc.sch_1.16

Sun Mar 18 18:43:11 2007

4 2

3

[PAGE_TITLE=PLL & CRT FILTERS]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

16

1

3.01

CR-17 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE17

8

7

89

1417

3438

85

D

3438

V_FSB_VTT

7

89

IN

14

17

85

C

B

7

891417

IN

3438

85

FSB COMP SIGNAL

TERMINATION

A

PCIE COMP SIGNAL TERMINATION

14

18

IN

7

V_FSB_VTT

IN

CAD NOTE:

CAP (C30UB) ON GTLREF SHOULD BE CLOSE TO MCH PIN
USE 10MIL TRACE, ISOLATE W/7MIL SPACE AFTER 250 MIL BREAKOUT

CAD NOTE:

HX_SWING VOLTAGE 10MIL TRACE, 10 MIL SPACE AFTER 250 MIL BREAKOUT.

1

PLACE DIVIDER RESISTORS NEAR VTT.

R49UB

301
1%

CH
402

2

HXSWING_DIVIDER

1

1

R48UB

100
1%

CH

2

402

2

CAD NOTE:

USE 4MIL TRACE, ISOLATE W/14MIL SPACE AFTER 300 MIL BREAKOUT

V_FSB_VTT

CAD NOTE:

49.9
402

49.9
402

C31UB

0.1UF
20%
16V
Y5V
402

R39UB

1

1

R46UB

R88UB

2

49.9
402

2

1%
CH

2

1%
CH

USE 5MIL TRACE, ISOLATE W/5MIL SPACE; IF >250MILS INCREASE TO 10/7

V_1P25_PCIEXPRESS

24.9

R53UB

1

402

1

R45UB

100
1%

CH
402

2

MCH_GTLREF0_DIVIDER

1

1

C32UB

R47UB

1%

CH

DESIGN NOTE:

1.0UF

200

20%

1%

10V

2

Y5V

CH

603

402

2

1

HXSWING

OUT

HX_SWING S/B 1/4*VTT +/- 2%

HXSCOMPB

2

1

C29UB

2.7PF

9.25%
25V
EMPTY
402

16.5
402

1%

CH

R50UB

1

2

1

2

2

HXRCOMP

1%

CH

GRCOMP

HXSCOMP

C26UB

2.7PF

9.25%
25V
EMPTY
402

OUT

OUT

OUT

OUT

6

R38UB

1

2

CPU_MCH_GTLREF

5%

0

EMPTY

402

R41UB

1

2

5%

51

CH

402

DESIGN NOTE:

MCH_GTLREF VOLTAGE SHOULD BE 0.67 * VTT = 0.8V
100 OHMS OVER 200 OHMS (072905)

10

10

10

10

10

C146UB

C30UB

220PF

EMPTY

6.3V

EMPTY

10%
50V

402

1

1UF
20%

DESIGN NOTE:

2

STUFF FOR CPU LEGACY

402

MCH_GTLREF

1

2

OUT

45

6

IN

10

DACREFSET & RGB MCH-SIDE TERMINATION

13

20

20

20

BOM NO TE:

VGA_DACREFSET

OUT

VGA_RED

1319

IN

VGA_GREEN

1319

IN

VGA_BLUE

1319

IN

CAD NOTE:

PLACE VGA RGB RESISTORS CLOSE
TO MCH: <250 MILS TO MCH BALLS

BOM NO TE:

VGA RGB RESISTORS (R54UB-R56UB): REPLACE 150 OHM WITH
0 OHM (A93549-001) FOR NON-GRAPHICS SKUS

STUFF R93UB FOR NON-GRAPHICS SKUS

BOM NO TE:

3

R56UB

R55UB

1

1

150

150

1%

1%

CH

2

CH

2

402

402

13

141618

213438

76

82838698

105

13

29

13

29

STUFF R98UB FOR NON-GRAPHICS SKUS

CAD NOTE:

HSYNC/VSYNC; LOCATE SERIES RESISTOR STRAPS (R52UB, R51UB) WITHIN 750 MILS OF MCH

BOM NO TE:

UN-STUFF 39 OHM SERIES RES (R52UB, R51UB) FOR NON-GRAPHICS SKUS

13

IN

13

IN

BOM NO TE:

HSYNC/VSYNC SLEW RATE & EMI CONTROL

VGA_VSYNC

VGA_HSYNC

39

402

39

402

R52UB

1

R51UB

1

2

5%
CH

2

5%
CH

2

R54UB

1

150
1%

CH

2

402

V_1P25_CORE

IN

CK_96M_DREF_DP

IN

CK_96M_DREF_DN

IN

M25UB

1

MULTI

EMPTY

402

MODULE REV DETAILS

MODULE NAME

CAD NOTE:

PLACE DACREFSET RES (R44UB) CLOSE
TO MCH: <500 MILS TO MCH BALL

R44UB

1

1.3K
1%

CH

2

402

BOM NO TE:

DACREFSET RESISTOR (R44UB): REPLACE 1.3K
WITH 0 OHM FOR NON-GRAPHICS SKUS

1

2

1

2

VGA_VSYNC_3V

VGA_HSYNC_3V

M26UB

1

2

402

MULTI

2

EMPTY

R93UB

10K
5%

EMPTY
402

R98UB

0
5%

EMPTY
402

1

REV

DATE

D

C

20

OUT

OUT

20

B

STUFF 0 OHM RES (M25UB, M26UB) FOR NON-GRAPHICS SKUS

DESIGN NOTE:

MULTI-SITES TO BE USED FOR SLEW RATE/EMI CAPS ON GRAPHIC SKUS

CAD NOTE:

DDC_DATA/DDC_CLK; LOCATE PULL-UPS
ANYWHERE ON ROUTE OF TRACE

BOM NO TE:

DDC MCH SIDE
TERMINATION

STUFF R42UB, R43UB FOR GRAPHICS/NON-GRAPHICS SKUS

VGA_MCH_DDCSDA

1320

IN

VGA_MCH_DDCSCL

1320

IN

VCC3 VCC3

1

2

R42UB

2.2K
5%

CH
402

1

2

R43UB

2.2K
5%

CH
402

A

BPAGE DRAWING

frostburg_fabc.sch_1.17

Sun Mar 18 18:43:12 2007

8

7

6

5

4 2

[PAGE_TITLE=MCH DECOUPLING AND COMP]

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

1

PAGE REV

17

3.01

CR-18 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE18

8

7

6

45

3

PCI EXPRESS DECOUPLING

V_SM

1419

2425

27

D

IN

80

81

8286

2

1

MCH MEMORY DECOUPLING

CAD NOTE:

SERIES RESISTOR ON SIGNAL MCH_DDR_RCOMPYPU
PLACE 2.2UF CAP (C64UB) ON V_SM CLOSE TO 20 OHM

C68UB

2.2UF
10%

6.3V
X5R
603

V_1P25_CORE

I163

IN

V_1P25_PCIEXPRESS

1

C70UB

10UF
20%

6.3V

2

X5R
805

OUT

1

C72UB

10UF
20%

6.3V

2

X5R
805

2

2

2

C61UB

2.2UF
10%

6.3V

1

X5R
603

2

C67UB

2.2UF
10%

6.3V

1

1

X5R
603

C66UB

2.2UF
10%

6.3V
X5R
603

C65UB

2.2UF
10%

6.3V

1

X5R
603

2

C64UB

2.2UF
10%

6.3V

1

X5R
603

2

MODULE REV DETAILS

MODULE NAME

14

17

1

REV

DATE

D

PCI-E SIGNAL TRANSITION STICHING CAPS

C

98105

V_1P25_CORE

3438

76

131416

IN

171821
828386

1

1

C36UB

0.1UF
20%
16V

2

Y5V
402

1

C37UB

0.1UF
20%

16V

2

2

Y5V
402

C135UB

0.1UF
20%
16V
Y5V
402

1

2

C136UB

0.1UF
20%

16V
Y5V
402

B

A

VCC_HVGIO DECOUPLING

VCC3

1

2

C62UB

.1UF
20%
25V
Y5V
603

VCC3

1

2

C35UB

4.7UF
20%
10V
Y5V
805

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.18

Sun Mar 18 18:43:13 2007

8

7

6

5

4 2

3

[PAGE_TITLE=MCH DCPL & VGA TERMINATION]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

18

1

3.01

CR-19 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE19

8

25

27
24

81

D

CAD NOTE:

PLACE RESISTORS CLOSE TO MCH
ON MCH_VREF

V_SM

1418

IN

19
80

1

8286

C141UB

.1UF
10%
10V

2

EMPTY
402

R75UB

1

19.1
4021%CH

2

MODULE REV DETAILS

MODULE NAME

2

MCH_DDR_RCOMPYPD

7

R72UB

1

1

2

1K

1%

402

CH

R71UB

2

1%

1K

CH

402

CAD NOTE:

PLACE 0.1UF CAP CLOSE TO MCH

1

2

C76UB

0.1UF
20%
16V
Y5V
402

MCH_VREF

6

12

OUT

45

3

1

REV

DATE

D

12

OUT

25

27
24

81

C

PLACE RESISTORS CLOSE TO CH_B DIMMS
ON DIMM_VREF_B

27
24

81

B

ON DIMM_VREF_A

86

1418

IN

19
80
8286

CAD NOTE:

8286
25
1418

IN

19
80

CAD NOTE:

V_SM

1

2

V_SM

1

2

C60MY

.1UF
10%
10V
EMPTY
402

C59MY

.1UF
10%
10V
EMPTY
402

1

1K 1%

402

1

1K

4021%CH

1

1K

402

1

1K

402

PLACE RESISTORS CLOSE TO CH_A DIMMS

V_1P25_CL_MCH

1416

IN

A

R69MY

R70MY

R67MY

R68MY

R57UB

R58UB

2

CH

2

2

1%
CH

2

1%
CH

1

DESIGN NOTE:

1K
1%

CL VREF TARGET: 0.349V

CH

2

402

CL_N_VREF_MCH

1

392

1%

CH

402

2

CAD NOTE:

PLACE 0.1UF CAP ON DIMM_VREF_B
CLOSE TO DIMM PIN

DIMM_VREF_B

1

C58MY

.1UF
20%
25V

2

Y5V
603

CAD NOTE:

PLACE 0.1UF CAP ON DIMM_VREF_A
CLOSE TO DIMM PIN

DIMM_VREF_A

1

C52MY

.1UF
20%
25V

2

Y5V
603

13

1

C73UB

0.1UF
20%
16V

2

Y5V
402

OUT

OUT

1317
20

1317
20

1317
20

25

24

IN
IN
IN

VGA_RED
VGA_GREEN
VGA_BLUE

VCC3

1

C80UB
.1UF
20%
25V
Y5V
603

2

CR3UB
GP

3

SOT23S SOT23S SOT23S

EMPTY

2

1

CR4UB
GP

3

EMPTY

2

1

19

2425

278081

8286

81

8286

81

8286

RGB ESD PROTECTION

CR5UB
GP

3

EMPTY

2

1

DESIGN NOTE:

MAX 0.5 PF

BOM NO TE:

STUFF FOR CRB

R70UB

R73UB

1

19.1
402

2

MCH_DDR_RCOMPYPU

1%

CH

402

MCH_DDR_RCOMPXPD

2

1%

CH

R74UB

1

19.1

2

1%

CH

402

CAD NOTE:

PLACE CAPS CLOSE
TO RCOMPXPU
AND VOH/VOL RESISTORS

1

R60UB

1K
1%

CH
402

2

MCH_DDR_RCOMPVOH

1

R61UB

3.01K
1%

CH
402

2

MCH_DDR_RCOMPVOL

1

R62UB

1K
1%

CH
402

2

MCH_DDR_RCOMPXPU

DESIGN NOTE:

DDR_RCOMPVOH: 0.8 * VSM

1

C133UB

.01UF
10%

25V

2

X7R
402

DESIGN NOTE:

DDR_RCOMPVOL: 0.2 * VSM

1

C134UB

.01UF
10%

25V

2

X7R
402

OUT

OUT

OUTOUT

OUT

OUT

12

C

12

12

B

12

A

12

.1UF

V_SM

C77UB
.1UF
20%
25V
Y5V
603

V_SM

1

2

1

19.1

C132UB

.01UF
10%
25V
EMPTY
402

1418

V_SM

IN

24252780

1

C145UB
20%

25V

2

Y5V
603

141819

IN

1

2

141819

24252780

IN

BPAGE DRAWING

frostburg_fabc.sch_1.19

Sun Mar 18 18:43:14 2007

8

7

6

5

4 2

3

[PAGE_TITLE=MCH VREFS & TERMINATION]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

19

1

3.01

BW_ATX_CORE

CR-20 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE20

8

BOM NO TE:

VGA_RED

131719

IN

VGA_GREEN

131719

IN

131719

IN

VGA_HSYNC_3V
VGA_VSYNC_3V

VGA_BLUE

D

17

IN

17

IN

CHANGE FOR BANDWIDTH OPTIMIZE FOR CRB

C

693286-006

FB3UB

1

1

C89UB

10PF
5%
50V

2

COG
402

7

M13UB

1

MULTI

FB

VGA_BLUE_FB1

2

FB

BOM NO TE:

DEFAULT: STUFF 10PF <A36094-025> FOR

1

2

BOM NO TE:

C90UB

22PF

DEFAULT: STUFF 22PF <A36095-030> FOR

5%
50V
COG
402

2

REPLACE WITH 3.3PF

FOR BANDWITH >200MHZREPLACE WITH 3.3PF

6

BOM NO TE:

DEFAULT: STUFF FERRITE BEAD <693286-006> FOR <200MHZ BANDWIDTH CUTOFF
REPLACE WITH 0OHM 603 FOR >200MHZ BANDWIDTH CUTOFF

M14UB

BANDWIDTH <200MHZ

FOR BANDWITH >200MHZ

693286-006

1

1

C93UB

10PF
5%
50V

2

COG
402

BANDWIDTH <200MHZ

FB4UB

1

VGA_GREEN_FB1

2

FB

1

C81UB

22PF
5%
50V

2

COG
402

MULTI

2

FB

45

693286-006

FB5UB

1

FB

1

C85UB

10PF
5%
50V

2

COG
402

3

M15UB

1

VGA_RED_FB1

2

1

C84UB

22PF
5%
50V

2

COG
402

MULTI

2

FB

VCC

2

C92281-003

RT1UB

1

THRMSTR

1.10

VGA_THERM_9
VGA_GREEN_CONN

VGA_BLUE_CONN

MODULE REV DETAILS

MODULE NAME

M12UB

2

VGA_THERM_PN1

1

MULTI

CH

J4UB

VGA_RED_CONN

TP_VGACONN_11_CORE_R
TP_VGACONN_4_CORE

1

C87UB

100PF
5%
50V

2

EMPTY
402

1
9
2

10

3

11
4

12
5

13
6

14
7

15
8

1

C88UB

100PF
5%
50V

2

EMPTY
402

1

REV

DATE

5-5-061.06.00BW_ATX_CORE

2

1

C94UB

805

.1UF

D

20%
25V

2

Y5V
603

16

RCPT

17

C

1

C92UB

BOM NO TE:

10PF
5%

DEFAULT: STUFF 10PF <A36094-025> FOR

50V

2

COG
402

EMPTY

FOR BANDWITH >200MHZ

BANDWIDTH <200MHZ

A36094-025

B

1

R84UB

150

CAD NOTE:

1%

CH

PLACE RESISTORS CLOSE

402

2

(CAPS / FERRITE-BEADS)

TO FILTERS

VCC3

R112UB

VGA_MCH_DDCSDA_R

2

13

BI

13

BI

VGA_MCH_DDCSDA

R114UB

1

0

402

VGA_MCH_DDCSCL

402

7

5%
CH

R115UB

1

0

A

17

VGA_MCHSIO_DDCSDA

70

BI

17

70

BI

VGA_MCHSIO_DDCSCL

8

1

5%

0

EMPTY

402

VCC3

2

R113UB

2

1

VGA_MCH_DDCSCL_R

0

5%

EMPTY

402

2

5%
CH

BOM NO TE:

UN-STUFF ALL COMPONENTS ON PAGE FOR NON-GRAPHICS SKUS

6

1

R85UB

150
1%

CH
402

2

VGA_DDCSDA_5V_R

Q2UB

BOM NO TE:

EMPTY

REPLACE 603400-001 WITH
C79254-001 (PB FREE #)

VGA_DDCSCL_5V_R

Q3UB

EMPTY

BOM NO TE:

REPLACE 603400-001 WITH
C79254-001 (PB FREE #)

5

R110UB

1

0

402

R111UB

402

1

2

5%

EMPTY

EMPTY

2

1

R13BU

0

1A

EMPTY
603

1

R80UB

2.2K
5%

CH
402

2

VGA_DDC_5V_R

BI

BI

3

1

2

BAT54C
SOT23C

70

C83UB
10PF
5%
50V
COG
402

1

2

70

"COG""COG"

CR7UB

1

R82UB

2.2K
5%

CH
402

2

2

0

402

0

402

2

3

R83UB

R81UB

VCC

VCC3

DIO

1

2

1

5%
CH

1

5%
CH

6.2V

1346

EMPTY

CUSTOM TEXT BPAGE

1

EMPTY

CR2UB

GPGP

3

SOT23SSOT23S

2

C144UB

.1UF
10%
10V
EMPTY
402

3

1

EMPTY

CR1UB

2

VGA_DDCSDA_CONN

VGA_DDCSCL_CONN

1

C86UB

100PF
5%
50V

CR6UB

TP_TVS6_2V_PIN6

TP_TVS6_2V_PIN4

TVS6_2V

2

EMPTY
402

25

[PAGE_TITLE=VGA CONNECTOR]

INTEL

CONFIDENTIAL

DOCUMENT_NUMBER

xxxxxx

1

1

C91UB

100PF
5%
50V

2

EMPTY
402

PAGE REV

20

3.01

B

A

C82UB
10PF
5%
50V
COG
402

"COG"

1

R86UB

150
1%

CH
402

2

2

201

5%

VGA_DDCSDA_5V

R116UB

2

1

100 5%

CH

402

R117UB

2

1

100 5%

CH

402

VGA_DDCSCL_5V

VGA_SIO_DDCSDA_5V

VGA_SIO_DDCSCL_5V

BPAGE DRAWING

frostburg_fabc.sch_1.20

Sun Mar 18 18:43:15 2007

4 2

BW_ATX_CORE

CR-21 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE21

8

SLOT 1

PCI EXPRESS
16-PORT

D

RIGHT LATCH

(DEFAULT)

BOM NO TE:

STUFF J6UB
EMPTY J10UB

102

C

B

C73571-001

A

PCI RETENTION MODEL

PCIE_RM

1

GND

2

GND

1.0

E

8

70

70101

8586

87

88

47

4849

102

9092

101

J5UB

EMPTY

7

4849

4849

708284

32333436373839

47

98

101

BI

101

102103105

22

27

283347

BI

102103105

103105
53596469
9212228

IN

3336

22

OUT

2223

IN

2223

IN

10

22

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

10

22

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

13

22

OUT

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

2223

IN

22

27

283347

SMB_CLK_RESUME

SMB_DATA_RESUME

V_3P3_STBY\G

WAKE_N

EXP_A_TX_0_C_DP
EXP_A_TX_0_C_DN

SDVO_CTRL_CLK

EXP_A_TX_1_C_DP
EXP_A_TX_1_C_DN

EXP_A_TX_2_C_DP
EXP_A_TX_2_C_DN

EXP_A_TX_3_C_DP
EXP_A_TX_3_C_DN

SDVO_CTRL_DATA

EXP_A_TX_4_C_DP
EXP_A_TX_4_C_DN

EXP_A_TX_5_C_DP
EXP_A_TX_5_C_DN

EXP_A_TX_6_C_DP
EXP_A_TX_6_C_DN

EXP_A_TX_7_C_DP
EXP_A_TX_7_C_DN

EXP_PRSNT_N

EXP_A_TX_8_C_DP
EXP_A_TX_8_C_DN

EXP_A_TX_9_C_DP
EXP_A_TX_9_C_DN

EXP_A_TX_10_C_DP
EXP_A_TX_10_C_DN

EXP_A_TX_11_C_DP
EXP_A_TX_11_C_DN

EXP_A_TX_12_C_DP

EXP_A_TX_12_C_DN

EXP_A_TX_13_C_DP
EXP_A_TX_13_C_DN

EXP_A_TX_14_C_DP
EXP_A_TX_14_C_DN

EXP_A_TX_15_C_DP

EXP_A_TX_15_C_DN

7

22

22

22
22

6

VCC3 +12V +12V VCC3

B1
B2
B3
B4
B5
B6
B7

TP_3G16_JTAG1

TP_3G16_RSVD_B12

TP_3G16_RSVD_B80
TP_16PRSNT_B82

B10
B11

B12
B13
B14
B15
B16
B17
B18

B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

B8
B9

6

12V
12V

12V
GND
SMCLK
SMDAT
GND

3.3V

JTAG1

3.3VAUX

WAKE*

RSVD
GND

HSOP0

HSON0
GND
PRSNT2*
GND

HSOP1

HSON1
GND
GND

HSOP2

HSON2
GND
GND

HSOP3

HSON3
GND
RSVD
PRSNT2*
GND

HSOP4

HSON4
GND
GND

HSOP5

HSON5
GND
GND

HSOP6

HSON6
GND
GND

HSOP7

HSON7
GND
PRSNT2*
GND

HSOP8

HSON8
GND
GND

HSOP9

HSON9
GND
GND

HSOP10

HSON10
GND
GND

HSOP11

HSON11
GND
GND

HSOP12

HSON12
GND
GND

HSOP13

HSON13
GND
GND

HSOP14

HSON14
GND
GND

HSOP15

HSON15
GND
PRSNT2*
RSVD

5

J6UB

3GIO_X16

REV=2.0

KEY

1OF1

PRSNT1*

JTAG2
JTAG3
JTAG4
JTAG5

3.3V

3.3V

PWRGD

REFCLK+
REFCLK-

HSIP0
HSIN0

RSVD

HSIP1
HSIN1

HSIP2
HSIN2

HSIP3
HSIN3

RSVD

RSVD

HSIP4
HSIN4

HSIP5
HSIN5

HSIP6
HSIN6

HSIP7
HSIN7

RSVD

HSIP8
HSIN8

HSIP9
HSIN9

HSIP10
HSIN10

HSIP11
HSIN11

HSIP12
HSIN12

HSIP13
HSIN13

HSIP14
HSIN14

HSIP15
HSIN15

12V
12V
GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND

CONN

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11

A12
A13
A14
A15
A16
A17
A18

A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

45

TP_3G16_JTAG2
TP_3G16_JTAG3
TP_3G16_JTAG4
TP_3G16_JTAG5

PLTRST_PCIE_SLOTS_N

CK_PE_100M_16PORT_DP

CK_PE_100M_16PORT_DN

EXP_A_RX_0_DP
EXP_A_RX_0_DN

TP_3G16RSVD_A19

EXP_A_RX_1_DP
EXP_A_RX_1_DN

EXP_A_RX_2_DP
EXP_A_RX_2_DN

EXP_A_RX_3_DP
EXP_A_RX_3_DN

TP_3G16_RSVD_A32

TP_3G16_RSVD_A33

EXP_A_RX_4_DP
EXP_A_RX_4_DN

EXP_A_RX_5_DP
EXP_A_RX_5_DN

EXP_A_RX_6_DP
EXP_A_RX_6_DN

EXP_A_RX_7_DP
EXP_A_RX_7_DN

TP_3G16_RSVD_A50

EXP_A_RX_8_DP
EXP_A_RX_8_DN

EXP_A_RX_9_DP
EXP_A_RX_9_DN

EXP_A_RX_10_DP
EXP_A_RX_10_DN

EXP_A_RX_11_DP
EXP_A_RX_11_DN

EXP_A_RX_12_DP
EXP_A_RX_12_DN

EXP_A_RX_13_DP
EXP_A_RX_13_DN

EXP_A_RX_14_DP
EXP_A_RX_14_DN

EXP_A_RX_15_DP
EXP_A_RX_15_DN

22
22
22
22

22

22

22

22

Sun Mar 18 18:43:16 2007

4 2

3

22

47 70 101

IN

22 29

IN

22 29

IN

10

22

OUT

10

22

OUT

47

48

49

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

10

22

OUT

BPAGE DRAWING

frostburg_fabc.sch_1.21

3

102

82848586878890

2

MODULE REV DETAILS

MODULE NAME

BW_ATX_CORE 5-5-061.06.00

1

REV

VCC3

C98UB

2

1

20%

.1UF

25V

EMPTY

603

+12V

C97UB

2

1

.1UF 20%

25V
Y5V

V_3P3_STBY\G

IN

1

.1UF

2

16V

13

IN

83

2

C46BU

0.1UF
20%

16V

1

Y5V
402

2

C51BU

0.1UF
20%
16V

1

Y5V
402

DOCUMENT_NUMBER

603

C96UB

2

20%
25V
Y5V
603

VCC3+12V

C95UB

100UF

1

20.0%

14 161718
86 98 105

2

C47BU

0.1UF
20%
16V

1

Y5V
402

xxxxxx

2

25V

ELEC

RDL

DESIGN NOTE:

ATX FF ONLY

34 387682

2

C48BU

0.1UF
20%

16V

1

EMPTY
402

1

92

101

102103105

32333436373839

70

CAD NOTE:

PLACE NEAR EDGE OF PEG SLOT
FOR SIGNAL TRANSITION REF

9212228

53

596469

DESIGN NOTE:

ALWAYS STUFF C99UB & C95UB
EVEN IF J6UB IS EMPTY
FOR X1 DECOUPLING

C99UB

470.0UF

1

20%

ALUM

RDL

V_1P25_CORE

2

2

C44BU

C45BU

0.1UF

0.1UF

20%

20%
16V
Y5V
402

C49BU

0.1UF
20%
16V
Y5V
402

16V

1

EMPTY

402

2

C50BU

0.1UF
20%

16V

1

EMPTY
402

1

2

1

[PAGE_TITLE=PCI EXPRESS X16]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DATE

PAGE REV

21

3.01

D

C

B

A

BW_ATX_CORE

CR-22 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE22

8

SLOT 1

PCI EXPRESS
16-PORT

D

LEFT LATCH

BOM NO TE:

STUFF J6UB
EMPTY J10UB

59

64

C

B

A

8

70101

70101

102103

87

889092

101

47

484953

102

102103105

7

4849

4849

32333436373839

47

98

101

BI

102103105

21

27

283347

BI

105

70

82848586

69
92128

IN

213336

OUT

21

23

IN

21

23

IN

10

21

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

10

21

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

13

21

OUT

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

23

IN

21

27

283347

SMB_CLK_RESUME

V_3P3_STBY\G

WAKE_N

EXP_A_TX_0_C_DP
EXP_A_TX_0_C_DN

SDVO_CTRL_CLK

EXP_A_TX_1_C_DP
EXP_A_TX_1_C_DN

EXP_A_TX_2_C_DP
EXP_A_TX_2_C_DN

EXP_A_TX_3_C_DP
EXP_A_TX_3_C_DN

SDVO_CTRL_DATA

EXP_A_TX_4_C_DP
EXP_A_TX_4_C_DN

EXP_A_TX_5_C_DP
EXP_A_TX_5_C_DN

EXP_A_TX_6_C_DP
EXP_A_TX_6_C_DN

EXP_A_TX_7_C_DP
EXP_A_TX_7_C_DN

EXP_PRSNT_N

EXP_A_TX_8_C_DP
EXP_A_TX_8_C_DN

EXP_A_TX_9_C_DP
EXP_A_TX_9_C_DN

EXP_A_TX_10_C_DP
EXP_A_TX_10_C_DN

EXP_A_TX_11_C_DP
EXP_A_TX_11_C_DN

EXP_A_TX_12_C_DP

EXP_A_TX_12_C_DN

EXP_A_TX_13_C_DP
EXP_A_TX_13_C_DN

EXP_A_TX_14_C_DP
EXP_A_TX_14_C_DN

EXP_A_TX_15_C_DP

EXP_A_TX_15_C_DN

7

21

21

21
21

6

VCC3 +12V +12V VCC3

B1
B2
B3
B4
B5
B6
B7

TP_3G16_JTAG1

B8
B9

B11

TP_3G16_RSVD_B12

TP_3G16_RSVD_B80
TP_16PRSNT_B82

B12
B13
B14
B15
B16
B17
B18

B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82

6

12V
12V

12V
GND
SMCLK
SMDAT
GND

3.3V

JTAG1

3.3VAUX

WAKE*

RSVD
GND

HSOP0

HSON0
GND
PRSNT2*
GND

HSOP1

HSON1
GND
GND

HSOP2

HSON2
GND
GND

HSOP3

HSON3
GND
RSVD
PRSNT2*
GND

HSOP4

HSON4
GND
GND

HSOP5

HSON5
GND
GND

HSOP6

HSON6
GND
GND

HSOP7

HSON7
GND
PRSNT2*
GND

HSOP8

HSON8
GND
GND

HSOP9

HSON9
GND
GND

HSOP10

HSON10
GND
GND

HSOP11

HSON11
GND
GND

HSOP12

HSON12
GND
GND

HSOP13

HSON13
GND
GND

HSOP14

HSON14
GND
GND

HSOP15

HSON15
GND
PRSNT2*
RSVD

5

J10UB

3GIO_X16

REV=2.0

KEY

1OF1

PRSNT1*

JTAG2
JTAG3
JTAG4
JTAG5

3.3V

3.3V

PWRGD

REFCLK+
REFCLK-

HSIP0
HSIN0

RSVD

HSIP1
HSIN1

HSIP2
HSIN2

HSIP3
HSIN3

RSVD

RSVD

HSIP4
HSIN4

HSIP5
HSIN5

HSIP6
HSIN6

HSIP7
HSIN7

RSVD

HSIP8
HSIN8

HSIP9
HSIN9

HSIP10
HSIN10

HSIP11
HSIN11

HSIP12
HSIN12

HSIP13
HSIN13

HSIP14
HSIN14

HSIP15
HSIN15

12V
12V
GND

GND

GND

GND

GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND

GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND
GND

GND

EMPTY

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10B10
A11

A12
A13
A14
A15
A16
A17
A18

A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82

45

TP_3G16_JTAG2
TP_3G16_JTAG3SMB_DATA_RESUME
TP_3G16_JTAG4
TP_3G16_JTAG5

PLTRST_PCIE_SLOTS_N

CK_PE_100M_16PORT_DP

CK_PE_100M_16PORT_DN

EXP_A_RX_0_DP
EXP_A_RX_0_DN

TP_3G16RSVD_A19

EXP_A_RX_1_DP
EXP_A_RX_1_DN

EXP_A_RX_2_DP
EXP_A_RX_2_DN

EXP_A_RX_3_DP
EXP_A_RX_3_DN

TP_3G16_RSVD_A32

TP_3G16_RSVD_A33

EXP_A_RX_4_DP
EXP_A_RX_4_DN

EXP_A_RX_5_DP
EXP_A_RX_5_DN

EXP_A_RX_6_DP
EXP_A_RX_6_DN

EXP_A_RX_7_DP
EXP_A_RX_7_DN

TP_3G16_RSVD_A50

EXP_A_RX_8_DP
EXP_A_RX_8_DN

EXP_A_RX_9_DP
EXP_A_RX_9_DN

EXP_A_RX_10_DP
EXP_A_RX_10_DN

EXP_A_RX_11_DP
EXP_A_RX_11_DN

EXP_A_RX_12_DP
EXP_A_RX_12_DN

EXP_A_RX_13_DP
EXP_A_RX_13_DN

EXP_A_RX_14_DP
EXP_A_RX_14_DN

EXP_A_RX_15_DP
EXP_A_RX_15_DN

21
21
21
21

21

21

21

21

Sun Mar 18 18:43:17 2007

4 2

3

21

47 70 101

IN

21

29

IN

21

29

IN

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

10

21

OUT

BPAGE DRAWING

frostburg_fabc.sch_1.22

3

102

DESIGN NOTE:

PCIE X16 GRAPHIC CONNECTOR WITH LEFT LATCH

2

MODULE REV DETAILS

MODULE NAME

BW_ATX_CORE 5-5-061.06.00

[PAGE_TITLE=PCI EXPRESS X16]

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

1

REV

1

DATE

PAGE REV

22

3.01

D

C

B

A

BW_ATX_CORE

CR-23 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE23

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

1

REV

DATE

5-5-061.06.00BW_ATX_CORE

D

10

IN

10

IN

EXP_A_TX_0_DN
EXP_A_TX_0_DP

C103UB

1

.1UF

C102UB

2

1

.1UF

2

10%

10V
X5R
402

BOM NO TE:

10%

10V
X5R
402

EXP_A_TX_0_C_DN
EXP_A_TX_0_C_DP

OUT
OUT

21

22

21

22

D

STUFF ALL THE CAPS
EVEN UNSTUFF THE PCIEX16

C101UB

1

10

IN

10

IN

10

IN

10

IN

10

IN

10

C

IN

10

IN
IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

EXP_A_TX_1_DN
EXP_A_TX_1_DP

EXP_A_TX_2_DN
EXP_A_TX_2_DP

EXP_A_TX_3_DN
EXP_A_TX_3_DP

EXP_A_TX_4_DN
EXP_A_TX_4_DP

EXP_A_TX_5_DN
EXP_A_TX_5_DP

EXP_A_TX_6_DN
EXP_A_TX_6_DP

EXP_A_TX_7_DN
EXP_A_TX_7_DP

B

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

IN

10

A

IN

10

IN

10

IN

10

IN

10

IN

EXP_A_TX_8_DN
EXP_A_TX_8_DP

EXP_A_TX_9_DN
EXP_A_TX_9_DP

EXP_A_TX_10_DN
EXP_A_TX_10_DP

EXP_A_TX_11_DN
EXP_A_TX_11_DP

EXP_A_TX_12_DN
EXP_A_TX_12_DP

EXP_A_TX_13_DN
EXP_A_TX_13_DP

EXP_A_TX_14_DN
EXP_A_TX_14_DP

EXP_A_TX_15_DN
EXP_A_TX_15_DP

.1UF

C107UB

1

.1UF

C116UB

1

.1UF

C112UB

1

.1UF

C122UB

1

.1UF

C118UB

1

.1UF

C128UB

1

.1UF

C124UB

1

.1UF

2

C100UB

1

.1UF

X5R
402

C106UB

1

.1UF

X5R
402

C115UB

1

.1UF

X5R
402

C111UB

1

.1UF

X5R
402

C121UB

1

.1UF

X5R
402

C131UB

1

.1UF

X5R
402

C127UB

1

.1UF

X5R
402

C123UB

1

.1UF

X5R
402

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

2

10%

10V

C109UB

1

.1UF

C104UB

1

.1UF

10V
X5R
402

C120UB

1

.1UF

10V
X5R
402

C130UB

1

.1UF

10V
X5R
402

C126UB

1

.1UF

10V
X5R
402

10V
X5R
402

C105UB

1

.1UF

X5R
402

C114UB

1

.1UF

X5R
402

2

C108UB

1

.1UF

C110UB

1

.1UF

X5R
402

C119UB

1

.1UF

X5R
402

C129UB

1

.1UF

X5R
402

C125UB

1

.1UF

X5R
402

10V
X5R
402

C117UB

1

.1UF

C113UB

1

.1UF

10V

10V

10V

10V

2

10%

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

2

10%

2

10%

2

10%

10%

2

10%

10V

2

10%

10V

2

10%

2

10%

2

10%

2

10%

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

2

10%

10V
X5R
402

EXP_A_TX_1_C_DN
EXP_A_TX_1_C_DP

EXP_A_TX_2_C_DN
EXP_A_TX_2_C_DP

EXP_A_TX_3_C_DN

EXP_A_TX_3_C_DP

EXP_A_TX_4_C_DN
EXP_A_TX_4_C_DP

EXP_A_TX_5_C_DN
EXP_A_TX_5_C_DP

EXP_A_TX_6_C_DN
EXP_A_TX_6_C_DP

EXP_A_TX_7_C_DN

EXP_A_TX_7_C_DP

EXP_A_TX_8_C_DN

EXP_A_TX_8_C_DP

EXP_A_TX_9_C_DN
EXP_A_TX_9_C_DP

EXP_A_TX_10_C_DN

EXP_A_TX_10_C_DP
EXP_A_TX_11_C_DN

EXP_A_TX_11_C_DP

EXP_A_TX_12_C_DN
EXP_A_TX_12_C_DP

EXP_A_TX_13_C_DN
EXP_A_TX_13_C_DP

EXP_A_TX_14_C_DN
EXP_A_TX_14_C_DP

EXP_A_TX_15_C_DN
EXP_A_TX_15_C_DP

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

2210

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

21

22

C

B

A

BPAGE DRAWING

frostburg_fabc.sch_1.23

Sun Mar 18 18:43:18 2007

8

7

6

5

4 2

[PAGE_TITLE=PCI EXPRESS X16 COUPLING]

INTEL

CONFIDENTIAL

3

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

23

1

3.01

24

112411

24

D

2426

C

24

24

B

A

CR-24 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE24

8

11

BI

M_DQS_A_DP<7..0>M_DQS_A_DP<7..0>

BI

M_ODT_A<3..0>

11

BI

11

11

112426

1

102

19

77

68

IO

NC

NC

ODT1

NC/TEST

VSS

VSS

VSS

VSS

VSS

852

11

14

M_DQS_A_DN<7..0>

BI

M_DQS_A_DP<7..0>

BI

M_ODT_A<3..0>

BI

19

102

68

IO

NC

NC

NC/TEST

VSS

VSS

VSS

VSS

852

11

0

195

ODT0

VSS

17

3

77

ODT1

VSS

14

VSS

20

2

195

ODT0

VSS

17

TP_SA_CB0_6

TP_SA_CB0_3

TP_SA_CB0_4

TP_SA_CB0_5

TP_SA_CB0_1

TP_SA_CB0_2

TP_SA_CB0_0

167

162

161

494843

42

CB<3>

CB<2>

CB<1>

CB<0>

CB<5>

CB<4>

VSS

VSS

VSS

VSS

VSS

VSS

383532

292623

41

TP_SA_CB_0

TP_SA_CB_3

TP_SA_CB_4

TP_SA_CB_5

TP_SA_CB_2

TP_SA_CB_1

161

494843

42

CB<3>

CB<2>

CB<1>

CB<0>

CB<4>

VSS

VSS

VSS

VSS

VSS

VSS

292623

20

TP_SA_CB0_7

CB<6>

VSS

TP_SA_CB_6

162

CB<5>

VSS

383532

168

CB<7>

VSS

167

CB<6>

VSS

41

VSS

TP_SA_CB_7

168

CB<7>

VSS

7

1

0

1

0

15

16

7

6

DQS<1>

DQS<0>

DQS*<1>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

0

1

0

16

7

6

DQS<1>

DQS<0>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

CHANNEL A

8

7

6

3

36

100

3

37

97

BI

4

84

DQS<4>

DQS*<3>

VSS

VSS

VSS

106

103

11

3

36

DQS<3>

DQS*<3>

VSS

VSS

VSS

100

103

M_DQM_A<7..0>

5

4

6

5

105

92

83

93

DQS<5>

DQS<6>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

VSS

VSS

121

124

118

115

112

109

M_DQM_A<7..0>

BI

5

4

5

4

92

83

93

84

DQS<5>

DQS<4>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

VSS

VSS

118

115

112

109

106

121

6

104

DQS*<6>

VSS

127

6

105

DQS<6>

VSS

124

VSS

130

6

104

DQS*<6>

VSS

127

7

114

DQS<7>

VSS

133

VSS

130

7

113

DQS*<7>

VSS

136

7
114

DQS<7>

VSS

133

VSS

139

8286

7

113

DQS*<7>

VSS

136

TP_SA_DQS0_8

46

DQS<8>

VSS

142

VSS

139

8286

TP_SA_DQSB0_8

45

DQS*<8>

VSS

145

TP_SA_DQS_8

46

DQS<8>

VSS

142

VSS

148

TP_SA_DQSB_8

45

DQS*<8>

VSS

145

81

0

125

DM0/DQS9

VSS

151

VSS

148

126

154

80

NC/DQS9*

VSS

278081

0

125

DM0/DQS9

VSS

151

VSS

157

126

NC/DQS9*

VSS

154

27

1

134

DM1/DQS10

VSS

160

VSS

157

135

NC/DQS10*

VSS

163

1

134

DM1/DQS10

VSS

160

VSS

166

2425

135

NC/DQS10*

VSS

163

27
27

2

146

DM2/DQS11

VSS

169

VSS

166

2425

147

NC/DQS11*

VSS

198

2

146

DM2/DQS11

VSS

169

VSS

201

24

147

NC/DQS11*

VSS

198

19

27
27

3

155

DM3/DQS12

VSS

204

2425
2425

VSS

201

156

NC/DQS12*

VSS

207

141819
19

3

155

DM3/DQS12

VSS

204

24

VSS

210

156

NC/DQS12*

VSS

207

4

202

213

BI
BI

210

1418
19

2425
2425

203

DM4/DQS13

NC/DQS13*

VSS

VSS

216

IN
IN

4

202

DM4/DQS13

VSS

VSS

213

5

211

212

DM5/DQS14

NC/DQS14*

VSS

VSS

VSS

VSS

222

219

225

228

V_SM

DIMM_VREF_A

SMB_CLK_MEM

SMB_DATA_MEM

5

211

212

203

DM5/DQS14

NC/DQS14*

NC/DQS13*

VSS

VSS

VSS

VSS

225

222

219

216

V_SM

IN

DIMM_VREF_A

IN
BI
BI

7

6

224

232

223

DM6/DQS15

NC/DQS15*

DM7/DQS16

VSS

VSS

VSS

VDDQ

51

237

231

234

27

6

224

223

DM6/DQS15

NC/DQS15*

VSS

VSS

VSS

VSS

237

228

234

231

SMB_CLK_MEM
SMB_DATA_MEM

27

233

NC/DQS16*

VDDQ

56

2425

7

232

DM7/DQS16

VDDQ

51

VDDQ

62

233

NC/DQS16*

VDDQ

56

2425

164

DM8/DQS17

VDDQ

IN

VDDQ

62

165

NC/DQS17*

VDDQ

164

DM8/DQS17

VDDQ

IN

VDDQ

787572

165

NC/DQS17*

VDDQ

M_DATA_A<63..0>M_DQS_A_DN<7..0>

1

0

3

9

4

DQ<1>

DQ<0>

DQ<2>

VDDQ

VDDQ

VDDQ

181

191

194

V_3P3_MEM

3

4

DQ<1>

DQ<0>

VDDQ

VDDQ

VDDQ

787572

194

191

11

24

2

3

2

37

27

28

DQS<2>

DQS<3>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

97

9491888582796665504744

24

1

2

2

15

27

28

DQS<2>

DQS*<1>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

9491888582796665504744

[PAGE_TITLE=240P CONN DDR2, CH A]

6

5

45

101112131415161718

9

8765432

13

12

129

128

123

122

10

DQ<3>

VDDQ

175

21

22

DQ<4>

DQ<5>

DQ<6>

DQ<7>

DQ<9>

DQ<8>

DQ<11>

DQ<10>

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDQ

69

64

59

53

187

197

170

172

TP_CH_A1_RC1_RCU
TP_CH_A1_RC0_RFU

M_DATA_A<63..0>

9

876543210

13

12

10

129

128

123

122

9

DQ<2>

VDDQ

181

DQ<3>

VDDQ

175

21

DQ<4>

DQ<5>

DQ<6>

DQ<7>

DQ<9>

DQ<8>

DQ<10>

VDD

VDD

VDD

VDD

VDD

VDD

VDDQ

69

64

59

53

170

172

197

TP_CH_A2_RC1_RCU
TP_CH_A2_RC0_RFU

V_3P3_MEM

4 2

131

DQ<12>

VDD

184

22

DQ<11>

VDD

187

132

DQ<13>

VDD

178

121110

131

DQ<12>

VDD

184

140

189

13

132

178

BI

30

141

25

24

DQ<15>

DQ<16>

DQ<14>

DQ<17>

DQ<18>

RC0

RC1

VDD

VDD

18

67

55

BI

1416151719

141

140

25

24

DQ<15>

DQ<16>

DQ<13>

DQ<14>

DQ<17>

RC1

VDD

VDD

VDD

18

67

189

11

24

19

202122232425262728

31

149

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<22>

SCL

SDA

VREF

VDDSPD

1

119

120

238

11

24

18

21

20222324262527

31

30

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<18>

RC0

SCL

VREF

VDDSPD

1

55

120

238

Sun Mar 18 18:43:19 2007

3

303132333435363738

29

393433

150

101

DQ<23>

DQ<24>

SA2

SA1

240

DQ<25>

SA0

239

159

158

153

152

81

80

40

DQ<26>

DQ<27>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

DQ<33>

BA1

BA0

CKE1

S1*

CKE0

71

76

52

171

190

1

31

283029

393433

159

158

153

152

150

149

40

DQ<25>

DQ<26>

DQ<27>

DQ<22>

DQ<23>

DQ<24>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

SDA

SA2

SA0

SA1

BA1

BA0

CKE1

CKE0

71

239

190

171

52

119

101

240

1

BPAGE DRAWING

frostburg_fabc.sch_1.24

3

39

199

87

86

206

205

200

DQ<34>

DQ<35>

DQ<36>

DQ<37>

DQ<39>

DQ<38>

S0*

CK1/RFU

CK1*/RFU

CK2*/RFU

CK2/RFU

137

193

138

221

220

01010

333235343637384039

199

87

868180

205

200

DQ<34>

DQ<35>

DQ<36>

DQ<37>

DQ<33>

DQ<38>

S0*

S1*

CK1*/RFU

CK2*/RFU

CK2/RFU

76

193

138

221

220

23230

404142434445464748

89

DQ<42>

DQ<41>

DQ<40>

CK0

CK0*

186

185

41

89

206

DQ<41>

DQ<40>

DQ<39>

CK0

CK1/RFU

CK0*

137

186

185

2

505152535455565758

49

108

107

99

98

969590

188

214

209

208

DQ<43>

DQ<46>

DQ<44>

DQ<45>

A2A1A0

63

182

183

215

DQ<47>

61

218

217

DQ<52>

DQ<51>

DQ<50>

DQ<49>

DQ<53>

DQ<48>

A10/AP

A9A8A7A6A5A4A3

70

60

177

17958180

9

876543210

42444345474649485051525453

107

108

99

98

969590

209

208

DQ<43>

DQ<42>

DQ<44>

DQ<45>

63

183

188

CONFIDENTIAL

CUSTOM TEXT BPAGE

214

DQ<46>

182

215

DQ<47>

DQ<48>

61

60

INTEL

217

DQ<52>

DQ<51>

DQ<50>

DQ<49>

177

17958180

9

876543210

MODULE REV DETAILS

MODULE NAME

63

626160

59

117

116

111

226

DQ<54>

A11

57

218

DQ<53>

A10/AP

70

227

DQ<55>

A12

176

121110

226

DQ<54>

A11A9A8A7A6A5A4A3A2A1A0

57

110

DQ<56>

A13

196

13

55

227

DQ<55>

A12

176

121110

236

235

230

229

DQ<57>

DQ<58>

DQ<62>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A16/BA2

RAS*

CAS*

74

73

54

M_RAS_A_N

192

173

174

M_CAS_A_N

2

M_SBS_A<2..0>

TP_M_MAA_A15

14

M_MAA_A<14..0>
CK_M_DDR0_A_DP
CK_M_DDR0_A_DN
CK_M_DDR1_A_DP
CK_M_DDR1_A_DN
CK_M_DDR2_A_DP
CK_M_DDR2_A_DN
M_SCS_A_N<3..0>
M_SCKE_A<3..0>
M_SBS_A<2..0>

565857

5961606362

117

111

116

110

235

230

229

DQ<56>

DQ<57>

DQ<58>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A13

A16/BA2

CAS*

74

54

192

173

174

196

2

M_CAS_A_N

M_SBS_A<2..0>

TP_M1_MAA_A15

14

13

M_MAA_A<14..0>

CK_M_DDR3_A_DP
CK_M_DDR3_A_DN
CK_M_DDR4_A_DP
CK_M_DDR4_A_DN
CK_M_DDR5_A_DP

CK_M_DDR5_A_DN
M_SCS_A_N<3..0>
M_SCKE_A<3..0>
M_SBS_A<2..0>

DOCUMENT_NUMBER

xxxxxx

REV

DQ<63>

ADDRESS: 000

X

0A0

J1MY

DDRII_240P

WE*

M_WE_A_N

236

DQ<63>

DQ<62>

ADDRESS: 001
0A2

J2MY

DDRII_240P

WE*

RAS*

M_WE_A_N

73

M_RAS_A_N

1

IN
IN
IN
BI

BI
IN
IN
IN
IN
IN
IN
BI
BI
BI

X

IN
IN
IN

BI

BI
IN
IN
IN
IN
IN
IN

BI

BI

BI

1

DATE

112426
112426

24

26

11

112426

112426
11
11
11
11
11
11

112426

112426

112426

11

24 26

11

24 26

11

24 26

11

24 26

11

24 26

11
11
11
11
11
11

11

24 26

11

24 26

11

24 26

PAGE REV

24

3.01

D

C

B

A

CR-25 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE25

8

M_DQS_B_DN<7..0>

12

25

BI

M_DQS_B_DP<7..0>

12

25

BI

M_ODT_B<3..0>

12

2526

D

BI

1

02

195

19

102

77

68

IO

NC

NC

ODT0

ODT1

NC/TEST

VSS

VSS

VSS

VSS

VSS

VSS

852

11

17

14

20

TP_SB_CB0_6

TP_SB_CB0_3

TP_SB_CB0_4

TP_SB_CB0_5

TP_SB_CB0_1

TP_SB_CB0_2

TP_SB_CB0_0

167

162

161

494843

42

CB<3>

CB<2>

CB<1>

CB<0>

CB<5>

CB<4>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

383532

292623

41

C

M_DQS_B_DN<7..0>

12

25

BI

M_DQS_B_DP<7..0>

12

25

BI

M_ODT_B<3..0>

12

2526

B

BI

3

195

102

19

77

68

IO

NC

NC

ODT0

ODT1

NC/TEST

VSS

VSS

VSS

VSS

VSS

VSS

852

17

11

14

20

TP_SB_CB_6

TP_SB_CB_3

TP_SB_CB_4

TP_SB_CB_5

TP_SB_CB_1

TP_SB_CB_2

TP_SB_CB_0

167

161

162

494843

42

CB<3>

CB<2>

CB<1>

CB<0>

CB<5>

CB<4>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

383532

292623

41

7

3

36

100

3

36

100

BI

4

84

DQS<4>

DQS*<3>

VSS

VSS

VSS

106

103

BI

4

84

DQS<4>

DQS*<3>

VSS

VSS

VSS

106

103

M_DQM_B<7..0>

5

4

5

92

83

93

DQS<5>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

118

115

112

109

121

M_DQM_B<7..0>

5

4

5

92

83

93

DQS<5>

DQS*<4>

DQS*<5>

VSS

VSS

VSS

VSS

118

115

112

109

121

12

25

1

0

2

TP_SB_CB0_7

0

168

7

6

CB<6>

CB<7>

DQS<0>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

VSS

0

TP_SB_CB_7

0

168

7

6

CB<6>

CB<7>

DQS<0>

DQS*<0>

VSS

VSS

VSS

VSS

VSS

VSS

3

1

2

37

15

16

27

28

DQS<1>

DQS<2>

DQS<3>

DQS*<1>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

97

9491888582796665504744

12

25

1

2

3

1

2

37

15

16

27

28

DQS<1>

DQS<2>

DQS<3>

DQS*<1>

DQS*<2>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

97

9491888582796665504744

6

M_DATA_B<63..0>

3

1

2

0

7

6

TP_SB_DQSB0_8

TP_SB_DQS0_8

7

6

104

114

105

DQS<6>

DQS<7>

DQS*<6>

DQS*<7>

VSS

VSS

VSS

VSS

VSS

VSS

VSS

139

136

133

130

124

127

81

8286

134

125

45

46

DQS<8>

DQS*<8>

NC/DQS9*

DM0/DQS9

DM1/DQS10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

160

154

148

145

142

157

151

25

27

80

126

113

135

NC/DQS10*

VSS

163

27
27

166

156

147

155

146

NC/DQS11*

DM2/DQS11

DM3/DQS12

NC/DQS12*

VSS

VSS

VSS

VSS

VSS

VSS

VSS

198

169

210

204

207

201

14181924

IN

19

25

IN

2425

BI

2425

BI

5

4

212

203

202

211

DM4/DQS13

DM5/DQS14

NC/DQS14*

NC/DQS13*

VSS

VSS

VSS

VSS

VSS

VSS

228

225

222

219

216

213

V_SM

DIMM_VREF_B

SMB_CLK_MEM

SMB_DATA_MEM

6

223

231

224

DM6/DQS15

NC/DQS15*

VSS

VSS

VSS

234

237

7

232

DM7/DQS16

VDDQ

51

233

56

0

3

165

164

9

4

DQ<1>

DQ<0>

NC/DQS16*

VDDQ

DQ<2>

NC/DQS17*

DM8/DQS17

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

787572

62

194

191

181

24

2527

IN

1

M_DATA_B<63..0>

3

1

0

7

6

TP_SB_DQSB_8

TP_SB_DQS_8

7

6

126

45

145

135

134

125

DQS*<8>

NC/DQS9*

DM0/DQS9

NC/DQS10*

DM1/DQS10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

166

163

160

154

148

157

151

113

104

114

105

46

DQS<6>

DQS<7>

DQS<8>

DQS*<6>

DQS*<7>

VSS

VSS

124

127

VSS

VSS

VSS

VSS

VSS

VSS

142

139

136

133

130

2

146

169

4

147

156

155

203

202

NC/DQS11*

DM2/DQS11

DM3/DQS12

NC/DQS12*

DM4/DQS13

NC/DQS13*

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

198

207

219

216

213

210

204

201

5

211

DM5/DQS14

VSS

222

212

NC/DQS14*

VSS

225

228

7

6

3

165

164

233

224

223

232

DM6/DQS15

NC/DQS15*

DM7/DQS16

NC/DQS16*

VSS

VSS

VSS

VSS

VDDQ

VDDQ

56

51

237

234

231

9

4

DQ<1>

DQ<0>

DQ<2>

NC/DQS17*

DM8/DQS17

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

78

75

72

62

194

191

181

A

V_SM

141819

2425

27

80

81

8286

27
27

IN

DIMM_VREF_B

19

25

IN
BI
BI

SMB_CLK_MEM

SMB_DATA_MEM

27

2425

2425
2425

45

101112131415161718

9

8765432

1312129

128

123

122

10

DQ<3>

VDDQ

175

21

22

DQ<4>

DQ<5>

DQ<6>

DQ<7>

DQ<9>

DQ<8>

DQ<11>

DQ<10>

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDDQ

69

64

59

53

170

172

187

197

TP_CH_B1_RC1_RCU
TP_CH_B1_RC0_RFU

V_3P3_MEM

9

876543210

13

12

10

129

128

123

122

DQ<4>

DQ<3>

VDDQ

VDDQ

170

175

TP_CH_B2_RC1_RCU
TP_CH_B2_RC0_RFU

IN

DQ<5>

DQ<6>

DQ<7>

DQ<8>

VDD

VDD

VDD

VDD

64

59

53

197

V_3P3_MEM

22

21

DQ<9>

DQ<11>

DQ<10>

VDD

VDD

VDD

69

172

187

141

140

132

131

DQ<12>

DQ<13>

DQ<14>

VDD

VDD

VDD

67

184

189

178

1416151719

13

121110

131

140

132

141

DQ<12>

DQ<13>

DQ<14>

VDD

VDD

VDD

67

184

189

178

BI

30

25

24

DQ<15>

DQ<16>

DQ<17>

RC1

VDD

18

55

BI

18

30

25

24

DQ<15>

DQ<16>

DQ<17>

RC1

VDD

18

55

12

25

19

202122232425262728

31

149

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<18>

DQ<22>

RC0

SCL

SDA

VREF

VDDSPD

1

119

120

238

12

25

20222324262527

21

31

149

144

143

DQ<21>

DQ<20>

DQ<19>

DQ<18>

DQ<22>

RC0

SCL

SDA

VREF

VDDSPD

1

119

120

238

150

101

150

101

3

303132333435363738

29

393433

159

158

153

152

80

40

DQ<25>

DQ<26>

DQ<27>

DQ<23>

DQ<24>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

SA2

SA0

SA1

BA1

BA0

CKE1

CKE0

71

52

190

171

240

239

1

31

283029

393433

159

158

153

152

40

DQ<25>

DQ<26>

DQ<27>

DQ<23>

DQ<24>

DQ<30>

DQ<29>

DQ<28>

DQ<31>

DQ<32>

SA2

SA0

SA1

BA1

BA0

CKE1

CKE0

71

52

190

171

240

239

1

199

87

86

206

205

200

81

DQ<34>

DQ<35>

DQ<36>

DQ<37>

DQ<33>

DQ<38>

S0*

S1*

CK1*/RFU

CK2*/RFU

CK2/RFU

76

193

138

137

221

220

01010

333235343637384039

199

206

205

200

87

868180

DQ<34>

DQ<35>

DQ<36>

DQ<37>

DQ<33>

DQ<38>

S0*

S1*

CK1*/RFU

CK2*/RFU

CK2/RFU

76

193

138

137

221

220

23230

39

404142434445464748

89

DQ<42>

DQ<41>

DQ<40>

DQ<39>

CK0

CK1/RFU

CK0*

186

185

42444345474649485051525453

41

89

DQ<42>

DQ<41>

DQ<40>

DQ<39>

CK0

CK1/RFU

CK0*

186

185

CHANNEL B

[PAGE_TITLE=240P CONN DDR2, CH B]

8

7

6

5

4 2

BPAGE DRAWING

frostburg_fabc.sch_1.25

Sun Mar 18 18:43:25 2007

3

2

505152535455565758

49

108

107

99

98

215

214

209

208

969590

DQ<43>

DQ<46>

DQ<47>

DQ<44>

DQ<45>

DQ<50>

DQ<49>

DQ<48>

A2A1A0

60

63

61

17958180

182

183

188

876543210

108

107

99

98

215

214

209

208

969590

DQ<43>

DQ<46>

DQ<47>

DQ<44>

DQ<45>

DQ<50>

DQ<49>

DQ<48>

60

63

61

17958180

182

183

188

876543210

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

63

626160

59

117

116

111

110

227

226

218

217

DQ<52>

DQ<51>

DQ<56>

DQ<53>

DQ<54>

DQ<55>

A10/AP

A13

A12

A11

A9A8A7A6A5A4A3

70

57

196

176

177

13

121110

9

CK_M_DDR0_B_DP
CK_M_DDR0_B_DN
CK_M_DDR1_B_DP
CK_M_DDR1_B_DN
CK_M_DDR2_B_DP

CK_M_DDR2_B_DN
M_SCS_B_N<3..0>
M_SCKE_B<3..0>
M_SBS_B<2..0>

565857

55

110

217

226

218

227

DQ<52>

DQ<51>

DQ<56>

DQ<53>

DQ<54>

DQ<55>

A10/AP

A13

A12

A11A9A8A7A6A5A4A3A2A1A0

70

57

196

176

177

13

121110

9

CK_M_DDR3_B_DP

CK_M_DDR3_B_DN

CK_M_DDR4_B_DP

CK_M_DDR4_B_DN

CK_M_DDR5_B_DP

CK_M_DDR5_B_DN

M_SCS_B_N<3..0>
M_SCKE_B<3..0>
M_SBS_B<2..0>

236

235

230

229

DQ<57>

DQ<58>

DQ<62>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A16/BA2

RAS*

CAS*

74

73

54

192

173

174

M_RAS_B_N

M_CAS_B_N

22

M_SBS_B<2..0>

TP_M_MAA_B15

M_MAA_B<14..0>

5961606362

117

111

116

236

235

230

229

DQ<57>

DQ<58>

DQ<62>

DQ<61>

DQ<60>

DQ<59>

A15

A14

A16/BA2

RAS*

CAS*

74

73

54

192

173

174

M_RAS_B_N

M_CAS_B_N

M_SBS_B<2..0>

TP_M_MAA0_B15

14 14

M_MAA_B<14..0>

DQ<63>

ADDRESS: 010
0A4

J3MY

DDRII_240P

WE*

M_WE_B_N

DQ<63>

ADDRESS: 011

J4MY

0A6

DDRII_240P

WE*

M_WE_B_N

DOCUMENT_NUMBER

xxxxxx

REV

X

X

1

IN
IN
IN

BI

BI
IN
IN
IN
IN
IN
IN
BI
BI
BI

IN
IN

IN

BI

BI
IN
IN
IN
IN
IN
IN
BI
BI
BI

PAGE REV

1

12 25
12 25
12 25

122526

122526
12
12
12
12
12
12

122526

122526

12

12 25
12 25

12 25

122526

122526
12
12
12
12
12
12

122526

122526

12

25

25

25

DATE

D

26
26

C

26

26

B

26
26

26

A

26

3.01

CR-26 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE26

8

14

D

13

12

11

10

9

8

C

7

6

5

4

3

B

2

1

M_MAA_A<14..0>

11

24

IN

11

24

IN

11

24

IN

11

24

A

IN

11

24

IN

0

M_RAS_A_N

M_CAS_A_N

M_WE_A_N

M_SBS_A<2..0>

8

262781

R1MY

CH

R11MY

1

CH

R47MY

1

CH

R54MY

1

CH

R17MY

1

CH

R48MY

1

CH

R22MY

1

CH

R45MY

1

33

CH

R23MY

1

33

CH

R49MY

1

33

CH

R24MY

1

33

CH

R15MY

1

33

CH

R18MY

1

33

CH

R25MY

1

33

CH

R5MY

1

33

CH

R7MY

1

33

CH

R21MY

1

33

CH

R19MY

1

33CH5%

0

2

1

33

33

33

33

33

33

33

1

7

IN

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

5%

402

402

1

33

402

1

33

4025%CH

1

33

402

7

V_SM_VTT

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

R36MY

5%
CH

R6MY

R46MY

5%
CH

6

IN

11

IN

IN

IN

V_SM_VTT

M_SCS_A_N<3..0>

3

2

1

0

M_SCKE_A<3..0>

3

2

1

0

M_ODT_A<3..0>

3

2

1

0

6

R12MY

1

43

CH

R8MY

1

43

CH

R13MY

1

43

CH

R20MY

1

43

CH

R52MY

1

43

CH

R50MY

1

CH43402

R51MY

1

43

CH

R53MY

1

43

CH

R14MY

1

43

CH

R9MY

1

43

CH

R16MY

1

43

CH

R10MY

1

43

CH

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

5

262781

24

11

24

11

24

2

2

2

45

27

81

M_MAA_B<14..0>

12

25

IN

M_RAS_B_N

12

25

IN

M_CAS_B_N

12

25

IN

M_WE_B_N

12

25

IN

M_SBS_B<2..0>

12

25

IN

Sun Mar 18 18:43:30 2007

4 2

3

V_SM_VTT

26

IN

R2MY

14

1

2

5%

33

402

CH

R32MY

1

13

1

12

1

11

1

10

1

9

1

8

R65MY

1

7

CH

R58MY

1

6

CH

R56MY

1

5

CH

R37MY

1

4

33

CH

R38MY

1

3

CH

R39MY

1

2

33

CH
R40MY

1

1

CH

R42MY

1

0

CH

R27MY

1

CH

R28MY

1

CH

R26MY

1

CH

BPAGE DRAWING

frostburg_fabc.sch_1.26

33

CH

R63MY

33

CH

R64MY

CH33402

R41MY

33

CH

R66MY

33

CH

R57MY

33

CH

33

33

33

5%

402

33

33

33

33

33

33

0

1

2

5%

402

5%

402

5%

5%

402

5%

402

5%

402

2

5%

402

2

5%

402

2

5%

402

2

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

2

5%

402

R43MY

1

33

4025%CH

R44MY

1

402

R62MY

1

402

2

2

2

2

2

2

3

81

2

2

5%33
CH

2

5%33
CH

[PAGE_TITLE=DDR VTT TERMINATION]

2

2627

IN

12

25

IN

M_SCKE_B<3..0>

1225

IN

M_ODT_B<3..0>

1225

IN

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

V_SM_VTT

M_SCS_B_N<3..0>

R31MY

3

2

1

0

3

2

1

0

3

2

1

0

1

43

CH

R30MY

1

CH

R35MY

1

43

CH

R29MY

1

43CH5%

R60MY

1

43CH5%

R59MY

1

43CH5%

R55MY

1

43CH5%

R61MY

1

CH

R4MY

1

43CH5%

R3MY

1

43

CH

R34MY

1

43CH5%

R33MY

1

43CH5%

5%

402

5%43

402

5%

402

402

402

402

402

5%43

402

402

5%

402

402

402

DOCUMENT_NUMBER

xxxxxx

REV

2

2

2

2

2

2

2

2

2

2

1

2

2

PAGE REV

1

DATE

D

C

B

A

26

3.01

CR-27 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE27

8

7

6

45

3

DECOUPLING CAPACITORS FOR DDR TERMINATION RESISTORS

8286
25

V_SM_VTT

262781

IN

D

DESIGN NOTE:

CH A V_SM_VTT DECOUPLING CAPS

V_SM_VTT

26

27

81

IN

C

DESIGN NOTE:

CH B V_SM_VTT DECOUPLING CAPS

DESIGN NOTE:

CH A ADDRESS/CONTROL STITCHING CAPS (V_SM_VTT - V_SM)

V_SM_VTT

262781

IN

B

82

82

2425

278081

2425

278081

V_SM

141819

IN

86

DESIGN NOTE:

CH B ADDRESS/CONTROL STITCHING CAPS (V_SM_VTT - V_SM)

V_SM_VTT

262781

IN

V_SM

141819

IN

86

A

V_SM

27

808182

86

1418192425

IN

10.0UF

C63MY

1

6.3V

EMPTY

1206

1

2

1

2

1

2

1

2

2

20%

C40MY

0.1UF
20%

16V
Y5V
402

C51MY

0.1UF
20%
16V
Y5V
402

C42MY

0.1UF
20%

16V
Y5V
402

C28MY

0.1UF
20%

16V
Y5V
402

1

2

1

2

1

2

1

2

C25MY

0.1UF
20%

16V
Y5V
402

C24MY

0.1UF
20%
16V
Y5V
402

C43MY

0.1UF
20%

16V
Y5V
402

C49MY

0.1UF
20%

16V
Y5V
402

1

1

C6MY

0.1UF
20%
16V

2

2

Y5V
402

1

C30MY

0.1UF
20%
16V

2

Y5V
402

1

C23MY

0.1UF
20%
16V

2

Y5V
402

1

C7MY

0.1UF
20%
16V

2

Y5V
402

1

2

1

2

1

2

C41MY

0.1UF
20%
16V
Y5V
402

C22MY

0.1UF
20%
16V
Y5V
402

C32MY

0.1UF
20%
16V
Y5V
402

C44MY

0.1UF
20%
16V
Y5V
402

1

2

1

C26MY

0.1UF
20%

16V

2

Y5V
402

1

C9MY

0.1UF
20%
16V

2

Y5V
402

1

C19MY

0.1UF
20%

16V

2

Y5V
402

1

C53MY

0.1UF
20%

16V

2

Y5V
402

102103105 28

1

2

1

2

70101

C20MY

0.1UF
20%
16V
Y5V
402

1

2

49

C10MY

0.1UF
20%
16V
Y5V
402

C11MY

0.1UF
20%

16V
Y5V
402

C27MY

0.1UF
20%

16V
Y5V
402

1

2

4748

C21MY

0.1UF
20%
16V
Y5V
402

1

2

33

C12MY

0.1UF
20%
16V
Y5V
402

48

1

C29MY

0.1UF
20%
16V

2

Y5V
402

1

C8MY

0.1UF
20%
16V

2

Y5V
402

588892
28

333438

IN

39

4056

57

49

70101
2228
47

2228

SMB_CLK_RESUME

21

IN

33
102103105

SMB_DATA_RESUME

21

IN

DESIGN NOTE:

VCC3

V_3P3_EPW

1

0

402

1

402

R73MY

R74MY

0

UNSTUFF FOR NON-ME SKU

[PAGE_TITLE=DDR VTT DECOUPLING]

8

7

6

5

4 2

27

1418

IN

19

24

80

81

R71MY

1

5%

0

EMPTY

402

R72MY

1

0

5%
CH

402

CAD NOTE:

OVERLAP PAD

2

5%

EMPTY

2

5%

EMPTY

FOR ME SKUSTUFF R73MY AND R74MY

BPAGE DRAWING

frostburg_fabc.sch_1.27

Sun Mar 18 18:43:31 2007

3

V_SM

C14MY

1

1.0UF
10V
Y5V
603

C39MY

1

1.0UF
10V
Y5V
603

C34MY

1

1.0UF
10V
Y5V
603

C18MY

1

1.0UF
10V
Y5V
603

C38MY

1

1.0UF
10V
Y5V
603

2

2

R75MY

1

2

5%

0

CH

402

R76MY

1

2

0

5%
CH

402

DESIGN NOTE:

STUFF FOR NON-ME SKU
UNSTUFF FOR ME SKU

SMB_CLK_MEM

SMB_DATA_MEM

2

C15MY

1

2

1.0UF

20%

20%

20%

20%

20%

10V
Y5V
603

C17MY

1

2

1.0UF
10V
Y5V
603

C35MY

2

1

1.0UF
10V
Y5V
603

C47MY

2

1

1.0UF
10V
Y5V
603

C46MY

2

1

1.0UF
10V
Y5V
603

V_3P3_MEM

C62MY

C61MY

0.1UF

0.1UF
20%

20%

16V

16V

Y5V

Y5V

402

402

SMB_CLK_MAIN

SMB_DATA_MAIN

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

MODULE REV DETAILS

MODULE NAME

C16MY

2

1

2

1.0UF

20%

2

20%

2

20%

2

20%

2

20%

10V
Y5V
603

C13MY

1

1.0UF
10V
Y5V
603

C3MY

1

1.0UF
10V
Y5V
603

C4MY

1

1.0UF
10V
Y5V
603

C36MY

1

1.0UF
10V
Y5V
603

C37MY

1

1.0UF
10V
Y5V
603

24 25

OUT

DESIGN NOTE:

20%

2

20%

2

20%

2

20%

2

20%

2

20%

DEFAULT: STUFF R72MY

28

IN

IN

24 25

OUT

24 25

OUT

DOCUMENT_NUMBER

xxxxxx

REV

70 97

70 97

1

PAGE REV

27

1

DATE

D

C

B

A

3.01

D

BOM NO TE:

EMPTY FOR NON AMT

BOM NO TE:

DUAL FOOTPRINT
FOR C112CK AND C113CK
STUFF ONLY ONE OF THEM

C

88
39
86
89

88
40

33

57

B

33

49

70

102

33

47

A

33
31

CR-28 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE28

8

BW_ATX_CORE

VCC3

SLP_M_CKL_R

1

C113CK

1.0UF
20%
10V

2

EMPTY
603

SLP_M

IN

58

39

27

IN

3438
56
92

7813

277097

102103

2227

277097

101

21

2227

48

4970

103105

IN

1

2

1

2

28

101
21
4748
105

R105CK

1

0

EMPTY

603

V_3P3_STBY\G

C112CK

4.7UF
20%
10V
EMPTY
805

R97CK

0
5%

EMPTY
402

V_3P3_EPW

IN

IN

BI

BI

BI

BI

2

1A

1

G

VDD_CLK_R

CK_PWRGD_R

H_FSBSEL1

SMB_DATA_MAIN

SMB_DATA_RESUME

SMB_CLK_MAIN

SMB_CLK_RESUME

BOM NO TE:

UNSTUFF R105CK FOR NON AMT

R10CK

1

2

0

1A
CH

603

2

Q2CK
EMPTY

S

D

3

R100CK

1

2

0

1A

EMPTY

603

R9CK

2

1

1A

0

EMPTY

603

DESIGN NOTE:

COST SAVING

1

C8CK

4.7UF
20%

16V

2

Y5V

1206

VDD_CLK

28

OUT

R60CK

1

0

402

14.318MHZ

5%
CH

402

R103CK

0

603

0

603

0

603

2

R109CK

402

R110CK

1

0

402

Y1CK

1

R18CK

1

0

202170-024

1

R101CK

1

R102CK

1

1

0

EMPTY

SM

2

C12CK

27PF
5%
50V

1

COG
603

VDD_CLK

28

IN

28

IN

28

IN

CK_14M_ICH

CK_48M_USB_ICH

1

2

1

2

R75CK

47K
5%

CH
402

R76CK

33K
5%

CH
402

2

2

1

1

R77CK

47K
5%

CH
402

R78CK

33K

5%
CH

402

8

603

2

R104CK

1

0

5%
CH

2

1A

CH

1A

CH

1A

CH

5%

EMPTY

2

5%

XTAL

7

2

1A
CH

2

2

2

R12CK

1

1K

402

2

R62CK

0

402

7

1

C10CK

.1UF
10%
16V

2

X7R
603

C13CK

4.7UF
20%
16V
Y5V
1206

C2CK

.1UF
10%
16V
X7R
603

C4CK

.1UF
10%
16V
X7R
603

C1CK

.1UF
10%
16V
X7R
603

2

5%
CH

2

5%
CH

OSC_CK14M_XTALOUT

OSC_CK14M_XTALIN

C11CK

27PF
5%
50V
COG
603

28

IN

33

IN

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

DESIGN NOTE:

BSEL BIASING RES

ALWAYS STUFF

VDD_CK_VDD_PCI

VDD_CK_VDD_48

C9CK

.1UF
10%
16V
X7R
603

VDD_CK_VDD_SRC

C3CK

.1UF
10%
16V
X7R
603

VDD_CK_VDD_CPU

VDD_CK_VDD_REF

SMB_FSBSEL_CK505

SMB_DATA_CK505
SMB_CLK_CK505

DESIGN NOTE:

ENGINEERING

TESTING PURPOSE

R67CK

VDD_CLK

1

0

603

CK_PWRGD

1A

EMPTY

6

2

1K

402

6

VDD_CLK_IO

R98CK

1

2

5%
CH

28

28

28

28

OUT

CK_PWRGD_R

45

7813

IN

7813

IN

28

IN

28

IN

7813

IN

7813

IN

2

9
16
39

55
61

56
57
63

64
59

60

28
29

OUT

402

402

402

4.7K
402

4.7K
402

R71CK

1

0

R72CK

1

1K

R69CK

1

1K

R73CK

1

R70CK

1

H_FSBSEL0

VDD_CLK

VDD_CLK

H_FSBSEL2

H_FSBSEL0

VDD_PCI
VDD_48
VDD_PLL3
VDD_SRC
VDD_CPU
VDD_REF

CKPWRGD/PWRDWN*
FSB/TESTMODE
SDA

SCL
XTAL_OUT

XTAL_IN

1.01

CK505_IO_VOUT_PIN48

28

IN

R2CK

1

2

CK505_IO_VOUT_R

33

5%

1

CH

402

C26CK

100.0PF
5%
50V

2

COG
603

28

402

2

5%

EMPTY

MBT3904DUAL

2

5%
CH

2

5%
CH

MBT3904DUAL

GATE1_FSBSEL2

2

5%
CH

GATE1_FSBSEL0

2

5%
CH

U1CK

CK505_64PIN

REF/FSC/TESTSEL

VDD_CLK

1

R74CK

2

1

5%

0

EMPTY

Q3CK

5

GATE2_FSBSEL2

Q4CK

5

PCIF5/ITP_EN
PCI4/SRC5_EN

PCI1/CR_B*
PCI0/CR_A*

R3CK

1

15
5%

2

CH
805

VDD-CLK_R_3

3

Q1CK

MMBT3904
XSTR

2

VDD_CLK_IO

3

4

3

4

PCI2/LTE

USB/FSA
VSS_PCI

VSS_48

VSS_REF

IO_VOUT

1of 2

CK_FSBSEL2H_FSBSEL2

CK_FSBSEL0

6

1

GATE2_FSBSEL0

6

1

PCI3

28

31

28

30

2868
2869
2853
28103
2848
2849

OUT

[PAGE_TITLE=CK505 PAGE 1 OF 2]

5

4 2

2

XSTR

2

XSTR

62
7

6
5
4
3
1

10
8

11
58

48

IC

IN
IN
IN
IN
IN
IN
IN
IN

28

OUT

OUT

CK_REF_R

CK_PCI5_R
CK_PCI4_R
CK_PCI3_R
CK_PCI2_R
CK_PCI1_R
CK_PCI0_R

CK_USB_R

CK_48M_USB_ICH
CK_P_33M_ICH
CK_P_33M_TPM
CK_P_33M_PA
CK_P_33M_1394
CK_P_33M_S3
CK_P_33M_S1
CK_P_33M_S2

29

3

28

28

VCC3

CAD NOTE:

OVERLAP PADS

1

C20CK

22PF
5%
50V

2

EMPTY
402

BPAGE DRAWING

frostburg_fabc.sch_1.28

Sun Mar 18 18:43:33 2007

3

2

MODULE REV DETAILS

MODULE NAME

STRAP MODE STUFF UNSTUFF

CK505 ATX BLB 9/7/2006

LT ENABLED

LTE

LT DISABLED
ITP ENABLED (SRC8 DISABLED)

ITP_EN

SRC8 ENABLED (ITP DISABLED)
SRC5 ENABLED

SRC5_EN

SCR5 DISABLED

R26CK

1

1

10K

5%

2

2

EMPTY
402

R24CK

1

10K

5%
CH

2

402

R11CK

R15CK

R20CK

R25CK

R17CK

BOM NO TE:

STUFF FOR ATX ONLY

R13CK

2

5%
CH

1

C15CK

22PF
5%
50V

2

EMPTY
402

CUSTOM TEXT BPAGE

R106CK

10K
5%

CH
402

R107CK

10K
5%

EMPTY
402

2

1

5%

1K

CH

402

2

1

5% 22
CH

402

1

2

5%

10

CH

402

2

1

22

5%
CH

402

2

1

5% 22
CH

402

1

1K

402

1

C6CK

22PF
5%
50V

2

EMPTY
402

CONFIDENTIAL

1

2

1

2

INTEL

R4CK

10K

5%
CH

402

R5CK

10K

5%
EMPTY

402

R14CK

2

R19CK

2

5%
CH

EMPTY

R22CK

2

5%
CH

1

2

R65CK

1

10K

5%

2

CH
402

DO NOT STUB OFF MORE THEN 250 MILS

R66CK

1

10K

5%
EMPTY

2

402

1

22CH5%

402

1

10

402

R21CK

2

1

5%

22

402

R23CK

2

1

22

5%
CH

402

R16CK

2

1

22

5%
CH

402

1

33

402

1

C7CK

C18CK

10PF

10PF

5%

5%

50V

50V

2

EMPTY

EMPTY
402

402

DOCUMENT_NUMBER

0.0.1

R65CK
R66CK
R26CK
R24CK

R5CK

CK_FSBSEL2

CK_14M_PA

CK_14M_ICH

CK_P_33M_ICH

CK_P_33M_1394

CK_P_33M_TPM

CK_P_33M_S2

CK_P_33M_S1

CK_P_33M_S3

CK_P_33M_PA

CK_48M_USB_ICH

CK_FSBSEL0

1

C17CK

10PF
5%
50V

2

EMPTY
402

xxxxxx

REV

R66CK
R65CK
R24CK
R26CK
R5CKR4CK
R4CK

CAD NOTE:

1

2

1

OUT

OUT

OUT

OUT

OUT

OUT

C14CK

10PF
5%
50V
EMPTY
402

PAGE REV

28

1

OUT

OUT

OUT

OUT

IN

DATE

D

C

28

IN

69

28

33

28

30

28 53

28 68

28 49

B

28 48

28 103

28 69

28

31

28

A

1

C16CK

10PF
5%
50V

2

EMPTY
402

3.01

BW_ATX_CORE

CR-29 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE29

8

7

6

45

3

2

MODULE REV DETAILS

MODULE NAME

CK505 ATX BLB 9-7-2006

0.0.1

1

REV

DATE

D

C

DESIGN NOTE:

STUFF C104CK AND C110CK
FOR 64 PINS CLOCK ONLY

1

2

B

A

C104CK

.1UF
20%
50V
X7R
805

1

2

47

97

47

97

8

28

C110CK

.1UF
20%
50V
X7R
805

OUT

OUT

OUT

OUT

IN

CK_H_XDP_DN

CK_H_XDP_DP

VDD_CLK_IO

CAD NOTE:

1

C105CK

.1UF
20%
50V

2

X7R
805

CK_1PORT_S1_DN

CK_1PORT_S1_DP

OUT

OUT

OUT

OUT

CK_H_MCH_DN

CK_H_MCH_DP

CK_H_CPU_DN

CK_H_CPU_DP

10

10

6

6

CAD NOTE:

1

C102CK
10UF
20%

6.3V

2

X5R
805

CK505 VDD_*_IO DCPL: PLACE (1) PER PIN

1

C106CK

.1UF
20%
50V

2

X7R
805

5%
CH

CK505 VDD_*_IO BULK DCPL: PLACE AROUND CK505

1

1

1

2

1

2

R27CK

1

R7CK

1

2

33

402

402

402

33

402

C108CK

10UF

20%

6.3V
X5R
805

C103CK

.1UF
20%
50V
X7R
805

2

33CH5%

402

R37CK

1

33

402

1

33

402

R35CK

1

33

R36CK

1

33

402

R33CK

1

33

R34CK

1

EMPTY

R30CK

5%
CH

C109CK

10UF

20%

6.3V

2

X5R
805

1

C100CK

.1UF
20%
50V

2

X7R
805

CK_PE_SRC8_R_DN

2

5%

CK_PE_SRC8_R_DP

2

5%

EMPTY

2

CK_H_MCH_R_DN

5%
CH

2

CK_H_MCH_R_DP

5%
CH

2

CK_H_CPU_R_DN

5%
CH

2

CK_H_CPU_R_DP

2

1

2

7

C111CK

10UF

20%

6.3V
X5R
805

C21CK

.1UF
10%

16V
X7R
603

D

101

101

102

102

21

22

C

21

22

10

10

33

33

98

98

31

B

31

32

32

53

98

56

A

13

17

13

17

12
20
26
45
49

36
46

47
50

51
53

54

15

19
23
42
52
29

VDD_IO
VDD_PLL3_IO
VDD_SRC_IO
VDD_SRC_IO
VDD_CPU_IO
VDD_SRC_IO

SRC8-/ITP­SRC8+/ITP+

CPU1­CPU1+

CPU0­CPU0+

VSS_IO
VSS_PLL3
VSS_SRC
VSS_SRC
VSS_CPU
VSS_SRC

1.01

U1CK

CK505_64PIN

64 PIN
PART ONLY

CPU_STOP*/SRC5­PCI_STOP*/SRC5+

SRC11-/CR_G*
SRC11+/CR_H*

SRC10­SRC10+

SRC9­SRC9+

SRC7-/CR_E*
SRC7+/CR_F*

SRC6­SRC6+

SRC4­SRC4+

SRC3-/CR_D*
SRC3+/CR_C*

SRC2-/SATA­SRC2+/SATA+

SRC1-/SE2
SRC1+/SE1

SRC0-/DOT96­SRC0+/DOT96+

2of 2

R90CK

2

CK_PE_SRC11_R_DN

CK_PE_SRC11_R_DP

CK_PE_SRC10_R_DN

CK_PE_SRC10_R_DP

CK_PE_SRC9_R_DN

CK_PE_SRC9_R_DP

CK_PE_SRC7_R_DN

CK_PE_SRC7_R_DP

32
33

35
34

31
30

43
44

40
41

37
38

28
27

25
24

22
21

18
17

14
13

CK_PE_SRC6_R_DN

CK_PE_SRC6_R_DP

CK_PE_SRC5_R_DN

CK_PE_SRC5_R_DP

CK_PE_SRC4_R_DN

CK_PE_SRC4_R_DP

CK_PE_SRC3_R_DN

CK_PE_SRC3_R_DP

CK_PE_SRC2_R_DN

CK_PE_SRC2_R_DP

CK_PE_SRC1_R_DP

CK_PE_SRC1_R_DN

IC

CK_96M_DOT_R_DN

CK_96M_DOT_R_DP

DESIGN NOTE:

96M DOT CLOCK SIGNALS: STUFF 33 OHM RES STRAPS FOR MCH GRAPHIC SKU'S
EMPTY 33 OHM SITES FOR MCH NON-GRAPHIC SKU'S

5%

EMPTY

R92CK

2

5%
CH

R94CK

2

5%
CH

R31CK

2

5%
CH

R45CK

2

5%
CH

R49CK

2

5%

EMPTY

R53CK

2

5%
CH

R52CK

5%
CH

R51CK

2

5%
CH

R41CK

2

5%

EMPTY

R39CK

2

5%
CH

R42CK

2

5%
CH

1

33

402

R91CK

2

5%

EMPTY

1

33

402

R93CK

2

5%
CH

1

33

402

R95CK

2

5%
CH

1

33

402

R32CK

2

5%
CH

1

33

402

R46CK

2

5%
CH

1

1K

402

R43CK

2

5%

EMPTY

1

33

402

R48CK

2

5%
CH

1332

402

R50CK

2

5%
CH

1

33

402

R38CK

2

5%
CH

1

33

402

1

33

402

R108CK

2

5% 22

EMPTY

1

33

402

R40CK

2

5%
CH

CK_PE_100M_LAN_2_DN

1

CK_PE_100M_LAN_2_DP

33

402

CK_1PORT_S2_DN

CK_1PORT_S2_DP

1

33

402

1

33

402

CK_PE_100M_16PORT_DN

1

CK_PE_100M_16PORT_DP

33

402

1

33

402

1

1K

402

CK_PE_100M_PATA_DN

CK_PE_100M_PATA_DP

1

33

402

1

33

402

1

33

402

1

402

1

33

402

CK_1PORT_S3_DN

CK_1PORT_S3_DP

CK_PE_100M_MCH_DN

CK_PE_100M_MCH_DP

CK_CPU_STOP_N

CK_PCI_STOP_N

CK_PE_100M_ICH_DN

CK_PE_100M_ICH_DP

CK_ICHSATA_DN

CK_ICHSATA_DP

CK_XT_24M_1394

CK_XT_25M_PATA

CK_XT_25M_LAN

CK_96M_DREF_DN

CK_96M_DREF_DP

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

[PAGE_TITLE=CK505 PAGE 2 OF 2]

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3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

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PAGE REV

29

1

3.01

CR-30 : @FROSTBURG_FABC_LIB.FROSTBURG_FABC(SCH_1):PAGE30

8

D

C

B

7

53103106

103

103

6

U1LB

ICH9

P_PAR

484953103106

BI

P_DEVSEL_N

48495053103106

BI

CK_P_33M_ICH

28

IN

P_PCIRST_N

484953103106

OUT

P_IRDY_N

48495053103106

OUT

P_PME_N

484953103

BI

P_SERR_N

48495053103

BI

P_STOP_N

48495053103106

BI

P_PLOCK_N

484950103

BI

P_TRDY_N

48495053103106

BI

P_PERR_N

48495053103

BI

P_FRAME_N

48495053103106

BI

P_GNT_N<3..0>

36

484953103106

OUT

P_REQ_N<3..0>

4849

50

IN

P_INTA_N

50103

IN

P_INTB_N

50103

IN

P_INTC_N

50103106

IN

P_INTD_N

5053103

IN

50
50
50
50

P_INTE_N

4849

IN

P_INTF_N

4849

IN

P_INTG_N

4849

IN

P_INTH_N

4849

IN

E3

PAR

C6

DEVSEL#

B3

PCICLK

R2

PCIRST#

J8

IRDY#

R3

PME#

K5

SERR#

F10

STOP#

H8

PLOCK#

E6

TRDY#
PERR#
FRAME#

GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55

REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

PCI

C/BE0#
C/BE1#
C/BE2#
C/BE3#

1OF6

F5

G12

0

H5

1

A7

2

C7

3

F7

K7

0

G13

1

F13

2

G8

3

J5
E1
F1
A3
K6
L7
F2 F11
G2

REV=1.00

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

45

P_AD<31..0>

C10

0

C8

1

E9

2

C9

3

A5

4
5

E12

6

E10
B7

7

B6

8

B4

9

E7

10

A4

11

H12

12

F8

13
14

C5
D2

15

E5

16
17

G7

18

E11
G10

19

G6

20

D3

21

H6

22

G5

23
24

C1
C2

25
26

C3
D1

27

J7

28

F3

29

G1

30

H3

31

P_C/BE_N<3..0>

0
1

G9

2

C4
E8

3

IC

3

BI

BI

48 49 53 103 106

48 49 53 103 106

2

MODULE REV DETAILS

MODULE NAME

ICH9

0.2.1

1

REV

DATE

08/30/06

D

C

B

J1LB

ICH6_HSK

NC_2

NC_3

C46655-001

IC

J2LB

1

A13494-008

2
3

A

HDR

1

NC_1

4

NC_4

NOTE:
NO PHYSICAL PINS

A

ON ALLEGRO MODEL

J3LB

1

NC NC

HDR

A13494-008

[PAGE_TITLE= ICH9 1 0F 6 CONTROL]

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Sun Mar 18 18:43:35 2007

8

7

6

5

4 2

3

INTEL

CONFIDENTIAL

CUSTOM TEXT BPAGE

DOCUMENT_NUMBER

xxxxxx

PAGE REV

30

1

3.01