Intel CORE PROCESSOR FAMILY MOBILE User Manual
2nd Generation Intel® Core™
Processor Family Mobile
Datasheet – Volume 1
Supporting Intel® Core™ i7 Mobile Extreme Edition Processor Series and
®
Intel
This is Volume 1 of 2
January 2011
Core™ i5 and i7 Mobile Processor Series
Document Number: 324692-001
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Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor,
an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing
®
Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code
®
Trusted Execution Technology (Intel® TXT) requires
Group and specific software for some uses. For more information, see http://www.intel.com/technology/security/
®
Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor
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®
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platform-technology/intel-amt/
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Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
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Copyright © 2011, Intel Corporation. All rights reserved.
2 Datasheet, Volume 1
Contents
1Introduction............................................................................................................ 11
1.1 Processor Feature Details ................................................................................... 13
1.1.1 Supported Technologies .......................................................................... 13
1.2 Interfaces ........................................................................................................ 13
1.2.1 System Memory Support ......................................................................... 13
1.2.2 PCI Express* ......................................................................................... 14
1.2.3 Direct Media Interface (DMI).................................................................... 15
1.2.4 Platform Environment Control Interface (PECI)........................................... 16
1.2.5 Processor Graphics ................................................................................. 16
1.2.6 Embedded DisplayPort* (eDP*)................................................................ 17
1.2.7 Intel
1.3 Power Management Support ............................................................................... 17
1.3.1 Processor Core....................................................................................... 17
1.3.2 System ................................................................................................. 17
1.3.3 Memory Controller.................................................................................. 17
1.3.4 PCI Express* ......................................................................................... 17
1.3.5 DMI...................................................................................................... 17
1.3.6 Processor Graphics Controller................................................................... 18
1.4 Thermal Management Support ............................................................................ 18
1.5 Package ........................................................................................................... 18
1.6 Terminology ..................................................................................................... 18
1.7 Related Documents ........................................................................................... 21
2Interfaces................................................................................................................ 23
2.1 System Memory Interface .................................................................................. 23
2.1.1 System Memory Technology Supported ..................................................... 23
2.1.2 System Memory Timing Support............................................................... 24
2.1.3 System Memory Organization Modes......................................................... 24
2.1.4 Rules for Populating Memory Slots............................................................ 25
2.1.5 Technology Enhancements of Intel
2.1.6 Memory Type Range Registers (MTRRs) Enhancement................................. 26
2.1.7 Data Scrambling .................................................................................... 26
2.1.8 DRAM Clock Generation........................................................................... 26
2.2 PCI Express* Interface....................................................................................... 27
2.2.1 PCI Express* Architecture ....................................................................... 27
2.2.2 PCI Express* Configuration Mechanism ..................................................... 29
2.2.3 PCI Express Graphics.............................................................................. 29
2.2.4 PCI Express Lanes Connection.................................................................. 30
2.3 Direct Media Interface (DMI)............................................................................... 30
2.3.1 DMI Error Flow....................................................................................... 30
2.3.2 Processor/PCH Compatibility Assumptions.................................................. 30
2.3.3 DMI Link Down ...................................................................................... 31
2.4 Processor Graphics Controller (GT) ...................................................................... 31
®
Flexible Display Interface (Intel® FDI) ............................................. 17
2.1.3.1 Single-Channel Mode................................................................. 24
2.1.3.2 Dual-Channel Mode – Intel
2.1.5.1 Just-in-Time Command Scheduling.............................................. 26
2.1.5.2 Command Overlap .................................................................... 26
2.1.5.3 Out-of-Order Scheduling............................................................ 26
2.2.1.1 Transaction Layer ..................................................................... 28
2.2.1.2 Data Link Layer ........................................................................ 28
2.2.1.3 Physical Layer .......................................................................... 28
®
Flex Memory Technology Mode ........... 24
®
Fast Memory Access (Intel® FMA).......... 26
Datasheet, Volume 1 3
2.4.1 3D and Video Engines for Graphics Processing ............................................32
2.4.1.1 3D Engine Execution Units..........................................................32
2.4.1.2 3D Pipeline...............................................................................32
2.4.1.3 Video Engine ............................................................................33
2.4.1.4 2D Engine ................................................................................33
2.4.2 Processor Graphics Display ......................................................................34
2.4.2.1 Display Planes ..........................................................................34
2.4.2.2 Display Pipes ............................................................................35
2.4.2.3 Display Ports ............................................................................35
2.4.2.4 Embedded DisplayPort (eDP) ......................................................35
2.4.3 Intel Flexible Display Interface..................................................................35
2.4.4 Multi-Graphics Controller Multi-Monitor Support ..........................................36
2.5 Platform Environment Control Interface (PECI) ......................................................36
2.6 Interface Clocking..............................................................................................36
2.6.1 Internal Clocking Requirements ................................................................36
3 Technologies............................................................................................................37
3.1 Intel® Virtualization Technology ..........................................................................37
3.1.1 Intel® VT-x Objectives ............................................................................37
3.1.2 Intel® VT-x Features...............................................................................38
3.1.3 Intel
®
VT-d Objectives ............................................................................38
3.1.4 Intel® VT-d Features...............................................................................39
3.1.5 Intel® VT-d Features Not Supported..........................................................39
®
3.2 Intel
Trusted Execution Technology (Intel® TXT) .................................................40
3.3 Intel® Hyper-Threading Technology .....................................................................40
3.4 Intel® Turbo Boost Technology ............................................................................41
3.4.1 Intel
®
Turbo Boost Technology Frequency...................................................41
3.4.2 Intel® Turbo Boost Technology Graphics Frequency.....................................42
3.5 Intel® Advanced Vector Extensions (AVX) .............................................................42
3.6 Advanced Encryption Standard New Instructions (AES-NI) ......................................42
3.6.1 PCLMULQDQ Instruction ..........................................................................43
®
3.7 Intel
64 Architecture x2APIC .............................................................................43
4 Power Management .................................................................................................45
4.1 ACPI States Supported .......................................................................................45
4.1.1 System States........................................................................................45
4.1.2 Processor Core/Package Idle States...........................................................45
4.1.3 Integrated Memory Controller States.........................................................46
4.1.4 PCIe Link States .....................................................................................46
4.1.5 DMI States ............................................................................................46
4.1.6 Processor Graphics Controller States .........................................................46
4.1.7 Interface State Combinations ...................................................................47
4.2 Processor Core Power Management......................................................................48
4.2.1 Enhanced Intel
®
SpeedStep® Technology ..................................................48
4.2.2 Low-Power Idle States.............................................................................48
4.2.3 Requesting Low-Power Idle States ............................................................50
4.2.4 Core C-states .........................................................................................51
4.2.4.1 Core C0 State ...........................................................................51
4.2.4.2 Core C1/C1E State ....................................................................51
4.2.4.3 Core C3 State ...........................................................................51
4.2.4.4 Core C6 State ...........................................................................51
4.2.4.5 Core C7 State ...........................................................................51
4.2.4.6 C-State Auto-Demotion..............................................................52
4.2.5 Package C-States ...................................................................................52
4.2.5.1 Package C0 ..............................................................................53
4.2.5.2 Package C1/C1E........................................................................54
4.2.5.3 Package C3 State ......................................................................54
4 Datasheet, Volume 1
4.2.5.4 Package C6 State...................................................................... 54
4.2.5.5 Package C7 State...................................................................... 55
4.2.5.6 Dynamic L3 Cache Sizing ........................................................... 55
4.3 IMC Power Management..................................................................................... 55
4.3.1 Disabling Unused System Memory Outputs ................................................ 55
4.3.2 DRAM Power Management and Initialization............................................... 56
4.3.2.1 Initialization Role of CKE............................................................ 57
4.3.2.2 Conditional Self-Refresh ............................................................ 57
4.3.2.3 Dynamic Power-down Operation ................................................. 58
4.3.2.4 DRAM I/O Power Management.................................................... 58
4.4 PCIe* Power Management .................................................................................. 58
4.5 DMI Power Management..................................................................................... 58
4.6 Graphics Power Management .............................................................................. 59
4.6.1 Intel
®
Rapid Memory Power Management (RMPM) (also know as CxSR)......... 59
4.6.2 Intel® Graphics Performance Modulation Technology(GPMT) ........................ 59
4.6.3 Graphics Render C-State ......................................................................... 59
4.6.4 Intel
®
Smart 2D Display Technology (Intel® S2DDT) .................................. 59
4.6.5 Intel® Graphics Dynamic Frequency.......................................................... 60
4.6.6 Display Power Savings Technology 6.0 (DPST) ........................................... 60
4.6.7 Automatic Display Brightness (ADB) ......................................................... 60
4.6.8 Seamless Display Refresh Rate Switching Technology (SDRRST)................... 61
4.7 Thermal Power Management............................................................................... 61
5 Thermal Management.............................................................................................. 63
5.1 Thermal Design Power (TDP) and Junction Temperature (Tj) ................................... 63
5.2 Thermal Considerations...................................................................................... 63
5.2.1 Intel
®
Turbo Boost Technology Power Control and Reporting........................ 64
5.2.2 Package Power Control............................................................................ 65
5.2.3 Power Plane Control................................................................................ 65
5.2.4 Turbo Time Parameter ............................................................................ 65
5.3 Thermal and Power Specifications........................................................................ 66
5.4 Thermal Management Features ........................................................................... 70
5.4.1 Processor Package Thermal Features......................................................... 70
5.4.1.1 Adaptive Thermal Monitor .......................................................... 70
5.4.1.2 Digital Thermal Sensor .............................................................. 72
5.4.1.3 PROCHOT# Signal..................................................................... 73
5.4.2 Processor Core Specific Thermal Features.................................................. 75
5.4.2.1 On-Demand Mode..................................................................... 75
5.4.3 Memory Controller Specific Thermal Features ............................................. 76
5.4.3.1 Programmable Trip Points .......................................................... 76
5.4.4 Platform Environment Control Interface (PECI)........................................... 76
5.4.4.1 Fan Speed Control with Digital Thermal Sensor ............................. 76
6 Signal Description ................................................................................................... 77
6.1 System Memory Interface .................................................................................. 78
6.2 Memory Reference and Compensation.................................................................. 79
6.3 Reset and Miscellaneous Signals.......................................................................... 80
6.4 PCI Express* Based Interface Signals................................................................... 80
6.5 Embedded DisplayPort (eDP) .............................................................................. 81
6.6 Intel
®
Flexible Display Interface Signals ............................................................... 81
6.7 DMI................................................................................................................. 81
6.8 PLL Signals....................................................................................................... 82
6.9 TAP Signals ...................................................................................................... 82
6.10 Error and Thermal Protection .............................................................................. 83
6.11 Power Sequencing ............................................................................................. 83
6.12 Processor Power Signals..................................................................................... 84
Datasheet, Volume 1 5
6.13 Sense Pins........................................................................................................84
6.14 Ground and NCTF ..............................................................................................85
6.15 Future Compatibility...........................................................................................85
6.16 Processor Internal Pull Up/Pull Down ....................................................................85
7 Electrical Specifications ...........................................................................................87
7.1 Power and Ground Pins.......................................................................................87
7.2 Decoupling Guidelines ........................................................................................87
7.2.1 Voltage Rail Decoupling ...........................................................................87
7.2.2 PLL Power Supply ...................................................................................87
7.3 Voltage Identification (VID).................................................................................88
7.4 System Agent (SA) V
VID ................................................................................92
CC
7.5 Reserved or Unused Signals ................................................................................92
7.6 Signal Groups ...................................................................................................93
7.7 Test Access Port (TAP) Connection .......................................................................95
7.8 Storage Condition Specifications ..........................................................................95
7.9 DC Specifications...............................................................................................96
7.9.1 Voltage and Current Specifications ............................................................97
7.10 Platform Environmental Control Interface (PECI) DC Specifications ......................... 103
7.10.1 PECI Bus Architecture............................................................................103
7.10.2 PECI DC Characteristics ......................................................................... 104
7.10.3 Input Device Hysteresis ......................................................................... 105
8 Processor Pin and Signal Information .................................................................... 107
8.1 Processor Pin As signments...............................................................................107
8.2 Package Mechanical Information ........................................................................ 157
9 DDR Data Swizzling................................................................................................169
6 Datasheet, Volume 1
Figures
1-1 2nd Generation Intel® Core™ Extreme Edition Processor Family Mobile
Platform ................................................................................................................ 12
2-1 Intel
2-2 PCI Express* Layering Diagram ................................................................................ 27
2-3 Packet Flow through the Layers ................................................................................ 28
2-4 PCI Express* Related Register Structures in the Processor............................................ 29
2-5 PCIe Typical Operation 16 lanes Mapping ................................................................... 30
2-6 Processor Graphics Controller Unit Block Diagram ....................................................... 31
2-7 Processor Display Block Diagram............................................................................... 34
4-1 Idle Power Management Breakdown of the Processor Cores .......................................... 49
4-2 Thread and Core C-State Entry and Exit..................................................................... 49
4-3 Package C-State Entry and Exit ................................................................................ 53
5-1 Package Power Control ............................................................................................ 65
5-2 Frequency and Voltage Ordering ............................................................................... 71
7-1 Example for PECI Host-clients Connection ................................................................ 104
7-2 Input Device Hysteresis ......................................................................................... 105
8-1 rPGA988B (Socket-G2) Pinmap (Top View, Upper-Left Quadrant) ................................ 108
8-2 rPGA988B (Socket-G2) Pinmap (Top View, Upper-Right Quadrant) .............................. 109
8-3 rPGA988B (Socket-G2) Pinmap (Top View, Lower-Left Quadrant) ................................ 110
8-4 rPGA988B (Socket-G2) Pinmap (Top View, Lower-Right Quadrant) .............................. 111
8-5 BGA1224 Ballmap (Top View, Upper-Left Quadrant) .................................................. 123
8-6 BGA1224 Ballmap (Top View, Upper-Right Quadrant) ................................................ 124
8-7 BGA1224 Ballmap (Top View, Lower-Left Quadrant) .................................................. 125
8-8 BGA1224 Ballmap (Top View, Lower-Right Quadrant) ................................................ 126
8-9 BGA1023 Ballmap (Top View, Upper-Left Quadrant) .................................................. 142
8-10 BGA1023 Ballmap (Top View, Upper-Right Quadrant) ................................................ 143
8-11 BGA1023 Ballmap (Top View, Lower-Left Quadrant) .................................................. 144
8-12 BGA1023 Ballmap (Top View, Lower-Right Quadrant) ................................................ 145
8-13 Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 1 of 2) ............................... 157
8-14 Processor rPGA988B 2C (GT2) Mechanical Package (Sheet 2 of 2) ............................... 158
8-15 Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 1 of 2) ............................... 159
8-16 Processor rPGA988B 4C (GT2) Mechanical Package (Sheet 2 of 2) ............................... 160
8-17 Processor BGA1023 2C (GT2) Mechanical Package (Sheet 1 of 2) ................................ 161
8-18 Processor BGA1023 2C (GT2) Mechanical Package (Sheet 2 of 2) ................................ 162
8-19 Processor BGA1224 4C (GT2) Mechanical Package (Sheet 1 of 2) ................................ 163
8-20 Processor BGA1224 4C (GT2) Mechanical Package (Sheet 2 of 2) ................................ 164
8-21 Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 1 of 2) ............................... 165
8-22 Processor rPGA988B 2C (GT1) Mechanical Package (Sheet 2 of 2) ............................... 166
8-23 Processor BGA1023 2C (GT1) Mechanical Package (Sheet 1 of 2) ................................ 167
8-24 Processor BGA1023 2C (GT1) Mechanical Package (Sheet 2 of 2) ................................ 168
®
Flex Memory Technology Operation ................................................................. 25
Datasheet, Volume 1 7
Tables
1-1 PCIe Supported Configurations in Mobile Products.......................................................14
1-2 Related Documents.................................................................................................21
2-1 Supported SO-DIMM Module Configurations 1,2 ..........................................................23
2-2 DDR3 System Memory Timing Support ......................................................................24
2-3 Reference Clock......................................................................................................36
4-1 System States........................................................................................................45
4-2 Processor Core/Package State Support ......................................................................45
4-3 Integrated Memory Controller States.........................................................................46
4-4 PCIe Link States .....................................................................................................46
4-5 DMI States ............................................................................................................46
4-6 Processor Graphics Controller States .........................................................................46
4-7 G, S, and C State Combinations................................................................................47
4-8 D, S, and C State Combination .................................................................................47
4-9 Coordination of Thread Power States at the Core Level ................................................50
4-10 P_LVLx to MWAIT Conversion...................................................................................50
4-11 Coordination of Core Power States at the Package Level ..............................................53
4-12 Targeted Memory State Conditions............................................................................58
5-1 TDP Specifications ..................................................................................................67
5-2 Junction Temperature Specification ...........................................................................67
5-3 Package Turbo Parameters.......................................................................................68
5-4 Idle Power Specifications .........................................................................................69
6-1 Signal Description Buffer Types ................................................................................77
6-2 Memory Channel A..................................................................................................78
6-3 Memory Channel B..................................................................................................79
6-4 Memory Reference and Compensation .......................................................................79
6-5 Reset and Miscellaneous Signals ...............................................................................80
6-6 PCI Express* Graphics Interface Signals ....................................................................80
6-7 Embedded Display Port Signals.................................................................................81
6-8 Intel® Flexible Display Interface...............................................................................81
6-9 DMI - Processor to PCH Serial Interface .....................................................................81
6-10 PLL Signals ............................................................................................................82
6-11 TAP Signals............................................................................................................82
6-12 Error and Thermal Protection....................................................................................83
6-13 Power Sequencing ..................................................................................................83
6-14 Processor Power Signals ..........................................................................................84
6-15 Sense Pins.............................................................................................................84
6-16 Ground and NCTF ...................................................................................................85
6-17 Future Compatibility................................................................................................85
6-18 Processor Internal Pull Up/Pull Down .........................................................................85
7-1 IMVP7 Voltage Identification Definition ......................................................................89
7-2 VCCSA_VID configuration ........................................................................................92
7-3 Signal Groups1.......................................................................................................93
7-4 Storage Condition Ratings........................................................................................96
7-5 Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications ..........97
7-6 Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications .......................98
7-7 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications ......................99
7-8 System Agent (VCCSA) Supply DC Voltage and Current Specifications ...........................99
7-9 Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications...........................99
7-10 Processor Graphics (VAXG) Supply DC Voltage and Current Specifications .................... 100
7-11 DDR3 Signal Group DC Specifications ......................................................................101
7-12 Control Sideband and TAP Signal Group DC Specifications ..........................................102
7-13 PCI Express DC Specifications ................................................................................102
7-14 eDP DC Specifications ...........................................................................................103
8 Datasheet, Volume 1
7-15 PECI DC Electrical Limits ....................................................................................... 104
8-1 rPGA988B Processor Pin List by Pin Name................................................................ 112
8-2 BGA1224 Processor Ball List by Ball Name ............................................................... 127
8-3 BGA1023 Processor Ball List by Ball Name ............................................................... 146
9-1 DDR Data Swizzling Table – Channel A.................................................................... 170
9-2 DDR Data Swizzling Table – Channel B.................................................................... 171
Datasheet, Volume 1 9
Revision History
Revision
Number
001 • Initial Release January 2011
Description Date
§ §
10 Datasheet, Volume 1
Introduction
1 Introduction
The 2nd Generation Intel® Core™ processor family mobile is the next generation of 64bit, multi-core mobile processor built on 32- nanometer process technology. Based on a
new micro-architecture, the processor is designed for a two-chip platform. The twochip platform consists of a processor and Platform Controller Hub (PCH). The platform
enables higher performance, lower cost, easier validation, and improved x-y footprint.
The processor includes Integrated Display Engine, Processor Graphics and Integrated
Memory Controller and is designed for mobile platforms. The processor comes with
either 6 or 12 Processor Graphics execution units (EU). The processor may be offered in
a rPGA988B, BGA1224 or BGA1023 package. Figure 1-1 shows an example platform
block diagram.
This document provides DC electrical specifications, signal integrity, differential
signaling specifications, pinout and signal definitions, interface functional descriptions,
thermal specifications, and additional feature information pertinent to the
implementation and operation of the processor on its respective platform.
Note: Throughout this document, the 2nd Generation Intel
®
Core™ processor family mobile
may be referred to simply as “processor”.
Note: Throughout this document, the Intel
series refers to the Intel
Note: Throughout this document, the Intel
Note: Throughout this document, the Intel
®
Intel
Core™ i7-2820QM, i7-2720QM, and i7-2620M processors.
®
Core™ i5-2540M and i5-2520M processors.
Intel
®
Core™ i7-2920XM processor.
Note: Throughout this document, the Intel
®
Core™ i7 Extreme Edition mobile processor
®
Core™ i7 mobile processor series refers to the
®
Core™ i5 mobile processor series refers to the
®
6 Series Chipset Platform Controller Hub may
also be referred to as “PCH”.
Note: Throughout this document, 2nd Generation Intel
®
Core™ processor family desktop
may be referred to as simply the processor.
Note: Some processor features are not available on all platforms. Refer to the processor
specification update for details.
Datasheet, Volume 1 11
Introduction
I
n
t
e
l
®
F
l
e
x
i
b
l
e
D
i
s
p
l
a
y
I
n
t
e
r
f
a
c
e
DMI2 x4
Discrete Graphics
(PEG)
Analog CR T
G igabit
Network C onnection
USB 2.0
Intel® HD Audio
FWH
Super I/ O
Serial ATA
DDR3
PC I Express* 2.0
1 x16 or 2x 8
8 PCI Expr es s* 2.0 x 1
Ports
(5 G T/s)
SPI
Dig ital Dis p lay x 3
PC I Express*
SPI Flash x 2
LPC
SMBUS 2 .0
GPI O
LVDS Flat Panel
WiFi / WiMax
C ontroller Link 1
Em bedded Display
Port
Processor
PEC I
Platform
Controller
Hub (PCH)
Intel®
Management
Engine
Figure 1-1. 2nd Generation Intel® Core™ Extreme Edition Processor Family Mobile
Platform
12 Datasheet, Volume 1
Introduction
1.1 Processor Feature Details
• Four or two execution cores
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data second-level cache (L2) for each core
• Up to 8-MB shared instruction/data third-level cache (L3), shared among all cores
1.1.1 Supported Technologies
•Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
•Intel® Virtualization Technology (Intel® VT-x)
•Intel® Active Management Technology 7.0 (Intel® AMT 7.0)
•Intel® Trusted Execution Technology (Intel® TXT)
•Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
•Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
•Intel® Hyper-Threading Technology
•Intel® 64 Architecture
• Execute Disable Bit
•Intel® Turbo Boost Technology
•Intel® Advanced Vector Extensions (Intel® AVX)
• Advanced Encryption Standard New Instructions (AES-NI)
• PCLMULQDQ Instruction
1.2 Interfaces
1.2.1 System Memory Support
• Two channels of DDR3 memory with a maximum of one SO-DIMM per channel
• Single-channel and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory DDR3 data transfer rates of 1066 MT/s, 1333 MT/s, and 1600 MT/s
• 64-bit wide channels
• DDR3 I/O Voltage of 1.5 V
• Non-ECC, unbuffered DDR3 SO-DIMMs only
• Theoretical maximum memory bandwidth of
— 17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s
— 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s
• 1Gb, 2Gb, and 4Gb DDR3 DRAM technologies are supported for x8 and x16
devices.
— Using 4Gb device technologies, the largest memory capacity possible is 16 GB,
assuming dual-channel mode with two x8, dual-ranked, un-buffered, non-ECC,
SO-DIMM memory configuration.
Datasheet, Volume 1 13
• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
• Memory organizations
— Single-channel modes
— Dual-channel modes - Intel® Flex Memory Technology:
- Dual-channel symmetric (Interleaved)
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Asynchronous ODT
•Intel® Fast Memory Access (Intel® FMA)
— Just-in-Time Command Scheduling
—Command Overlap
— Out-of-Order Scheduling
1.2.2 PCI Express*
• The PCI Express* port(s) are fully-compliant to the PCI Express Base Specification,
Revision 2.0.
Table 1-1. PCIe Supported Configurations in Mobile Products
• Processor with mobile PCH supported configurations
Introduction
Configuration Mobile
1x8
2x4
2x8
1x16
GFX,
I/O
GFX,
I/O
GFX,
I/O
• The port may negotiate down to narrower widths
— Support for x16/x8/x4/x1 widths for a single PCI Express mode
• 2.5 GT/s and 5.0 GT/s PCI Express* frequencies are supported
• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1
• Gen 2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s when x16 Gen 2
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
14 Datasheet, Volume 1
Introduction
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism; accessing the device configuration
space in a flat memory mapped fashion
• Automatic discovery, negotiation, and training of link out of reset
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0
— DMI -> PCI Express* Port 0
— DMI -> PCI Express* Port 1
— PCI Express* Port 0 -> DMI
— PCI Express* Port 1 -> DMI
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• PCI Express* reference clock is 100-MHz differential clock
• Power Management Event (PME) functions
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages
• Polarity inversion
• Dynamic lane numbering reversal as defined by the PCI Express Base Specification.
• Static lane numbering reversal
— Does not support dynamic lane reversal, as defined (optional) by the PCI
Express Base Specification.
• Supports Half Swing “low-power/low-voltage” mode.
Note: The processor does not support PCI Express* Hot-Plug.
1.2.3 Direct Media Interface (DMI)
• DMI 2.0 support
• Four lanes in each direction
• 5 GT/s point-to-point DMI interface to PCH is supported
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4
• Shares 100-MHz PCI Express* reference clock
Datasheet, Volume 1 15
Introduction
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros)
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH
—DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
• DC coupling – no capacitors between the processor and the PCH
• Polarity inversion
• PCH end-to-end lane reversal across the link
• Supports Half Swing “low-power/low-voltage”
1.2.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The processors support the PECI 3.0
Specification.
1.2.5 Processor Graphics
• The Processor Graphics contains a refresh of the sixth generation graphics core
enabling substantial gains in performance and lower power consumption. Up to 12
EU Support.
• Next Generation Intel Clear Video Technology HD support is a collection of video
playback and enhancement features that improve the end user’s viewing
experience.
— Encode/transcode HD content
— Playback of high definition content including Blu-ray Disc*
— Superior image quality with sharper, more colorful images
— Playback of Blu-ray disc S3D content using HDMI (V.1.4 with 3D)
• DirectX* Video Acceleration (DXVA) support for accelerating video processing
— Full AVC/VC1/MPEG2 HW Decode
• Advanced Scheduler 2.0, 1.0, XPDM support
• Windows* 7, XP, Windows Vista*, OSX, Linux OS Support
• DX10.1, DX10, DX9 support
•OGL 3.0 support
16 Datasheet, Volume 1
Introduction
1.2.6 Embedded DisplayPort* (eDP*)
• Stand alone dedicated port (unlike previous generation processor that shared pins
with PCIe interface)
1.2.7 Intel® Flexible Display Interface (Intel® FDI)
• For SKUs with graphics, carries display traffic from the Processor Graphics in the
processor to the legacy display connectors in the PCH
• Based on DisplayPort standard
• Two independent links – one for each display pipe
• Four unidirectional downstream differential transmitter pairs
— Scalable down to 3X, 2X, or 1X based on actual display bandwidth
requirements
— Fixed frequency 2.7 GT/s data rate
• Two sideband signals for Display synchronization
— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)
• One Interrupt signal used for various interrupts from the PCH
— FDI_INT signal shared by both Intel FDI Links
• PCH supports end-to-end lane reversal across both links
• Common 100-MHz reference clock
1.3 Power Management Support
1.3.1 Processor Core
• Full support of ACPI C-states as implemented by the following processor C-states
— C0, C1, C1E, C3, C6, C7
• Enhanced Intel SpeedStep® Tec h nol o gy
1.3.2 System
• S0, S3, S4, S5
1.3.3 Memory Controller
• Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))
• Dynamic power-down
1.3.4 PCI Express*
• L0s and L1 ASPM power management capability
1.3.5 DMI
• L0s and L1 ASPM power management capability
Datasheet, Volume 1 17
1.3.6 Processor Graphics Controller
• Rapid Memory Power Management RMPM – CxSR
• Graphics Performance Modulation Technology (GPMT)
• Intel Smart 2D Display Technology (Intel S2DDT)
• Graphics Render C-State (RC6)
•Intel® Seamless Display Refresh Rate Switching with eDP port
1.4 Thermal Management Support
• Digital Thermal Sensor
•Intel® Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Open and Closed Loop Throttling
• Memory Thermal Throttling
• External Thermal Sensor (TS-on-DIMM and TS-on-Board)
• Render Thermal Throttling
• Fan speed control with DTS
Introduction
1.5 Package
• The processor is available on two packages:
— A 37.5 x 37.5 mm rPGA package (rPGA988B)
— A 31 x 24 mm BGA package (BGA1023 or BGA1224)
1.6 Terminology
Term Description
BLT Block Level Transfer
CRT Cathode Ray Tube
DDR3 Third-generation Double Data Rate SDRAM memory technology
DMA Direct Memory Access
DMI Direct Media Interface
DP DisplayPort*
DTS Digital Thermal Sensor
eDP* Embedded DisplayPort*
Enhanced Intel
SpeedStep
®
Technology
Technology that provides power management capabilities to laptops.
18 Datasheet, Volume 1
Introduction
Term Description
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
Execute Disable Bit
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel
®
64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
IMC Integrated Memory Controller
®
Intel
64 Technology 64-bit memory extensions to the IA-32 architecture
®
Intel
DPST Intel® Display Power Saving Technology
®
Intel
FDI Intel® Flexible Display Interface
®
Intel
TXT Intel® Trusted Execution Technology
®
Intel
Virtualization
Technology
®
VT-d
Intel
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
®
Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a
Intel
hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA remapping, a
key feature of Intel VT-d.
IOV I/O Virtualization
ITPM Integrated Trusted Platform Module
LCD Liquid Crystal Display
LVDS
NCTF
Low Voltage Differential Signaling. A high speed, low power data transmission
standard used for display connections to LCD panels.
Non-Critical to Function. NCTF locations are typically redundant ground or noncritical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Platform Controller Hub. The new, 2009 chipset with centralized platform
PCH
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features.
PECI Platform Environment Control Interface
PEG
PCI Express* Graphics. External Graphics using PCI Express* Architecture. A
high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
Processor The 64-bit, single-core or multi-core component (package).
The term “processor core” refers to Si die itself which can contain multiple
Processor Core
Processor Graphics Intel
Rank
execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
®
Processor Graphics
A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC.
These devices are usually, but not always, mounted on a single side of a SODIMM.
SCI System Control Interrupt. Used in ACPI protocol.
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
Storage Conditions
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(that is, unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
TAC Thermal Averaging Constant.
TDP Thermal Design Power.
Datasheet, Volume 1 19
Term Description
V
AXG
V
V
V
V
V
CC
CCIO
CCPLL
CCSA
DDQ
Graphics core power supply.
Processor core power supply.
High Frequency I/O logic power supply
PLL power supply
System Agent (memory controller, DMI, PCIe controllers, and display engine)
power supply
DDR3 power supply.
VLD Variable Length Decoding.
V
SS
Processor ground.
x1 Refers to a Link or Port with one Physical Lane.
x16 Refers to a Link or Port with sixteen Physical Lanes.
x4 Refers to a Link or Port with four Physical Lanes.
x8 Refers to a Link or Port with eight Physical Lanes.
Introduction
20 Datasheet, Volume 1
Introduction
1.7 Related Documents
Refer to Table 1-2 for additional information.
Table 1-2. Related Documents
Document Document Number/ Location
2nd Generation Intel
2
2nd Generation Intel
Update
®
Intel
6 Series Chipset Datasheet www.intel.com/Assets/PDF/datas
®
Intel
6 Series Chipset Thermal Mechanical Specifications and Design
Guidelines
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/
PCI Local Bus Specification 3.0 http://www.pcisig.com/specifica-
PCI Express* Base Specification 2.0 http://www.pcisig.com
DDR3 SDRAM Specification http://www.jedec.org
DisplayPort* Specification http://www.vesa.org
®
Intel
64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/products/pr
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669
®
Core™ Processor Family Mobile Datasheet, Volume
®
Core™ Processor Family Mobile Specification
www.intel.com/Assets/PDF/datas
heet/324803.pdf
www.intel.com/Assets/PDF/specu
pdate/324693.pdf
heet/324645.pdf
www.intel.com/Assets/PDF/desig
nguide/324647.pdf
tions
ocessor/manuals/index.htm
§ §
Datasheet, Volume 1 21
Introduction
22 Datasheet, Volume 1
Interfaces
2 Interfaces
This chapter describes the interfaces supported by the processor.
2.1 System Memory Interface
2.1.1 System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two
independent, 64-bit wide channels each accessing one DIMM. It supports a maximum
of one unbuffered non-ECC DDR3 DIMM per-channel; thus, allowing up to two device
ranks per-channel.
• DDR3 Data Transfer Rates
— 1066 MT/s (PC3-8500), 1333 MT/s (PC3-10600), 1600 MT/s (PC-12800)
• DDR3 SO-DIMM Modules
— Raw Card A – Dual Ranked x16 unbuffered non-ECC
— Raw Card B – Single Ranked x8 unbuffered non-ECC
— Raw Card C – Single Ranked x16 unbuffered non-ECC
— Raw Card F – Dual Ranked x8 (planar) unbuffered non-ECC
• DDR3 DRAM Device Technology
Standard 1-Gb, 2-Gb, and 4-Gb technologies and addressing are supported for x16 and
x8 devices. There is no support for memory modules with different technologies or
capacities on opposite sides of the same memory module. If one side of a memory
module is populated, the other side is either identical or empty.
Table 2-1. Supported SO-DIMM Module Configurations
Raw
Card
Version
A
B
C
F
DIMM
Capacity
1 GB 1 Gb 64 M x 16 8 2 13/10 8 8K
2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K
1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K
2 GB 2 Gb 256 M x 8 8 1 15/10 8 8K
512 MB 1 Gb 64 M x 16 4 1 13/10 8 8K
1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K
2 GB 1 Gb 128 M x 8 16 2 14/10 8 8K
4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K
8 GB 4 Gb 512 M x 8 16 2 16/ 10 8 8K
DRAM Device
Technology
Notes:
1. System memory configurations are based on availability and are subject to change.
2. Interface does not support ULV/LV memory modulates or ULV/LV DIMMs.
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
1,2
# of
Row/Col
Address Bits
# of Banks
Inside
DRAM
Page Size
Datasheet, Volume 1 23
2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
•tCL = CAS Latency
•t
•tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
Table 2-2. DDR3 System Memory Timing Support
= Activate Command to READ or WRITE Command delay
RCD
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
Interfaces
Segment
Extreme
Edition (XE)
and
Quad Core SV
Dual Core SV,
Low voltage
and Ultra low
voltage
Notes:
1. System memory timing support is based on availability and is subject to change.
Transfer
Rate
(MT/s)
1066 7 7 7 6 1n/2n
1333 9 9 9 7 1n/2n
1600 11 11 11 8 1n/2n
1066
1333 9 9 9 7 1n/2n
tCL
(tCK)
77761n/2n
88861n/2n
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
CMD
Mode
2.1.3 System Memory Organization Modes
The IMC supports two memory organization modes—single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1 Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode
Notes
1
The IMC supports Intel Flex Memory Technology Mode. Memory is divided into a
symmetric and an asymmetric zone. The symmetric zone starts at the lowest address
in each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note: Channels A and B can be mapped for physical channels 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
24 Datasheet, Volume 1
Interfaces
CH BCH A
B B
C
B
B
C
Non interleaved
access
Dual channel
interleaved access
TOM
B – The largest physical memory amount of the sm aller size memory module
C – The remaining physical mem ory amount of the larger size mem ory module
Figure 2-1. Intel
®
Flex Memory Technology Operation
2.1.3.2.1 Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note: The DRAM device technology and width may vary from one channel to the other.
2.1.4 Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one DIMM connector
per channel. The usage of DIMM modules with different latencies is allowed. For dualchannel modes, both channels must have an DIMM connector populated. For singlechannel mode, only a single-channel can have a DIMM connector populated.
Datasheet, Volume 1 25
Interfaces
2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel FMA technology enhancements.
2.1.5.1 Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2 Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3 Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6 Memory Type Range Registers (MTRRs) Enhancement
The processor has 2 additional MTRRs (total 10 MTRRs). These additional MTRRs are
specially important in supporting larger system memory beyond 4 GB.
2.1.7 Data Scrambling
The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1s and 0s on the
data bus. Past experience has demonstrated that traffic on the data bus is not random
and can have energy concentrated at specific spectral harmonics creating high di/dt
that is generally limited by data patterns that excite resonance between the package
inductance and on-die capacitances. As a result, the memory controller uses a data
scrambling feature to create pseudo-random patterns on the DDR3 data bus to reduce
the impact of any excessive di/dt.
2.1.8 DRAM Clock Generation
Every supported DIMM has two differential clock pairs. There are a total of four clock
pairs driven directly by the processor to two DIMMs.
26 Datasheet, Volume 1
Interfaces
2.2 PCI Express* Interface
This section describes the PCI Express interface capabilities of the processor. See the
PCI Express Base Specification for details of PCI Express.
The processor has one PCI Express controller that can support one external x16 PCI
Express Graphics Device. The primary PCI Express Graphics port is referred to as
PEG 0.
2.2.1 PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express configuration uses standard mechanisms as defined in the PCI
Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction that provides a 250 MB/s communications channel in each direction
(500 MB/s total). That is close to twice the data rate of classic PCI. The fact that
8b/10b encoding is used accounts for the 250 MB/s where quick calculations would
imply 300 MB/s. The external graphics ports support Gen2 speed as well. At 5.0 GT/s,
Gen 2 operation results in twice as much bandwidth per lane as compared to Gen 1
operation. When operating with two PCIe controllers, each controller can be operating
at either 2.5 GT/s or 5.0 GT/s.
The PCI Express architecture is specified in three layers—Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-2 for the PCI Express Layering Diagram.
Figure 2-2. PCI Express* Layering Diagram
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side, the reverse process occurs and
Datasheet, Volume 1 27
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 2-3. Packet Flow through the Layers
2.2.1.1 Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
Interfaces
2.2.1.2 Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets that are used for Link management functions.
2.2.1.3 Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
28 Datasheet, Volume 1
Interfaces
PCI-PCI
Bridge
representing
root PCI
Express ports
(Device 1 and
Device 6)
PCI
Compatible
Host Bridge
Device
(Device 0)
PCI
Express
Device
PEG0
DMI
2.2.2 PCI Express* Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge
structure.
Figure 2-4. PCI Express* Related Register Structures in the Processor
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(that consists of the remaining configuration space). The PCI-compatible region can be
accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for
details of both the PCI-compatible and PCI Express Enhanced configuration
mechanisms and transaction rules.
2.2.3 PCI Express Graphics
The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port. The
PEG port is being designed to be compliant with the PCI Express Base Specification,
Revision 2.0.
Datasheet, Volume 1 29
2.2.4 PCI Express Lanes Connection
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1 X 16 Controller
Lane 0
0
1
2
3
4
5
6
7
8
9
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15
Lane 1
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
Lane 7
Lane 8
Lane 9
Lane 10
Lane 11
Lane 12
Lane 13
Lane 14
Lane 15
0
1
2
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4
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6
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1 X 8 Controller
0
1
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1 X 4 Controller
Figure 2-5 demonstrates the PCIe lanes mapping.
Figure 2-5. PCIe Typical Operation 16 lanes Mapping
Interfaces
2.3 Direct Media Interface (DMI)
Direct Media Interface (DMI) connects the processor and the PCH. Next generation
DMI2 is supported. The DMI is similar to a four-lane PCI Express supporting up to
1 GB/s of bandwidth in each direction.
Note: Only DMI x4 configuration is supported.
2.3.1 DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
2.3.2 Processor/PCH Compatibility Assumptions
30 Datasheet, Volume 1
GPE. Any DMI related SERR activity is associated with Device 0.
The processor is compatible with the Intel
compatible with any previous PCH products.
®
6 Series Chipset PCH. The processor is not
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