Intel CORE PROCESSOR FAMILY DESKTOP Manual

2nd Generation Intel® Core™ Processor Family Desktop

Specification Update

January 2011

Reference Number: 324643-001

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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details.

Intel® Active Management Technology requires the computer system to have an Intel(R) AMT-enabled chipset, network hardware and software, as well as connection with a power source and a corporate network connection. Setup requires configuration by the purchaser and may require scripting with the management console or further integration into existing security frameworks to enable certain functionality. It may also require modifications of implementation of new business processes. With regard to notebooks, Intel AMT may not be available or certain capabilities may be limited over a host OS-based VPN or when connecting wirelessly, on battery power, sleeping, hibernating or powered off. For more information, see www.intel.com/ technology/platform-technology/intel-amt/

Intel® Trusted Execution Technology (Intel® TXT) requires a computer system with Intel® Virtualization Technology (Intel® Virtualization Technology (Intel® VT-x) and Intel® Virtualization Technology for Directed I/O (Intel® VT-d)), a Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). The MLE could consist of a virtual machine monitor, an OS or an application. In addition, Intel TXT requires the system to contain a TPM v1.2, as defined by the Trusted Computing Group and specific software for some uses. For more information, see http://www.intel.com/technology/security

Intel® Virtualization Technology requires a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor.

* Intel® Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see http://www.intel.com/technology/turboboost

Intel® Hyper-threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology-enabled chipset, BIOS, and operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see http://www.intel.com/info/hyperthreading.

64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel® 64 architecture. Performance will vary depending on your hardware and software configurations. Consult with your system vendor for more information.

Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by visiting Intel's website at http://www.intel.com.

Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others. Copyright © 2011, Intel Corporation. All Rights Reserved.

2

Specification Update

Contents
Contents
Revision History...............................................................................................................	5
Preface ..............................................................................................................................	6
Summary Tables of Changes..........................................................................................	8
Identification Information ..............................................................................................	12
Errata...............................................................................................................................	14
Specification Changes...................................................................................................	37
Specification Clarifications ...........................................................................................	38
Documentation Changes...............................................................................................	39
	§

3

Specification Update

Contents

4

Specification Update

Revision History

Revision	Description	Date
-001	Initial Release	January 2011

Specification Update

5

Preface

This document is an update to the specifications contained in the Affected Documents table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools.

Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents.

This document may also contain information that was not previously published.

Affected Documents

	Document Title	Document
		Number
	2nd Generation Intel® Core™ Processor Family Desktop Datasheet, Volume 1	324641-001
	2nd Generation Intel® Core™ Processor Family Desktop Datasheet, Volume 2	324642-001

Related Documents

	Document Title	Document Number/
		Location
	AP-485, Intel® Processor Identification and the CPUID Instruction	http://www.intel.com/
		design/processor/
		applnots/241618.htm
	Intel® 64 and IA-32 Architectures Software Developer’s Manual,
	Volume 1: Basic Architecture
	Intel® 64 and IA-32 Architectures Software Developer’s Manual,
	Volume 2A: Instruction Set Reference Manual A-M
	Intel® 64 and IA-32 Architectures Software Developer’s Manual,	http://www.intel.com/
	Volume 2B: Instruction Set Reference Manual N-Z
		products/processor/
	Intel® 64 and IA-32 Architectures Software Developer’s Manual,
		manuals/index.htm
	Volume 3A: System Programming Guide
	Intel® 64 and IA-32 Architectures Software Developer’s Manual,
	Volume 3B: System Programming Guide
	Intel® 64 and IA-32 Intel Architecture Optimization Reference
	Manual
	Intel® 64 and IA-32 Architectures Software Developer’s Manual	http://www.intel.com/
		design/processor/
	Documentation Changes
		specupdt/252046.htm
	ACPI Specifications	www.acpi.info

6	Specification Update

Nomenclature

Errata are design defects or errors. These may cause the processor behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices.

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics such as, core speed, L2 cache size, package type, etc. as described in the processor identification information table. Read all notes associated with each S-Spec number.

Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification.

Specification Clarifications describe a specification in greater detail or further highlight a specification’s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification.

Documentation Changes include typos, errors, or omissions from the current published specifications. These will be incorporated in any new release of the specification.

Note: Errata remain in the specification update throughout the product’s lifecycle, or until a particular stepping is no longer commercially available. Under these circumstances, errata removed from the specification update are archived and available upon request. Specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (datasheets, manuals, etc.).

Specification Update

7

Summary Tables of Changes

The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the processor. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. These tables uses the following notations:

Codes Used in Summary Tables

Stepping

X:	Errata exists in the stepping indicated. Specification Change or
	Clarification that applies to this stepping.
(No mark)
or (Blank box):	This erratum is fixed in listed stepping or specification change
	does not apply to listed stepping.

Page

(Page): Page location of item in this document.

Status

Doc:	Document change or update will be implemented.
Plan Fix:	This erratum may be fixed in a future stepping of the product.
Fixed:	This erratum has been previously fixed.
No Fix:	There are no plans to fix this erratum.
Row

Change bar to left of a table row indicates this erratum is either new or modified from the previous version of the document.

Errata (Sheet 1 of 4)

		Steppings
	Number			Status	ERRATA
		D-2	Q-0
					An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/
	BJ1	X	X	No Fix	POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point
					Exception
	BJ2	X	X	No Fix	APIC Error “Received Illegal Vector” May be Lost
	BJ3	X	X	No Fix	An Uncorrectable Error Logged in IA32_CR_MC2_STATUS May also Result in a
					System Hang
	BJ4	X	X	No Fix	B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set
	BJ5	X	X	No Fix	Changing the Memory Type for an In-Use Page Translation May Lead to Memory-
					Ordering Violations

8	Specification Update

Errata (Sheet 2 of 4)

		Steppings
	Number			Status	ERRATA
		D-2	Q-0
	BJ6	X	X	No Fix	Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher
					Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
	BJ7	X	X	No Fix	Corruption of CS Segment Register During RSM While Transitioning From Real
					Mode to Protected Mode
	BJ8	X	X	No Fix	Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled
					Breakpoints
	BJ9	X	X	No Fix	DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is
					Followed by a Store or an MMX Instruction
	BJ10	X	X	No Fix	EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a
					Translation Change
	BJ11	X	X	No Fix	Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
	BJ12	X	X	No Fix	Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
	BJ13	X	X	No Fix	FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM
	BJ14	X	X	No Fix	General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be
					Preempted
	BJ15	X	X	No Fix	#GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not
					Provide Correct Exception Error Code
	BJ16	X	X	No Fix	IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly
	BJ17	X	X	No Fix	IRET under Certain Conditions May Cause an Unexpected Alignment Check
					Exception
	BJ18	X	X	No Fix	LER MSRs May Be Unreliable
	BJ19	X	X	No Fix	LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs
					in 64-bit Mode
	BJ20	X	X	No Fix	MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB
					Error
	BJ21	X	X	No Fix	MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang
	BJ22	X	X	No Fix	MOV To/From Debug Registers Causes Debug Exception
	BJ23	X	X	No Fix	PEBS Record not Updated when in Probe Mode
	BJ24	X	X	No Fix	Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some
					Transitions
					REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
	BJ25	X	X	No Fix	Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or
					Lead to Memory-Ordering Violations
	BJ26	X	X	No Fix	Reported Memory Type May Not Be Used to Access the VMCS and Referenced
					Data Structures
	BJ27	X	X	No Fix	Single Step Interrupts with Floating Point Exception Pending May Be Mishandled
	BJ28	X	X	No Fix	Storage of PEBS Record Delayed Following Execution of MOV SS or STI
	BJ29	X	X	No Fix	The Processor May Report a #TS Instead of a #GP Fault
	BJ30	X	X	No Fix	VM Exits Due to “NMI-Window Exiting” May Be Delayed by One Instruction
	BJ31	X	X	No Fix	Pending x87 FPU Exceptions (#MF) May be Signaled Earlier Than Expected
	BJ32	X	X	No Fix	Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM
	BJ33	X	X	No Fix	Unsupported PCIe Upstream Access May Complete with an Incorrect Byte Count

Specification Update

9

Errata (Sheet 3 of 4)

		Steppings
	Number			Status	ERRATA
		D-2	Q-0
	BJ34	X	X	No Fix	Malformed PCIe Transactions May be Treated as Unsupported Requests Instead of
					as Critical Errors
	BJ35	X	X	No Fix	PCIe Root Port May Not Initiate Link Speed Change
	BJ36	X	X	No Fix	Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/
					XRSTOR Image Leads to Partial Memory Update
	BJ37	X	X	No Fix	Performance Monitor SSE Retired Instructions May Return Incorrect Values
	BJ38	X	X	No Fix	FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
					Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode
	BJ39	X	X	No Fix	FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which
					Wraps a 64-Kbyte Boundary in 16-Bit Code
	BJ40	X	X	No Fix	Spurious Interrupts May be Generated From the Intel® VT-d Remap Engine
	BJ41	X	X	No Fix	Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation
					Descriptors
	BJ42	X	X	No Fix	VPHMINPOSUW Instruction in Vex Format Does Not Signal #UD When vex.vvvv
					!=1111b
	BJ43	X	X	No Fix	LBR, BTM or BTS Records May have Incorrect Branch From Information After an
					EIST/T-state/S-state/C1E Transition or Adaptive Thermal Throttling
	BJ44	X	X	No Fix	VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported
					Field in VMCS
	BJ45	X	X	No Fix	Clock Modulation Duty Cycle Cannot be Programmed to 6.25%
	BJ46	X	X	No Fix	Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for
					VEX.vvvv May Produce a #NM Exception
	BJ47	X	X	No Fix	Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
	BJ48	X	X	No Fix	PCI Express Graphics Receiver Error Reported When Receiver With L0s Enabled
					and Link Retrain Performed
	BJ49	X	X	No Fix	Unexpected #UD on VZEROALL/VZEROUPPER
	BJ50	X	X	No Fix	Perfmon Event LD_BLOCKS.STORE_FORWARD May Overcount
	BJ51	X	X	No Fix	Conflict Between Processor Graphics Internal Message Cycles And Graphics
					Reads From Certain Physical Memory Ranges May Cause a System Hang
	BJ52	X	X	No Fix	Execution of Opcode 9BH with the VEX Opcode Extension May Produce a #NM
					Exception
	BJ53	X	X	No Fix	Executing The GETSEC Instruction While Throttling May Result in a Processor
					Hang
	BJ54	X	X	No Fix	A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain
					Conditions
	BJ55	X	X	No Fix	Instruction Fetch May Cause Machine Check if Page Size and Memory Type Was
					Changed Without Invalidation
	BJ56	X	X	No Fix	Reception of Certain Malformed Transactions May Cause PCIe Port to Hang
					Rather Than Reporting an Error
	BJ57	X	X	No Fix	PCIe LTR Incorrectly Reported as Being Supported
	BJ58	X	X	No Fix	PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have
					Occurred
	BJ59	X	X	No Fix	XSAVE Executed During Paging-Structure Modification May Cause Unexpected
					Processor Behavior

10	Specification Update

Errata (Sheet 4 of 4)

		Steppings
	Number			Status	ERRATA
		D-2	Q-0
	BJ60	X	X	No Fix	C-state Exit Latencies May be Higher Than Expected
	BJ61	X	X	No Fix	MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control
					Offset Field
	BJ62	X	X	No Fix	Intel® VT-d Interrupt Remapping Will Not Report a Fault if Interrupt Index Exceeds
					FFFFH
	BJ63	X	X	No Fix	PCIe Link Speed May Not Change From 5.0 GT/s to 2.5 GT/s
	BJ64	X	X	No Fix	L1 Data Cache Errors May be Logged With Level Set to 1 Instead of 0
	BJ65	X	X	No Fix	An Unexpected Page Fault or EPT Violation May Occur After Another Logical
					Processor Creates a Valid Translation for a Page
	BJ66	X	X	No Fix	TSC Deadline Not Armed While in APIC Legacy Mode
	BJ67	X	X	No Fix	PCIe Upstream TCfgWr May Cause Unpredictable System Behavior
	BJ68	X	X	No Fix	Processor May Fail to Acknowledge a TLP Request
	BJ69	X	X	No Fix	Executing The GETSEC Instruction While Throttling May Result in a Processor
					Hang
	BJ70	X	X	No Fix	PerfMon Event LOAD_HIT_PRE.SW_PREFETCH May Overcount
	BJ71	X	X	No Fix	Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM
					Exception
	BJ72	X	X	No Fix	Unexpected #UD on VPEXTRD/VPINSRD
	BJ73	X	X	No Fix	Restrictions on ECC_Inject_Count Update When Disabling and Enabling Error
					Injection
	BJ74	X	X	No Fix	Successive Fixed Counter Overflows May be Discarded
	BJ75	X	X	No Fix	#GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch
					Instructions
	BJ76	X	X	No Fix	A Read from The APIC-Timer CCR May Disarm The TSC_Deadline Counter
	BJ77	X	X	No Fix	An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2

Specification Changes

Number

SPECIFICATION CHANGES

None for this revision of this specification update.

Specification Clarifications

Number

SPECIFICATION CLARIFICATIONS

None for this revision of this specification update.

Documentation Changes

Number

DOCUMENTATION CHANGES

None for this revision of this specification update.

Specification Update

11

Identification Information

Component Identification using Programming Interface

The processor stepping can be identified by the following register contents:

Reserved	Extended	Extended	Reserved	Processor	Family	Model	Stepping
	Family1	Model2		Type3	Code4	Number5	ID6
31:28	27:20	19:16	15:14	13:12	11:8	7:4	3:0
	00000000b	0010b		00b	0110	1010b	xxxxb

Note:

1.The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8],

to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, or Intel® Core™ processor family.

2.The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor’s family.

3.The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor system).

4.The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan.

5.The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan.

6.The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 1 for the processor stepping ID number in the CPUID information.

When EAX is initialized to a value of ‘1’, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number and Stepping ID value in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register.

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers after the CPUID instruction is executed with a 2 in the EAX register.

The processor can be identified by the following register contents:

Stepping	Vendor ID	1	Host Device ID	2	Processor Graphics	Revision ID	4
					Device ID3
					GT1: 0102h
D-2	8086h		0100h		GT2: 0112h	09h
					GT2 (>1.3 GHz Turbo): 122h
					GT1: 0102h
Q-0	8086h		0100h		GT2: 0112h	09h
					GT2 (>1.3 GHz Turbo): 122h

Notes:

1.The Vendor ID corresponds to bits 15:0 of the Vendor ID Register located at offset 00–01h in the PCI function 0 configuration space.

2.The Host Device ID corresponds to bits 15:0 of the Device ID Register located at Device 0 offset 02–03h in the PCI function 0 configuration space.

3.The Processor Graphics Device ID (DID2) corresponds to bits 15:0 of the Device ID Register located at Device 2 offset 02–03h in the PCI function 0 configuration space.

4.The Revision Number corresponds to bits 7:0 of the Revision ID Register located at offset 08h in the PCI function 0 configuration space.

12	Specification Update

Component Marking Information

The processor stepping can be identified by the following component markings.

Figure 1. Processor Production Top-side Markings (Example)

i M ©'10 BRAND PROC# SLxxx SPEED [COO] [FPO] e4

LOT NO S/N

Table 1.		Processor Identification (Sheet 1 of 2)
					Core Frequency	Max Intel®
	S-	Processor		Processor	(GHz) /	Turbo Boost	Shared
					DDR3 (MHz) /
	SpecNu		Stepping			Technology	L3 Cache	Notes
		Number		Signature	Processor
	mber					2.0 Frequency	Size (MB)
					Graphics
						(GHz)1
					Frequency
						4 core: 3.4
	SR008	i5-2500K	D-2	000206a7h	3.3 / 1333 / 850	3 core: 3.5	6	4, 6
						2 core: 3.6
						1 core: 3.7
						4 core: 3.4
	SR00T	i5-2500	D-2	000206a7h	3.3 / 1333 / 850	3 core: 3.5	6	3, 4, 5, 6
						2 core: 3.6
						1 core: 3.7
						4 core: 3.2
	SR00Q	i5-2400	D-2	000206a7h	3.1 / 1333 / 850	3 core: 3.3	6	3, 4, 5, 6
						2 core: 3.3
						1 core: 3.4
						4 core: 2.8
	SR009	i5-2500S	D-2	000206a7h	2.7 / 1333 / 850	3 core: 3.2	6	3, 4, 5, 6
						2 core: 3.6
						1 core: 3.7
						4 core: 2.6
	SR00S	i5-2400S	D-2	000206a7h	2.5 / 1333 / 850	3 core: 2.8	6	3, 4, 5, 6
						2 core: 3.2
						1 core: 3.3

Specification Update

13