Intel BX80633I74930K, BX80633I74820K User Manual

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Intel® Core™ i7 Processor Family for LGA2011 Socket

Datasheet – Volume 1 of 2

Supporting Desktop Intel® Core™ i7-4960X Extreme Edition Processor Series for the LGA2011 Socket

Supporting Desktop Intel® Core™ i7-49xx and i7-48xx Processor Series for the LGA2011 Socket

September 2013

329366-001

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Intel, Intel, Enhanced Intel® SpeedStep® Technology, Intel® 64 Technology, Intel® Virtualization Technology (Intel® VT), Intel® VT-d, Intel® Turbo Boost Technology, Intel® Hyper-Threading Technology (Intel® HT Technology), Intel® Streaming SIMD Extensions (Intel® SSE) Intel Core, and the Intel logo are trademarks of Intel Corporation in the U. S. and/or other countries.

*Other names and brands may be claimed as the property of others. Copyright © 2013, Intel Corporation. All rights reserved.

2

Datasheet

Table of Contents

1

Introduction

..............................................................................................................

8

 

1.1

Processor Feature Details .....................................................................................

9

 

1.2

Supported .....................................................................................Technologies

10

 

1.3

Interfaces ........................................................................................................

10

 

 

1.3.1 .........................................................................

System Memory Support

10

 

 

1.3.2 .........................................................................................

PCI Express*

11

 

 

1.3.3 .........................................................Direct Media Interface Gen 2 (DMI2)

12

 

 

1.3.4 ...........................................Platform Environment Control Interface (PECI)

13

 

1.4

Power Management ...............................................................................Support

13

 

 

1.4.1 ...........................................................Processor Package and Core States

13

 

 

1.4.2 ...........................................................................

System States Support

13

 

 

1.4.3 ..................................................................................

Memory Controller

13

 

 

1.4.4 .........................................................................................

PCI Express*

13

 

1.5

Thermal ............................................................................Management Support

13

 

1.6

Package .............................................................................................Summary

14

 

1.7

Terminology .....................................................................................................

14

 

1.8

Related ............................................................................................Documents

16

2

Interfaces................................................................................................................

 

18

 

2.1

System ...................................................................................Memory Interface

18

 

 

2.1.1 ........................................................System Memory Technology Support

18

 

 

2.1.2 ...............................................................System Memory Timing Support

18

 

2.2

PCI Express* .......................................................................................Interface

19

 

 

2.2.1 .......................................................................

PCI Express* Architecture

19

 

 

2.2.2 .....................................................PCI Express* Configuration Mechanism

20

 

2.3

Direct Media .......................................Interface 2 (DMI2) / PCI Express* Interface

21

 

 

2.3.1 .....................................................................................

DMI2 Error Flow

21

 

 

2.3.2 ................................................Processor / PCH Compatibility Assumptions

21

 

 

2.3.3 .....................................................................................

DMI2 Link Down

21

 

2.4

Platform ......................................................Environment Control Interface (PECI)

21

3

Technologies ...........................................................................................................

22

 

3.1

Intel® Virtualization ..........................................................Technology (Intel® VT)

22

 

 

3.1.1 ............................................................................

Intel ® VT - x Objectives

22

 

 

3.1.2 ...............................................................................

Intel ® VT - x Features

23

 

 

3.1.3 ............................................................................

Intel ® VT - d Objectives

23

 

 

3.1.4 .................................Intel® Virtualization Technology Processor Extensions

24

 

3.2

Security ........................................................................................Technologies

25

 

 

3.2.1 Intel® Advanced Encryption Standard New Instructions

 

 

 

....................................................................

(Intel ® AES - NI) Instructions

25

 

 

3.2.2 .................................................................................

Execute Disable Bit

25

 

3.3

Intel® Hyper ....................................-Threading Technology (Intel® HT Technology)

25

 

3.4

Intel® Turbo ............................................................................Boost Technology

26

 

 

3.4.1 ...................................................Intel® Turbo Boost Operating Frequency

26

 

3.5

Enhanced .............................................................Intel® SpeedStep® Technology

26

 

3.6

Intel® Advanced ...................................................Vector Extensions (Intel® AVX)

27

4

Power Management.................................................................................................

29

 

4.1

Advanced ......................Configuration and Power Interface (ACPI) States Supported

29

 

 

4.1.1 .......................................................................................

System States

29

 

 

4.1.2 ...........................................................Processor Package and Core States

29

 

 

4.1.3 ................................................Integrated Memory Controller (IMC) States

31

 

 

4.1.4 ...................Direct Media Interface Gen 2 (DMI2) / PCI Express* Link States

31

 

 

4.1.5 ...............................................................G, S, and C State Combinations

32

Datasheet

3

 

 

4.2

......................................................Processor Core / Package Power Management

32

 

 

 

4.2.1 Enhanced Intel® SpeedStep® Technology .................................................

32

 

 

 

4.2.2

Low-Power Idle States............................................................................

33

 

 

 

4.2.3 Requesting Low-Power Idle States ...........................................................

34

 

 

 

4.2.4

Core C-states ........................................................................................

35

 

 

 

4.2.5

Package C-States...................................................................................

36

 

 

 

4.2.6 Package C-State Power Specifications.......................................................

39

 

4.3

System Memory Power Management ...................................................................

39

 

 

 

4.3.1

CKE Power-Down ...................................................................................

40

 

 

 

4.3.2

Self-Refresh..........................................................................................

40

 

 

 

4.3.3 DRAM I/O Power Management .................................................................

41

 

4.4

Direct Media Interface 2 (DMI2) / PCI Express* Power Management ........................

41

5

 

Thermal Management Specifications .......................................................................

42

6

 

Signal Descriptions .................................................................................................

43

 

6.1

System Memory Interface Signals .......................................................................

43

 

6.2

PCI Express* Based Interface Signals ..................................................................

44

 

6.3

Direct Media Interface Gen 2 (DMI2) / PCI Express* Port 0 Signals..........................

46

 

6.4

Platform Environment Control Interface (PECI) Signal ............................................

46

 

6.5

System Reference Clock Signals..........................................................................

46

 

6.6

Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals.........................

46

 

6.7

Serial Voltage Identification (SVID) Signals ..........................................................

47

 

6.8

Processor Asynchronous Sideband and Miscellaneous Signals..................................

47

 

6.9

Processor Power and Ground Supplies .................................................................

50

7

 

Electrical Specifications ..........................................................................................

51

 

7.1

Processor Signaling ...........................................................................................

51

 

 

 

7.1.1 System Memory Interface Signal Groups...................................................

51

 

 

 

7.1.2

PCI Express* Signals..............................................................................

51

 

 

 

7.1.3 Direct Media Interface Gen 2 (DMI2) / PCI Express* Signals ........................

51

 

 

 

7.1.4 Platform Environmental Control Interface (PECI) ........................................

52

 

 

 

7.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) ........................

52

 

 

 

7.1.6 Joint Test Action Group (JTAG) and Test Access

 

 

 

 

 

Port (TAP) Signals..................................................................................

53

 

 

 

7.1.7

Processor Sideband Signals .....................................................................

53

 

 

 

7.1.8 Power, Ground and Sense Signals ............................................................

53

 

 

 

7.1.9 Reserved or Unused Signals ....................................................................

58

 

7.2

Signal Group Summary......................................................................................

58

 

7.3

Power-On Configuration (POC) Options ................................................................

61

 

7.4

Absolute Maximum and Minimum Ratings.............................................................

62

 

 

 

7.4.1

Storage Conditions Specifications.............................................................

62

 

7.5

DC Specifications ..............................................................................................

63

 

 

 

7.5.1 Voltage and Current Specifications ...........................................................

63

 

 

 

7.5.2

Die Voltage Validation ............................................................................

66

 

 

 

7.5.3

Signal DC Specifications .........................................................................

67

8

 

Processor Land Listing ............................................................................................

73

9

 

Package Mechanical Specifications.........................................................................

116

10

 

Boxed Processor Specifications..............................................................................

117

 

10.1

Introduction....................................................................................................

117

 

10.2

Boxed Processor Contents.................................................................................

117

4

Datasheet

Figures

1-1 Processor Platform Block Diagram Example.............................................................

9

1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) ..................

12

2-1 PCI Express* Layering Diagram...........................................................................

19

2-2 Packet Flow through the Layers...........................................................................

19

4-1 Idle Power Management Breakdown of the Processor Cores.....................................

33

4-2 Thread and Core C-State Entry and Exit ...............................................................

33

4-3

Package C-State Entry and Exit ...........................................................................

37

7-1

Input Device Hysteresis......................................................................................

52

7-2

Voltage Regulator (VR) Power-State Transitions ....................................................

56

7-3

VCC Overshoot Example Waveform ......................................................................

66

Tables

1-1

Terminology .....................................................................................................

14

1-2

Processor Documents.........................................................................................

16

1-3

Public Specifications ..........................................................................................

17

4-1

System States ..................................................................................................

29

4-2

Package C-State Support....................................................................................

30

4-3

Core C-State Support.........................................................................................

30

4-4

System Memory Power States .............................................................................

31

4-5

DMI2 / PCI Express* Link States .........................................................................

31

4-6

G, S and C State Combinations ...........................................................................

32

4-7

Coordination of Thread Power States at the Core Level ...........................................

34

4-8

P_LVLx to MWAIT Conversion..............................................................................

34

4-9

Coordination of Core Power States at the Package Level .........................................

37

4-10

Package C-State Power Specifications ..................................................................

39

6-1

Memory Channel DDR0, DDR1, DDR2, DDR3.........................................................

43

6-2

Memory Channel Miscellaneous ...........................................................................

44

6-3

PCI Express* Port 1 Signals ................................................................................

44

6-4

PCI Express* Port 2 Signals ................................................................................

44

6-5

PCI Express* Port 3 Signals ................................................................................

45

6-6

PCI Express* Miscellaneous Signals .....................................................................

45

6-7

DMI2 and PCI Express Port 0 Signals ...................................................................

46

6-8

Platform Environment Control Interface (PECI) Signals ...........................................

46

6-9

System Reference Clock (BCLK{0/1}) Signals .......................................................

46

6-10

Joint Test Action Group (JTAG) and Test Access Port (TAP) Signals...........................

46

6-11

Serial Voltage Identification (SVID) Signals...........................................................

47

6-12

Processor Asynchronous Sideband Signals ............................................................

47

6-13

Miscellaneous Signals.........................................................................................

49

6-14

Power and Ground Signals ..................................................................................

50

7-1

Power and Ground Lands....................................................................................

54

7-2

Serial Voltage Identification (SVID) Address Usage ................................................

57

7-3

VR12.0 Reference Code Voltage Identification (VID) Table ......................................

57

7-4

Signal Description Buffer Types ...........................................................................

58

7-5

Signal Groups ...................................................................................................

59

7-6

Signals with On-Die Termination..........................................................................

61

7-7

Power-On Configuration Option Lands ..................................................................

61

7-8

Processor Absolute Minimum and Maximum Ratings ...............................................

62

7-9

Storage Condition Ratings ..................................................................................

62

Datasheet

5

 

7-10

........................................................................................Voltage Specifications

63

7-11

Current Specifications........................................................................................

65

7-12

VCC Overshoot Specifications..............................................................................

66

7-13

DDR3 and DDR3L Signal DC Specifications ...........................................................

67

7-14

PECI DC Specifications ......................................................................................

68

7-15

System Reference Clock (BCLK{0/1}) DC Specifications.........................................

69

7-16

SMBus DC Specifications....................................................................................

69

7-17

Joint Test Action Group (JTAG) and Test Access Point (TAP) Signals DC Specifications 70

7-18

Serial VID Interface (SVID) DC Specifications .......................................................

70

7-19

Processor Asynchronous Sideband DC Specifications..............................................

71

7-20

Miscellaneous Signals DC Specifications ...............................................................

71

8-1

Land List by Land Name.....................................................................................

74

8-2

Land List by Land Number..................................................................................

95

6

Datasheet

Revision History

Revision

Description

Date

 

Number

 

 

 

 

 

 

 

 

001

• Initial release

September

2013

 

 

 

 

§

Datasheet

7

Introduction

1 Introduction

The Intel® Core™ i7 processor family for LGA2011 socket are the next generation of 64-bit, multi-core desktop processors built on 22-nanometer process technology. Based on the low-power/high-performance Intel® Core™ i7 processor micro-architecture, the processor is designed for a two-chip platform instead of to the traditional three-chip platforms (processor, Memory Controller Hub, and Platform Controller Hub). The twochip platform consists of a processor and the Platform Controller Hub (PCH) enabling higher performance, easier validation, and improved x-y footprint. Refer to Figure 1-1 for a platform block diagram.

The processor features per socket, up to 40 lanes of PCI Express* 3.0 links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space and a 48-bit virtual address space.

Included in this family of processors is an integrated memory controller (IMC) and integrated I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single die solution is known as a monolithic processor.

The Datasheet - Volume 1 covers DC electrical specifications, land and signal definitions, differential signaling specifications, interface functional descriptions, power management descriptions, and additional feature information pertinent to the implementation and operation of the processor on its platform. Volume 2 provides register information. Refer to the Related Documents section for access to Volume 2.

Note: Throughout this document, the Intel® Core™ i7 processor family for LGA2011 socket may be referred to as “processor”.

Note: Throughout this document, the Intel® Core™ i7-49xx processor series for the LGA2011 socket refers t the Intel® Core™ i7-4930K processor.

Note: Throughout this document, the Intel® Core™ i7-48xx processor series for the LGA2011 socket refers to the Intel® Core™ i7-4820K processor.

Note: Throughout this document, the Intel® X79 Chipset Platform Controller Hub may be referred to as “PCH”.

Note: Some processor features are not available on all platforms. Refer to the processor specification update for details.

8

Datasheet

Introduction

Figure 1-1. Processor Platform Block Diagram Example

1.1Processor Feature Details

Up to 6 execution cores

Each core supports two threads (Intel® Hyper-Threading Technology), up to 12 threads per socket

32KB instruction and 32-KB data first-level cache (L1) for each core

256KB shared instruction/data mid-level (L2) cache for each core

Up to 15MB last level cache (LLC): up to 2.5MB per core instruction/data last level cache (LLC), shared among all cores

Datasheet

9

Introduction

1.2Supported Technologies

Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d)

Intel® Virtualization Technology (Intel® VT) Processor Extensions

Intel® 64 Architecture

Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)

Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)

Intel® Advanced Vector Extensions (Intel® AVX)

Intel® AVX Floating Point Bit Depth Conversion (Float 16)

Intel® Hyper-Threading Technology

Execute Disable Bit

Intel® Turbo Boost Technology

Enhanced Intel® SpeedStep® Technology

1.3Interfaces

1.3.1System Memory Support

Supports four DDR3 channels

Unbuffered DDR3 DIMMs supported

Independent channel mode or lockstep mode

Data burst length of eight cycles for all memory organization modes

Memory DDR3 data transfer rates of 1066 MT/s, 1333 MT/s, 1600 MT/s, and 1866 MT/s

64-bit wide channels

DDR3 standard I/O Voltage of 1.5 V

1-Gb, 2-Gb, 4-Gb, and 8-Gb DDR3 DRAM technologies supported for these devices:

UDIMMs x8, x16

Up to 4 ranks supported per memory channel, 1, 2, or 4 ranks per DIMM

Open with adaptive idle page close timer or closed page policy

Per channel memory test and initialization engine can initialize DRAM to all logical zeros or a predefined test pattern

Minimum memory configuration: independent channel support with 1 DIMM populated

Command launch modes of 1n/2n

Improved Thermal Throttling

Memory thermal monitoring support for DIMM temperature using two memory signals, MEM_HOT_C{01/23}_N

10

Datasheet

Introduction

1.3.2PCI Express*

The PCI Express* port(s) are fully-compliant with the PCI Express* Base Specification, Revision 3.0 (PCIe 3.0)

Support for PCI Express* 3.0 (8.0 GT/s), 2.0 (5.0 GT/s), and 1.0 (2.5 GT/s)

Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express* devices at PCIe* 3.0 speeds that are configurable for up to 10 independent ports

4 lanes of PCI Express* at PCIe* 2.0 speeds when not using DMI2 port (Port 0), also can be downgraded to x2 or x1

Negotiating down to narrower widths is supported, see Figure 1-2:

x16 port (Port 2 and Port 3) may negotiate down to x8, x4, x2, or x1

x8 port (Port 1) may negotiate down to x4, x2, or x1

x4 port (Port 0) may negotiate down to x2, or x1

When negotiating down to narrower widths, there are caveats as to how lane reversal is supported

Address Translation Services (ATS) 1.0 support

Hierarchical PCI-compliant configuration mechanism for downstream devices

Traditional PCI style traffic (asynchronous snooped, PCI ordering)

PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.

PCI Express* Enhanced Access Mechanism – accessing the device configuration space in a flat memory mapped fashion

Automatic discovery, negotiation, and training of link out of reset

Supports receiving and decoding 64 bits of address from PCI Express*:

Memory transactions received from PCI Express* that go above the top of physical address space (when Intel VT-d is enabled, the check would be against the translated Host Physical Address (HPA)) are reported as errors by the processor.

Outbound access to PCI Express* will always have address bits 63:46 cleared

Re-issues Configuration cycles that have been previously completed with the Configuration Retry status

Power Management Event (PME) functions

Message Signaled Interrupt (MSI and MSI-X) messages

Degraded Mode support and Lane Reversal support

Static lane numbering reversal and polarity inversion support

Support for PCIe* 3.0 atomic operation, PCIe 3.0 optional extension on atomic read-modify-write mechanism

Datasheet

11

Introduction

Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)

1.3.3Direct Media Interface Gen 2 (DMI2)

Serves as the chip-to-chip interface to the PCH

The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2

Operates at PCI Express* 1.0 or 2.0 speeds

Transparent to software

Processor and peer-to-peer writes and reads with 64-bit address support

APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of Interrupt” broadcast message when initiated by the processor.

System Management Interrupt (SMI), SCI, and SERR error indication

Static lane numbering reversal support

Supports DMI2 virtual channels VC0, VC1, VCm, and VCp

12

Datasheet

Introduction

1.3.4Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a PECI client (the processor) and a PECI master (the PCH). Refer to the Processor Thermal Mechanical Specifications and Design Guide for additional details on PECI services available in the processor (Refer to the Related Documents section).

Supports operation at up to 2 Mbps data transfers

Link layer improvements to support additional services and higher efficiency over PECI 2.0 generation

Services include processor thermal and estimated power information, control functions for power limiting, P-state and T-state control, and access for Machine Check Architecture registers and PCI configuration space (both within the processor package and downstream devices)

Single domain (Domain 0) is supported

1.4Power Management Support

1.4.1Processor Package and Core States

Advance Configuration and Power Interface (ACPI) C-states as implemented by the following processor C-states:

Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported)

Core: CC0, CC1, CC1E, CC3, CC6, CC7

Enhanced Intel SpeedStep Technology

1.4.2System States Support

S0, S1, S3, S4, S5

1.4.3Memory Controller

Multiple CKE power-down modes

Multiple self-refresh modes

Memory thermal monitoring using MEM_HOT_C01_N and MEM_HOT_C23_N signals

1.4.4PCI Express*

L1 ASPM power management capability; L0s is not supported

1.5Thermal Management Support

Digital Thermal Sensor with multiple on-die temperature zones

Adaptive Thermal Monitor

THERMTRIP_N and PROCHOT_N signal support

On-Demand mode clock modulation

Fan speed control with DTS

Two integrated SMBus masters for accessing thermal data from DIMMs

New Memory Thermal Throttling features using MEM_HOT_C{01/23}_N signals

Datasheet

13

Introduction

1.6Package Summary

The processor socket type is noted as LGA2011. The processor package is a

52.5 x 45 mm FC-LGA package (LGA2011). Refer to the Processor Thermal Mechanical Specification and Design Guide (see Related Documents section) for the package mechanical specifications.

1.7Terminology

Table 1-1.

Terminology (Sheet 1 of 3)

 

 

 

 

 

Term

 

Description

 

 

 

 

 

ACPI

 

Advanced Configuration and Power Interface

 

 

 

 

 

ASPM

 

Active State Power Management

 

 

 

 

 

CCM

 

Continuous Conduction Mode

 

 

 

 

 

DCM

 

Discontinuous Conduction Mode

 

 

 

 

 

DDR3

 

Third generation Double Data Rate SDRAM memory technology that is the successor

 

 

to DDR2 SDRAM

 

 

 

 

 

 

 

 

DMA

 

Direct Memory Access

 

 

 

 

 

DMI

 

Direct Media Interface

 

 

 

 

 

DMI2

 

Direct Media Interface Gen 2

 

 

 

 

 

DTS

 

Digital Thermal Sensor

 

 

 

 

 

Enhanced Intel

 

Allows the operating system to reduce power consumption when performance is not

 

SpeedStep®

 

needed.

 

Technology (EIST)

 

 

 

 

 

 

 

EPT

 

Extended Page Tables

 

 

 

 

 

ESD

 

Electro-Static Discharge

 

 

 

 

 

 

 

The Execute Disable bit allows memory to be marked as executable or non-

 

 

 

executable when combined with a supporting operating system. If code attempts to

 

Execute Disable Bit

 

run in non-executable memory, the processor raises an error to the operating

 

 

system. This feature can prevent some classes of viruses or worms that exploit buffer

 

 

 

overrun vulnerabilities and can thus help improve the overall security of the system.

 

 

 

See the Intel® 64 and IA-32 Architectures Software Developer's Manuals for more

 

 

 

detailed information.

 

 

 

 

 

Functional Operation

Refers to the normal operating conditions in which all processor specifications,

 

including DC, AC, system bus, signal quality, mechanical, and thermal are satisfied.

 

 

 

 

 

 

 

 

 

 

Integrated Heat Spreader. A component of the processor package used to enhance

 

IHS

 

the thermal performance of the package. Component thermal solutions interface with

 

 

 

the processor at the IHS surface.

 

 

 

 

 

IIO

 

The Integrated I/O Controller. An I/O controller that is integrated in the processor

 

 

die.

 

 

 

 

 

 

 

 

IMC

 

The Integrated Memory Controller. A Memory Controller that is integrated in the

 

 

processor die.

 

 

 

 

 

 

 

 

Intel® 64 Technology

64-bit memory extensions to the IA-32 architecture. Further details on Intel 64

 

architecture and programming model can be found at

 

 

 

http://developer.intel.com/technology/intel64/.

 

 

 

 

 

Intel® ME

 

Intel® Management Engine (Intel® ME)

 

Intel® Turbo Boost

 

Intel® Turbo Boost Technology is a way to automatically run the processor core faster

 

 

than the marked frequency if the part is operating under power, temperature, and

 

Technology

 

current specifications limits of the Thermal Design Power (TDP). This results in

 

 

 

increased performance of both single and multi-threaded applications.

 

 

 

 

Intel® Virtualization

Processor virtualization, which when used in conjunction with Virtual Machine Monitor

 

®

VT)

software, enables multiple robust independent software environments inside a single

 

Technology (Intel

platform.

 

 

 

 

14

 

 

Datasheet

Introduction

Table 1-1.

Terminology (Sheet 2 of 3)

 

 

 

 

Term

Description

 

 

 

 

 

Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel VT-d is a hardware

 

Intel® VT-d

assist, under system software (Virtual Machine Manager or operating system)

 

control, for enabling I/O device virtualization. Intel VT-d also brings robust security

 

 

by providing protection from errant DMAs by using DMA remapping, a key feature of

 

 

Intel VT-d.

 

 

 

 

IOV

I/O Virtualization

 

 

 

 

Jitter

Any timing variation of a transition edge or edges from the defined Unit Interval (UI).

 

 

 

 

JTAG

Joint Test Action Group

 

 

 

 

LGA2011-0 Socket

The LGA2011-0 land FCLGA package mates with the system board through this

 

surface mount, LGA2011-0 contact socket.

 

 

 

 

 

 

LLC

Last Level Cache

 

 

 

 

MCH

Memory Controller Hub

 

 

 

 

 

Non-Critical to Function: NCTF locations are typically redundant ground or non-

 

NCTF

critical reserved; thus, the loss of the solder joint continuity at end of life conditions

 

 

will not affect the overall product functionality.

 

 

 

 

NEBS

Network Equipment Building System. NEBS is the most common set of environmental

 

design guidelines applied to telecommunications equipment in the United States.

 

 

 

 

 

 

 

Platform Controller Hub. The next generation chipset with centralized platform

 

PCH

capabilities including the main I/O interfaces along with display connectivity, audio

 

 

features, power management, manageability, security, and storage features.

 

 

 

 

PCI Express*

PCI Express* Generation 2.0/3.0

 

 

 

 

PCI Express* 2

PCI Express* Generation 2.0

 

 

 

 

PCI Express* 3

PCI Express* Generation 3.0

 

 

 

 

PCU

Power Control Unit

 

 

 

 

PECI

Platform Environment Control Interface

 

 

 

 

PLE

Pause Loop Exiting

 

 

 

 

Processor

The 64-bit, single-core or multi-core component (package)

 

 

 

 

 

The term “processor core” refers to silicon die itself that can contain multiple

 

Processor Core

execution cores. Each execution core has an instruction cache, data cache, and

 

256-KB L2 cache. All execution cores share the L3 cache. All DC and AC timing and

 

 

signal integrity specifications are measured at the processor die (pads), unless

 

 

otherwise noted.

 

 

 

 

QoS

Quality of Service

 

 

 

 

Rank

A unit of DRAM corresponding four to eight devices in parallel. These devices are

 

usually, but not always, mounted on a single side of a DDR3 DIMM.

 

 

 

 

 

 

SCI

System Control Interrupt. Used in Advanced Configuration and Power Interface

 

(ACPI) protocol.

 

 

 

 

 

 

 

System Management Bus. A two-wire interface through which simple system and

 

SMBus

power management related devices can communicate with the rest of the system. It

 

is based on the principals of the operation of the I2C* two-wire serial bus from

 

 

Philips* Semiconductor.

 

 

 

 

SSE

Intel® Streaming SIMD Extensions (Intel® SSE)

 

STD

Suspend-to-Disk

 

 

 

 

STR

Suspend-to-RAM

 

 

 

 

SVID

Serial Voltage Identification

 

 

 

 

TAC

Thermal Averaging Constant

 

 

 

 

TAP

Test Access Port

 

 

 

 

TCC

Thermal Control Circuit

 

 

 

 

TDP

Thermal Design Power

 

 

 

 

TLP

Transaction Layer Packet

 

 

 

Datasheet

 

15

 

 

 

 

 

Introduction

Table 1-1. Terminology (Sheet 3 of 3)

 

 

 

 

 

 

 

 

 

 

 

 

Term

Description

 

 

 

 

 

 

 

 

 

 

 

 

TSOD

Thermal Sensor on DIMM

 

 

 

 

 

 

 

 

 

 

 

 

UDIMM

Unbuffered Dual In-line Module

 

 

 

 

 

 

 

 

 

 

 

 

Uncore

The portion of the processor comprising the shared cache, IMC, HA, PCU, and UBox.

 

 

 

 

 

 

 

 

 

 

 

Signaling convention that is binary and unidirectional. In this binary signaling, one bit

 

 

 

 

is sent for every edge of the forwarded clock, whether it be a rising edge or a falling

 

 

 

Unit Interval

edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at

 

 

 

 

instance “n” is defined as:

 

 

 

 

 

 

UI n = t n – t n – 1

 

 

 

 

 

VCC

Processor core power supply

 

 

 

 

 

VCCD_01, VCCD_23

Variable power supply for the processor system memory interface. VCCD is the

 

 

 

generic term for VCCD_01, VCCD_23.

 

 

 

 

 

 

 

 

 

 

 

VID

Voltage Identification

 

 

 

 

 

 

 

 

 

 

 

 

VM

Virtual Machine

 

 

 

 

 

 

 

 

 

 

 

 

VMM

Virtual Machine Monitor

 

 

 

 

 

 

 

 

 

 

 

 

VPID

Virtual Processor ID

 

 

 

 

 

 

 

 

 

 

 

 

VR

Voltage Regulator

 

 

 

 

 

 

 

 

 

 

 

 

VRD

Voltage Regulator Down

 

 

 

 

 

 

 

 

 

 

 

 

VRM

Voltage Regulator Module

 

 

 

 

 

 

 

 

 

 

 

 

VSS

Processor ground

 

 

 

 

 

x1

Refers to a Link or Port with one Physical Lane

 

 

 

 

 

 

 

 

 

 

 

 

x16

Refers to a Link or Port with sixteen Physical Lanes

 

 

 

 

 

 

 

 

 

 

 

 

x4

Refers to a Link or Port with four Physical Lanes

 

 

 

 

 

 

 

 

 

 

 

 

x8

Refers to a Link or Port with eight Physical Lanes

 

 

 

 

 

 

 

1.8

Related Documents

 

 

 

 

 

Refer to the following documents for additional information.

 

 

Table 1-2.

Processor Documents

 

 

 

 

 

 

 

 

 

 

 

 

 

Document

Document Number /

 

 

 

 

 

Location

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® Core™ i7 Processor Family for LGA2011 Socket Datasheet – Volume 2 of

329367

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® Core™ i7 Processor Families for the LGA2011-0 Socket Thermal

329368

 

 

 

 

Mechanical Specifications and Design Guide

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® Core™ i7 Processor Family for LGA2011 Socket Specification Update

326199

 

16

Datasheet

Introduction

Table 1-3.

Public Specifications

 

 

 

 

 

Document

Document Number / Location

 

 

 

 

Advanced Configuration and Power Interface Specification 3.0

http://www.acpi.info

 

 

 

 

PCI Local Bus Specification 3.0

http://www.pcisig.com/specifications

 

 

 

 

PCI Express Base Specification - Revision 2.1 and 1.1

http://www.pcisig.com

 

PCI Express Base Specification - Revision 3.0

 

 

 

 

 

 

System Management Bus (SMBus) Specification, Revision 2.0

http://smbus.org/

 

 

 

 

DDR3 SDRAM Specification

http://www.jedec.org

 

 

 

 

Low (JESD22-A119) and High (JESD-A103) Temperature Storage Life

http://www.jedec.org

 

Specifications

 

 

 

 

 

 

Intel® 64 and IA-32 Architectures Software Developer’s Manuals

 

 

• Volume 1: Basic Architecture

 

 

• Volume 2A: Instruction Set Reference, A-M

 

 

• Volume 2B: Instruction Set Reference, N-Z

http://www.intel.com/products/proce

 

• Volume 3A: System Programming Guide

ssor/manuals/index.htm

 

• Volume 3B: System Programming Guide

 

 

Intel® 64 and IA-32 Architectures Optimization Reference Manual

 

 

Intel® Virtualization Technology Specification for Directed I/O

http://download.intel.com/technolog

 

Architecture Specification

y/computing/vptech/Intel(r)_VT_for_

 

 

Direct_IO.pdf

 

 

 

 

National Institute of Standards and Technology NIST SP800-90

http://csrc.nist.gov/publications/Pubs

 

 

SPs.html

 

 

 

§

Datasheet

17

Interfaces

2 Interfaces

This chapter describes the functional behaviors supported by the processor. Topics covered include:

System Memory Interface

PCI Express* Interface

Direct Media Interface 2 (DMI2) / PCI Express* Interface

Platform Environment Control Interface (PECI)

2.1System Memory Interface

2.1.1System Memory Technology Support

The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.

2.1.2System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

tCL = CAS Latency

tRCD = Activate Command to READ or WRITE Command delay

tRP = PRECHARGE Command Period

CWL = CAS Write Latency

Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

18

Datasheet

Interfaces

2.2PCI Express* Interface

This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0.

2.2.1PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.

The PCI Express* architecture is specified in three layers – Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. Refer to the following figure for the PCI Express* Layering Diagram.

Figure 2-1. PCI Express* Layering Diagram

PCI Express* uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, the packets are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device.

Figure 2-2. Packet Flow through the Layers

Datasheet

19

Interfaces

2.2.1.1Transaction Layer

The upper layer of the PCI Express* architecture is the Transaction Layer. The Transaction Layer's primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs.

2.2.1.2Data Link Layer

The middle layer in the PCI Express* stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer include link management, error detection, and error correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP sequence number, and submits them to Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing. On detection of TLP error(s), this layer is responsible for requesting retransmission of TLPs until information is correctly received, or the Link is determined to have failed. The Data Link Layer also generates and consumes packets that are used for Link management functions.

2.2.1.3Physical Layer

The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry. It also includes logical functions related to interface initialization and maintenance. The Physical Layer exchanges data with the Data Link Layer in an implementation-specific format, and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express* Link at a frequency and width compatible with the remote device.

2.2.2PCI Express* Configuration Mechanism

The PCI Express* link is mapped through a PCI-to-PCI bridge structure.

PCI Express* extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express* configuration space is divided into a PCI-compatible region (which consists of the first 256 bytes of a logical device's configuration space) and an extended PCI Express* region (which consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express* configuration access mechanism described in the PCI Express* Enhanced Configuration Mechanism section.

The PCI Express* Host Bridge is required to translate the memory-mapped PCI Express* configuration space accesses from the host processor to PCI Express* configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using 32-bit operations (32-bit aligned) only.

See the PCI Express* Base Specification for details of both the PCI-compatible and PCI Express* Enhanced configuration mechanisms and transaction rules.

20

Datasheet

Interfaces

2.3Direct Media Interface 2 (DMI2) / PCI Express* Interface

Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub (PCH). DMI2 is similar to a four-lane PCI Express* supporting a speed of 5 GT/s per lane. Refer to Section 6.3 for additional details.

Note: Only DMI2 x4 configuration is supported.

2.3.1DMI2 Error Flow

DMI2 can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or GPE. Any DMI2 related SERR activity is associated with Device 0.

2.3.2Processor / PCH Compatibility Assumptions

The processor is compatible with the PCH and is not compatible with any previous Intel Memory Controller Hub (MCH) and Integrated Controller Hub (ICH) products.

2.3.3DMI2 Link Down

The DMI2 link going down is a fatal, unrecoverable error. If the DMI2 data link goes to data link down, after the link was up, then the DMI2 link hangs the system by not allowing the link to retrain to prevent data corruption. This is controlled by the PCH.

Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal. No completions from downstream, non-posted transactions are returned upstream over the DMI2 link after a link down event.

2.4Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) uses a single wire for self-clocking and data transfer. The bus requires no additional control lines. The physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established with every message. In this way, it is highly flexible even though underlying logic is simple.

The interface design was optimized for interfacing to Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information.

Datasheet

21

Technologies

3 Technologies

This chapter covers the following technologies:

Intel® Virtualization Technology (Intel® VT)

Security Technologies

Intel® Hyper-Threading Technology (Intel® HT Technology)

Intel® Turbo Boost Technology

Enhanced Intel® SpeedStep® Technology

Intel® Advanced Vector Extensions (Intel® AVX)

3.1Intel® Virtualization Technology (Intel® VT)

Intel® Virtualization Technology (Intel® VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets.

Intel® Virtualization Technology (Intel® VT) for Intel® 64 and IA-32 Intel® Architecture (Intel® VT-x) adds hardware support in the processor to improve

the virtualization performance and robustness. Intel VT-x specifications and functional descriptions are included in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at http://www.intel.com/products/processor/manuals/index.htm

Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) adds processor and uncore implementations to support and

improve I/O virtualization performance and robustness. The Intel VT-d specification and other Intel VT documents can be referenced at http://www.intel.com/technology/virtualization/index.htm

3.1.1Intel® VT-x Objectives

Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable virtualized platforms. By using Intel VT-x, a VMM is:

Robust: VMMs no longer need to use para-virtualization or binary translation. This means that off-the-shelf operating systems and applications can be run without any special steps.

Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors.

More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts.

More secure: The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.

22

Datasheet

Technologies

3.1.2Intel® VT-x Features

The processor core supports the following Intel VT-x features:

Extended Page Tables (EPT)

hardware assisted page table virtualization.

eliminates VM exits from guest operating system to the VMM for shadow pagetable maintenance.

Virtual Processor IDs (VPID)

Ability to assign a VM ID to tag processor core hardware structures (such as, TLBs).

This avoids flushes on VM transitions to give a lower-cost VM transition time and an overall reduction in virtualization overhead.

Guest Preemption Timer

Mechanism for a VMM to preempt the execution of a guest operating system after an amount of time specified by the VMM. The VMM sets a timer value before entering a guest.

The feature aids VMM developers in flexibility and Quality of Service (QoS) guarantees.

Descriptor-Table Exiting

Descriptor-table exiting allows a VMM to protect a guest operating system from internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector).

A VMM using this feature can intercept (by a VM exit) attempts to relocate these data structures and prevent them from being tampered by malicious software.

Pause Loop Exiting (PLE)

PLE aims to improve virtualization performance and enhance the scaling of virtual machines with multiple virtual processors

PLE attempts to detect lock-holder preemption in a VM and helps the VMM to make better scheduling decisions

3.1.3Intel® VT-d Objectives

The key Intel VT-d objectives are domain-based isolation and hardware-based virtualization. A domain can be abstractly defined as an isolated environment in a platform to which a subset of host physical memory is allocated. Virtualization allows for the creation of one or more partitions on a single system. This could be multiple partitions in the same operating system, or there can be multiple operating system instances running on the same system – offering benefits such as system consolidation, legacy migration, activity partitioning, or security.

Datasheet

23

Technologies

3.1.3.1Intel® VT-d Features Supported

The processor supports the following Intel VT-d features:

Root entry, context entry, and default context

Support for 4-K page sizes only

Support for register-based fault recording only (for single entry only) and support for MSI interrupts for faults

Support for fault collapsing based on Requester ID

Support for both leaf and non-leaf caching

Support for boot protection of default page table

Support for non-caching of invalid page table entries

Support for hardware based flushing of translated but pending writes and pending reads upon IOTLB invalidation

Support for page-selective IOTLB invalidation

Support for ARI (Alternative Requester ID – a PCI SIG ECR for increasing the function number count in a PCIe* device) to support I/O Virtualization (IOV) devices

Improved invalidation architecture

End point caching support (ATS)

Interrupt remapping

3.1.4Intel® Virtualization Technology Processor Extensions

The processor supports the following Intel VT processor extension features:

Large Intel VT-d Pages

Adds 2MB and 1GB page sizes to Intel VT-d implementations

Matches current support for Extended Page Tables (EPT)

Ability to share processor EPT page-table (with super-pages) with Intel VT-d

Benefits:

Less memory foot-print for I/O page-tables when using super-pages

Potential for improved performance – due to shorter page-walks, allows hardware optimization for IOTLB

Transition latency reductions expected to improve virtualization performance without the need for VMM enabling. This reduces the VMM overheads further and increase virtualization performance.

24

Datasheet

Technologies

3.2Security Technologies

3.2.1Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) Instructions

These instructions enable fast and secure data encryption and decryption, using the Advanced Encryption Standard (Intel AES-NI) which is defined by FIPS Publication number 197. Since Intel AES-NI is the dominant block cipher, and it is deployed in various protocols, the new instructions will be valuable for a wide range of applications.

The architecture consists of six instructions that offer full hardware support for Intel AES-NI. Four instructions support the Intel AES-NI encryption and decryption, and the other two instructions support the Intel AES-NI key expansion. Together, they offer a significant increase in performance compared to pure software implementations.

The Intel AES-NI instructions have the flexibility to support all three standard Intel AES-NI key lengths, all standard modes of operation, and even some nonstandard or future variants.

Beyond improving performance, the Intel AES-NI instructions provide important security benefits. Since the instructions run in data-independent time and do not use lookup tables, the instructions help in eliminating the major timing and cache-based attacks that threaten table-based software implementations of Intel AES-NI. In addition, these instructions make AES simple to implement, with reduced code size. This helps reducing the risk of inadvertent introduction of security flaws, such as difficult-to-detect side channel leaks.

3.2.2Execute Disable Bit

The Intel Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system.

Allows the processor to classify areas in memory by where application code can execute and where it cannot.

When a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage and worm propagation.

3.3Intel® Hyper-Threading Technology (Intel® HT Technology)

The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology) that allows an execution core to function as two logical processors. While some execution resources such as caches, execution units, and buses are shared, each logical processor has its own architectural state with its own set of general-purpose registers and control registers. This feature must be enabled using the BIOS and requires operating system support.

For more information on Intel Hyper-Threading Technology, see

http://www.intel.com/products/ht/hyperthreading_more.htm.

Datasheet

25

Technologies

3.4Intel® Turbo Boost Technology

Intel Turbo Boost Technology is a feature that allows the processor to opportunistically and automatically run faster than its rated operating frequency if it is operating below power, temperature, and current limits. The result is increased performance in multithreaded and single threaded workloads. It should be enabled in the BIOS for the processor to operate with maximum performance.

3.4.1Intel® Turbo Boost Operating Frequency

The processor’s rated frequency assumes that all execution cores are running an application at the thermal design power (TDP). However, under typical operation, not all cores are active. Therefore, most applications are consuming less than the TDP at the rated frequency. To take advantage of the available TDP headroom, the active cores can increase their operating frequency.

To determine the highest performance frequency amongst active cores, the processor takes the following into consideration:

number of cores operating in the C0 state

estimated current consumption

estimated power consumption

die temperature

Any of these factors can affect the maximum frequency for a given workload. If the power, current, or thermal limit is reached, the processor will automatically reduce the frequency to stay with its TDP limit.

Note: Intel Turbo Boost Technology is only active if the operating system is requesting the P0 state. For more information on P-states and C-states, refer to Chapter 4.

3.5Enhanced Intel® SpeedStep® Technology

The processor supports Enhanced Intel SpeedStep® Technology as an advanced means of enabling very high performance while also meeting the power-conservation needs of the platform.

Enhanced Intel SpeedStep Technology builds upon that architecture using design strategies that include the following:

Separation between Voltage and Frequency Changes. By stepping voltage up and down in small increments separately from frequency changes, the processor is able to reduce periods of system unavailability that occur during frequency change. Thus, the system is able to transition between voltage and frequency states more often, providing improved power/performance balance.

Clock Partitioning and Recovery. The bus clock continues running during state transition, even when the core clock and Phase-Locked Loop are stopped, which allows logic to remain active. The core clock can also restart more quickly under Enhanced Intel SpeedStep Technology.

For additional information on Enhanced Intel SpeedStep® Technology, refer to Section 4.2.1.

26

Datasheet

Technologies

3.6Intel® Advanced Vector Extensions (Intel® AVX)

Intel Advanced Vector Extensions (Intel AVX) is a new 256-bit vector SIMD extension of Intel Architecture. The introduction of Intel AVX started with the 2nd Generation Intel® Core™ processor family. Intel AVX accelerates the trend of parallel computation in general purpose applications like image, video and audio processing, engineering applications (such as 3D modeling and analysis), scientific simulation, and financial analysts.

Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture. The main elements of Intel AVX are:

Support for wider vector data (up to 256-bit) for floating-point computation

Efficient instruction encoding scheme that supports 3 operand syntax and headroom for future extensions

Flexibility in programming environment, ranging from branch handling to relaxed memory alignment requirements

New data manipulation and arithmetic compute primitives, including broadcast, permute, fused-multiply-add, and so on

Floating point bit depth conversion (Float 16)

A group of 4 instructions that accelerate data conversion between 16-bit floating point format to 32-bit and vice versa.

This benefits image processing and graphical applications allowing compression of data so less memory and bandwidth is required.

The key advantages of Intel AVX are:

Performance – Intel AVX can accelerate application performance using data parallelism and scalable hardware infrastructure across existing and new application domains:

256-bit vector data sets can be processed up to twice the throughput of 128-bit data sets

Application performance can scale up with the number of hardware threads and number of cores

Application domain can scale out with advanced platform interconnect fabrics

Power Efficiency – Intel AVX is extremely power efficient. Incremental power is insignificant when the instructions are unused or scarcely used. Combined with the high performance that it can deliver, applications that lend themselves heavily to using Intel AVX can be much more energy efficient and realize a higher performance-per-watt.

Extensibility – Intel AVX has built-in extensibility for the future vector extensions:

Operating System context management for vector-widths beyond 256 bits is streamlined

Efficient instruction encoding allows unlimited functional enhancements:

Vector width support beyond 256 bits

256-bit Vector Integer processing

Additional computational and/or data manipulation primitives

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Technologies

Compatibility – Intel AVX is backward compatible with previous ISA extensions including Intel SSE4:

Existing Intel SSE applications/library can:

Run unmodified and benefit from processor enhancements

Recompile existing Intel® SSE intrinsic using compilers that generate Intel AVX code

Inter-operate with library ported to Intel AVX

Applications compiled with Intel AVX can inter-operate with existing Intel SSE libraries.

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Power Management

4 Power Management

This chapter provides information on the following power management topics:

Advanced Configuration and Power Interface (ACPI) States Supported

Processor Core / Package Power Management

System Memory Power Management

Direct Media Interface 2 (DMI2) / PCI Express* Power Management

4.1Advanced Configuration and Power Interface (ACPI) States Supported

The ACPI states supported by the processor are described in this section.

4.1.1System States

Table 4-1. System States

State

Description

 

 

G0/S0

Full On

 

 

G1/S3-Cold

Suspend-to-RAM (STR). Context saved to memory.

 

 

G1/S4

Suspend-to-Disk (STD). All power lost (except wakeup on PCH).

 

 

G2/S5

Soft off. All power lost (except wakeup on PCH). Total reboot.

 

 

G3

Mechanical off. All power removed from system.

 

 

4.1.2Processor Package and Core States

The following table lists the package C-state support as: 1) the shallowest core C-state that allows entry into the package C-state, 2) the additional factors that will restrict the state from going any deeper, and 3) the actions taken with respect to the Ring Vcc, PLL state, and LLC.

Table 4-3 lists the processor core C-states support.

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Power Management

Table 4-2. Package C-State Support

Package C-

Core

 

 

Retentionand

LLC

Notes1

 

Limiting Factors

Fully

State

States

 

 

PLL-Off

Flushed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PC0 – Active

CC0

N/A

 

No

No

2

 

 

 

 

 

 

 

 

• PCIe/PCH and Remote Socket

 

 

 

 

 

 

Snoops

 

 

 

PC2 –

 

• PCIe/PCH and Remote Socket

VccMin

 

 

CC3–CC7

 

Accesses

No

2

Snoopable

Interrupt response time

Freq = MinFreq

Idle

 

PLL = ON

 

 

 

 

requirement

 

 

 

 

 

 

 

 

 

 

DMI Sidebands

 

 

 

 

 

Configuration Constraints

 

 

 

 

 

 

 

 

 

 

 

at least

Core C-State

 

 

 

PC3 – Light

Snoop Response Time

Vcc = retention

No

2, 3, 4

Retention

one Core

Interrupt Response Time

PLL = OFF

in C3

 

 

 

 

• Non Snoop Response Time

 

 

 

 

 

 

 

 

 

 

PC6 -

 

LLC ways open

 

 

 

 

Snoop Response Time

Vcc = retention

 

 

Deeper

CC6–CC7

No

2, 3, 4

Non Snoop Response Time

PLL = OFF

Retention

 

 

 

 

Interrupt Response Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.Package C7 is not supported.

2.All package states are defined to be "E" states – such that the states always exit back into the LFM point upon execution resume

3.The mapping of actions for PC3, and PC6 are suggestions – microcode will dynamically determine which actions should be taken based on the desired exit latency parameters.

4.CC3/CC6 will all use a voltage below the VccMin operational point. The exact voltage selected will be a function of the snoop and interrupt response time requirements made by the devices (PCIe* and DMI) and the operating system.

Table 4-3. Core C-State Support

Core C-State

Global Clock

PLL

L1/L2 Cache

Core VCC

Context

 

 

 

 

 

 

CC0

Running

On

Coherent

Active

Maintained

 

 

 

 

 

 

CC1

Stopped

On

Coherent

Active

Maintained

 

 

 

 

 

 

CC1E

Stopped

On

Coherent

Request LFM

Maintained

 

 

 

 

 

 

CC3

Stopped

On

Flushed to LLC

Request Retention

Maintained

 

 

 

 

 

 

CC6

Stopped

Off

Flushed to LLC

Power Gate

Flushed to LLC

 

 

 

 

 

 

CC7

Stopped

Off

Flushed to LLC

Power Gate

Flushed to LLC

 

 

 

 

 

 

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