8XC196NP, 80C196NU
Microcontroller
User’s Manual
8XC196NP, 80C196NU
Microcontrol ler
User’s Manual
August 2004 Order Number 272479-003
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, i ncluding
infringement of any patent or copyrig ht, for sale and use of Intel products except as provided in Intel’s Terms and Conditions
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© INTEL CORPORATION, 1996
ii
CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.
1 MANUAL CONTENTS ................................................................................................... 1-1
1.
2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
1.
3 RELATED DOCUMENTS .............................................................................................. 1-5
4 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-8
1.
1.4.
4 World Wide Web .....................................................................................................1-11
1.
5 TECHNICAL SUPPORT .............................................................................................. 1-11
6 PRODUCT LITERATURE............................................................................................ 1-11
1.
CHAPTER 2
ARCHITECTURAL
2.
1 TYPICAL APPLICATIONS............................................................................................. 2-1
2 DEVICE FEATURES ..................................................................................................... 2-2
2.
2.
3 BLOCK DIAGRAM......................................................................................................... 2-2
2.3.
1 CPU Control ..............................................................................................................2-3
2.3.
2 Register File ..............................................................................................................2-3
2.3.
3 Register Arithmetic-logic Unit (RALU) .......................................................................2-4
2.3.3.1 Code Execution ....................................................................................................2-4
2 Instruction Format ................................................................................................2-5
2.3.3.
2.3.
4 Memory Controller ....................................................................................................2-5
2.3.
5 Multiply-accumulate (80C196NU Only) .....................................................................2-6
2.3.
6 Interrupt Service ........................................................................................................2-6
2.
4 INTERNAL TIMING........................................................................................................ 2-7
2.
5 INTERNAL PERIPHERALS ......................................................................................... 2-11
2.5.
1 I/O Ports ..................................................................................................................2-11
2.5.
2 Serial I/O (SIO) Port ................................................................................................2-11
2.5.
3 Event Processor Array (EPA) and Timer/Counters .................................................2-11
2.5.
4 Pulse-width Modulator (PWM) ................................................................................2-12
2.
6 SPECIAL OPERATING MODES ................................................................................. 2-12
2.6.
1 Reducing Power Consumption ...............................................................................2-12
2.6.
2 Testing the Printed Circuit Board ............................................................................2-13
7 DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS ...... 2-13
2.
OVERVIEW
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8XC196NP, 80C196NU USER ’S MANUAL
CHAPTER 3
ADVANCED MATH FEATURES
3.1 ENHANCED MULTIPLICATION INSTRUCTIONS........................................................ 3-1
3.2 OPERATING MODES.................................................................................................... 3-2
3.2.1 Saturation Mode ........................................................................................................3-2
3.2.2 Fractional Mode ................................................................................ ........................3-3
3.3 ACCUMULATOR REGISTER (ACC_0
3.4 ACCUMULATOR CONTROL AND STATUS REGISTER (ACC_STAT) ....................... 3-5
CHAPTER 4
PROGRAMMING CONSIDERATIONS
4.1 OVERVIEW OF THE INSTRUCTION SET.................................................................... 4-1
4.1.1 BIT Operands ............................................................................................................4-2
4.1.2 BYTE Operands ........................................................................................................4-2
4.1.3 SHORT-INTEGER Operands .................................................................................... 4-2
4.1.4 WORD Operands ......................................................................................................4-3
4.1.5 INTEGER Operands .................................................................................................4-3
4.1.6 DOUBLE-WORD Operands ......................................................................................4-3
4.1.7 LONG-INTEGER Operands ...................................................................................... 4-4
4.1.8 QUAD-WORD Operands ..........................................................................................4-4
4.1.9 Converting Operands ................................................................................................4-4
4.1.10 Conditional Jumps ....................................................................................................4-4
4.1.11 Floating Point Operations .........................................................................................4-5
4.1.12 Extended Instructions ...............................................................................................4-5
4.2 ADDRESSING MODES . ................................................................................................ 4-6
4.2.1 Direct Addressing ......................................................................................................4-7
4.2.2 Immediate Addressing ..............................................................................................4-7
4.2.3 Indirect Addressing ...................................................................................................4-7
4.2.3.1 Extended Indirect Addressing ..............................................................................4-8
4.2.3.2 Indirect Addressing with Autoincrement ...............................................................4-8
4.2.3.3 Extended Indirect Addressing with Autoincrement ...............................................4-8
4.2.3.4 Indirect Addressing with the Stack Pointer . ..........................................................4-9
4.2.4 Indexed Addressing . .................................................................................................4-9
4.2.4.1 Short-indexed Addressing ....................................................................................4-9
4.2.4.2 Long-indexed Addressin g ....................................................................................4-9
4.2.4.3 Extended Indexed Addressing ...........................................................................4-10
4.2.4.4 Zero-indexed Addressing ................................................................................... 4-10
4.2.4.5 Extended Zero-indexed Addressing ...................................................................4-10
4.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS................................ 4-11
4.3.1 Direct Addressing ....................................................................................................4-11
4.3.2 Indexed Addressing . ...............................................................................................4-11
4.3.3 Extended Addressing . .............................................................................................4-11
4.4 DESIGN CONSIDERATIONS FOR 1-MBYTE DEVICES............................................ 4-11
4.5 SOFTWARE STANDARDS AND CONVENTIONS ..................................................... 4-11
x
).. .............. ........ ....... ....... ........ ....... ....... ....... .... 3-4
iv
CONTENTS
4.5.1 Using Registers .......................................................................................................4-12
4.5.2 Addressing 32-bit Operands ...................................................................................4-12
4.5.3 Addressing 64-bit Operands ...................................................................................4-12
4.5.4 Linking Subroutines ................................................................................................4-13
4.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES .................................... 4-14
CHAPTER 5
MEMORY PARTITIONS
5.1 MEMORY MAP OVERVIEW.......................................................................................... 5-1
5.2 MEMORY PARTITIONS................................................................................................ 5-3
5.2.1 External Memory .......................................................................................................5-5
5.2.2 Program and Special-purpose Memory ....................................................................5-5
5.2.2.1 Program Memory in Page FFH ............................................................................5-5
5.2.2.2 Special-purpose Memory .....................................................................................5-6
5.2.2.3 Reserved Memory Locations ...............................................................................5-7
5.2.2.4 Interrupt and PTS Vectors ........... ............ .................... ............ ................. ............5-7
5.2.2.5 Chip Configuration Bytes ............................................ .........................................5-7
5.2.3 Peripheral Special-function Registers (SFRs) ........................ .................... ...............5-7
5.2.4 Register File ..............................................................................................................5-9
5.2.4.1 General-purpose Register RAM .........................................................................5-11
5.2.4.2 Stack Pointer (SP) .............................................................................................. 5-11
5.2.4.3 CPU Special-function Registers (SFRs) .............................................................5-12
5.3 WINDOWING.................................................................... ........................................... 5-13
5.3.1 Selecting a Window ................................................................................................5-14
5.3.2 Addressing a Location Through a Window ............................................................. 5-16
5.3.2.1 32-byte Windowing Example ..............................................................................5-18
5.3.2.2 64-byte Windowing Example ..............................................................................5-18
5.3.2.3 128-byte Windowing Example ............................................................................5-18
5.3.2.4 Unsupported Locations Windowin g Example (8XC196NP Only) .......................5-19
5.3.2.5 Using the Linker Locator to Set Up a Window ........ ............................................5-19
5.3.3 Windowing and Addressing Modes .........................................................................5-21
5.4 REMAPPING INTERNAL ROM (83C196NP ONLY). .................................................. 5-22
5.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES .............. 5-23
5.5.1 Fetching Instructions ...............................................................................................5-23
5.5.2 Accessing Data .......................................................................................................5-23
5.5.3 Code Fetches in the 1-Mbyte Mode ........................................................................5-25
5.5.4 Code Fetches in the 64-Kbyte Mode ......................................................................5-25
5.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes .................................................5-26
5.6 MEMORY CONFIGURATION EXAMPLES................................................................. 5-27
5.6.1 Example 1: Using the 64-Kbyte Mode ....................................................................5-27
5.6.2 Example 2: A 64-Kbyte System with Additional Data Storage ................................5-29
5.6.3 Example 3: Using 1-Mbyte Mode ............................................................................ 5-31
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8XC196NP, 80C196NU USER ’S MANUAL
CHAPTER 6
STANDARD AND PTS INTERRUPTS
6.1 OVERVIEW OF INTERRUPTS............. ........................... ........................... ................... 6-1
6.2 INTERRUPT SIGNALS AND REGISTERS ................................................................... 6-3
6.3 INTERRUPT SOURCES AND PRIORITIES.................................................................. 6-4
6.3.1 Special Interrupts ........................................................................... ............ ..... ....... ...6-4
6.3.1.1 Unimplemented Opcode ......................................................................................6-5
6.3.1.2 Software Trap .......................................................................................................6-5
6.3.1.3 NMI ................................................................................ .......................................6-6
6.3.2 External Interrupt Pins .... ..........................................................................................6-6
6.3.3 Multiplexed Interrupt Sources ............................................ ................. ................. .....6-6
6.3.4 End-of-PTS Interrupts ...............................................................................................6-6
6.4 INTERRUPT LATENCY................................................................................................. 6-7
6.4.1 Situations that Increase Interrupt Latency ................................................................ 6-7
6.4.2 Calculating Latency ...................................................................................................6-8
6.4.2.1 Standard Interrupt Latenc y ...................................................................................6-8
6.4.2.2 PTS Interrupt Latency ..........................................................................................6-9
6.5 PROGRAMMING THE INTERRUPTS......................................................................... 6-10
6.5.1 Programming Considerations for Multiplexed Interrupts ..................... ....................6-11
6.5.2 Modifying Interrupt Priorities ...................................................................................6-13
6.5.3 Determining the Source of an I nterrupt ...................................................................6-15
6.6 INITIALIZING THE PTS CONTROL BLOCKS ............................................................. 6-17
6.6.1 Specifying the PTS Count ....................................................................................... 6-18
6.6.2 Selecting the PTS Mode .................................................... .....................................6-19
6.6.3 Single Transfer Mode ..............................................................................................6-20
6.6.4 Block Transfer Mode ...............................................................................................6-23
6.6.5 PWM Modes ...........................................................................................................6-26
6.6.5.1 PWM Toggle Mode Example .............................................................................6-27
6.6.5.2 PWM Remap Mode Example .............................................................................6-32
CHAPTER 7
I/O PORTS
7.1 I/O PORTS OVERVIEW ................................................................................................ 7-1
7.2 BIDIRECTIONAL PORTS 1–4 . ...................................................................................... 7-1
7.2.1 Bidirectional Port Operation ......................................................................................7-3
7.2.2 Bidirectional Port Pin Configurations ............ .......... ........ ....... ....... ....... .......... ....... ..... 7-7
7.2.3 Bidirectional Port Pin Configuration Example ...........................................................7-8
7.2.4 Bidirectional Port Considerations ..............................................................................7-9
7.2.5 Design Considerations for External Interrupt Inputs ...............................................7-11
7.3 EPORT ........................................................................................................................ 7-11
7.3.1 EPORT Operation ...................................................................................................7-12
7.3.1.1 Reset ............................................................ ....................................... ...............7-14
7.3.1.2 Output Enable ....................................................................................................7-14
7.3.1.3 Complementary Output Mode ............................................................................7-14
vi
CONTENTS
7.3.1.4 Open-drain Output Mode ...................................................................................7-14
7.3.1.5 Input Mode ................................................................................... .. ....................7-16
7.3.2 Configuring EPORT Pins .................................................................. ......................7-17
7.3.2.1 Configuring EPORT Pins for Extended-address Functions ................................7-17
7.3.2.2 Configuring EPORT Pins for I/O ........................................................................7-17
7.3.3 EPORT Considerations ....................................................................... ....................7-18
7.3.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold .............7-18
7.3.3.2 EP_REG Settings for Pins Configured as Extended-address Signals ...............7-18
7.3.3.3 EPORT Status During Instruction Execution ......................................................7-18
7.3.3.4 Design Considerations .......................................................................................7-19
CHAPTER 8
SERIAL I/O (SIO) PORT
8.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW................................................... 8-1
8.2 SERIAL I/O PORT SIGNALS AND REGISTERS. ......................................................... 8-2
8.3 SERIAL PORT MODES................................................................................................. 8-4
8.3.1 Synchronous Mode (Mode 0) ....................................................................................8-4
8.3.2 Asynchronous Modes (Modes 1, 2, and 3) ...............................................................8-5
8.3.2.1 Mode 1 .................................................................................................................8-6
8.3.2.2 Mode 2 .................................................................................................................8-7
8.3.2.3 Mode 3 .................................................................................................................8-7
8.3.2.4 Mode 2 and 3 Timings ..........................................................................................8-7
8.3.2.5 Multiprocessor Communications . .........................................................................8-8
8.4 PROGRAMMING THE SERIAL PORT.......................................................................... 8-8
8.4.1 Configuring the Serial Port Pins ........................ .......... ............ ............ .......... ............8-8
8.4.2 Programming the Control Register ............................................................................8-8
8.4.3 Programming the Baud Rate and Clock Source .......................................................8-8
8.4.4 Enabling the Serial Port Interrupts ...................................................... ............... ..... 8 -13
8.4.5 Determining Serial Port Status .... ............................................................................8-13
CHAPTER 9
PULSE-WIDTH MODULATOR
9.1 PWM FUNCTIONAL OVERVIEW.................................................................................. 9-1
9.2 PWM SIGNALS AND REGISTERS............................................................................... 9-2
9.3 PWM OPERATION . ....................................................................................................... 9-3
9.4 PROGRAMMING THE FREQUENCY AND PERIOD.................................................... 9-5
9.5 PROGRAMMING THE DUTY CYCLE........................................................................... 9-7
9.5.1 Sample Calculations .................................................................................................9-9
9.5.2 Enabling the PWM Outputs ......... ........................................................ ...................... 9-9
9.5.3 Generating Analog Outputs ......................................................................................9-9
CHAPTER 10
EVENT PROCESSOR ARRAY (EPA)
10.1 EPA FUNCTIONAL OVERVIEW ................................................................................. 10-1
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8XC196NP, 80C196NU USER ’S MANUAL
10.2 EPA AND TIMER/COUNTER SIGNALS AND REGI STERS ....................................... 10-2
10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 10-5
10.3.1 Cascade Mode (Timer 2 Only) .......................... ..... ..... ..... .......................................10-6
10.3.2 Quadrature Clocking Mode .....................................................................................10-6
10.4 EPA CHANNEL FUNCTIONAL OVERVIEW............................................................... 10-8
10.4.1 Operating in Capture Mode .....................................................................................10-9
10.4.1.1 EPA Overruns ..................................................................................................10-11
10.4.1.2 Preventing EPA Overruns ................................................................................10-12
10.4.2 Operating in Compare Mode .................................................................................10-12
10.4.2.1 Generating a Low-speed PWM Output ............................................................10-12
10.4.2.2 Generating a Medium-speed PWM Output .............................. ....... ..... ..... ......10-13
10.4.2.3 Generating a High-speed PWM Output ...........................................................10-14
10.4.2.4 Generating the Highest-speed PWM Output ....................................................10-15
10.5 PROGRAMMING THE EPA AND TIMER/COUNTERS............................................. 10-15
10.5.1 Configuring the EPA and Timer/Counter Port Pins ...............................................10-15
10.5.2 Programming the Timers .......................................................................................10-15
10.5.3 Programming the Capture/Compare Channels .....................................................10-18
10.6 ENABLING THE EPA INTERRUPTS........................................................................ 10-22
10.7 DETERMINING EVENT STATUS.............................................................................. 10-22
10.7.1 Using Software to Service the Multiplexed Overrun Interrupts .............................10-23
10.8 PROGRAMMING EXAMPLES FOR EPA CHANNELS............................................. 10-24
10.8.1 EPA Compare Event Program ..............................................................................10-24
10.8.2 EPA Capture Event Program ................................................................................10-25
10.8.3 EPA PWM Output Program ..................................................................................10-26
CHAPTER 11
MINIMUM HARDWARE CONSIDERATIONS
11.1 MINIMUM CONNECTIONS ......................................................................................... 11-1
11.1.1 Unused Inputs .........................................................................................................11-2
11.1.2 I/O Port Pin Connections ........................................................................................11-2
11.2 APPLYING AND REMOVING POWER ....................................................................... 11-4
11.3 NOISE PROTECTION TIPS. ....................................................................................... 11-4
11.4 THE ON-CHIP OSCILLATOR CIRCUITRY ............................................................... .. 11-5
11.5 USING AN EXTERNAL CLOCK SOURCE.................................................................. 11-7
11.6 RESETTING THE DEVICE.......................................................................................... 11-8
11.6.1 Generating an External Reset .................................................................................11-9
11.6.2 Issuing the Reset (RST) Instruction ......................................................................11-11
11.6.3 Issuing an Illegal IDLPD Key Operand .................................................................11-11
CHAPTER 12
SPECIAL OPERATING MODES
12.1 SPECIAL OPERATING MODE SIGNA LS AND REGI STERS..................................... 12-1
12.2 REDUCING POWER CONSUMPTION....................................................................... 1 2-3
viii
CONTENTS
12.3 IDLE MODE................................................................................................................. 12-5
12.4 STANDBY MODE (80C196NU ONLY)........................................................................ 12-6
12.4.1 Enabling and Disabling Standby Mode . ..................................................................12-6
12.4.2 Entering Standby Mode ..........................................................................................12-6
12.4.3 Exiting Stan dby Mode .................... ....... ....... .......... .......... ....... .......... ....... ........ .......12-7
12.5 POWERDOWN MODE................................................................................................ 12-7
12.5.1 Enabling and Disabling Powerdown Mode ..............................................................12-7
12.5.2 Entering Powerdown Mode .....................................................................................12-7
12.5.3 Exiting Powerdown Mode .......................................................................................12-8
12.5.3.1 Generating a Hardware Reset .... .......................................................................12-8
12.5.3.2 Asserting an External Interrupt Signal ................................................................12-8
12.5.3.3 Selecting C
.....................................................................................................12-10
1
12.6 ONCE MODE............................................................................................................. 12-12
12.7 RESERVED TEST MODES (80C196NU ONLY)....................................................... 12-12
CHAPTER 13
INTERFACING WITH EXTERNAL MEMORY
13.1 INTERNAL AND EXTERNAL ADDRESSES............................................................... 13-1
13.2 EXTERNAL MEMORY INTERFACE SIGNALS........................................................... 13-2
13.3 THE CHIP-SELECT UNIT............................................................................................ 1 3-5
13.3.1 Defining Chip-select Address Ranges ....................................................................13-7
13.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing ....................................13-10
13.3.3 Chip-select Unit Initial Conditions ............................... ..........................................13-11
13.3.4 Initializing the Chip-select Registers ........................................................ ............. 13-11
13.3.5 Example of a Chip-select Setup ............................................................................13-12
13.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES ....... 13-14
13.5 BUS WIDTH AND MULTIPLEXING........................................................................... 13-18
13.5.1 A 16-bit Example System ......................................................................................13-21
13.5.2 16-bit Bus Timings ................................ ...................... ................. ...................... ... 13-22
13.5.3 8-bit Bus Timings ..................................................................................................13-24
13.5.4 Comparison of Multiplexed and Demultiplexed Buses ..........................................13-26
13.6 WAIT STATES (READY CONTROL)......................................................................... 13-26
13.7 BUS-HOLD PROTOCOL........................................................................................... 13-30
13.7.1 Enabling the Bus-hold Protocol .............................................................................13-32
13.7.2 Disabling the Bus-hold Protocol ............................................................................13-32
13.7.3 Hold Latency .........................................................................................................13-32
13.7.4 R egai ni ng Bu s Control ....... .. ..... .. ..... ..... ... .... ... .. ..... ..... ... .... ... ..... .. ..... .. ..... ... ..... .. ... 13-33
13.8 WRITE-CONTROL MODES...................................................................................... 13-33
13.9 SYSTEM BUS AC TIMING SPECIFICATIONS......................................................... 13-36
13.9.1 Deferred Bus-cycle Mode (80C196NU Only) ........................................................13-40
13.9.2 Explanation of AC Symbols ..................................................................................13-42
13.9.3 AC Timing Definitions ...........................................................................................13-42
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8XC196NP, 80C196NU USER ’S MANUAL
APPENDIX A
INSTRUCTION SET REFERENCE
APPENDIX B
SIGNAL DESCRIPTIONS
B.1 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. B-1
B.2 SIGNAL DESCRIPTIONS............................................................................................. B-6
B.3 DEFAULT CONDITIONS............................................................................................ B-13
APPENDIX C
REGISTERS
GLOSSARY
INDEX
x
CONTENTS
FIGURES
Figure Page
2-1 8XC196NP and 80C196NU Block Diagram.................................................................2-2
2-2 Block Diagram of the Core ...........................................................................................2-3
2-3 Clock Circuitry (8XC196NP)......................................................................................... 2-7
2-4 Clock Circuitry (80C196NU).........................................................................................2-8
2-5 Internal Clock Phases ..................................................................................................2-9
2-6 Effect of Clock Mode on CLKOUT Frequency............................................................2-10
3-1 Accumulator (ACC_0
3-2 Accumulator Control and Status (ACC_STAT) Register..............................................3-5
5-1 16-Mbyte Address Space.............................................................................................5-2
5-2 Pages FFH and 00H.....................................................................................................5-3
5-3 Register File Memory Map .............................. ............................................ ...............5-10
5-4 Windowing..................................................................................................................5-13
5-5 Window Selection (WSR) Register.............................................................................5-14
5-6 Window Selection 1 (W SR1) Register........................................................................5-15
5-7 The 24-bit Program Counter.......................... ....... ............... ............ ....... ............... ..... 5-23
5-8 Formation of Extended and Nonextended Addresses................................................5-24
5-9 A 64-Kbyte System With an 8-bit Bu s ........................................................................5-27
5-10 A 64-Kbyte System with Additional Data Storage ......................................................5-29
5-11 Example System Using the 1-Mbyte Mode ................................................................5-31
6-1 Flow Diagram for PTS and Standard Interrupts ...........................................................6-2
6-2 Standard Interrupt Response Time..............................................................................6-9
6-3 PTS Interrupt Response Time......................................................................................6-9
6-4 PTS Select (PTSSEL) Register...... ............................................................................6-11
6-5 Interrupt Mask (INT_MASK) Register.........................................................................6-12
6-6 Interrupt Mask 1 (INT_MASK1) Register......................................... ................. .......... 6-13
6-7 Interrupt Pending (INT_PEND) Register .. .................................................................. 6-16
6-8 Interrupt Pending 1 (INT_PEND1) Register ...............................................................6-17
6-9 PTS Control Blocks ....................................................................................................6-18
6-10 PTS Service ( PTSSRV) Register...............................................................................6-19
6-11 PTS Mode Selection Bi ts (PTSCON Bits 7:5) ............................................................6-20
6-12 PTS Control Block — Single Transfer Mode..............................................................6-21
6-13 PTS Control Block — Block Transfer Mode...............................................................6-24
6-14 A Generic PWM Waveform ................................................. .......................................6-27
6-15 PTS Control Block — PWM Toggle Mode .................................................................. 6-29
6-16 EPA and PTS Operations for the PWM Toggle Mode Example.................................6- 31
6-17 PTS Contr ol Block — PWM Remap Mode.................................................................6-34
6-18 EPA and PTS Operations for the PWM Remap Mode Example................................6-36
7-1 Bidirectional Port Structure...........................................................................................7-5
7-2 EPORT Block Diagram...............................................................................................7-13
7-3 EPORT Structure .......................................................................................................7-15
8-1 SIO Block Diagram .......................................................................................................8-1
8-2 Typical Shift Register Circuit for Mode 0.. ................. ...................... ...................... ....... 8-4
8-3 Mode 0 Timing.............................. .. .......... ....... ..... ..... .......... .. ..... .......... .. .......... ..... .. .....8-5
8-4 Serial Port Frames for Mode 1 .....................................................................................8-6
x
) Register ........................................... .......................................3-4
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8XC196NP, 80C196NU USER ’S MANUAL
FIGURES
Figure Page
8-5 Serial Port Frames in Mode 2 and 3.............................................................................8-7
8-6 Serial Port Control (SP_CON) Register........................................................................ 8-9
8-7 Serial Port Baud Rate (SP_BAUD) Register..............................................................8-11
8-8 Serial Port Status (SP_STATUS) Register ............................ ..................................... 8-14
9-1 PWM Block Diagram (8XC196NP Only).......................................................................9-1
9-2 PWM Block Diagram (80C196NU Only).......................................................................9-2
9-3 PWM Output Waveforms .. ..................................................... ....................................... 9-5
9-4 Control (CON_REG0) Register ....................................................................................9-7
9-5 PWM Control (PW M
9-6 D/A Buffer Block Diagram...........................................................................................9-10
9-7 PWM to Analog Conversion Circuitry.........................................................................9-10
10-1 EPA Block Diagram....................................................................................................10-2
10-2 EPA Timer/Counters ..................................................................................................10-5
10-3 Quadrature Mode Interface................................................................................... .....1 0-7
10-4 Quadrature Mode Timing and Count..........................................................................10-8
10-5 A Single EPA Capture/Compare Channel..................................................................10-9
10-6 EPA Simplifie d Input-capture Structure....................................................................10-10
10-7 Valid EPA Input Events............................................................................................10-10
10-8 Timer 1 Control (T1CONTROL) Register .................................................................10-16
10-9 Timer 2 Control (T2CONTROL) Register .................................................................10-17
10-10 EPA Control (EPA
10-11 EPA Interrupt Mask (EPA_MASK) Register.............................................................10-22
10-12 EPA Interrupt Pending (EPA_PEND) Register.........................................................10-23
11-1 Minimum Hardware Connections...............................................................................11-3
11-2 Power and Return Connections .................................................................................11-4
11-3 On-chip Oscillator Circuit................................................ ..... .......................................11-5
11-4 External Crystal Connections.....................................................................................11-6
11-5 External Clock Connections .......................................................................................11-7
11-6 External Clock Drive Waveforms................................................................................11-7
11-7 Reset Timing Sequence.............................................................................................11-8
11-8 Internal Reset Circuitry................... .......... ....... ..... .......... ..... ....... ..... ....... ..... .......... .. ...11-9
11-9 Minim um Reset Circuit .............................................................................................11-10
11-10 Example System Reset Circuit.................................................................................11-10
12-1 Clock Control During Power-saving Modes (8XC196NP) ..........................................1 2-4
12-2 Clock Control During Power-saving Modes (80C196NU)...........................................12-5
12-3 Power-up and Powerdown Sequence When Using an External Interrupt..................12-9
12-4 External RC Circuit........................................ .............................................................12-9
12-5 Typical Voltage on the RPD Pin While Exiting Powerdown.....................................12-11
13-1 Calculation of a Chip-select Output............................................................................13-6
13-2 Ad dress Compare (ADDRCOM
13-3 Address Mask (ADDRMSK
13-4 Bus Control (BUSCON
13-5 Example System for Setting Up Chip-s elect Outputs...............................................13-13
13-6 Chip Configuration 0 (CCR0) Register .....................................................................13-15
x
_CONTROL) Register................................................................9-8
x
_CON) Registers .......................................................................10-19
x
) Register ................................................................13-7
x
) Regi st er ........ .. ....... ........ .. ....... ... ....... ....... ... ....... ... .......13-8
x
) Register............................................................................13-10
xii
CONTENTS
FIGURES
Figure Page
13-7 Chip Configuration 1 (CCR1) Register .....................................................................13-16
13-8 Multiplexing and Bus Width Options.........................................................................13-19
13-9 Bus Activit y for F our Types of Buses........................................................................13-20
13-10 1 6-bit External Devices in Demultiplexed Mode... ....................................................13-22
13-11 Timings for Multiplexed and Demultiplexed 16-bit Buses (8XC196NP) ...................13-23
13-12 Timings for Multiplexed and Demultiplexed 8-bit Buses (8XC196NP) .....................13-25
13-13 READY Tim ing Diagram — Multiplexed Mode.........................................................13-28
13-14 READY Timing Diagram — Demultiplexed Mode (8XC196NP). ..............................13-29
13-15 READY Timing Diagram — Demultiplexed Mode (80C196NU). ..............................13-30
13-16 HOLD#, HLDA# Timing ............................................................................................13-31
13-17 Write-control Signal Waveforms...............................................................................13-34
13-18 Decoding WRL# and WRH#.....................................................................................13-35
13-19 A System with 8-bit and 16-bit Buses.......................................................................13-36
13-20 Multiplexed System Bus Timing (8XC196NP).......................................................... 13-37
13-21 Multiplexed System Bus Timing (80C196NU)..........................................................13-38
13-22 Demulti ple xed System Bus Timing (8XC196NP).....................................................13-39
13-23 Demulti plexed System Bus Timing (80C196NU).................................... ..................13-40
13-24 Deferr e d Bus-cycle Mode Timing Diagram (80C196NU) .........................................13-41
B-1 8XC196NP 100-lead SQFP Package..........................................................................B-2
B-2 8XC196NP 100-lead QFP Package............................................................................ B-3
B-3 80C196NU 100-lead SQFP Package..........................................................................B-4
B-4 80C196NU 100-lead QFP Package............................................................................B-5
xiii
8XC196NP, 80C196NU USER ’S MANUAL
TABLES
Table Page
1-1 Handbooks and Product Information . .. ..... ..... ....... ..... ..... ....... ..... ..... ....... ..... ..... ..... .......1-6
1-2 Application Notes, Application Briefs, and Article Reprints ..........................................1-6
1-3 MCS
1-4 MCS
1-5 MCS
2-1 Features of the 8XC196NP and 80C196NU.................................................................2-2
2-2 State Times at Various Frequencies ............................................................................2-9
2-3 Relationships Between Input Frequency, Clock Multiplier, and State Times.............2-10
3-1 Multiply/Accumulate Example Code.............................................................................3-2
3-2 Effect of SME and FME Bit Combinations....................................................................3-6
4-1 Operand Type Definitions.............................................................................................4-1
4-2 Equivalent Operand Types for Assembly and C Programming Languages.................4-2
4-3 Definition of Temporary Registers................................................................................4-7
5-1 8XC196NP and 80C196NU Memory Map....................................................................5-4
5-2 Program Memory Access for the 83C196NP ............................................................... 5-5
5-3 8XC196NP and 80C196NU Special-purpose Memory Addresses...............................5-6
5-4 Special-purpose Memory Access for the 83C196NP...................................................5-6
5-5 Peripheral SFRs...........................................................................................................5-8
5-6 Register File Memory Addresses ...............................................................................5-11
5-7 CPU SFRs..................................................................................................................5-12
5-8 Selecting a Window of Peripheral SFRs..................................................................... 5-15
5-9 Selecting a Window of the Upper Register File.. ........................................................5-15
5-10 Windows.....................................................................................................................5-17
5-11 Windowed Base Addresses .......................................................................................5-18
5-12 Memory Map for the System in Figure 5-9.. ............................................................ ...5 -28
5-13 Memory Map for the System in Figure 5-10...............................................................5-30
5-14 Memory Map for the System in Figure 5-11...............................................................5-32
6-1 Interrupt Signals .............................................. ............................................................. 6-3
6-2 Interrupt and PTS Control and Status Registers.......................................................... 6-3
6-3 Interrupt Sources, Ve ctors, and Priorities.................. ............ .......... ............ ............ ..... 6-5
6-4 Execution Times for PTS Cycles............................................................ ....................6-10
6-5 Single Transfer Mode PTSCB....................................................................................6-23
6-6 Block Transfer Mode PTSCB.....................................................................................6-23
6-7 Comparison of PWM Modes.......................................................................................6-26
6-8 PWM Toggle Mode PTSCB........................................................................................6-28
6-9 PWM Remap Mode PTSCB.......................................................................................6-33
7-1 Device I/O Ports ...................... ....... ..... ........ .... ........ ....... ..... ....... ..... ....... ..... ........ .... ..... 7- 1
7-2 Bidirectional Port Pins .................. ........................................................................... .....7-2
7-3 Bidirectional Port Control and Status Registers ... ........................................................7-3
7-4 Logic Table for Bidire ctional Ports in I/O Mode............................................................7-6
7-5 Logic Table for Bidire ctional Ports in Special-function Mode .......................................7-6
7-6 Control Register Valu es for Each Configuration. ..........................................................7-8
7-7 Port Configuration Example ......................................................................................... 7-8
7-8 Port Pin States After Reset and After Example Code Execution..................................7-9
®
96 Microcontroller Datasheets (Commercial/Express)......................................1-7
®
96 Microcontroller Datasheets (Automotive).....................................................1-7
®
96 Microcontroller Quick References. ...............................................................1-8
xiv
CONTENTS
TABLES
Table Page
7-9 EPORT Pins...............................................................................................................7-11
7-10 EPORT Contr ol and Status Registers........................................................................7-12
7-11 L ogic Table for EPORT in I/O Mode...........................................................................7-16
7-12 L ogic Table for EPORT in Address Mode ..... ...................... ................... ................. ...7 -16
7-13 Co nfiguratio n Register Settings for EPORT Pins.......................................................7-17
8-1 Serial Port Signals........................................................................................................ 8-2
8-2 Serial Port Control and Status Registers......................................................................8-2
8-3 SP_BAUD Values When Using the Internal Clock at 25 MHz....................................8-12
8-4 SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only) ......8-13
9-1 PWM Signals................................................................................................................9-2
9-2 PWM Control and Status Registers ........................................................ ...................... 9-3
9-3 PWM Output Frequencies (8XC196NP)....................................................................... 9-6
9-4 PWM Output Frequencies (80C196NU) .......................................................................9-6
9-5 PWM Output Alternate Functions........................................................... ...................... 9-9
10-1 EPA and Timer/Counter Signals.................................................................................10-2
10-2 EPA Control and Status Registers .............................................................................10-3
10-3 Quadrature Mode Truth Table....................................................................................10-7
10-4 Action Taken when a Valid Edge Occurs.................................................................10-11
10-5 E xample Co ntrol Register Settings and EPA Operations.........................................10-18
11-1 Minim um Required Signals.........................................................................................1 1-1
11-2 I/O Port Configuration Guide ......................................................................................11-2
12-1 Operating Mode Control Signals ................................................................................1 2-1
12-2 Operati ng Mode Control and Status Registers...........................................................12-2
12-3 80C196NU Clock Modes..........................................................................................12-13
13-1 E xample of Internal and External Addresses.............................................................13-1
13-2 External Memory Interface Signals.............................................................................13-2
13-3 Chip-select Registers............................................................................................ .. ...13-6
13-4 ADDRCOM
13-5 ADDRMSK
13-6 Base Addresses for Several Sizes of the Address Range.........................................13-9
13-7 BUSCON
13-8 BUSCON
13-9 Results for the Chip-select Example........................................................................13-14
13-10 Comparison of AC Timi ngs for Demultiplexed and Multiplexed 16-bit Buses ..........13-26
13-11 READY Signal Timing Definitions........................................................... ................. .13-27
13-12 HOLD#, HLDA# Timing Definitions ..........................................................................13-31
13-13 Maximum Hold Latency............................................................................................13-33
13-14 Write Signals for Standard and Write Strobe Modes ...... ............ ............ .......... ........ 13-34
13-15 AC Timing Symbol Definitions..................................................................................13-42
13-16 AC Timing Definitions...............................................................................................13-42
A-1 Opcode Map (Left Half)......................................................... ...................... ................ A-2
A-1 Opcode Map (Right Half).. ...................................................................... ..................... A-3
A-2 Processor Status Word (PSW) Flags.......................................................................... A-4
A-3 Effect of PSW Flags or Specified Conditions o n Conditional Jump Instructions.........A-5
x
Addresses and Reset Values................................................................13-7
x
Addresses and Reset Values................................................................13-8
x
Addresses and Reset Values.................................................................13-11
x
Registers for the Example System.........................................................13-13
xv
8XC196NP, 80C196NU USER ’S MANUAL
TABLES
Table Page
A-4 PSW Flag Setting Symbols .........................................................................................A-5
A-5 Operand Variables ...................................................................................................... A-6
A-6 Instructi on Set ........ ....... ..... ..... ....... ..... ..... ....... ..... ..... .......... .. ..... .......... .. ..... .......... .. .... A-7
A-7 Instructi on Opcodes ..................................................................................................A-47
A-8 Instruction Lengths and Hexadecimal Opcodes........................................................A-53
A-9 Instruction Executio n Times (in State Times)............................................................ A-60
B-1 8XC196NP and 80C196NU Signals Arranged by Function......................................... B-1
B-2 Description of Columns of Table B-3... ........................................................................B-6
B-3 Signal Descriptions...................................................................................................... B-6
B-4 Definition of Status Symbols .....................................................................................B-13
B-5 8XC196NP and 80C196NU Pin Status..................................................................... B-13
C-1 Module s and Related Registers.................................................................................. C- 1
C-2 Register Name, Address, and Reset Status............................................................ ....C-2
C-3 ACC_0
C-4 Effect of SME and FME Bit Combinations...................................................................C-7
C-5 ADDRCOM
C-6 ADDRMSK
C-7 BUSCON
C-8 EPA
C-9 EPA
C-10 P
C-11 P
C-12 Special-function Signals for Ports 1–4...... ..... ..... ..... ..... ..... .... ..... ..... ..... ....... ..... ..... .. ..C-31
C-13 P
C-14 P
C-15 PWM
C-16 SP_BAUD Values When Using the Internal Clock at 25 MHz...................................C-43
C-17 TIMER
C-18 WSR Settings and Direct Addresses for Windowable SFRs.....................................C-49
C-19 WSR1 Settings and Direct Addresses for Windowable SFRs................................... C-52
x
Addresses and Reset Values........................................................................C-5
x
Addresses and Reset Values.................................................................C-8
x
Addresses and Reset Values.................................................................C-9
x
Addresses and Reset Values..................................................................C-10
x
_CON Addresses and Reset Values................................................................C-23
x
_TIME Addresses and Reset Values................................................................C-24
x
_DIR Addresses and Reset Values.......................................................................C-30
x
_MODE Addresses and Reset Values..................................................................C-31
x
_PIN Addresses and Reset Values.......................................................................C-32
x
_REG Addresses and Reset Values.....................................................................C-33
x
_CONTROL Addresses and Reset Values.....................................................C-38
x
Addresses and Reset Values......................................................................C-48
xvi
Guide to This Manual
1
CHAPT ER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC196NP and 80C196NU embedded microcontrollers. It is intended
for use by both software and hardware designers familiar with the principles of microcontrollers.
This chapter describes w hat you’ll find in this man ual, lists other documents tha t ma y be useful,
and explains how to access the support services we provide to help you complete your design.
1.1 MANUAL CONTENTS
This manual contai ns several chapters and appen dixes, a glossary, and an index. This chapter,
Chapter 1, provides an ov e rview of the manua l. Thi s section su m mariz es the conte nts of the remaining chapters and appendixes. The remainder of this chapter describes notational conventions
and terminology used throughout the manual, provides references to related documentation, describes custome r support services, and explains how to access information and assi stance .
Chapter 2 — Architectural Overvi ew — provides an over view of the device hardware. It describes the core, internal timing, int ernal periphera ls, and special operati ng modes.
Chapter 3 — Advanced Math Features — describes the advanced mathematical features of the
80C196NU. The 80C19 6NU is the first m ember of the MCS
corporate enhanced 16-bit multiplication instructions for performing multiply-accumulate operations and a dedicated, 32-bit accumulator register for storing the results of these operations. The
accumulator and the enhanc ed ins tructions combi ne to decre ase the amount o f time required to
perform multiply-accumulate operati ons. The instructions a nd accumulat or support signed and
unsigned integers as wel l as signed fractional data.
Chapter 4 — Programming Considerations — provides an overview of the instruction set, describes general standards a nd conventions, and defines the operand types and addressing modes
supported by the MCS
tion set, see Appendix A.)
Chapter 5 — Me m ory Par titions — describe s the ad d ressable me mory spa ce of the device . It
describes the memory partitions, explains how to use windows to increase the amount of memory
that can be accessed with direct addressing, and provides exam ples of memo ry configurations.
Chapter 6 — Standard and PTS Interrupts — describes the interrupt control circuitry, priority
scheme, and timing for standard and perip heral transaction server (PTS) inte rrupts. It also explains interrupt programming and control.
Chapter 7 — I/O Ports — describes the input/out put ports and explains how to configure the
ports for input, output, or special functions.
®
96 microcontroller family . (For additional information about the instruc-
®
96 microcontroller fam ily to in-
1-1
8XC196NP, 80C196NU USER’S MANUAL
Chapter 8 — Serial I/O (SIO) Port — describes the asynchronous/synchronous serial I/O (SIO)
port and expla ins how to program it.
Chapter 9 —Pulse-width Modulator — provides a functional overview of the pulse width modulator (PWM) modules, descri bes how to program them, and provides sample circuitry for con verting the PWM outputs to analog signals.
Chapter 10 — Eve nt Processor Array (E PA) — de scribes the event processor array, a timer/counter-based, high-speed input/output u nit. It de scri bes t he time r/c ounters and explains h o w
to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs.
Chapter 11 — Minimum Hardware Considerations — describes options for providing the basic requirements for devi ce operat ion w ithin a system , discuss es other hardware considerations,
and describes device reset o ptions.
Chapter 12 — Spec ial Operating Modes — provides an overview of the idle, powerdown,
standby, and on-circuit emulation (ONCE) modes and describes how to enter and exit each mode.
Chapter 13 — Interfacing with External Memory — lists the external memory signals and describes the registers that control the external memory interface. It discusses the chip selects, multiplexed and demultiplexed bus modes, bus width and memory configurations, the bus-hold
protocol, write-control modes, and internal wait states and ready control. Finally, it provides timing informat ion for the system bus.
Appendix A — Instruction Set Reference — provides reference information for the instruction
set. It describes each instruction; defines the processor sta tus word (PSW) flags; shows the relationships between instructions and PSW flags; and lists hexadecimal opcodes, instruction
lengths, and execution times. (For additional information about the instruction set, see Chapter 4,
“Programming Consideratio ns.”)
Appendix B — Signal Descr iptions — provides referenc e information for the device pins, including descriptions of the pin functions, reset status of the I/O and control pins, and package pin
assignments.
Appendix C — Re gisters — provides a compilation of all device special-function registers
(SFRs) arranged alphabeti cally by register mnemonic . It also includes tables that list the windowed direct addresses for all SFRs in each possible window.
Glossary — define s terms with spec ial me aning used th roughout this manual.
Index — lists key topics with page number references.
1-2
GUIDE TO THIS MANUAL
1.2 N O TATIO NAL CONV ENTI ONS AND TERMINOLOGY
The following notations an d terminol ogy are used throughout this manual. The Glossary defines
other terms with special meanings.
# The pound symbol (#) has either of two meanings, depending on the
context. When used wi th a signal name, the symbol means that the
signal is active low. When used in an instruction, the symbol prefixes
an immediate value in immediate addressing mode.
addresses In this manual, both internal and external addresses use the number
of hexadecimal digits that correspond with the number of available
address lines. For example, the highe st possible internal address i s
shown as FFFFFFH, while the highest possible external address is
shown as FFFFFH. When w riting code, use the appropriate address
conventions for the software tool you are using. (In general,
assemblers require a zero preceding an alphabetic hexadecimal
character and an “H” following any hexadecimal value, so FFFFFFH
must be written as 0FF FFFFH. ANSI ‘C’ compilers require a z ero
plus an “x” precedin g a hexadecimal value, so FFFFFFH must be
written as 0xFFFFFF.) Consult the manual for your assembler or
compiler to determine its specific requirement s.
assert and deassert The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active
polarity (low or high) is defined by the signal name. Active-low
signals are designated by a pound symbol (#) suffix; active-high
signals have no suffix. To assert RD# is to drive it low; to assert ALE
is to drive it high; to deassert RD# is to drive it high; to deassert ALE
is to drive it low.
clear and set The terms clear and set refer to the val ue of a bit or the act of giving
it a value. If a bit is c lear, it s val ue is “0”; cleari ng a bit gi ves it a “0”
value. If a bit is set, its value is “1”; settin g a bit gives it a “1” value.
f Lowercase “f” represents the internal operating frequency. See
“Internal Timing” on page 2-7 for details.
instructions Instruction mnem onics are shown in upper case to av oid confusion.
In general, you may use either upper case or lower case when
programming. Consult the manual for your assembl er or compiler to
determine its specific req uirem ent s.
1-3
8XC196NP, 80C196NU USER’S MANUAL
italics Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible
meanings.
Variables in registers and signal names are commonly repres ented by
x and y, where x represents the first variable and y represents the
second variable . For example, in register P x_MODE.y, x represent s
the variable that identifies the specific port associated with the
register, and y represents the register bit variable (7:0 or 15:0).
Variables must be replace d with the correct values when configuring
or programming regi sters or ident ifyi ng signals.
numbers Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are
represented by t heir customa ry notations. (That is, 255 is a decimal
number and 1111 1111 is a binary number. In some cases, the letter B
is appended to binary numbers for clarity.)
register bits Bit locatio ns are indexed by 7:0 (or 15:0), where bit 0 is the least-
significant bit and bit 7 (or 15) is the most-significant bit. An
individual bit is represented by the register name, followed by a
period and the bit number. For example, WSR.7 is bit 7 of the
window selection register. In some discuss ions, bit names are used.
register names Register mnemonics are shown in upper case. For example, TIMER2
is the timer 2 register; timer 2 is the timer . A register name containing
a lowercase italic character represents more than one register. For
example, the x in Px_REG indicate s that the register name re fers to
any of the p ort data registers.
reserved bits Certain bits are described a s reserved bits. In illustrat ions, reserved
bits are indicated with a dash (—). These bits are not used in this
device, but they may be used in future implementations. To help
ensure that a current software design is compatible with future implementations, rese rved bits should be c leared (given a value of “0”) or
left in thei r de fault states, unl es s ot herwis e not ed. D o not rel y o n the
values of reserved bits; conside r them undefin ed.
signal names Signal names are shown in upper case. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number. For example, the EPA signals are named
EPA0, EPA1, EPA2, etc. Port pins a re repres ente d by t he p ort ab breviation, a period, a nd the pin number (e.g., P1.0, P 1.1); a range of
pins is represented by Px.y:z (e.g., P1.4:0 represents five port pins:
P1.4, P1.3, P1.2, P1.1, P1.0). A pound symbol (#) appended to a
signal name identifies an active-low signal.
1-4
GUIDE TO THIS MANUAL
t Lowercase “t” represents the internal operating period. See “Internal
Timing” on page 2-7 for details.
units of measure The following abbreviations are used to represent units of measure:
A amps, ampere s
DCV direct curre nt volts
Kbytes kilobytes
kHz kilohertz
kΩ kilo-ohms
mA milliamps, milliamperes
Mbytes megabytes
MHz megahertz
ms milliseconds
mW milliwatts
ns nanoseconds
pF picofarads
W watts
V volts
µA microamps, microam peres
µF microfarads
µs microseconds
µW microwatts
X Uppercase X (no italics) represents an unknown value or an
irrelevant (“don ’t care”) state o r condition. The val ue may be eit her
binary or hexadecimal, depending on the context. For example,
2XAFH (hex) indicates that bits 11:8 are unknown; 10XXB (binary)
indicates that the two least-significant bits are unknown.
1.3 RELATED DOCUMENTS
The tables in this section list additional documents that you may find useful in designing systems
incorporating MCS 96 microcontrollers. These are not comprehensive lists, but are a representative sample of relevant documents. For a complete list of available printed documents, please order the literature catalog (order number 210621). To order documents, please call the Intel
literature center for your area (telephone numbers are listed on page 1-11).
Intel’s ApBUILDER software, hypertext manuals and datasheets , and electronic versions of application notes and code examples are also available from the BBS (see “Bulletin Board System
(BBS)” on page 1- 9). New inform ation is available first from FaxBa ck and the BB S. Refer to
“Electronic Support Systems” on page 1-8 for details.
1-5
8XC196NP, 80C196NU USER’S MANUAL
Table 1-1. Handbooks and Product Information
Title and Description Order Number
Intel Embedded Quick Reference Guide
Solution s for Embedd ed Appl icat io ns Guide
Data on Demand
Data on Demand
Complete set of Intel handbooks on CD-ROM.
Handboo k Set
Complete set of Intel’s product line handbooks. Contains datasheets, application
notes, article reprints and other desig n informatio n on microprocessors, peripherals, embedded controllers, memory components, single-board computers,
microcommunications, software development tools, and operating systems.
Automotive Products
Application notes and article reprints on topics including the MCS 51 and MCS 96
microcon trol le r s. Docu men t s in this handb ook discuss hardware and software
implementations and present helpful design techniques.
Embedded Applications
Datasheets, architecture descriptions, and application notes on topics including
flash memor y device s, netwo rkin g chips, an d MCS 51 and MCS 96 microc ontrollers. Documents in this handbook discuss hardware and software implementations and present helpful design techniques.
Embedded Microcontrollers
Datasheets and architecture descriptions for Intel’s three industry-standard microcontrollers, the MCS 48, MCS 51, and MCS 96 microcontrollers.
Peripheral Components
Comprehensive information on Intel’s peripheral components, including
datasheets, application notes, and technical briefs.
Flas h Memory
A collection of datasheets and application notes devoted to techniques and
information to help design semiconductor memory into an application or system.
Packaging
Detailed information on the manufacturing, applications, and attributes of a variety
of semiconductor packages.
Development Tools Handbook
Information on third-party hardware and software tools that support Intel’s
embedded microcontrollers.
†
Included in handbook set (order num be r 231003)
fact sheet 240952
annual subscription (6 issues; Windows* version)
— ha ndbooks and product overview
†
†
(2 volume set)
†
handbook (2 volume set)
†
†
†
272439
240691
240897
231003
231792
270648
270646
296467
210830
240800
272326
AB-71,
AP-125,
AP-155,
AR-375,
AP-406,
†
Included in
††
Included in
†††
Included in
1-6
Table 1-2. Application Notes, Application Briefs, and Article Reprints
Title Order Number
Using the SIO on the 8XC196MH
Design Microcontroller Systems for Electrically Noisy Environments
Oscillators for Microcontrollers
Motor Controllers Take the Single-Chip Route
MCS® 96 Analog Acquisition Primer
Automotive Products
Embedded Applications
Automotive Products
(application brief) 272594
†††
†††
(article reprin t) 270056
†††
handbook (order number 231792)
handbook (order number 270648)
and
Embedded Applications
handbooks
210313
230659
270365
GUIDE TO THIS MANUAL
Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued)
Title Order Number
AP-445,
AP-449,
8XC196KR Peripherals: A User’s Point of View
A Comparison of the Event Processor Array (EPA) and High Speed
Input/Output (HSIO) Unit
AP-475,
Using the 8XC196NT
AP-477,
AP-483,
AP-700,
AP-711,
AP-715,
†
††
†††
Low Voltage Embedded Design
Application Examples Using the 8XC196MC/MD Microcontroller
Intel Fuzzy Logic Tool Simplifies ABS Design
EMI Design Techniques for Microcon tro llers in Auto mo ti ve Appl icat io ns
Interfacing an I2C Serial EEPROM to an MCS® 96 Microcontroller
Included in
Included in
Included in
Automotive Products
Embedded Applications
Automotive Products
†
††
††
handbook (order number 231792)
handbook (order number 270648)
and
Embedded Applications
†
†
handbooks
Table 1-3. MCS® 96 Microcontroller Datasheets (Commercial/Express)
Title Order Number
8XC196KR/K Q/JR/ JQ Commercia l/E xpress CHMOS Micro co ntrolle r
8XC196KT Com mercia l CHMOS Microcontro ller
†
87C196KT /87C1 96 KS 20 MHz Advan ced 16-Bit CHMOS Micro co ntrol ler
8XC196MC Industrial Motor Control Microcontroller
†
87C196M D Industrial Motor Control CHMOS Microcontro ll er
8XC196NP Commercial CHMOS 16-Bit Microcontroller
†
8XC196NT CHMOS Microcontroller with 1-Mbyte Linear Address Space
80C196NU Commercial CHMOS 16-Bit Microcontroller
†
Included in
Embedded Microcontro llers
handbook (order number 270646)
†
†
†
†
270873
270968
272315
272324
272282
272595
272324
272680
270912
272266
272513
272323
270946
272459
272267
272644
Table 1-4. MCS® 96 Microcont rol ler Datasheets (Automotive)
Title and Description Order Number
87C196CA/87C196CB 20 MH z Advanced 16-Bi t CHMO S Micro con troller with
Integrated CAN 2.0
87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller
87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller
87C196KR/KQ, 87C196JV/JT, 87C196JR/JQ Advanced 16-Bit CHMOS
Microcontroller
87C196KT/87C196KS Advanced 16-Bit CHMOS Microcontroller
87C196KT/KS 20 MHz Advanced 16-Bit CHMOS Microcontroller
†
Included in
Automotive Products
†
†
†
†
†
†
handbook (order number 231792)
272405
272529
272580
270827
270999
272513
1-7
8XC196NP, 80C196NU USER’S MANUAL
Table 1-5. MCS® 96 Microcontroller Quick References
Title and Description Order Number
8XC196KR Quick Reference
8XC196KT Quick Reference
8XC196MC Quick Reference
8XC196NP Quick Reference
8XC196NT Quick Reference
(includes the JQ, JR, KQ, KR) 272113
272269
272114
272466
272270
1-8
GUIDE TO THIS MANUAL
Page Intentionally Left Blank
1-9
8XC196NP, 80C196NU USER’S MANUAL
Page Intentionally Left Blank
1-10
GUIDE TO THIS MANUAL
1.4.4 World Wide Web
We offer a variety of information through the W or ld Wide W eb (URL:http://www.intel.com/). Select “Embedded Design Products” from the Intel home page.
1.5 TECHNICAL SUPPO RT
In the U.S. and Canada, technical support representatives are availabl e to answer your questions
between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice
telephone number and indicate whether you prefer a response b y phone or by fax). Outside the
U.S. and Canada, please contac t your local distribut or.
1-800-628-8686 U.S. and Canada
916-356-7599 U.S. and Canada
916-356-6100 (fax) U.S. and Canada
1.6 PRODUCT LITER AT URE
You can order product literature from the following Intel literature centers.
1-800-468-8118, ext. 283 U.S. and Canada
708-296-9333 U.S. (from overseas)
44(0)1793-431155 Europe (U.K.)
44(0)1793-421333 Germany
44(0)1793-421777 France
81(0)120-47-88-32 Japan (fax only)
1-11
Architectural
Overview
2
CHAPT ER 2
ARCHITECTURAL OVERVIE W
The 16-bit 8XC196NP and 80C196NU CHMOS microcontrol lers are designed to handle highspeed calculations and fast input/output (I/O) operations. They share a common architecture and
instruction se t with other me mbers of the MC S
16-bit address/data buses, both microcontrollers have extended addressing ports consisting of 4
external address pins, for a total of 20 address pins. With 20 address pins, these microcontrollers
can access up to 1 M byte of linear address spa ce. Both devi ces also have chip-selec t units that
provide a glueless interface to external memory devices. The extended addressing port and chipselect unit enable these microcont rollers to handle larger, more complex programs and to acces s
more external memory at a faster rate than could earli er MCS 9 6 microcont rollers.
The 8XC196NP and 80C196NU are pin-compatible and have identical cores. However, the
80C196NU can operate at twice the frequency of the 8XC196NP. The 80C196NU also employs
an accumulator an d enhanc ed m ultiplicat ion instruct ions to support m ultiply-ac cumul ate ope rations. The 80C196NU is the first MCS 96 microcontroller with this capability. This chapter provides a high-level overview of the architecture .
2.1 TYPICAL APPLICATIONS
MCS 96 microcont rollers are t ypically use d for high-speed event control s ystems. Commerci al
applications include modems, motor-control systems, printers, photocopiers, air conditioner control systems, disk drives, and medical instruments. Automotive customers use MCS 96 microcontrollers in engi ne-control systems, airba gs, suspension systems, and a ntilock braking system s
(ABS).
®
96 microcontroller family. In addition to their
2-1
8XC196NP, 80C196NU USER’S MANUAL
2.2 DEVICE FE ATURES
Table 2-1 lists the features of the 8XC196NP and 80C196NU.
Table 2-1. Features of the 8XC196NP and 80C196NU
Device Pins
8XC196N P 100 4 K 10 2 4 64 4 1 3 6 4
80C196NU 10 0 0 1024 64 4 1 3 6 4
NOTES:
1. Nonvolatile memory is optional for the 8XC196NP, but is not available for the 80C196NU. The second
character of t he device name indicates the presence and typ e of nonvolatile memory. 80C196NP =
none; 83C196NP = ROM.
2. Re gister RAM amoun ts include the 24 byte s allocated to core spe cial-function re gisters (SFRs) and
the stack pointer.
3. I /O pins include address, dat a, and bus control pins and 32 I/O port pins.
ROM
(Note 1)
Register
RAM
(Note 2)
I/O Pins
(Note 3)
EPA
Pins
SIO
Ports
PWM
Channels
Chip-
select
Pins
External
Interrupt
Pins
2.3 BL OCK DIA GR AM
Figure 2-1 shows the major blocks within the device. The core of the device (Figure 2-2) consists
of the central processing unit (CPU) and memory controller. The CPU contains the regis ter file
and the register arithmetic-logic unit (RALU). The CPU connects to both the memory controller
and an interrupt controller via a 16-bit internal bus. An extension of this bus connects the CPU to
the internal peripheral modules. In addition, an 8-bit internal bus transfers instruction bytes from
the memory controller to the instruct ion regist er in the RALU.
2-2
Core
Clock and
Power Mgmt.
I/O
Optional
SIO
ROM
PWM
Interrupt
Controller
PTS
EPA
Figure 2-1. 8XC196NP and 80C196NU Block Diagram
A2801-01
ARCHITECTURAL OVERVIEW
Memory Controller
Prefetch Queue
Slave PC
Address Register
Data Register
Bus Controller
A2797-01
Register File
Register
RAM
CPU SFRs
Figure 2-2. Block Diagram of the Core
CPU
RALU
Microcode
Engine
ALU
Master PC
PSW
Registers
2.3.1 CPU Control
The CPU is controlled by the microcode engine, which instructs the RALU to perform operations
using bytes, words, or double words from either the 256-byte lower register fi le or through a win-
dow that directly accesses the upper register file. (See Chapter 5, “Memory Partitions,” for more
information about the register file and windowing.) CPU instruct ions move from the 4-byte (for
the 8XC196NP) or 8-byte (for the 80C196NU) prefetch queue in the memory controll e r into the
RALU’s instruction register. The microcode e n gine decodes the inst ruc tio ns and then generates
the sequence of events that cause desired functi ons to occur.
2.3.2 Register File
The register file is divided into an upper and a lower file. In the lower register file, the l owest 24
bytes are allocated to the CPU’s special-function registers (SFRs) and the stack pointer, while the
remainder is available as general -purpose register RAM. The upper register file cont ains only
general-purpose register RAM. The register RAM can be accessed as bytes, words, or double words.
The RALU accesses the upper and lower register files differently. The lower register file is always
directly accessible with direct addressing (see “Addressing Modes” on page 4-6). The upper register file is accessible with direct addressing only when windowing is enabled. Window ing is a
technique that maps blocks of the upper register file into a window in the lower regist er file. See
Chapter 5, “Memory Partitions,” for more information about the register file and windowing.
2-3
8XC196NP, 80C196NU USER’S MANUAL
2.3.3 Register Arithmetic-lo gi c Unit (RALU)
The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master program counter (PC), the processor status word (PSW), and several registers. The regist ers in the
RALU are the instr uction register, a constants register, a bit-select register, a loop counter, and
three temporary registers (the upper-word, lower-word, and second-operand registers).
The 24-bit master program counter (PC) provides a linear, nonsegmented 16-Mbyte memory
space. Only 20 of the address lines are implemented with external pins, so you can physically address only 1 Mbyte. (For compatibility with earlier devices, the PC can be configured as 16 bits
wide.) The master PC cont ains the a d dress of the ne xt inst ruct ion and has a built -in increm ente r
that automatically loads the next sequential address. However, if a jump, interrupt, call, or return
changes the address sequence , the ALU loads the appropriate address into the master PC.
The PSW contains one bit (PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six
Boolean flags that reflect the state of your program. Appendix A, “Instruction Set Refe rence,”
provides a detailed descript ion of the PSW.
All registers, except the 3-bit bit-select register and the 6-bit loop counter, are either 16 or 17 bits
(16 bits plus a sign extension). Some of these registe rs can reduce the ALU’s workload by performing simple operations.
The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as
temporary registers for many instructions. These registers have their own shift logic and are used
for operations that require logical shifts, including norm alize, multiply, and divide operati ons.
The six-bit loop counter counts repetitive shifts. The seco nd-operand register stores the second
operand for two-operand instructions, including the multiplier during multiply operations and the
divisor during divide operations. During subtraction operations, the output of this register is complemented before it is moved into the ALU.
The RALU speeds up calculations by storing constants (e.g., 0, 1, and 2) in the constants register
so that they are readily available when complem enting, incre menti ng, or decreme nting bytes or
words. In addition, the co nstants regi ster ge nera tes singl e-bit mas ks, base d on the bit-se lect register, for bit-test instructions.
2.3.3.1 Code Execution
The RALU performs most calculations for the device, but it does not use an accumulator. Instead
it operates direc tly on the lowe r regist er file , which e ssenti ally provides 256 accumulators. Because data does not flow through a single accumulator, the device’ s code executes faster and more
efficiently.
2-4
ARCHITECTURAL OVERVIEW
2.3.3.2 Instruction Format
MCS 96 microcontrollers combi ne a la rge set of general-purpose registers wi th a three - operand
instruction form at. This format allows a single inst ruction to spe cify two source re gisters an d a
separate destination register. For example, the following instructio n multiplies two 16-bit variables and stores the 32-bit result in a thir d variable .
MUL RESULT, FACTOR_1, FACTOR_2 ;multiply FACTOR_1 and FACTOR_2
;and store answer in RESULT
;(RESULT)←(FACTOR_1 × FACTOR_2)
An 80C186 device requires four instructions to accomplish the same operation. The following example shows the equivalent code for an 80C186 device.
MOV AX, FACTOR_1 ;move FACTOR_1 into accumulator (AX)
MUL FACTOR_2 ;multiply FACTOR_2 and AX
MOV RESULT, AX ;move lower byte into RESULT
MOV RESULT+2, DX ;move upper byte into RESULT+2
;(AX)←FACTOR1
;(DX:AX)←(AX)×(FACTOR_2)
;(RESULT)←(AX)
;(RESULT+2)←(DX)
2.3.4 Memory Control l er
The RALU communicates with all memory , except the register file and peripheral SFRs, through
the memory controller. (It communicates with the upper register file through the memory controller except when windowing is used; see Chapter 5, “Memory Partitions,”) The memory controller
contains the prefetch queue, the slave program counter (slave PC), address and data registers, and
the bus co ntroller.
The bus controller drives t he memory bus, which consists of an internal memory bus and the external address/data bus. The bus controller receives memory-access requests from either the
RALU or the prefetch queue; queue requests always have priority. This queue is transparent to
the RALU and your software.
NOTE
When using a logic analyzer to debug code, remember that instructi ons are
preloaded into the prefetch queue and are not necessari l y execute d
immediately aft er they are fetched.
When the bus controller receives a re quest from the queue, it fetches the code from the addres s
contained in the sl ave PC . The slave PC increa ses exec utio n speed bec ause the next inst ructi on
byte is available immediately and the processor need not wait for the master PC to send the address to the memory controller. If a jump, interrupt, call, or return changes the address sequence,
the master PC loads the new address into the slave PC, then the CPU flushes the queue and continues processing.
2-5
8XC196NP, 80C196NU USER’S MANUAL
The extended program counter (EPC) is an extension of the slave PC. The EPC generates the upper eight address bits for extended code fetches and outputs them on the extended addressing port
(EPORT). Because only four EPORT pins are implemented, only the lower four address bits are
available. (See Chapter 5, “Mem ory Part itions, ” for additional information.)
The memory controller includes a chip-select unit with six chip-select outputs for selecting an external device during an external bus cycl e. During an exte rnal memory acce ss, a chip-selec t output is asserted if the addre ss falls wi thin the address range assi gned to that chip-select. The bu s
width, the number of wa it states, and mult iplexed or de multiplexed address /data lines a re programmed independently for the six chip-selects. The address range of the chip-selects can be programmed for various granularities: 256 b ytes, 512 bytes, … 512 Kbytes, or 1 Mbyt e. The base
address can be any address that is evenly divisible by the selected address range. See Chapter 13,
“Interfacing wi th External Memory,” for more information.
2.3.5 Multiply-accumulate (80C196NU Only)
The 80C196NU is able to process multiply-accumulate operations through the use of a hardware
accumulator and enhanced mul tiplicatio n inst ruct ions. The a ccum ula tor include s a 16-bit adder,
a 3-to-1 multiplexer, a 32-bit accumulator register, and a control register. The multiply -accu mulate function is enabled by any 16-bit multiplication instruction with a dest ination address that is
in the range 00–0FH. The instructio ns can operate on signe d integers, unsigned integers, and
signed fractional numbers. The control re gister a llows you to ena ble saturation mode and frac-
tiona l mode for signed multiplication. Chapter 3, “Advanced Math Features,” describes the accumulator.
2.3.6 Interrupt Service
The device’s flexible interrupt-handling system has two main components: the programmable interrupt controller a nd t he peripheral transac tion s erver ( PTS). The p rogrammable inte rrupt controller has a hardware priority scheme that can be modified by your software. Interrupts that go
through the interrupt controller are serviced by interrupt service routines that you provide. The
peripheral transaction se rver (PTS), a microcoded hardware interrupt processor, pr ovides highspeed, low-overhead interrupt handling. You can configure most interrupts (except NMI, trap,
and unimpleme nted opcode) to be serviced by the PTS instead of the interrupt controller.
The PTS can transfer bytes or words, either individually or in blocks, between any memory locations and can generate pulse-wi dth modula ted (PWM ) signals . PTS interrupts have a higher priority than standard interrupts and may temporarily suspend interrupt service routines. See
Chapter 6, “Standard and PTS Interrupts, ” for more informatio n.
2-6
ARCHITECTURAL OVERVIEW
2.4 INTERNAL TIMING
The clock circuitry of the 8XC196NP (Figure 2-3) is identical to that of earlier MCS 96 microcontrollers. It recei ves an input c l ock signa l on XTAL1 provided by an external cryst al or clock
and divides the frequency by two. The clock ge ne rators accept the divided input frequency from
the divide-by-two circuit and produce two nonoverlapping internal tim ing signals, PH1 and PH2.
These signals are active when hig h.
Disable Clock Input
(Powerdown)
F
XTAL1
XTAL2
XTAL1
Disable
Oscillator
(Powerdown)
Divide-by-two
Circuit
Clock
Generators
Disable Clocks
(Powerdown)
Peripheral Clocks (PH1, PH2)
CLKOUT
CPU Clocks (PH1, PH2)
Disable Clocks
(Idle, Powerdown)
A3161-01
Figure 2-3. Clock Circuitry (8XC196NP)
The 80C196NU’ s clock c ircuitry (Figure 2-4) implements phase-locked loop and clock multiplier
circuitry, which can substantially increase the CPU clock rate while using a lower-frequency input clock. The clock circuitry ac cepts an input cloc k signal on XTAL1 provided by an external
crystal or oscillator. Depending on the val ues of the P LLE N1 and PLLE N 2 pins, this fre quency
is routed either through the phase-locked loop and multiplier or directly to the divide-by-two circuit. The multiplier circuitry can double or quadruple the input frequency (F
) before the fre-
XTAL1
quency (f) reaches the divide-by-two circuitry. The clock generators accept the divided in put
frequency (f/2) from the divide-by-two circuit and produce two nonoverlapping internal timing
signals, PH1 and PH2. These signals are active when high.
NOTE
For brevity, this manual uses lowerca se “f” to represent the internal clock
frequency of both the 8XC196NP and the 80C196NU. For the 8XC196NP, f is
equal to F
4F
XTAL1
. For the 80C196NU, f is equal to either F
XTAL1
, depending on the clock multiplier mode, which is controlled by the
XTAL1
, 2F
XTAL1
, or
PLLEN1 and PLLEN2 in put pins.
2-7
8XC196NP, 80C196NU USER’S MANUAL
Disable
PLL
(Powerdown)
F
XTAL1
XTAL2
PLLEN1
PLLEN2
XTAL1
Disable
Oscillator
(Powerdown)
XTAL1
F
XTAL1
2F
XTAL1
4F
Disable Clock Input
(Powerdown)
f
Divide-by-two
Circuit
f
2
Clock
Generators
Phase
Comparator
Phase-
locked
Oscillator
Phase-locked Loop
Disable Clocks
(Standby, Powerdown)
Filter
Clock Multiplier
Peripheral Clocks (PH1, PH2)
CLKOUT
CPU Clocks (PH1, PH2)
Disable Clocks
(Idle, Standby, Powerdown)
A3063-02
Figure 2-4. Clock Circuitry (80C196NU)
For both the 8XC196NP and 80C196NU, the rising edges of PH1 and PH2 generate CLKOUT
(Figure 2-5). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibility in power management. (“Reducing Power Consumption” on page 12-3
describes the powe r ma nagem ent m odes.) It also outputs the CLKOUT signal on the CLKOUT
pin. Because of the complex logic in the clock circuit r y, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal. This delay varies with tempera ture and volta ge.
2-8
XTAL1
PH1
PH2
CLKOUT
tt
1 State Time
ARCHITECTURAL OVERVIEW
1 State Time
Phase 1 Phase 2
Phase 1 Phase 2
A0805-01
Figure 2-5. Internal Clock Phases
The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic
time unit known a s a state time or state. T a ble 2-2 l ists state time durations at various frequencies.
Table 2-2. State Times at Var ious Frequencies
(Frequency Input to the
Divide-by-two Circu it)
f
State Time
12.5 MHz 160 ns
25 MHz 80 ns
50 MHz 40 ns
The following formulas calculate the frequency of PH1 and PH2, the duration of a state time, and
the duration of a clock period (t).
PH1 (in MHz)
f
-- -
PH2== State Time (in µs)
2
2
-- -
= t
f
1
-- -
=
f
Because the device can operate at many frequencies, this manual defines time requirements (such
as instruction execution times) in terms of state times rather than specific measurements.
Datasheets list AC charac teris tics in terms of clock period s (t).
For the 80C196NU, Table 2-3 details the relationships between the input frequency (F
XTAL1
), the
configuration of PLLEN1 a nd PLLEN2, the operating frequency (f), the c lock period (t), and
state times. Fig ure 2 -6 il lust rat es the timing relationships be twe en t he i n p ut frequency (F
XTAL1
the operating frequency (f), and the CLKOUT signal with each of the three valid PLLEN x pin
configurations. (Since t he m aximum operating fre quency is 5 0 MHz, only a 12.5 M Hz external
clock frequency allows all three clock modes.)
2-9
),
8XC196NP, 80C196NU USER’S MANUAL
T able 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times
F
XTAL1
(Frequency
on XTAL1)
50 MHz
25 MHz
PLLEN2:1 Multiplier
†
00 1 50 MHz 20 ns 40 ns
00 1 25 MHz 40 ns 80 ns
10 2 50 MHz 20 ns 40 ns
(Input Frequency to
the Divide-by-two Circuit)
00 1 12.5 MHz 80 ns 160 ns
12.5 MHz
10 2 25 MHz 40 ns 80 ns
11 4 50 MHz 20 ns 40 ns
†
Assumes an external clock. The maxi mum frequen c y for an extern al crysta l oscilla tor is 25 MHz.
XTAL1
(12.5 MHz)
f
t
(Clock
State Time
Period)
T
XHCH
PLLEN2:1=00
PLLEN2:1=10
PLLEN2:1=11
2-10
CLKOUT
CLKOUT
CLKOUT
f
f
f
t = 40ns
t = 80ns
t = 20ns
Figure 2-6. Effect of Clock Mode on CLKOUT Frequency
A3160-01
ARCHITECTURAL OVERVIEW
2.5 INTERNAL PERIPHERALS
The internal peripheral modules provide special func tions for a variety of applications. This section provides a brief description of the periphera ls; su bsequent chapters descri be them in detail.
2.5.1 I/O Ports
The 8XC196NP and 80C196NU have five I/O ports, ports 1–4 and the EPORT. Individual port
pins are multiplexed to serve as standard I/O or to carry special -function signa ls associ ated with
an on-chip peripheral or an off-chip component. If a particular special-function signal is not used
in an application, the associated pin can be individually configured to serve as a standard I/O pin.
Port 4 has a higher drive capability than the other ports to support pulse-width modulator (PWM)
high-drive outputs.
Ports 1–4 are eight-bit, bidirectional, standard I/O ports. Only the lower nibble of port 4 is implemented in current package offerings. Port 1 provides I/O pins for the four event proce ssor ar ray
(EPA) modules and the two timers. Port 2 is used for the serial I/O (SIO) port, two external interrupts, and bus hold functions. Port 3 is used for chip-select functions and two external interrupts.
Port 4 (functionally only a 4-bit port) provides I/O pins associated wi t h the three on-chip pulse width modulators. The EPORT provides address lines A19:16 to support ext ended addressin g.
See Chapter 7, “I/O Ports,” for more information.
2.5.2 Serial I/O (SIO) Port
The serial I/O (SIO) port is an asynchronous/synchronous port that includes a universal asynchronous receiver and transmitter (UART). The UART has one synchronous mode (mode 0) and three
asynchronous modes (modes 1, 2, and 3) for both transmission and recepti on. The asynchronous
modes are full duplex, meaning that they can trans mit and receive dat a simultaneousl y. The receiver is buffered, so the recepti on of a sec ond byte ca n begin before the first byt e is read. The
transmitter is also buffered, allowing continuous transmissions. See Chapter 8, “Serial I/O (SIO)
Port,” for details.
2.5.3 Event Processor Array (EPA) and Time r/Co un ters
The event processor array (EPA) performs high-speed input and output functions associated with
its timer/counte rs. In t he input mode, the EPA monitors an input for signal tra nsit i ons. Wh e n an
event occurs, the EPA records the timer value assoc iated with it. This is a capture event. In the
output mode, the EPA monitors a timer until its value matc hes tha t of a stored time value. When
a match occurs, the EPA triggers an outp ut event, whic h can se t, clear, or toggle an outp ut pin.
This is a compare event. Both capture and compare events can initiate interrupts, which can be
serviced by either the inte rrupt controller or the PTS.
2-11
8XC196NP, 80C196NU USER’S MANUAL
Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or extern ally. Ea ch t imer/ coun ter is ca lled a timer if it is clocked internally and a counter if it is clock ed
externally. See Chapter 10, “ Event Processor Array (EPA),” for additional information on the
EPA and timer/counte rs.
2.5.4 Pulse-width Mod ulator (P WM )
The output waveform from each PWM channel is a variable duty-cycle pulse with a programmable frequency that occurs every 256 or 512 state times (for the 8XC196NP) or every 256, 512, or
1024 state times (for the 80C196NU), as programmed. Several types of motors require a PWM
waveform for most efficient operation. When filtere d, the PWM waveform produces a DC level
that can change in 256 steps by varying the duty cycle. See Chapter 9, “Pulse-width Modulator,”
for more information.
2.6 SPECIAL OPERATING MODES
In addition to the normal execution mode, the device operates in several special-purpose modes.
Idle and powerdown modes co nserve power when the device is inactive. An additiona l power
conservation mode, standby, is available on the 80C196NU. On-circuit emulation (ONCE) mode
electrically isolates the microco ntroller from the system. See Chapter 12, “Special Operat ing
Modes,” for more information about idle, powerd own, standby, and ONCE modes.
2.6.1 Reducing Power Consumptio n
The power saving modes selectively disable internal clocks to reduce power consumption. Figure
2-3 on page 2-7 an d Figure 2-4 on page 2-8 illustrate the clock circuitry of the 8XC196NP and
80C196NU, respectively.
In idle mode, the CPU stops executing instructions, but the peripheral clocks remain active. Power consumption drops to about 40% of normal execution mode consumption. Either a hardware
reset or any enabled interrupt source wil l brin g the device out of idle mode.
The 80C196NU has an additional power saving mode, standby. In standby mode, all internal
clocks are frozen at logic state zero, but the oscillator and phas e-locked loop continue to run.
Power consumption drops to about 10% of normal execution mode consumpt ion. Either a hardware reset or any enabled external interrupt source will bring the device out of standby mode.
In powerdown mode, all internal clocks are frozen at logic state zero and the oscillator is shut off .
The register fi le and most periphera ls retain t heir da ta if V
is maintained. Power consumption
CC
drops into the µW range.
2-12
ARCHITECTURAL OVERVIEW
2.6.2 Testing the Prin ted Ci rcui t Boa rd
The on-circuit emulation (ONCE) mode electrically isolates the 8XC196 device from the system.
By invoking ONCE mode, you can test the printed circuit board while the device is soldered onto
the board.
2.7 DE S IGN CONS IDERAT IONS FOR 80C196NP TO 80C196NU CONVE RSIO NS
This section summarizes differences to consider when converting your design requ ire men ts from
the 80C196NP to the 80C196NU.
• The 80C196NU can achieve an operating frequency of 50 MHz, while the 80C196NP can
achieve only 25 MHz.
• The 80C196NU is pin-compa tible with the 80C 196NP. The functions of four pins differ:
— the 80C196NU has PLLEN1 in place of a no-connection pin of the 80C196NP
— the 80C196NU has PLLEN2 in place of a V
— the 80C196NU has a V
— the 80C196NU has a no-connection pin in place o f the EA# pin of the 80C196NP
pin in place of a no-connection pin of the 80C196NP
CC
pin of the 80C196NP
SS
• The 80C196NU requires that yo u tie the PLLEN1 and PLLEN2 pins either high or low,
depending on the clock multiplier mode you select.
• The 80C196NU requires that you connect an external capacitor to the RPD pin if your
design uses both powerdown mode and a clock multiplier mode.
• The 80C196NU has a new, 32-bit accumulator register and an accumulator status register to
support its multiply-accumulate functions.
• The 80C196NU, since it has no nonvolatile memory, has no REMAP bit in the CCB.
• The 80C19 6NU can window additional me mory into the lower register file via a se cond
window selection register (WSR1).
• Unlike the 80C1 96N P, the 80C196NU’s EPORT special-function registers are located in
SFR address space, rather than in memory-mapped space, so they can be windowed for
direct access.
• The 80C196NU has an 8-byte prefetch queue, while the 80C196NP ha s a 4-byte prefetch
queue.
• In the 80C196NU, data accesses have a higher priority than instruction queue fetches. In the
80C196NP, the opposite is true (instruct ion fetches have the highes t priorit y).
• The 80C196NU’s serial I/O port has a divide-by-2 prescaler, controlled by the SP_C ON
register.
• The 80C196NU’s EPA has an additional prescaler option (divide-by-128), controlled by the
timer control register (Tx_CONTROL).
2-13
8XC196NP, 80C196NU USER’S MANUAL
• The 80C196NU’s PWM has an additional prescaler option (divide-by-4), controlled by the
PWM control register (CON_REG0).
• When operating with a demultiplexed bus, the 80C196NU can add an automatic delay in the
first cycle following a chip-sel ect cha nge or in a write cycle that follows a rea d. This mode,
calle d def erred mode, extends the following timing specifications by two clock periods (2t):
, T
, T
, T
, T
, T
, T
, T
, T
T
AVDV
AVWL
AVRL
RLDV
RHDZ
RHRL
LHLH
RHLH
SLDV
, and T
WHLH
.
• The 80C196NU has an additional power-saving mode, standby (IDLPD #3).
• The 8XC196NP allows you to change the value of EP_REG to control which memory page
a nonextended instruction accesse s. However, software tools require that EP_REG be equal
to 00H. The 80C196NU f orces a ll nonextended da ta a ccesses to page 0 0H. You cannot use
EP_REG to change pages.
• After a HOLD request, the 80C196NU’s chip-select channel s become inactive be fore the
80C196NU asserts HLDA#.
• In demultiplexed mode, the 80C196NU’s RD# and WR# signals are asserted one clock
period (1t) earlier than on the 80C196NP.
2-14
Advanced Math
Features
3
CHAPT ER 3
ADVANCED MATH FEAT URES
The 80C196NU is the first member of the MCS® 96 microcontroller family to incorporate enhanced 16-bit multiplic ation instructions for perf orming multiply-accumulat e operations and a
dedicated, 32-bit accumulator register for storing the results of these operations. The accumulator
and the enhanced instruct ions c ombine to decrease the amo unt of time required to perform multiply-accumulate operations. The instructions and accumulator support signed and unsigned int egers as well as signed fractional data. This chapter describes the 80C196NU’s advanced
mathematica l features.
3.1 ENHANCE D MU LTIPLICATI ON INST RUCT IONS
The 16-bit multiplication instructions, MULU and MUL, that exist for all MCS 96 microcontrollers have been enhanced for the 80C196NU. The MULU instruct ion supports unsigned inte gers,
while the MUL instruction supports signed integers and signed fractionals.
When you execute a 16-bit multiplica tion instruction with a destinat ion address that is 0FH or
below , the 80C196NU automatically stores the result in the accumulator. If bit 3 of the destination
address is set (address 08H, 09H, …, 0FH), the 80C196NU clears the accumulator before it stores
the result of the current instruction. If bit 3 of the destination address is clear (address 00H, 01H,
…, 07H), it adds the result of the current instruction to the existing contents of the accumulator.
This simple exampl e illustra te s the re sult s of consecut ive mult ipl y-acc umula te inst r uctions. The
results of the first three inst ructions are a utomatic ally adde d together in the accumul ator, while
the last instruction clears the accumulator before the result is stored.
register_1 = 10 decimal (0AH),register_2 = 20 decimal (14H)
register_3 = 30 decimal (1EH),register_4 = 40 decimal (28H)
mul 00H,register_1,register_2 ;10×20= 200. Accumulator = 200 decimal.
mul 00H,register_3,register_4 ;30×40=1200. Accumulator =1400 decimal.
mul 00H,register_2,register_4 ;20×40= 800. Accumulator =2200 decimal.
mul 08H,register_2,register_3 ;20×30= 600. Accumulator = 600 decimal.
Table 3-1 compares the instructions required to perform a multiply-accumulate operation for the
8XC196NP and those required for the 80C196NU. The 8XC196NP requires four instruct ions,
while the 80C196NU requires only one to accomplish the same operation. The four 8XC196NP
instructions take a total of 32 state times to execute, while the single 80C196NU instruction takes
only 16 state times. In addition, the 80C196NU can operate at twice the frequency of the
8XC196NP; therefore, a state time for t he 80C1 96NU is half that of the 8XC 196NP. These two
factors combine to make the 80C196NU code execute in one-fourth the time require d for the
8XC196NP code.
3-1
8XC196NP, 80C196NU USER’S MANUAL
Table 3-1. Multiply/Accumulate Example Code
Device Instructions Execution Time
8XC196NP
(25 MHz; 1 state time = 80 ns)
80C196NU
(50 MHz; 1 state time = 40 ns)
†
Because bit 3 of the destination address (08H) is set, the 80C196NU clears the accumulator before
adding the result of th e curren t instru ct io n to it. If bit 3 were clear (de st ina ti on add ress 07H–00H), the
80C196NU would add the result of the current instruction to the existing value of the accumulator.
mul t emp,operand_2,operand _1
shll temp,#1
add out_l,temp_l
addc out_h,temp_h
mul 08H,operand_2,operand_1
32 states total
†
16 states total
16 states
8 states
4 states
4 states
16 states
1280 ns
640 ns
320 ns
320 ns
2560 ns total
640 ns
640 ns total
3.2 OPERA TING MODES
The accumulator has two opera tin g modes that a llow y o u to co ntrol the resul ts of ope rat ions o n
signed numbers. These modes are called saturatio n mode and fractional mo de.
3.2.1 Saturation Mode
Saturation occurs when the result of two positive numbers generates a negative sign bit or the result of two negative numbers generates a positive sign bit. Without saturation mode, an underflow
or overflow occurs and the overflow (OVF) flag is set. Saturation mode prevents an underflow or
overflow of the accumulated value. In saturation mode, the accumul ator’s value is changed to
7FFFFFFFH for a positive saturation or 80000000H for a negative saturation and the sticky saturation (STSAT) flag is set. The following two examples illustrate the contents of the accumulator
as a result of positive and negative saturatio n, respec tivel y:
7FFFFFFFH = 0111 1111 1111 1111 1111 1111 1111 1111 = 231 – 1 = +2147483647
8000 0000H = 1000 0000 0000 0000 0000 0000 0000 0000 = –2147483648
3-2
ADVANCED MATH FEATURES
3.2.2 Fractional Mode
A signed fractional contains an imaginary decimal point between the sign bit (the MSB) and the
adjacent bit. These example s illustrat e the representa tion of 32-bit signed fractional numbers :
2147483647
0.111 1111 1111 1111 1111 1111 1111 1111
0.000 0000 0000 0000 0000 0000 0000 0000 = 0
1.111 1111 1111 1111 1111 1111 1111 1111 =
1.000 0000 0000 0000 0000 0000 0000 0000 = –1
------ ----------- --------- ------ -
2147483648
------- ----------- --------- ----- -
2147483648
1–
1==
0–=
Fractional mode shift s the re sult of a multipl ication inst r uct ion left by one bit before writ ing the
result to the accumula tor. This left shift eliminates the extra sign bit when b oth operands are
signed, leaving a correctly signed result and the correc t decimal pla ceme nt.
3-3
8XC196NP, 80C196NU USER’S MANUAL
3.3 ACCUMULATOR REGISTER (ACC_0x)
The 32-bit accumulator register (Figure 3-1) resides at locations 0C–0FH. Read from or write to
the accumulator regist er as two words at locatio ns 0CH and 0EH.
ACC_0
x
= 0, 2 (80C196NU)
x
The 32-bit accumulator register (ACC_0
the accumulator register as two words at locations 0CH and 0EH.
80C196NU 15 8
7 0
ACC_02
15 8
7 0
ACC_00
Bit
Number
15:0 Accumulator Value
You can read this registe r to determ in e the curren t value of the accumulato r. You can
write to this register to clear or preload a value into the accumulator.
x
) resides at locations 0C–0FH. You can read from or write to
Accumulator Value (word 1, high byte)
Accumulator Value (word 1, low byte)
Accumulator Value (word 0, high byte)
Accumulator Value (word 0, low byte)
Function
Address:
Reset State:
0EH, 0CH
00H
Figure 3-1. Accumulator (ACC_0x) Register
3-4
ADVANCED MATH FEATURES
3.4 ACCUM ULATO R CONTRO L AND STATUS REGIST ER (ACC_STAT)
The ACC_STAT register controls the operating mode and refl ec ts the status of the a ccum ulator.
The mode bits (FME and SME) are effective only f or signed multipl ication. Table 3-2 describes
the 80C196NU’s operation with each of the four possible configurations of these bits.
ACC_STAT
(80C196NU)
The accumulator contro l and statu s (ACC_ STAT) register en able s and disa bles fract iona l and
saturation modes and contains three status flags that indicate the status of the accumulator’s
contents.
7 0
80C196NU
Bit
Number
7 FME Fractional Mode Enable
6 SME Saturation Mode En ab le
5:3 — Reserved; for compatib ility with future devices, write zeros to these bits.
2 STOVF Sticky Overflow Flag
1 OVF Overflow Flag
0 STSAT Sticky Saturation Flag
FME SME — — — STOVF OVF STSAT
Bit
Mnemonic
Set this bit to enable fraction al mode. (See Table 3-2.) In this mode, the
result of a signed multiplication instruction is shifted left by one bit before it
is added to the contents of the accumulator.
For unsign ed multiplication , th is bi t i s ig nored.
Set this bit to enabl e sa tu rati on mod e. (See Table 3-2.) In this mod e, the
result of a signed multiplication operation is not al lo wed to overflow or
underflow.
For unsign ed multiplication , th is bi t i s ig nored.
For unsigned multiplica tion , this bit is set if a carry out of bit 31 occur s.
Unless saturation mode is enabled, this bit is set for signed multiplication to
indicate that the sign bit of the accumulator and the sign bit of the addend
are equal, but the sign bit of the result is the opposite. (See Table 3-2.)
Software can clear this flag; hardware does not clear it.
This bit indi cate s that an overflow occurred duri ng the prece di ng accum u lation. (See Table 3-2.)
This flag is dynamic; it can change after each accumulation.
This bit indicates that a saturation has occurred during accumulation with
satura ti on mode en ab le d. (See Table 3-2.)
Software can clear this flag; hardware does not clear it.
Function
Address:
Reset State:
0BH
00H
Figure 3-2. Accumulator Control and Status (ACC_STAT) Register
3-5
8XC196NP, 80C196NU USER’S MANUAL
Table 3-2. Effect of SME and FME Bit Combinations
SME FME Description
0 0 Sets the OVF and STOVF flags if the sign bit s of the accumu lator and the addend (the
0 1 Shifts the addend (the number to be added to the contents of the accumulator) left by one
1 0 Accumulates a signe d integ er value up or down to satura ti on and sets the STSAT flag.
1 1 Shifts the addend (the number to be added to the contents of the accumulator) left by one
number to be added to the contents o f the accum u lator) are equ al, but the sign bit of the
result is the opposite.
bit before adding it to the accumulator. Sets the OVF and STOVF flags if the sign bits of the
accumula tor and the adden d are equ al, but the sign bi t of the result is the opposit e.
Positive satura tio n change s the accumu lato r value to 7FFFFFF FH; ne gative saturation
changes the accumu lator valu e to 80000000 H. Accumu la tion proce eds norm ally afte r
saturation, which means that the accumulator value can increase from a negative saturation
or decrease from a positive saturation.
bit before adding it to the accumulator. Accumulates a signed integer value up or down to
saturation an d sets the STSAT flag. Positive saturati on changes the accum ul ator valu e to
7FFFFFFFH; negative saturation changes the accumulator value to 80000000H. Accumulation proceeds normally after saturation, which means that the accumulator value can
increase from a negati ve sat uratio n or decre ase from a positive satu rat ion.
3-6
Programming
Considerations
4
CHAPT ER 4
PROGRAMMING CONSIDERATIONS
This section provides an overview of the instruction set of the MCS® 96 microcontrollers and offers guidelines for program development. For detailed information ab out specific instructions,
see Appendix A.
4.1 OVERVIEW OF THE
INSTRUCTION SET
The instructi on se t supports a variety of operand types likely to be useful in control applicatio n s
(see Table 4-1).
NOTE
The operand-type variables are shown in all capitals to avoid confusion. For
example , a BYT E is an unsigned 8-bit variable in an instruction, while a byte is
any 8-bit unit of data (either signed or unsigned).
Table 4-1. Operand Type Definitions
Operand Type
BIT 1 No True (1) or False (0) As components of bytes
BYTE 8 No 0 through 2
SHORT-INTEGER 8 Yes –2
WORD 16 No 0 through 2
INTEGER 16 Yes –2
DOUBLE-WORD
(Note 1)
LONG-INTEGER
(Note 1)
QUAD-WORD
(Note 3)
NOTES:
1. The 32-bit variables are supported only as the operand in shift operations, as the dividend in 32-by16 divide opera ti ons, and as the produ ct of 16-b y- 16 multip ly operations.
2. F or consistency with thir d-party software , you should adopt the C prog ramming conventio ns for
addressing 32-bit operands. For more information, refer to page 4-11.
3. QUAD-WORD variables are supported only as the operan d for th e EBMOV I instru ct ion.
No. of
Signed Possible Values
Bits
7
through +27–1
(–128 through +127)
(0 through 65,535)
15
through +215–1
(–32,768 through +32,767)
32 No 0 through 2
32 Yes –2
64 No 0 through 2
(0 through 4,294,967,295)
31
through +231–1
(–2,147,483,648 through
+2,147,483,647)
8
–1 (0 through 255) None
16
–1
32
–1
64
–1 An address in the lowe r
Addressing
Restrictions
None
Even byte address
Even byte address
An address in the lowe r
register file that is evenly
divisible by four (Note 2)
An address in the lowe r
register file that is evenly
divisible by four (Note 2)
register file that is evenly
divisible by eight
4-1
8XC196NP, 80C196NU USER’S MANUAL
Table 4-2 lists the equivalent operand-type names for both C programming and asse mbly language.
Table 4-2. Equivalent Operand Types for Assembly and C Programmin g Languages
Operand Types Assembly Language Equivalent C Programming Language Equivalent
BYTE BYTE unsigned char
SHORT-INTEGER BYTE char
WORD WORD uns i gned int
INTEGER WORD int
DOUBLE-WORD LONG unsigned long
LONG-INTEGER LONG long
QUAD-WORD — —
4.1.1 BIT Operands
A BIT is a single-bit variable that can have the Boolean values, “true” and “false.” The architecture requires that BITs be addressed as components of BYTEs or WORDs. It does not support the
direct addressing of BITs.
4.1.2 BYTE Operands
8
A BYTE is an unsigned, 8-bit variabl e that can take on values from 0 through 255 (2
–1). Arithmetic and relational operators can be applied to BYTE operands, but the result must be interpreted in modulo 256 arithmetic. Logical operations on BYTEs are applied bitwise. Bits within
BYTEs are label ed from 0 to 7; bit 0 is the least-sig nificant bit. There are no alignme nt restric tions for BYTEs, so they may be placed anywhere in the address space.
4.1.3 SHORT-INTEGER Operands
7
A SHORT-INTEGER is an 8-bit, signed variable that can take on values from –128 (–2
7
+127 (+2
–1). Arithme tic opera tio ns t hat g e nerat e re sult s outside the range of a SHORT-INTE-
) through
GER set the overflow flags in the p rocesso r status word (PSW). The numeric result is the same
as the result of the e quival ent ope rat ion o n BYTE vari abl es. There are no a lig nment rest ric tion s
on SHORT-INTEGERs, so they may be placed anywhere in the address spa ce.
4-2
4.1.4 WORD Operands
PROGRAMMING CONSIDERATIONS
A WORD is an unsigned, 16-bit variable that can take on values from 0 through 65,535 (2
16
–1).
Arithmetic and relational operators can be applied to WORD operands, but the result must be interpreted in modulo 65536 arithmetic. Logical operations on W ORDs are applied bitwi se. Bits
within WORDs are labeled from 0 to 15; bit 0 is the least-significant bit.
WORDs must be aligned at even byte boundaries in the address space. The least-significant byte
of the WORD is in the even byte address, and the most-significant byte is in the next higher (odd)
address. The address of a WORD is that of its least-significant byte (the even byte address).
WORD operations to odd addresses are not guaranteed to operate in a consis tent manner.
4.1.5 INTEGER Operands
15
An INTEGER is a 16-bit, si gned variable that can t ake on values from –32,768 ( –2
15
+32,767 (+2
–1). Arithmetic operations that generate results outside the range of an INTEGER
) through
set the overflow flags in the processor status word (PSW). The nume ric result is the same as the
result of the equivalent operati on on WORD varia ble s.
INTEGERs must be aligned at eve n byte boundaries in the address space. The leas t-sig nificant
byte of the INTEGER is in the even byte address, and the most-significant byte is in the next higher (odd) address. The addre ss of an INTEGER is that of its least-signifi cant byte (the even byte
address). INTEGE R operations to odd address es are not guaranteed t o operate in a consistent
manner.
4.1.6 DOUBLE-WORD Operands
A DOUBLE-WORD is an unsigned, 32-bit variable that can take on values from 0 through
32
4,294,967,295 (2
–1). The architecture directly supports DOUBLE-WORD opera nds only as
the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product
of 16-by-16 multiply operations. For these operat ions, a DOUBL E-WOR D vari able must reside
in the lower registe r file and must be aligned at an address t hat is eve nly divisibl e by four. The
address of a DOUBLE-WORD is that of its least-significant byt e (the even byte address). The
least-significant word of the DOUBLE-WORD is always in the lower address, even when the
data is in the stack. This means that the most-significant word must be pushed into the stack first.
DOUBLE-WORD operations that are not directly supported can be easil y im plemen ted with two
WORD operations. For example, the following sequences of 16-bit operations perform a 32-bit
addition and a 32-bit subtraction, respectively.
ADD REG1,REG3 ; (2-operand addition)
ADDC REG2,REG4
SUB REG1,REG3 ; (2-operand subtraction)
SUBC REG2,REG4
4-3
8XC196NP, 80C196NU USER’S MANUAL
4.1.7 LONG-INTEGER Ope rand s
A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648
31
) through +2,147,483,647 (+231–1). The architecture directly supports LONG-INTEGER
(– 2
operands only as the o perand in shi ft operat ions, a s the divi dend in 32-by-16 divide operations,
and as the product of 16-by-16 multiply operations. For these operations, a LONG-INTEGER
variable must reside in the lower register file and must be aligned at an address that is evenly divisible by four. The addres s of a LONG-INTEGER is that of its least-significant byte (the even
byte address).
LONG-INTEGER operations that are not directly suppor ted can be easily implemented with two
INTEGER operations. See the example in “DOUBLE-WORD O perands” on page 4-3.
4.1.8 QUAD-WORD Operands
64
A QUAD-WORD is a 64-bit, unsigned variable that can take on values from 0 through 2
–1.
The architecture directly supports the QUAD-WORD operand only as the operand of the EBMOVI instruction. For t his operation, t he QUAD-WORD vari abl e mus t reside in the lowe r register file and must be aligned at an address that is evenly divisible by eight.
4.1.9 Converting Operands
The instruction set supports conversions between the operand types. The LDBZE (load byte, zero
extended) instruction converts a BYTE to a WORD. CLR (clear) converts a WORD to a
DOUBLE-WORD by clea ring (writing zeros to) the upper WORD of the DO UBLE-WORD.
LDBSE (load byte, sign extended) convert s a SHORT-INTEGER into an INTEGER . EXT (sign
extend) converts an INTEGER to a LONG-INTEGER.
4.1.10 Conditional Jumps
The instructio ns for a ddit ion, subtraction, and c omparison do not distinguish between unsi g ned
(BYTE, WORD) and signed (SHOR T - INTEGER, INTEGER) operands. However, the conditional jump instructions allow you to treat the results of these operations as signed or unsigned quantities. For example, the CMP (compare) instruction is use d to compare both signed and unsigned
16-bit quantities. Following a compare operation, you can use the JH (jump if higher) instruction
for unsigned operands or the JGT (jump if greater than) instruction for signed operands.
4-4
PROGRAMMING CONSIDERATIONS
4.1.11 Floating Point Operations
The hardware does not directly support operations on REAL (floating point) variables. Those operations are supported by floating point libraries from third-party tool vendors. (See the Develop-
ment Tools Handbook.) The performance of these operations is signifi cantly improved by the
NORML instruction and by the sticky bit (ST) flag in the p rocessor status word (PSW). The
NORML instruction normalizes a 32-bit variable; the sticky bit (ST) flag can be used in conjunction with the carry (C) flag to achieve finer resolution in roundin g.
4.1.12 Extended Instruc tions
This section briefly describes the instructions that have been added to enable code execution and
data access anywhere in the 1-Mbyte address space.
NOTE
In 1-Mbyte mode, ECALL, LCALL, and SCALL always push two words onto
the stack; therefore, a RET must always pop two words from the stack.
Because of the extra push and pop operations, interrupt routines and
subroutines take slightly longer to execute in 1-Mbyte mode than in 64-Kbyte
mode.
EBMOVI Extended interruptable block move. Moves a block of word data from one
memory location to anot her. This instruct ion al lows you t o move blocks of up to
64K words between any two locations in the address spac e. It uses two 24-bit
autoincrementing pointers and a 16-bit counter.
EBR Extended branch. This instruction is an unconditional indirect jump to
anywhere in the address space. It functions only in extended addressing modes.
ECALL Extended c all. This instruction is an unconditional relative ca ll to anywhere in
the address space. It functions only in extended addressing modes.
EJMP Extended jump. This instruction i s an unc o nditional, re lative jump t o anywhere
in the address space. It functions only in extended addressing mo des.
ELD Extended load word. Loads the value of the source word operand into the
destination opera n d. This inst r uction al lows y ou to m o ve dat a from anywhere in
the address space int o the lowe r regi st er file . It operat es i n exte nded in direc t an d
extended indexed modes.
ELDB Extended load byte. Loads the value of the source byte operand into the
destination opera n d. This inst r uction al lows y ou to m o ve dat a from anywhere in
the address space int o the lowe r regi st er file . It operat es i n exte nded in direc t an d
extended indexed modes.
4-5
8XC196NP, 80C196NU USER’S MANUAL
EST Extended store word. Stores the value of the sourc e (leftmos t) word operand
into the destination (rightm ost) operand. This instruction allows you to move
data from the lowe r register fil e to anywhere in the address space. It operates in
extended indirect and extended indexed modes.
ESTB Extended store byte. Stores the value of the source (leftmo st) byte operand into
the destina tion (rightmost) operand. This inst ruction allows you to move data
from the lower register file to anywhere in the address space. It operates in
extended indirect and extended indexed modes.
4.2 ADDRESSING MODES
The instruction set uses four basic addressing modes:
• direct
• immediate
• indirect (with or without autoincrement)
• indexed (short-, long-, or zero-indexed)
The stack pointer ca n be used with indirect addressin g to access the top of the stac k, and it can
also be used with short-indexed addressin g to access data within the stack. The zer o register can
be used with long-indexed addressing to access any memory location.
Extended variations of the indirec t and indexed modes support the extended load and store instructions. An extended load instruction moves a word (ELD) or a byte (ELDB) from any location
in the address space into the l ower register file. An extended store inst ruction moves a word
(EST) or a byte (ESTB) from the lower register file into any location in the address space. An
instruction can cont ain only o ne imme dia te, indirect , or indexed refe rence ; any rem aining op erands must be direct references.
This section describes the addressing modes as they are handled by the hardware. An understanding of these details will help programmers to take full advantage of the architecture. The assembly
language hides some of the details of how these addres sing modes work. “Assembl y Language
Addressing Mode Selections” on page 4-11 describes how the assembly language handles direct
and indexed addressing modes.
The examples in this section assume that temporary registers are defined as shown in th is segmen t
of assembly code an d describe d in Table 4-3.
AX DSW 1
BX DSW 1
CX DSW 1
DX DSW 1
EX DSL 1
4-6
Oseg at 1ch
PROGRAMMING CONSIDERATIONS
Table 4-3. Definition of Temporary Registers
Temporary Register Description
AX word-aligned 16-b it registe r; AH is the high byte of AX and AL is the low byte
BX word-aligned 16-b it registe r; BH is the high byte of BX and BL is the low byte
CX word-aligned 16-b it reg iste r; CH is the high byte of CX and CL is the low byte
DX word-aligned 16-b it reg iste r; DH is the high byte of DX and DL is the low byte
EX double-word-aligned 24-bit register
4.2.1 Direct Addressing
Direct addressing directly accesses a location in the 256-byte lower register file, without involving the memory controller. Windowing allows you to remap other sections of memory into the
lower register file for direct access (see Chapter 5, “Memory Partitions,” for details). Y ou specify
the registers as operands within the instruction. The register addresses must conform to the alignment rules for the operand type. Depending on the instruction, up t o three registers can take part
in a calculation. The following instr uctions use direct add ressin g:
ADD AX,BX,CX ; AX ← BX + CX
ADDB AL,BL,CL ; AL ← BL + CL
MUL AX,BX ; AX ← AX × BX
INCB CL ; CL ← CL + 1
4.2.2 Immediate Addressing
Immediate addressing mode a ccepts one immedia te value as an operand in the instruc tion. You
specify an immediate value by preceding it with a number symbol (#). An instruction can contain
only one imme dia te val ue; t he remaining o perands must be direct reference s. The following instructions use immediate addressing:
ADD AX,#340 ; AX ← AX + 340
PUSH #1234H ; SP ← SP - 2
DIVB AX,#10 ; AL ← AX/10
; MEM_WORD(SP) ← 1234H
; AH ← AX MOD 10
4.2.3 Indirect Addressing
The indirect addressing mode accesses an operand by obtaining its address from a WORD register in the lower register file. You specify the register containing the indirect address by enclosing
it in square brackets ([ ]). The indirect address can refer to any location within the address space,
including the register file. The regi ster that contains the indirect address must be word-aligne d,
and the indirect address must conform to the rules for the operand type. An instruction can contain
only one indirect reference; any remaining operands must be direct references. The following instructions use indirect addressing:
4-7
8XC196NP, 80C196NU USER’S MANUAL
LD AX,[BX] ; AX ← MEM_WORD(BX)
ADDB AL,BL,[CX] ; AL ← BL + MEM_BYTE(CX)
POP [AX] ; MEM_WORD(AX) ← MEM_WORD(SP)
; SP ← SP + 2
4.2.3.1 Extended Indirect Addressing
Extended load and st ore i nstruc tions can use indirect add ressin g. The onl y difference is t hat the
register containing the indirect address must be a word-aligned 24-bit register to allow access to
the entire 1-Mbyte addre ss space. The foll owing instruc tio ns use extended indi rect addressi n g:
ELD AX,[EX] ; AX ← MEM_WORD(EX)
ELDB AL,[EX] ; AL ← MEM_BYTE(EX)
EST AX,[EX] ; MEM_WORD(EX) ← AX
ESTB AL,[EX] ; MEM_BYTE(EX) ← AL
4.2.3.2 Indirect Addressing with Autoincrement
Y ou c an choose to automatically increment the indirect address after the current access. You specify autoincrementi ng by adding a plus sign (+) to the end of the indirect reference. In this case,
the instruction automatically increments the indirect address (by one if the destination is an 8-bit
register or by two if it is a 16-bit register). When your code is assembled, the assembler automatically sets the least-significa nt bit of the indirec t address register. The following instructions use
indirect addressing with autoincrement:
LD AX,[BX]+ ; AX ← MEM_WORD(BX)
ADDB AL,BL,[CX]+ ; AL ← BL + MEM_BYTE(CX)
PUSH [AX]+ ; SP ← SP - 2
; BX ← BX + 2
; CX ← CX + 1
; MEM_WORD(SP) ← MEM_WORD(AX)
; AX ← AX + 2
4.2.3.3 Extended Indirect Addressing with Autoincrement
The extended load and store instructions can also use indirect addressing with autoincrement. The
only difference is that the register c o ntaining the indi rect address must be a word-aligne d 24-bit
register to allow access to the entire 1-Mbyte address space. The followi ng instructions use extended indirect addressing with autoincrement:
ELD AX,[EX]+ ; AX ← MEM_WORD(EX)
ELDB AL,[EX]+ ; AL ← MEM_BYTE(EX)
EST AX,[EX]+ ; MEM_WORD(EX) ← AX
ESTB AL,[EX]+ ; MEM_BYTE(EX) ← AL
4-8
; EX ← EX + 2
; EX ← EX + 2
; MEM_WORD(EX) ← MEM_WORD(EX + 2)
; MEM_BYTE(EX) ← MEM_BYTE(EX + 2)
PROGRAMMING CONSIDERATIONS
4.2.3.4 Indirect Addressing with the Stack Pointer
You can also use indirect addressi ng to access the t op of the stack b y using the stac k pointer as
the WORD register in an indirect reference. The following instruction us es indirect addressing
with the stack pointer:
PUSH [SP] ; duplicate top of stack
; SP ← SP +2
4.2.4 Indexed Addressing
Indexed addressing calcula tes an address by adding an offset to a base ad dress. There are three
variations of indexed addressing: short-indexed, long-indexed, and zero-indexed. Both short- and
long-indexed addressing are use d to a ccess a specific element within a structure. Short-indexed
addressing can access up to 255 byte locations, long-indexed addressing can access up to 65,535
byte locations, and zero-indexed addressing can access a single location. An instruction can contain only one indexed reference; any remaining operands must be direc t reference s.
4.2.4.1 Short-indexed Addressing
In a short-indexed instruction, you specify the offset as an 8-bit constant and the base address as
an indirect address register (a WORD). The following instructions use short-indexe d addressing.
LD AX,12H[BX] ; AX ← MEM_WORD(BX+12H)
MULB AX,BL,3[CX] ; AX ← BL × MEM_BYTE(CX+3)
The instruction LD AX,12H[BX] loads AX with the contents of the memory location that resides
at address BX+12H. That is, the instruction adds the constant 12 (the offset) to the contents of BX
(the base address), then loads AX with the c ontent s of the result ing address. For example , if BX
contains 1000H, then AX is loaded with the contents of location 1012H. Short-indexed addressing is typically used to access elements in a structure, where BX contains the base address of the
structure and the constant (12H in this example) is the offset of a specific element in a structure.
You can also use the stack pointer in a short-in dexed instruction to acces s a particular locati on
within the stack, as shown in the following instruct i on.
LD AX,2[SP]
4.2.4.2 Long-indexed Addressing
In a long-indexed instructio n, you specify the ba se address as a 16-bit vari able and the offset a s
an indirect address register (a WOR D). The followi ng instruct ions use long-indexe d addressing.
LD AX,TABLE[BX] ; AX ← MEM_WORD(TABLE+BX)
AND AX,BX,TABLE[CX] ; AX ← BX AND MEM_WORD(TABLE+CX)
4-9
8XC196NP, 80C196NU USER’S MANUAL
ST AX,TABLE[BX] ; MEM_WORD(TABLE+BX) ← AX
ADDB AL,BL,LOOKUP[CX] ; AL ← BL + MEM_BYTE(LOOKUP+CX)
The instruction LD AX, T ABLE[BX] loads AX with the contents of the memory location that resides at address TABLE+ BX. That is, the instruct ion adds the contents of BX (the offset) to the
constant TABLE (the base address), then loads AX with the contents of the resulting address. For
example, if TABLE equals 4000H and BX contains 12H, then AX is loaded with the contents of
location 4012H. Long-indexed addressing is typi cally use d to access elements in a table, where
TABLE i s a constant tha t is the ba se addre ss of the st ruct u re and BX is the scal ed o ffset (n × el ement size, in bytes) into the str ucture .
4.2.4.3 Extended Indexed Addressing
The extended loa d and store instruct i ons ca n use exte nde d inde xed a dd ressing. T he o nly difference from long-indexed addressing is that both the base address and the offset must be 24 bits to
support access to the entire 1-Mbyte address space. The following inst ructions use extended indexed addressing. (In these instructions, OFFSET is a 24-bit variable conta ining the offset, and
EX is a double-word aligned 24-bit register containing the base address.)
ELD AX,OFFSET[EX] ; AX ← MEM_WORD(EX+OFFSET)
ELDB AL,OFFSET[EX] ; AL ← MEM_BYTE(EX+OFFSET)
EST AX,OFFSET[EX] ; MEM_WORD(EX+OFFSET) ← AX
ESTB AL,OFFSET[EX] ; MEM_BYTE(EX+OFFSET) ← AL
4.2.4.4 Zero-ind exed Addressing
In a zero-indexed instructi on, you specif y the add ress as a 16-bit va ria ble; the offset is zero, a nd
you can express it in one of three ways: [0], [ZERO_REG], or nothing. Each of the following load
instructions loads AX with the contents of the variable THISVAR.
LD AX,THISVAR[0]
LD AX,THISVAR[ZERO_REG]
LD AX,THISVAR
The following instructio ns also use zero-indexed ad dressin g:
ADD AX,1234H[ZERO_REG] ; AX ← AX + MEM_WORD(1234H)
POP 5678H[ZERO_REG] ; MEM_WORD(5678H) ← MEM_WORD(SP)
4.2.4.5 Extended Zero-indexed Addressing
; SP ← SP + 2
The extended ins truct ions can also use z ero-i nde xed addres sing. The only difference is tha t yo u
specify the address as a 24-bit constan t or variable. The following extended instruction uses zeroindexed addressing. ZERO_REG acts as a 32-bit fixed source of the constant zero for an extended
indexed reference.
ELD AX,23456H[ZERO_REG] ; AX ← MEM_WORD(23456H)
4-10
PROGRAMMING CONSIDERATIONS
4.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS
The assembly language simplifies the choice of addressing modes. Use these features wherever
possible.
4.3.1 Direct Addressing
The assembly la nguage chooses betwee n direct and zero-indexed addressing depending on the
memory location of the operand. Simply refer to the operand by its symbolic name. If the operand
is in the lower regis ter file, the asse mbly language choose s a direct reference . If the ope rand is
elsewhere in memory, it chooses a zer o-indexed refere nce.
4.3.2 Indexed Addressing
The assembly language chooses betw een short-indexe d an d long-indexed ad dressing depending
on the value of the index expression. If the value can be expressed in eight bits, the assembly language chooses a short-indexed reference. If the value is greater than ei ght bits, it chooses a longindexed reference.
4.3.3 Extended Addressing
If the operand is outside page 00H, then you must use the extended loa d and store instructi ons,
ELD, ELDB, EST, and ES TB.
4.4 DESIGN CONSIDE RAT IO NS FOR 1-MBYT E DEV ICES
In general, you should avoid creating tables or arrays that cross page boundaries. For example, if
you are building a large array, start it at a base address that will acc ommodate the entire a rray
within the same page. If you cannot avoid crossing a page boundary, keep in mind that you must
use extended instructions to acce ss dat a outside the origina l page.
4.5 SOFTWARE STANDARDS AND CONVENTIONS
For a software project of any size, it is a good idea to develop the program in modules and to establish standards that control communication between the modules. These standards vary with the
needs of the final application. However, all standards must include some mechanism for passing
parameters to procedures and returning results from procedures. We recommend that you use the
conventions adopted by the C programming language for procedure linkage. These standards are
usable for both the assembly language and C programming environments, and they offer compatibility between these environments.
4-11
8XC196NP, 80C196NU USER’S MANUAL
4.5.1 Using Registers
The 256-byte lower register file contains the CPU special-function registers and the stack pointer.
The remainder of the lower register file and all of the upper register file is available for your use.
Peripheral special-function registers (SFRs) and memory-mapped SFRs reside in higher memory.
The peripheral SFRs can be windowed into the lower register file for direct acc ess. Memorymapped SFRs cannot be windowed; you must use indirect or indexed addressing to access them.
All SFRs can be operated on as BYTEs or WORDs, unless otherwise specified. See “Peripheral
Special-function Regi sters (SFR s)” on page 5- 7 and “Regi ster File” o n page 5-9 for more information.
To use t hese re gist ers effectively, you must have some overall strategy for allocating the m. The
C programm ing l angu age adopts a simple , ef fe ctive strat egy. It allocates the e ight o r sixteen bytes
beginning at address 1CH as te mporary storage and trea ts the rem aining area i n the regist er file
as a segment of memory that is allocated as required.
NOTE
Using any SFR as a base or index register for indirect or indexed operations
can cause unpredictable results because external events can c hange the
contents of SFRs. Also, because some SFRs are cleared when read, consider
the implications of using an SFR as an operand in a read-modify-write
instructi on (e.g., XORB ).
4.5.2 Addressing 32-bit Operands
The 32-bit operands (DOUBL E-WORDs and LONG-INTE GERs) are formed by t wo adjacent
16-bit words in memory. The least-significant word of a DOUBLE-WORD is always in the lower
address, even when the data is in the stack (which means that the most-si gni fic ant word must be
pushed into the stack first). The address of a 32-bit operand is that of its least-signifi ca nt b yte.
The hardware supports the 32-bit data types as operands in shift operations, as divi dends of 3 2by-16 divide operations, and as products of 16-by-16 multiply operations. For these operations,
the 32-bit operand must reside in the lower register file and must be aligned at an address that is
evenly divisible by four.
4.5.3 Addressing 64-bit Operands
The hardware supports the QUAD-WORD only as the operand of the EBMOVI instruction. For
this operation, the QUAD-WORD variable must reside in the lower register file and must be
aligned at an address that is evenly divisible by eight.
4-12
PROGRAMMING CONSIDERATIONS
4.5.4 Linking Subroutines
Parameters are passed to subroutines via the stack. Parameters are pushed into the stack from the
rightmost parameter to the left. The 8-bit parameters are pushed into the stack with the high-order
byte undefined. The 32-bit parameters are pushed onto t he stack as two 16-bit values; t he mostsignificant hal f of the parame ter is pushe d into the st ack first. As an example, c onsider the following procedure:
void example_procedure (char param1, long param2, int param3);
When this procedure is entered at run-time, the sta ck wi ll contain the parameters in the following
order :
param3
low word of param2
high word of param2
undefined;param1
return address ← Stack Pointer
If a procedure returns a value to the calling code (as opposed to modifying more global variables)
the result is returned in the temporary storage space (TMPREG0, in this example) starting at 1CH.
TMPREG0 is viewed as either an 8-, 16-, 32-, or 64- bit variable, depending on the type of the
procedure.
The standard calling convention adopte d by the C programming language has several key features:
• Procedures can always assume that the eight or sixteen bytes of register file memory
starting at 1CH can be used as temporary storage within the body of the procedure.
• Code that calls a procedure must assume tha t the procedure modifies the eight or sixteen
bytes of register file memory starting at 1CH.
• Code that calls a procedure must assume that the procedure modifies the processor stat us
word (PSW) condition flags because procedures do not save and restore the PSW.
• Function results from procedures are always returned in the variable TMPREG0.
The C programming language allows the definitio n of i nterrupt p rocedures, whi ch are exe cute d
when a predefined interrupt request occ urs. Interrupt procedures do not conform to the rules o f
normal procedures. Parameters c annot be passed to these procedures and they cannot return results. Since interrupt procedures ca n exe cute e sse nti al ly a t any t i me, t hey m us t save and restore
both the PSW and TMPREG0.
4-13
8XC196NP, 80C196NU USER’S MANUAL
4.6 S OF TWARE PROTECTION FEATU RES AND G UI DEL INES
The device has several features to assist in recoverin g from hardware and software errors. The
unimplemented opcode interrupt provides protection from executing unimplemented opcodes.
The hardware reset instruction (RST) can cause a reset if the program counter goes out of bounds.
The RST instruction opcode is FFH, so the processor will reset itself if it tries to fetch an instruction from unprogrammed locations in nonvolatile memory or from bus lines that have been pulled
high.
We recommend that you fill unused areas of code with NOPs and periodic jumps to an error routine or RST instruction. This is particularly important in the code surrounding loo kup tabl es, sinc e
accidentally exec uting from lookup tables will cause undesired resul ts. Wherever space allows,
surround each table with seven NOPs (because the longest device instruction has seven bytes) and
a RST or a jump to an error routine. Since RST is a one-byte instruction, the NOPs are u nnecessary if RSTs are used instead of jumps to an error routine. This wi ll help to ensure a speedy recovery from a software error.
4-14
Memory Partitions
5
CHAPT ER 5
MEMORY PARTITIONS
This chapter describes the organization of the address space, its major partitions, and the 1-Mbyte
and 64-Kbyte operating modes. 1-Mbyt e refers to the address spa ce defined by the 20 ext ernal
address lines. In 1-Mbyte mode, c ode c an e xecute from almost a nywhere i n t he 1-M byte spac e.
In 64-Kbyte mode, code can execut e only fr om the 64-Kbyte area FF0000–FFFFFFH. The 64Kbyte mode provides compat ibility with software written for p revious 16-bit MCS
controllers. In either mode, nearl y all of the 1-Mbyte address space is available for data storage.
Other topics covered in this chapter include the following:
• the relationship between the 1-Mbyte address space defined by the 20 external address lines
and the 16-Mbyte address space defined by the 24 internal address lines
• extended and nonextended data accesses
• a windowing technique for accessing the upper register file and peripheral special-function
registers (SFRs) with direct addressing
• examples of external memory configurations for the 1-Mbyte and 64-Kbyte operating
modes
• a method for remapping t h e 4-Kbyte internal ROM (83C196NP only)
5.1 MEMORY MA P OVERVIEW
®
96 micro-
The instructions can address 16 Mbytes of memory . However, only 20 of the 24 address lines are
implemented by e xternal pins: A19:0 in de multiplexe d mode, or A19:16 a nd AD15:0 in multiplexed mode. T he lower 16 address /data line s, AD15:0, are the same as those in all other MCS
96 microcontrollers. The four extended address lines, A19:16, are provided by the EPOR T. If, for
example, an internal 24-bit address is FF2018H, the 20 external-address pins output F2018H.
Further, the address seen by an external device depends on how many of the extended addres s
lines are connected to the device. (See “Interna l and Exter nal Addresses” on page 13-1.)
The 20 external-address pins can address 1 Mbyte of external memory. For purposes of discussion
only, it is convenient to view this 1-Mbyte address spac e as sixteen 64-Kbyte pages, numbered
00H–0FH (see Figure 5-1 on page 5-2). The lower 16 address lines enable the device to address
page 00H. The four extended address lines enable the device to a ddress the re maini ng ext ernal
address space, pages 01H–0FH.
5-1
8XC196NP, 80C196NU USER’S MANUAL
Because the four most-significant bits (MSBs) of the internal address can take any values without
changing the external address, these four bits effectively produce 16 copies of the 1-Mbyte address space, for a total of 16 Mbytes in 256 pages, 00H–FFH (Figure 5- 1). For example, page 01H
has 15 duplicates: 11H, 21H, ..., F1H. The shaded areas in Figure 5-1 represent the overlaid areas.
16 Mbyte
FFH
•
•
•
F1H
F0H
3 Mbyte
2FH
•
••
•
Figure 5-1. 16-Mbyte Address Space
•
•
21H
20H
2 Mbyte
1FH
•
•
•
11H
10H
1 Mbyte
0FH
•
•
•
01H
00H
Externally
Addressable
A2541-02
The memory pages of interest are 00H–0EH and FFH. Pages 01H–0EH are external memory with
unspecified contents; they can store either code or data. Page s 00H and FFH, shown in Figure
5-2, have special significance. Page 00H contains the register file and the special-function registers (SFRs), while page FFH contains special-purpose memory (chip configuration bytes and interrupt vectors) and program memory. The device fetches its first instruction from location
FF2080H. Addresses in page FFH exist only in the internal 24-bit address space.
The implementation of page FFH in the 83C196NP differs from that in the 80C196NP and
80C196NU. For th e 83C1 96NP, loca tions FF2000 –FF2 FFFH are i mplemented by 4 Kbytes of internal ROM and the remain der of page FFH (FF3000–FFFFFFH) is implemented by ext ernal
memory in page 0FH. For the 80C196NP and the 80C196NU, which have no internal ROM , all
of page FFH is implemented by external mem ory in page 0FH.
5-2
NOTE
Because the device has 24 bits of address internally, all programs must be
written as though the device uses all 24 bits. The device resets from page FFH,
so all code must originate from this page. (Use the asse mble r directi ve, “cseg
at 0FFxxxxH.”) This is true even if the code is actually stored in exter nal
memory.
MEMORY PARTITIONS
FFFFFFH
FF3000H
FF2FFFH
FF2080H
FF207FH
FF2000H
FF1FFFH
FF0100H
FF00FFH
FF0000H
Page FFH
External Memory
Program Memory
80C196NP/NU: External
83C196NP: ROM
Special Purpose Memory
80C196NP/NU: External
83C196NP: ROM
External Memory
Reserved
00FFFFH
003000H
002FFFH
002000H
001FFFH
001F00H
001EFFH
001C00H
001BFFH
000400H
0003FFH
000100H
0000FFH
000000H
External Memory
80C196NP/NU:
External Memory
External Memory if
Peripheral SFRs
External Memory
External Memory
Upper Register File
Lower Register File
Page 00H
83C196NP:
CCB1.2 = 0
A Copy of
Page FFH if
CCB1.2 = 1
(Future SFR
Expansion)
A2462-03
Figure 5-2. Pages FFH and 00H
5.2 MEMORY PARTITIONS
T able 5-1 is a memory map of the 8XC196NP and 80C196NU. The remainder of this section describes the partitions.
5-3
8XC196NP, 80C196NU USER’S MANUAL
Table 5-1. 8XC196NP and 80C196NU Memory Map
Hex
Address
FFFFFF
FF3000
FF2FFF
FF2080
FF207F
FF2000
FF1FFF
FF0100
FF00FF
FF0000
FEFFFF
0F0000
0EFFFF
010000
00FFFF
003000
002FFF
002000
001FFF
001F00
001EFF
001C00
001BFF
000400
0003FF
000100
0000FF
000000
NOTES:
1. For th e 80C19 6NP an d 80C19 6NU, th e pro gra m an d sp ecia l-p urpose memory locat ions (FF 20 00–
2. Do not use th ese locat ions exce pt to initia lize them. Except as otherwise n oted, initia lize unuse d
3. Fo r the 80C19 6NP and 80C19 6NU, loca tio ns 00200 0– 002F FFH reside in exte rna l memor y. For the
4. For the 8XC196NP, locations 1FE0–1FFFH contain memory-mapped SFRs. They must be
5. WARNING: The contents or functions of these locations may change with future device revisions, in
External device (memory or I/O) connected to address/data
bus
Program memory (Note 1)
After a device reset, the first instruction fetch is from FF2080H
(or F2080H in externa l memor y).
Special-purpose me mory (Note 1) In direct, indexed , extende d
External device (memory or I/O) connected to address/data
bus
Reserved (Note 2) —
Overlaid memory; xF0000—xF00FFH are reserved Indirect, indexed, extended
External device (memory or I/O) connected to address/data
bus
External device (memory or I/O) connected to address/data
bus
External device (memory or I/O) connected to address/data
bus (Note 3)
Peripheral SFRs (Note 4)
External device (memory or I/O) connected to address/data
bus; future SFR expansion (Note 5)
External device (memory or I/O) connected to address/data
bus
Upper registe r file (regi ste r RAM)
Lower register file (register RAM, stack pointer, CPU SFRs) Direct, indirect, indexed
FF2FFFH) reside in external memory. For the 83C196NP, these locations can reside either in external memory or in internal ROM.
program memory locations and reserved memory locations to FFH.
83C196NP, locations 00 2000 –002FFF H can be externa l memory (CCB1. 2= 0) or a copy of program
and special-purpose memory stored in the internal ROM (CCB1.2=1).
accessed with indirect, indexe d, or extended addres sing and they cannot be windowed .
which case a program that relies on one or more of these locations might not function properly.
Descrip tion Addressi ng Mode s
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed, extended,
windowed direct
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed,
windowed direct
5-4
MEMORY PARTITIONS
5.2.1 External Memory
Several partitions in pages 00H and FFH and all of pages 01H–0EH are assigned to external
memory (see Table 5-1). Data can be stored in any part of this memory . Instructions can be stored
in any part of this memory i n 1-Mbyte m ode, but can be stored only in page F FH in 64-Kbyte
mode. “Memory Configuration Examples” on page 5-27 contains examples of memory configu rations in the two modes. Chapter 13, “Interfacing with External Memory,” describes the external
memory interface and shows additional examples of external memory configurations.
5.2.2 Program and Special-pu rpose Memory
Program memory and special-purpose memory occupy a 4-Kbyte memory partition from
FF2000–FF2FFFH. For the 8 0C196NP and 80C196NU, th is p art ition r esides in external memory
(external ad dresses F 2000–F2FFFH). For t he 83C196NP, this partition resides in on-chip ROM
in page FFH, and it can also be mapped to page 00H (see “Remapping Internal ROM (83C196NP
Only)” on page 5-22).
5.2.2.1 Program Memory in Page FFH
Three partitions in page FFH can be used for program memory:
• FF0100–FF1FFFH in external memory (external addresses F0100–F1FFFH)
• FF2080–FF2FFFH
— 80C196NP and 80C196NU: This partiti on is in external memory (externa l addresses
F2080–F2FFFH).
— 83C196NP: The REMAP bit (CCB1.2), the EA# input, and the type of instruction
(extended or nonextended) control access to this partition, as shown in Table 5-2.
Table 5-2. Program Memory Access for the 83C196NP
REMAP
(CCB1.2)
X Assert ed Extende d or nonextende d Extern al memo ry, F2080–F2FFFH
0 Deas serte d Exten de d or none xten de d Int ern al ROM , FF2080 –F F2 FFF H
1 Deas serte d
EA# Pin Instruction Type Memory Location Accessed
Extended Internal ROM, FF2080–FF2FFFH
Nonextended External memory, 02080–02FFFH
• FF3000–FFFFFH in external memory (external addresses F3000–FFFFFH)
NOTE
We recommend that you write FFH (the opcode for the RST instruction) to
unused program memory locations. This causes a device reset if a program
unintentional ly begins to exec ute in unused mem o ry.
5-5
8XC196NP, 80C196NU USER’S MANUAL
5.2.2.2 Special-purpose Memory
Special-purpose memory resides in locations FF2000–FF207FH. It contains several reserved
memory locations, the c hip configuration bytes (CC Bs), and vectors for both peripheral transaction server (PTS) and standard interrupts. Note tha t the speci al-purpose memory partition of the
80C196NU differs slightly from that of the 8XC196NP. Table 5-3 describes the spe ci al -purpose
memory; bold type highlights the differences.
Tabl e 5 -3. 8XC196NP and 80C196NU Special-purpose Memory Addresses
8XC196N P
Address
(Hex)
FF207F
FF205E
FF205D
FF2040
FF203F
FF2030
FF202F
FF201B
FF201A FF201A CCB1
FF2019 FF2019 Reserved (must contain 20H)
FF2018 FF2018 CCB0
FF2017
FF2014
FF2013
FF2000
80C196 N U
Address
(Hex)
FF207F
FF2060
FF205F
FF2040
FF203F
FF2030
FF202F
FF201B
FF2017
FF2010
FF200F
FF2000
Description
Reserved (each byte must contain FFH)
PTS vectors
Upper interr upt vectors
Reserved (each byte must contain FFH)
Reserved (each byte must contain FFH)
Lower interrupt vectors
— 80C196NP and 80C196NU: This parti tion is in external memory (exte rnal addresses
F2000–F207FH).
— 83C196NP: The REMAP bit (CCB1.2), the EA# input, and the type of instruction
(extended or nonextended) control access to this partition, as shown in Table 5-4.
Table 5-4. Special-purpose Memory Access for the 83C196NP
5-6
REMAP
(CCB1.2)
X Asserted Extended or nonextended External memory , F2000–F207FH
0 Deasserted Extended or nonextended Internal ROM, FF2000–FF207FH
1 Deasserted
EA# Pin
Instruction
Type
Extended Internal ROM, FF2000–FF207FH
Nonextended External memory, 02000–0207FH
Memory Location Accessed
MEMORY PARTITIONS
5.2.2.3 Reserved Memory Locations
Several memory locations are reserved for testing or for use in future products. Do not read or
write the se locations except t o i nit iali ze t hem to the val ues shown in Table 5-3. The function or
contents of these locations ma y chan ge in future revis ions; software that uses rese r ved locatio ns
may not function properly.
5.2.2.4 Interrupt and PTS Vectors
The peripheral transaction server ( PTS) vectors contain the addresses of the PTS control blocks.
The upper and lower interrupt vectors contain the addresses of the interrupt service routines. See
Chapter 6, “Standard and PTS Interrupts, ” for more informatio n.
5.2.2.5 Chip Configuration Bytes
The chip configuration bytes (CCB0 and CCB1) specify the operating environment. They specify
the bus width, bus mode (multiplexed or demultiplexed), write-control mode, wait states, powerdown enabling, and the operating mode (1-Mbyte or 64-Kbyte mode). For the 83C196NP , CCB1
also controls ROM remapping. For the 80C196NP and 80C196NU, the CCBs are stored in external memory (locations F2018–F201AH). For the 83C196NP, the C CBs can be s tored either in external memory (locations F2018–F201AH) or in the on-chip ROM (locations FF2018–
FF201AH).
The chip configuration bytes are the first bytes fetched from memory when the device leaves the
reset state. The post-reset sequence loads the CCBs into the chip configuration registers (CCRs).
Once they are loaded, the CCRs can not be changed unt il the next devi ce reset. Typically, the
CCBs are programmed once when the user program is compiled and are not redefined during normal operation. “Chip Configuration Registers an d Chip Configuration Bytes” on page 13-14 describes the CCBs and CCRs.
5.2.3 Peripheral Special-func tio n Registers (S FR s)
Locations 1F00–1FFFH provide access to the peripheral SFR s (see Table 5-5). Locations in this
range that are omitted from the table are reserved. The peripheral SFRs are I/O control registers;
they are physically located in the on-chip peripherals. Peripheral SFRs can be windowed and they
can be addressed either as words or bytes, except as noted in the table.
5-7
8XC196NP, 80C196NU USER’S MANUAL
Table 5-5. Peripheral SFRs
Reserved Locations EPORT SFRs
Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte
1FEEH Reserved Reserved
1FECH Reserved Reserved
1FEAH Reserved Reserved
1FE8H Reserved Reserved
Ports 1–4 SFRs Serial I/O and PWM SFRs
Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte
1FDEH P4_PIN P3_PIN 1FBEH Reserved Reserved
1FDCH P4_REG P3 _RE G 1 FBCH SP_ BAUD (H) SP_BAUD (L)
1FDAH P4_DIR P3_DI R 1FBAH SP_CON SBUF_TX
1FD8H P4_MODE P3_MO DE 1F B8H SP_STATUS SBUF_RX
1FD6H P2_PIN P1_PIN 1FB6H Reserved CON_R EG0
1FD4H P2_ REG P1_REG 1FB4H Reserved PW M2_CONT R OL
1FD2H P2_ DIR P1 _DIR 1FB2H Reserved PW M1_CONT ROL
1FD0H P2_ MO DE P1 _MO DE 1FB0 H Reserved PW M0_CONT R OL
1FCEH Reserved Reserved 1FAEH Reserved Reserved
• • • • • • • • • • • • • • • • • •
1FC0H Reserved Reserved 1FA0H Reserved Reserved
EPA, Timer 1, and Timer 2 SFRs Chip-sel ect SFR s
Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte
1F9EH Reserved EPA_PEND
††† †
1F9CH Reserved EPA_MASK
1F9AH Reserved Reserved
1F98H Reserved Reserved 1F68H ADDRCOM 5 (H) ADDRCOM5 (L)
†
1F96H TIMER2 (H) TIMER2 (L)
1F94H Reserved T2CONTROL
†
1F92H TIMER1 (H) TIMER1 (L)
1F90H Reserved T1CONTROL 1F60H ADDRCOM4 (H) ADDRCOM 4 (L)
†
1F8EH EPA3_TIME (H) EPA3_TIME (L) 1F5EH Reserved Reserved
†
1F8CH EPA3_CON (H) EPA3_CON (L) 1F5CH Reserved BUSCON3
†
1F8AH EPA2_TIME (H) EPA2_TIME (L) 1F5AH ADDRMSK3 (H) ADDRMSK3 (L)
1F88H Reserved EPA2_CON 1F58H ADDRCOM 3 (H) ADDRCOM3 (L)
†
1F86H EPA1_TIME (H) EPA1_TIME (L) 1F56H Reserved Reserved
†
1F84H EPA1_CON (H) EPA1_CON (L) 1F54H Reserved BUSCON2
†
1F82H EPA0_TIME (H) EPA0_TIME (L) 1F52H ADDRMSK2 (H) ADDRMSK2 (L)
1F80H Reserved EPA0_CON 1F50H ADDRCOM 2 (H) ADDRCOM2 (L)
†
Must be addressed as a word.
††
For the 8XC196NP, these are memory-mapped locations. They must be addressed with indirect or
indexed instructions, and they cannot be windowed.
†††
The EPA_PEND register was called EPA_STAT in previous documentation for the 8XC196NP.
††††
The 8XC1 9 6NP can be identif ie d by its signature word , 80 EFH, at locatio n s 1F46–1F 47H. The
8XC196NU has no signature word; locations 1F 46 –1F4 7H are reser ved.
††
1FE6H EP_PIN Reserved
††
1FE4H EP_REG Reserved
††
1FE2H EP_DIR Reserved
††
1FE0H EP_MODE Reserved
1F6EH Reserved Reserved
†
1F6CH Reserved BUSCON5
†
1F6AH ADDRMSK5 (H) ADDRMSK5 (L)
†
1F66H Reserved Reserved
†
1F64H Reserved BUSCON4
†
1F62H ADDRMSK4 (H) ADDRMSK4 (L)
5-8
MEMORY PARTITIONS
Table 5-5. Peripheral SFRs (Contin ued)
EP A, Timer 1, and Timer 2 SFRs (Continued) Chip-select SFRs (Continued)
Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte
1F7EH Reserved Reserved 1F4EH Reserved Reserved
1F7CH Reserved Reserved 1F4CH Reserved BUSCON1
1F7AH Reserved Reserved 1F4AH ADDRMSK1 (H) ADDRMSK1 (L)
1F78H Reserved Reserved 1F48H ADDRCOM 1 (H) ADDRCOM1 (L)
1F76H Reserved Re served 1F46H Signature (H)
1F74H Reserved Reserved 1F44H Reser ve d BUSCON0
1F72H Reserved Reserved 1F42H ADDRMSK0 (H) ADDRMSK0 (L)
1F70H Reserved Reserved 1F40H ADDRCOM 0 (H) ADDRCOM0 (L)
†
Must be addressed as a word.
††
For the 8XC196NP, these are memory-mapped locations. They must be addressed with indirect or
indexed instructions, and they cannot be windowed.
†††
The EPA_PEND register was called EPA_STAT in previous documentation for the 8XC196NP.
††††
The 8XC1 9 6NP can be identif ie d by its signature word , 80 EFH, at locatio n s 1F46–1F 47H. The
8XC196NU has no signature word; locations 1F 46 –1F4 7H are reser ved.
††††
Signature (L)
††††
NOTE
Using any SFR as a base or index register for indirect or indexed operations
can cause unpredictable results because external events can c hange the
contents of SFRs. Also, because some SFRs are cleared when read, consider
the implications of using an SFR as an operand in a read-modify-write
instructi on (e.g., XORB ).
5.2.4 Register File
The register fi le is divided into an u pper registe r file and a lower registe r file (Figure 5-3). The
upper register file consists of general-purpose register RAM. The lower register file contains additional general-purpose regi ster RAM alo ng with the stack pointer (SP ) and the CPU specialfunction registers (SFRs).
5-9
8XC196NP, 80C196NU USER’S MANUAL
Page 00H
Address
03FFH
General-purpose
Register RAM
0100H
Address
03FFH
0100H
00FFH
0000H
Upper
Register File
Lower
Register File
General-purpose
Register RAM
Stack Pointer
CPU SFRs
0100H
00FFH
00FFH
001AH
001AH
0019H
0019H
0018H
0018H
0017H
0017H
0000H
0000H
A0301-02
Figure 5-3. Register File Memory Map
Table 5-6 on page 5-11 lists the register file memory addresses. The RAL U accesses the lower
register file directly, without the use of the memory controller. It also acc es ses a windowed loca-
tion directly (se e “Windowing” on page 5-13). Only the upper register file and the peripheral
SFRs can be windowed. Registers in the lower register file and registers being windowed can be
accessed with direc t addressi n g.
5-10
NOTE
The register file must n ot contain code. An attempt to exec ute an instruct ion
from a location in the register file cause s the me mory controller to fetch the
instruction from externa l memo ry.
MEMORY PARTITIONS
Table 5-6. Register File Memory Addresses
Address
Range
03FFH
0100H
00FFH
001AH
0019H
0018H
0017H
0000H
5.2.4.1 General-purpose Register RAM
General-purpose register RAM; upper register file Indirect, indexed, windowed direct
General-purpose register RAM; lower register file Direct, indirect, indexed
Stack pointer (SP); lower register file Direct, indirect, indexed
CPU special-function registers (SFRs); lower register file Direct, indirect, indexed
Description Addressing Modes
The lower regis ter file conta ins general -purpose register RAM. The s tack pointer l ocations can
also be used as general-purpose register RAM when stack operations are not being performed.
The RALU can acce ss thi s m em ory direc tly, using direct addressi ng.
The upper register file also contains ge neral-purpose registe r RAM. The RALU n ormally uses
indirect or indexed addressing to acces s the RAM in the upper register file . Windowing enables
the RALU t o use direct addressi n g t o a ccess this memory. (See Chapter 4, “Programming Considerations,” for a discussion o f addressing modes. ) Windowing provides fast context swi tching
of interrupt tasks and faster program exec ution. (See “ Windowing” on page 5-13.) PTS control
blocks and the stack are most efficient when located in the upper register fil e.
5.2.4.2 Stack Pointer (S P)
Memory locations 0018H and 0019H contain the stack pointer (SP). The SP contains the address
of the stack. The SP must point to a word (eve n ) address t hat i s two byt es ( for 64-Kbyte m o de)
or four bytes (for 1-Mbyt e mode) greater than the desire d sta rting address. Before the CPU executes a subroutine call or interrupt service routine, it decrement s the SP (by two in 64-Kbyte
mode; by four in 1-Mbyte mode). Ne xt, it copies (PUSHes) the address of the next inst ruction
from the program counter onto the stack. It then loads the address of t he subroutine or i nte rr upt
service routine into the program counter. When it executes the return-from-subroutine (RET) instruction at the end of the subroutine or interrupt service routine, the CPU loads (POPs) the contents of the top of the stack (that is, the return address) into the program counter. Finally, it
increments the SP (by two in 64-Kbyte mode; by four in 1-Mbyte mode).
5-11
8XC196NP, 80C196NU USER’S MANUAL
Subroutines may be nested. That is, each subroutine may call other subroutines. The CPU PUSHes the contents of the program counter onto the stack each time it executes a subroutine call. The
stack grows downward as entries are added. The only limit to the nesting depth is the amount of
available m em ory. As the CP U returns from e ach nest ed subroutine, it POPs t he address off the
top of the stack, and the next return address moves to the top of the stack.
Your program must load a word-aligned (even) address i nto the stack pointer. Select an address
that is two bytes (for 64-Kbyte mode) or four bytes (for 1-Mbyte mode) greater than the desired
starting address because the CPU automatically decrements the stack pointer before it pushes the
first byte of the return address onto the stack. Remember that the stack grows downward, so allow
sufficient room for the maximum number of stack entries. The stack must be located in page 00H,
in either the internal regi ste r file or ext ernal R AM . The stack c an be use d m ost effic ientl y w hen
it is located in the upper register file.
The following example initializes the top of the upper register file as the stack.
LD SP, #400H ;Load stack pointer
5.2.4.3 CPU Special-function Registers (SFRs)
Locations 0000–0017H in the lower register file are the CPU SFRs. Table 5-7 lists the CPU SFRs
for the 8XC196NP an d the 80C196NU and highlights those that are unique to the 80C196NU.
Appendix C desc ribes the CPU SFRs.
T able 5-7. CPU SFRs
8XC196NP CPU SFRs 80C196NU CPU SFRs
Address H igh (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Eve n) Byte
0016H Reserved Reserved 001 6H Reserved Reserved
ACC_03
†
†
†
WSR
ACC_02
ACC_00†
†
0014H Reserved WSR 0014H WSR1
0012H INT_MASK1 INT _PE ND1 001 2H INT_MASK 1 INT _PE ND1
0010H Reserved Reserved 001 0H Reserved Reserved
000EH Reser ved Reserved 000 EH
000CH Reserved Reserved 000CH††ACC_01
000AH Rese rved Reser ved 000AH ACC_ STAT† Rese r ved
0008H INT_PEND INT_MASK 0008H INT_PE ND INT_MASK
0006H PTSSRV (H) PTSSRV (L) 0006H PTSSRV (H) PTSSRV (L)
0004H PTSSEL (H) PTSSEL (L) 0004H PTSSEL (H) PTSSEL (L)
0002H ONES_REG (H) ONES_REG (L) 0002H ONES_REG (H) ONES_REG (L)
0000H ZERO_REG (H) ZERO_REG (L) 0000H ZERO_REG (H) ZER O_REG (L)
†
These SFRs are unique to the 80C196NU.
††
Must be addressed as a word.
††
5-12
MEMORY PARTITIONS
5.3 WINDOWING
Windowing expands the amount of memory that is accessible with direct addressing. Dire ct addressing can acces s the l ower regi ster fil e w ith s hort, fast-e xec uti ng inst ruc tions. With windowing, direct addressing can also access the upper register file and peripheral SFRs.
Windowing maps a se gment of hig her memory (the upper register file or peripheral SFRs) into
the lower register file. The 8XC196NP has a single window selection register, while the
80C196NU has two. The first, WSR, is the same in both devices. WSR selects a 32-, 64-, or 128byte segment of higher memory to be windowed into the top of the lower register file space.
The second, WSR1, is unique to the 80C196NU. WSR1 selects a 32- or 64-byte segment of higher memor y to be windowed i nto the middle of the lower register fi le (Fig ure 5-4). Because the
areas in the lower register file do not overlap, two windows can be in effect at the same time. For
example, you can activa te a 128-byte window using WSR and a 64-byte window using WSR1
(Figure 5-4). These two wind ows occupy locations 0040–00FFH in the lower register file, leaving locations 001A–003FH for use as general-purpose register RAM, locations 0018–0019H for
the stack pointer or general-purpose register RAM, and locations 0000–0017H fo r the CPU SFRs.
128-byte Window
(WSR = 17H)
Window in
Lower Register File
8XC196NP 80C196NU
03FFH
0380H
037FH
0340H
00FFH
0080H
007FH
0040H
003FH
0000H
128-byte Window
(WSR = 17H)
64-byte Window
(WSR1 = 2DH)
WSR Window in
Lower Register File
WSR1 Window in
Lower Register File
Figure 5-4. Windowing
A3053-02
5-13
8XC196NP, 80C196NU USER’S MANUAL
5.3.1 Selecting a Window
The window selection register (Figure 5-5) has two functions. The HLDEN bit (WSR.7) enables
and disables the bus-hold protocol (see Cha pter 13, “Interfacing with Exte rnal Memory”); it is
unrelated to windowing. The remaining bits select a window to be mapped into the top of the lower register file. Window selection register 1 (Figure 5-6) selects a second window to be mapped
into the middle of the 80C196NU’s lower register file .
Table 5-8 provides a quick reference of WSR values for windowing the peripheral SFRs. Table
5-9 on page 5-15 lists the WSR values for windowing the upper register file.
WSR
The window selectio n registe r (WSR) has two functi ons. One bit enable s and disa bles the bus-h old
protocol. The remaining bits select windo w s. Windows map section s of RAM into the top of the lower
register file, in 32-, 64-, or 128-byte in crem ents. PUS HA saves this register on the stack and POPA
res tores it .
7 0
HLDEN W6 W5 W4 W3 W2 W1 W0
Bit
Number
7 HLDEN HOLD#, HLDA# Protocol Enable
6:0 W6:0 Window Selection
Bit
Mnemonic
Function
This bit enables and disables the bus-hold protocol (see Chapter 13,
“Interfacing with External Memory”). It has no effect on windowing.
1 = enable
0 = disab le
These bits specify the window size and window number. See Table 5-8
on page 5-15 or T able 5-9 on page 5-15.
Address:
Reset State:
0014H
00H
Figure 5-5. Window Selection (WSR) Register
5-14
MEMORY PARTITIONS
WSR1
(80C196NU)
Address:
Reset State:
Window select ion 1 (WSR1 ) registe r selects a 32- or 64-byte segme nt of the upper registe r file or
peripheral SFRs to be windowed into the middle of the lower register file, below any window selected
by the WSR.
7 0
80C196NU
Bit
Number
— W6 W5 W4 W3 W2 W1 W0
Bit
Mnemonic
Function
7 — Reserved; always write as zero.
6:0 W6:0 Window Selection
These bits specify the window size and window number. See Table 5-8 on
page 5-15 or Table 5-9 on page 5-15.
Figure 5-6. Window Selection 1 (WSR1) Register
Table 5-8. Selecting a Window of Peripheral SFRs
Peripheral
for 32-byte Window
(00E0–00FFH or 0060–007FH)
WSR or WSR1 Value
EPORT
†
7FH
†
Ports 1–4 7EH
PWM and SIO 7DH
Chip selects 4–5 7BH
†
For the 8XC196NP, the EPORT SFRs are memory-mapped SFRs. They must be accessed with
indirect, indexed, or extended addres sing; they cann ot be windowe d.
WSR or WSR1 Value
for 64-byte Wind ow
(00C0–00FFH or 0040–007FH)
†
3FH
3EHEPA and Timers 7CH
3DH 1EHChip selects 0–3 7AH
WSR Value for
128-byte Window
(0080–00FFH)
1FH
0015H
00H
†
Table 5-9. Selecting a Window of the Upper Register File
Register RAM
Locations
(Hex)
03E0–03FF 5FH
03C0–03DF 5EH
03A0–03BF 5DH
WSR or WSR1 Value
for 32-byte Window
(00E0–00FFH or 00 60–007F H)
WSR or WSR1 Value
for 64-byte Window
(00C 0–00FFH or 0040–007FH)
2FH
2EH0380–039F 5CH
WSR Value
for 128-byte Window
(0080–00FFH)
17H
5-15
8XC196NP, 80C196NU USER’S MANUAL
Table 5-9. Selecting a Window of the Upper Register File (Continued)
Register RAM
Locations
(Hex)
0360–037F 5BH
0340–035F 5AH
0320–033F 59H
02E0–02FF 57H
02C0–02DF 56H
02A0–02BF 55H
0260–027F 53H
0240–025F 52H
0220–023F 51H
01E0–01FF 4FH
01C0–01DF 4EH
01A0–01BF 4DH
0160–017F 4BH
0140–015F 4AH
0120–013F 49H
WSR or WSR1 Value
for 32-byte Window
(00E0–00FFH or 00 60–007F H)
WSR or WSR1 Value
for 64-byte Window
(00C 0–00FFH or 0040–007FH)
2DH
2CH03 00–031F 58H
2BH
2AH0280–029F 54H
29H
28H0200–021F 50H
27H
26H0180–019F 4CH
25H
24H0100–011F 48H
WSR Value
for 128-byte Window
(0080–00FFH)
16H
15H
14H
13H
12H
5.3.2 Addressing a Location Through a Window
After you have selected the desired wi n dow, you need to know the direct address of the memory
location (the ad dress in the lower regist er file). For SFR s, refer to the WSR tables in Appen dix
C. For register file locations, calculat e the direct address as follows:
1. Subtract the base address of the area to be remapped (from Table 5-10 on page 5-17) from
the address of the desired location. This give s you the offset of that particular locat ion.
2. Add the offset to the base address of the window (from Table 5-11). The result is the direct
address.
5-16
MEMORY PARTITIONS
Table 5-10. Windows
Base
Address
(Hex)
WSR or WSR1 Value
for 32-byte Window
(00E0–00FFH or 00 60–007F H)
WSR or WSR1 Value
for 64-byte Window
(00C 0–00FFH or 0040–007FH)
Periphe ral SFRs
†
1FE0
1FC0 7EH
†
7FH
†
3FH
1FA0 7DH
3EH1F80 7C H
1F60 7 B H
1F40 7 A H
3DH
1F20 79H
3CH1F00 78H
Upper Register File
03E0H 5FH
03C0H 5EH
2FH
03A0H 5DH
2EH0380H 5CH
0360H 5BH
0340H 5AH
2DH
0320H 59H
2CH0300H 58H
02E0H 57H
02C0H 56H
2BH
02A0H 55H
2AH0280H 54H
0260H 53H
0240H 52H
29H
0220H 51H
28H0200H 50H
01E0H 4FH
01C0H 4EH
27H
01A0H 4DH
26H0180H 4CH
0160H 4BH
0140H 4AH
25H
0120H 49H
24H0100H 48H
†
For the 8XC196NP, locations 1FE0–1FFF H conta in memory-m ap ped SFRs that cannot be
windowed. Reading these locations through a window returns FFH; writing these locations through
a window has no effect. For the 80C196NU, these locations are not memory-mapped; they can be
windowed.
WSR Value for
128-byte
Window
(0080–00FFH)
†
1FH
1EH
17H
16H
15H
14H
13H
12H
5-17
8XC196NP, 80C196NU USER’S MANUAL
Table 5-11. Windowed Base Addresses
Window Size
32-byte 00E0H 0060H
64-byte 00C0H 0040H
128-byte 0080H —
WSR Windowed Base Address
(Base Addres s in Lowe r Regis ter File )
WSR1 Windowed Bas e Addre ss
(Base Addre ss in Lower Re gister File)
80C196NU Only
Appendix C includes a table of the windowable SFRs with the window selection regis ter values
and direct addresses for each window size. The following examples explain how to determine the
WSR value and direct address for any windowable location. An additional example shows how
to set up a window by using the li nker locator.
5.3.2.1 32-byte Windowing Example
Assume that you wish to access location 014BH (a location in the upper register file used for general-purpose register RAM) with direct addressing through a 32-byte window . Table 5-10 on page
5-17 shows that you need to write 4AH to the window sel ection register. It also shows that the
base address of the 32-byte memory area is 0140H. To determine the offset, subtract that base address from the address to be accessed (014BH – 0140H = 000BH). Add the offset to the base address of the window in the lower register file (from Table 5-11). The direct address is 00EBH
(000BH + 00E0H) for a WSR window or 006BH (000BH + 0060H) for a WSR1 window.
5.3.2.2 64-byte Windowing Example
Assume that you wish to access the SFR at location 1F8CH with direct addressing through a 64byte window. Table 5-10 on page 5-17 shows that you need to write 3EH to the window selection
register. It also shows that the base address of t he 6 4-byte me mory a rea is 1F80H. To determine
the offset, subtract that base address from the address to be accessed (1F8CH – 1F80H = 000CH).
Add the offset to the base address of the window in the lower register file (from Table 5-11). The
direct address is 00CCH (000CH + 00C0H) for a WSR window or 004CH (000CH + 0040H) for
a WSR1 window.
5.3.2.3 128-byte Windowing Example
Assume that you wish to access the SFR at location 1F82H with direct addressing through a 128byte window. Table 5-11 on page 5-18 shows that you need to write 1FH to the window selection
register. It also shows that the base address of the 128-byte mem ory area is 1F80H. To determine
the offset, subtract that base address from the address to be accessed (1F82H – 1F80H = 0002H).
Add the offset to the base address of the window in the lower register file (from Table 5-11). The
direct address is 0082H (0002H + 0080H).
5-18
MEMORY PARTITIONS
5.3.2.4 Unsupported Locations Wi ndowing Example (8XC196NP Only)
Assume that you wish to access location 1FE7H (the EP_PIN re gister, a memory-map ped SFR)
with direct addressing through a 128-byte window. This location is in the range of addresses
(1FE0–1FFFH) that cannot be windowed. Although y ou could s et up the window by writing 1FH
to the WSR, reading this location thr ough the window would return FFH (all ones) and writing
to it would not change the contents. However, you could directly address the remaining SFR s in
the range of 1F80–1FDFH.
5.3.2.5 Using the Linker Locator to Set Up a Window
In this example, the linker locator is used to set up a window. The linker locator locates the window in the upper register file and determines the value to load in the WSR for access to that window. (Plea se consult the manual provided with the linker locato r for details.)
********* mod1 **************
mod1 module main ;Main module for linker
public function1
extrn ?WSR ;Must declare ?WSR as external
wsr equ 14h:byte
sp equ 18h:word
oseg
var1: dsw 1 ;Allocate variables in an overlayable segment
var2: dsw 1
var3: dsw 1
cseg
function1:
push wsr ;Prolog code for wsr
ldb wsr, #?WSR ;Prolog code for wsr
add var1, var2, var3 ;Use the variables as registers
;
;
;
ldb wsr, [sp] ;Epilog code for wsr
add sp, #2 ;Epilog code for wsr
ret
end
******** mod2 **************
5-19
8XC196NP, 80C196NU USER’S MANUAL
public function2
extrn ?WSR
wsr equ 14h:byte
sp equ 18h:word
oseg
var1: dsw 1
var2: dsw 1
var3: dsw 1
cseg
function2:
push wsr ;Prolog code for wsr
ldb wsr, #?WSR ;Prolog code for wsr
add var1, var2, var3
;
;
;
ldb wsr, [sp] ;Epilog code for wsr
add sp, #2 ;Epilog code for wsr
ret
end
******************************
The following is an example of a linker invocation to link and loc ate the modules and to determine the proper windowing.
RL196 MOD1.OBJ, MOD2.OBJ registers(100h-03ffh) windowsize(32)
The above linker control s tel l the lin ker to us e regist ers 0100– 0 3FFH for windowing an d to use
a window size of 32 bytes. (These two controls enable windowing.)
The following is the map listing for the resultant output module (MOD1 by default):
SEGMENT MAP FOR mod1(MOD1):
TYPE BASE LENGTH ALIGNMENT MODULE NAME
---- ---- ------ --------- ----------**RESERVED* 0000H 001AH
STACK 001AH 0006H WORD
*** GAP *** 0020H 00E0H
OVRLY 0100H 0006H WORD MOD2
OVRLY 0106H 0006H WORD MOD1
*** GAP *** 010CH 1F74H
CODE 2080H 0011H BYTE MOD2
CODE 2091H 0011H BYTE MOD1
*** GAP *** 20A2H DF5EH
5-20
MEMORY PARTITIONS
This listing shows the disassembled code:
2080H ;C814 | PUSH WSR
2082H ;B14814 | LDB WSR,#48H
2085H ;44E4E2E0 | ADD E0H,E2H,E4H
2089H ;B21814 | LDB WSR,[SP]
208CH ;65020018 | ADD SP,#02H
2090H ;F0 | RET
2091H ;C814 | PUSH WSR
2093H ;B14814 | LDB WSR,#48H
2096H ;44EAE8E6 | ADD E6H,E8H,EAH
209AH ;B21814 | LDB WSR,[SP]
209DH ;65020018 | ADD SP,#02H
20A1H ;F0 | RET
The C compiler can also take a dvantage of this fea ture if the “windows” switch is enabled. F or
details, see the MCS 96 microcontroller architecture software products in the Development Tools
Handbook.
5.3.3 Windowing and Addressi ng Mod es
Once windowing is enabled, the windowed locations can be accessed both through the window
using direct addressing and through its actual address using indi rect or indexed ad dressing. The
lower register fi le loc ations tha t are cove red by the wi n d ow are alwa ys ac cessi ble by i ndirec t or
indexed operations. To re-enable direct access to the entire lower register file, clear bits 6:0 of the
window selection register. T o enable direct access to a particular location in the lower register file,
you may select a smaller window that does not cover that location.
When windowing is enabled:
• a direct instr uction that uses an ad dress within the lowe r register file actually accesse s the
window in the upper register file;
• an indirect or indexed instruction that uses an address within either the lower register file or
the upper register file acces ses the actual location in mem o ry.
The following sample code illustrates the difference between direct and indexed addressing when
using windowing.
PUSHA ; Pushes the contents of WSR onto the stack
LDB WSR, #17H ; Selects window 17H, a 128-byte block
ADD 40H, 80H ; mem_word(40H)←mem_word(40H) + mem_word(380H)
ADD 40H, 80H[0] ; mem_word(40H)←mem_word(40H) + mem_word(80H +0)
ADD 40H, 380H[0] ; mem_word(40H)←mem_word(40H) + mem_word(380H +0)
POPA ; reloads the previous contents into WSR
; (windows 0380-03FFH into 0080-00FFH)
; The next instruction uses direct addr
; The next two instructions use indirect addr
5-21
8XC196NP, 80C196NU USER’S MANUAL
5.4 REM APPING INTERNAL ROM (83C196NP ONLY)
The 83C196NP’s 4 Kbytes of ROM are located in FF2000–FF2FFFH. By using the REMAP bit
(CCB1.2) and the E A# input, you can also access these locations in external memory (page 0FH
or page 00H). The REMA P bit is l oaded from CCB1 upon leaving reset and cannot be c han ged
until the next reset . Tie EA# low to access ext ernal me mory or tie it high to a ccess the on-chip
ROM. (Refer to the EA# description in Appendix B for additional information on using the EA#
pin.)
NOTE
The EA# input is effective only for accesses to the 83C196NP’s on-chip ROM
(FF2000–FF2FFFH). For an access to an y other location, the value of EA# is
irrelevant.
Without remapping (CCB1.2 = 0), an access to FF2000–FF2FFFH is directed to internal ROM
(FF2000–FF2FFFH) if EA# is high and to external memory (F2000–F2FFFH) if EA# is low. In
either case, data in this area must be ac cessed wit h extende d instruct ions.
With remapping enabled (CCB1.2 = 1) and EA# hig h, you can access the contents of FF2000–
FF2FFFH in two ways:
• in internal ROM (FF2000–FF2FFFH) using an extended instruction
• in external memory (002000–002FFFH) using a nonextended ins truction. This makes the
far data in FF2000–FF2FFFH accessibl e as near dat a.
With remapping enabled (CCB1.2 = 1) and EA# low, you can access the contents of FF2000–
FF2FFFH in external memory (F2000–F2FFFH) using an extended instruction.
An advantage of remapping ROM is that it makes the data in ROM accessible as near data in external memory page 00H. The data can then be accessed more quickly with nonextended instructions. An advantage of not rem apping ROM is that the c orresponding area in external memory
page 00H is available for storing additional near data.
5-22
MEMORY PARTITIONS
5.5 F ETCHI NG CODE AND DATA IN THE 1-MBYT E AND 64-KBYTE MO DES
This section descri bes how the devic e fetc hes instruct ions a n d access es data in the 1-M byte and
64-Kbyte modes. When the devic e leaves rese t, the MODE64 bit (C CB1. 1) selec ts the 1-Mbyte
or 64-Kbyte mode. The mode cannot be changed until the next reset.
NOTE
The 8XC196NP and 80C196NU have two major differences concerning code
and data fetches. The 8XC196NP’s prefetch queue is four bytes, whil e the
80C196NU’s is eight bytes. The 8XC196NP gives higher priority to
instruction fetches than to data fetches, while the 80C196NU gives hig her
priority to data accesses than to instruction fetches.
5.5.1 Fetching Instructions
The 24-bit program counter (Figure 5-7) consists of the 8-bit extended pr ogram counter (EPC)
concatenated wi th the 16-bit master program counter (PC). It holds the address of the next instruction to be fetched. The page number of the inst r uction is in the EPC . In 1-Mbyte mode, the
EPC can have any 8-bit value. H owever, only the four LSBs of the EPC are implemented externally, as EPORT pins A19:16. This means t hat in the 1-Mbyte mode, t he device can fetch code
from any page in the 1-Mbyte address space: 00H–0FH and FFH (FFH overlays 0FH). In 64Kbyte mode, the EPC is fixed at FFH, which limi ts program memory to page FFH (and 0FH).
EPC PC
23 16 15 0
A2513-03
Figure 5-7. The 24-bit Program Counter
5.5.2 Accessing Data
Internally, data addresses have 24 bits (Figure 5-8 on page 5-24). The lower 16 bits are supplied
by the 16-bit data address register. The upper 8 b its (the page number) come from different sour ces for nonextended and extended instructions. (“EPORT Operation” on page 7-12 describes how
the page number is output to the EPORT pins.)
5-23
8XC196NP, 80C196NU USER’S MANUAL
For nonextended instructions, the EP_REG register provides the page number. Data and constants
in this page are called near data and near constants.
NOTE
The 8XC196NP allows you to cha nge the value of EP_REG to control which
memory page a nonextended instruction accesses. However, software tools
require that EP_REG be equal to 00H. The 80C196NU forces all nonextended
data accesses to page 00H. You cannot use EP_REG to change pages.
Data outside the page specified by EP_REG is called far data. To access far data, you must use
extended instructions. Fo r extended instruct ions, the CPU provides the page number.
From EP_REG 16-bit Data Address Register
Nonextended Address
23 16 15 0
From CPU 16-bit Data Address Register
Extended Address
23 16 15 0
A2514-01
Figure 5-8. Formation of Extended and Nonextended Addre sses
The code example below illust rates the use of exten ded instruct ions to acce ss data in page 01H.
EP_REG EQU 1FE5H
TEMP: DSW 1
RESULT: DSW 1
SUBB: PUSHA ;save flags, disable interrupts
DONE: BR DONE
5-24
RSEG AT 1CH
CSEG AT 0FF2080H
. ;some code
.;
.;
LD TEMP,#1234H ;
EST TEMP,010600H ;store temp value in 010600H
ADD RESULT,TEMP,#4000H ;do something with registers
EST RESULT,010602H ;store result in 010602H
. ;more eld/est instructions
.;
.;
POPA ;restore flags and interrupts
RET ;
. ;more code
.;
.;
END
MEMORY PARTITIONS
5.5.3 Code Fetches in the 1-Mbyte Mode
CCR1.1 (the MODE64 bit) controls whether t he device opera tes in 1-Mbyte or 64-Kbyte mode.
CCR1 is loaded with the contents of CCB1 at reset. When MODE64 is clear, the device operates
in 1-Mbyte mode. In this mode, code can execute from any page in the 1-Mbyte add ress space.
An extended jump, branch, or call instruction across pages changes the EPC value to the destination page. For example, assume that code is executing f rom page FFH. The following code segment branches to an exter nal memory loca tio n in page 00H and continues exec ution.
0FF2090H: LD TEMP,#12H ; code executing in page FFH
003000H: ADD TEMP,#50H ; code executing in page 00H
ST TEMP,PORT1 ; code executing in page FFH
EBR 003000H ; jump to location 3000H in page 00H
Code fetches are from external memory or internal memory , depending on the device, the instruction address, and the value of the EA# input.
80C196NU:
Code executes from any page in external memory.
80C196NP:
For devices without internal nonvolatile memory, EA# must be tied low, and code executes from
any page in external memory.
83C196NP:
Code in all locations except FF2000–FF2FF FH executes from external memory.
Instruction fet ches from FF2000–FF2FFFH are controlled by the EA# input:
• If EA# is low, code executes from external memory.
• If EA# is high, code executes from internal ROM.
Note that the EA# input functions only for the address range FF2000–FF2FFFH.
5.5.4 Code Fetches in the 64-Kbyte Mode
CCR1.1 (the MODE64 bit) controls whether t he device opera tes in 1-Mbyte or 64-Kbyte mode.
CCR1 is loaded with the contents of CCB1 at reset. When MODE64 is set, the device operates in
64-Kbyte mode. In this mode, the EPC (Figure 5-7 on page 5-23) is fixed at FFH, whi ch allow s
instructions to execute from page FFH only. Extended jump, branch, and call instructions do not
function in the 64-Kbyte mode.
5-25
8XC196NP, 80C196NU USER’S MANUAL
Code fetches are from external memo ry or interna l memory, depending on the device, the memory location, and the value of the EA# input.
80C196NU:
Code executes from page 0FH in external memory. (The 80C196NU has no EA # input.)
80C196NP:
For devices without internal nonvolatile memory, EA# must be tied low, and code executes only
from page 0FH in exter nal memory.
83C196NP:
Code in all locations except FF2000–FF2FFFH executes from external memory.
Instruction fetches from FF2000–FF2FFFH are controlled by the EA# input:
• If EA# is low, code executes from exter nal memory (page 0FH).
• If EA# is high, code executes from internal ROM (page FFH).
5.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes
Data fetches are the same in the 1-Mbyte and 64-Kbyte modes. The device can access data in any
page. Data accesses to page 00H are nonextended. Data accesses to any other page are extended.
NOTE
This information on data fetches appli es only for EP_REG = 00H.
80C196NP and 80C196NU:
Data accesses to the register file (0000–03FFH) and the SFRs (1F00–1FFFH) are directed to the
internal regist ers. All other data ac cesse s are direc te d to external mem ory.
83C196NP:
Data accesses to the register file (0000–03FFH) and the SFRs (1F00–1FFFH) are directed to the
internal registe rs. Accesses to other loca tions are directed t o external memor y, except as note d
below:
Data accesses to FF2000–FF2FFFH depend on the EA# input:
• If EA# is low, accesses are to external memory (page 0FH).
• If EA# is high, accesses are to the internal ROM (page FFH ).
5-26
MEMORY PARTITIONS
Data accesses to 002000–002FFFH depend on the REMA P bit and the EA# input:
• If remapping is disabled (CC B1 .2 = 0), accesse s are exte rnal .
• If remapping is enabled (CCB1.2 = 1), accesses depen d on EA#:
— If EA# is low, a ccesse s are ext ernal (REMAP is ignored).
— If EA# is high, accesses are to the internal ROM.
5.6 MEMORY CONFIGURATION EXAMPLES
This section provides examples of memory configurations for both 64-Kbyte and 1-Mbyte mode.
Each example consist s of a circuit diagram and a memory map that describes how the address
space is imple mented. Chapte r 13, “Interfa cing with E xterna l Memory,” discusses the i nterfa ce
in detail and provides additio nal examples.
5.6.1 Example 1: Using the 64-Kbyte Mode
Figure 5-9 shows a system designed for operation in the 64-Kbyte mode. Code executes only
from page FFH, which is implemented by the 64-Kbyte flash memory . The 32-Kbyte RAM in the
upper half of page 00H stores near data. Table 5-12 on page 5-28 lists the memory addresses for
this example. (For memory map details, see Table 5-1 on page 5-4.)
CS1#
CS0#
A15:0
8XC196NP, NU
AD7:0
WR#
RD#
A15:0
AD7:0
Page FFH
A15:0
Code & Data
D7:0
OE# WE#
CE#
Flash
64Kx8
FF0000–
FFFFFFH
A14:0
AD7:0
A14:0
D7:0
CE#
Page 00H
RAM
32Kx8
Data
008000–
00FFFFH
OE# WE#
A2474-02
Figure 5-9. A 64-Kbyte System With an 8-bit Bus
80C196NP and 80C196NU: The flash memory, which implements page FFH, holds the specialpurpose memory (FF2000–FF207FH), code, and far constants.
5-27
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