Intel 8XC196NP, 80C196NU User Manual
8XC196NP, 80C196NU
Microcontroller
User’s Manual
8XC196NP, 80C196NU
Microcontrol ler
User’s Manual
August 2004 Order Number 272479-003
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, i ncluding
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© INTEL CORPORATION, 1996
ii
CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.
1 MANUAL CONTENTS ................................................................................................... 1-1
1.
2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
1.
3 RELATED DOCUMENTS .............................................................................................. 1-5
4 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-8
1.
1.4.
4 World Wide Web .....................................................................................................1-11
1.
5 TECHNICAL SUPPORT .............................................................................................. 1-11
6 PRODUCT LITERATURE............................................................................................ 1-11
1.
CHAPTER 2
ARCHITECTURAL
2.
1 TYPICAL APPLICATIONS............................................................................................. 2-1
2 DEVICE FEATURES ..................................................................................................... 2-2
2.
2.
3 BLOCK DIAGRAM......................................................................................................... 2-2
2.3.
1 CPU Control ..............................................................................................................2-3
2.3.
2 Register File ..............................................................................................................2-3
2.3.
3 Register Arithmetic-logic Unit (RALU) .......................................................................2-4
2.3.3.1 Code Execution ....................................................................................................2-4
2 Instruction Format ................................................................................................2-5
2.3.3.
2.3.
4 Memory Controller ....................................................................................................2-5
2.3.
5 Multiply-accumulate (80C196NU Only) .....................................................................2-6
2.3.
6 Interrupt Service ........................................................................................................2-6
2.
4 INTERNAL TIMING........................................................................................................ 2-7
2.
5 INTERNAL PERIPHERALS ......................................................................................... 2-11
2.5.
1 I/O Ports ..................................................................................................................2-11
2.5.
2 Serial I/O (SIO) Port ................................................................................................2-11
2.5.
3 Event Processor Array (EPA) and Timer/Counters .................................................2-11
2.5.
4 Pulse-width Modulator (PWM) ................................................................................2-12
2.
6 SPECIAL OPERATING MODES ................................................................................. 2-12
2.6.
1 Reducing Power Consumption ...............................................................................2-12
2.6.
2 Testing the Printed Circuit Board ............................................................................2-13
7 DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS ...... 2-13
2.
OVERVIEW
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8XC196NP, 80C196NU USER ’S MANUAL
CHAPTER 3
ADVANCED MATH FEATURES
3.1 ENHANCED MULTIPLICATION INSTRUCTIONS........................................................ 3-1
3.2 OPERATING MODES.................................................................................................... 3-2
3.2.1 Saturation Mode ........................................................................................................3-2
3.2.2 Fractional Mode ................................................................................ ........................3-3
3.3 ACCUMULATOR REGISTER (ACC_0
3.4 ACCUMULATOR CONTROL AND STATUS REGISTER (ACC_STAT) ....................... 3-5
CHAPTER 4
PROGRAMMING CONSIDERATIONS
4.1 OVERVIEW OF THE INSTRUCTION SET.................................................................... 4-1
4.1.1 BIT Operands ............................................................................................................4-2
4.1.2 BYTE Operands ........................................................................................................4-2
4.1.3 SHORT-INTEGER Operands .................................................................................... 4-2
4.1.4 WORD Operands ......................................................................................................4-3
4.1.5 INTEGER Operands .................................................................................................4-3
4.1.6 DOUBLE-WORD Operands ......................................................................................4-3
4.1.7 LONG-INTEGER Operands ...................................................................................... 4-4
4.1.8 QUAD-WORD Operands ..........................................................................................4-4
4.1.9 Converting Operands ................................................................................................4-4
4.1.10 Conditional Jumps ....................................................................................................4-4
4.1.11 Floating Point Operations .........................................................................................4-5
4.1.12 Extended Instructions ...............................................................................................4-5
4.2 ADDRESSING MODES . ................................................................................................ 4-6
4.2.1 Direct Addressing ......................................................................................................4-7
4.2.2 Immediate Addressing ..............................................................................................4-7
4.2.3 Indirect Addressing ...................................................................................................4-7
4.2.3.1 Extended Indirect Addressing ..............................................................................4-8
4.2.3.2 Indirect Addressing with Autoincrement ...............................................................4-8
4.2.3.3 Extended Indirect Addressing with Autoincrement ...............................................4-8
4.2.3.4 Indirect Addressing with the Stack Pointer . ..........................................................4-9
4.2.4 Indexed Addressing . .................................................................................................4-9
4.2.4.1 Short-indexed Addressing ....................................................................................4-9
4.2.4.2 Long-indexed Addressin g ....................................................................................4-9
4.2.4.3 Extended Indexed Addressing ...........................................................................4-10
4.2.4.4 Zero-indexed Addressing ................................................................................... 4-10
4.2.4.5 Extended Zero-indexed Addressing ...................................................................4-10
4.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS................................ 4-11
4.3.1 Direct Addressing ....................................................................................................4-11
4.3.2 Indexed Addressing . ...............................................................................................4-11
4.3.3 Extended Addressing . .............................................................................................4-11
4.4 DESIGN CONSIDERATIONS FOR 1-MBYTE DEVICES............................................ 4-11
4.5 SOFTWARE STANDARDS AND CONVENTIONS ..................................................... 4-11
x
).. .............. ........ ....... ....... ........ ....... ....... ....... .... 3-4
iv
CONTENTS
4.5.1 Using Registers .......................................................................................................4-12
4.5.2 Addressing 32-bit Operands ...................................................................................4-12
4.5.3 Addressing 64-bit Operands ...................................................................................4-12
4.5.4 Linking Subroutines ................................................................................................4-13
4.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES .................................... 4-14
CHAPTER 5
MEMORY PARTITIONS
5.1 MEMORY MAP OVERVIEW.......................................................................................... 5-1
5.2 MEMORY PARTITIONS................................................................................................ 5-3
5.2.1 External Memory .......................................................................................................5-5
5.2.2 Program and Special-purpose Memory ....................................................................5-5
5.2.2.1 Program Memory in Page FFH ............................................................................5-5
5.2.2.2 Special-purpose Memory .....................................................................................5-6
5.2.2.3 Reserved Memory Locations ...............................................................................5-7
5.2.2.4 Interrupt and PTS Vectors ........... ............ .................... ............ ................. ............5-7
5.2.2.5 Chip Configuration Bytes ............................................ .........................................5-7
5.2.3 Peripheral Special-function Registers (SFRs) ........................ .................... ...............5-7
5.2.4 Register File ..............................................................................................................5-9
5.2.4.1 General-purpose Register RAM .........................................................................5-11
5.2.4.2 Stack Pointer (SP) .............................................................................................. 5-11
5.2.4.3 CPU Special-function Registers (SFRs) .............................................................5-12
5.3 WINDOWING.................................................................... ........................................... 5-13
5.3.1 Selecting a Window ................................................................................................5-14
5.3.2 Addressing a Location Through a Window ............................................................. 5-16
5.3.2.1 32-byte Windowing Example ..............................................................................5-18
5.3.2.2 64-byte Windowing Example ..............................................................................5-18
5.3.2.3 128-byte Windowing Example ............................................................................5-18
5.3.2.4 Unsupported Locations Windowin g Example (8XC196NP Only) .......................5-19
5.3.2.5 Using the Linker Locator to Set Up a Window ........ ............................................5-19
5.3.3 Windowing and Addressing Modes .........................................................................5-21
5.4 REMAPPING INTERNAL ROM (83C196NP ONLY). .................................................. 5-22
5.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES .............. 5-23
5.5.1 Fetching Instructions ...............................................................................................5-23
5.5.2 Accessing Data .......................................................................................................5-23
5.5.3 Code Fetches in the 1-Mbyte Mode ........................................................................5-25
5.5.4 Code Fetches in the 64-Kbyte Mode ......................................................................5-25
5.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes .................................................5-26
5.6 MEMORY CONFIGURATION EXAMPLES................................................................. 5-27
5.6.1 Example 1: Using the 64-Kbyte Mode ....................................................................5-27
5.6.2 Example 2: A 64-Kbyte System with Additional Data Storage ................................5-29
5.6.3 Example 3: Using 1-Mbyte Mode ............................................................................ 5-31
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8XC196NP, 80C196NU USER ’S MANUAL
CHAPTER 6
STANDARD AND PTS INTERRUPTS
6.1 OVERVIEW OF INTERRUPTS............. ........................... ........................... ................... 6-1
6.2 INTERRUPT SIGNALS AND REGISTERS ................................................................... 6-3
6.3 INTERRUPT SOURCES AND PRIORITIES.................................................................. 6-4
6.3.1 Special Interrupts ........................................................................... ............ ..... ....... ...6-4
6.3.1.1 Unimplemented Opcode ......................................................................................6-5
6.3.1.2 Software Trap .......................................................................................................6-5
6.3.1.3 NMI ................................................................................ .......................................6-6
6.3.2 External Interrupt Pins .... ..........................................................................................6-6
6.3.3 Multiplexed Interrupt Sources ............................................ ................. ................. .....6-6
6.3.4 End-of-PTS Interrupts ...............................................................................................6-6
6.4 INTERRUPT LATENCY................................................................................................. 6-7
6.4.1 Situations that Increase Interrupt Latency ................................................................ 6-7
6.4.2 Calculating Latency ...................................................................................................6-8
6.4.2.1 Standard Interrupt Latenc y ...................................................................................6-8
6.4.2.2 PTS Interrupt Latency ..........................................................................................6-9
6.5 PROGRAMMING THE INTERRUPTS......................................................................... 6-10
6.5.1 Programming Considerations for Multiplexed Interrupts ..................... ....................6-11
6.5.2 Modifying Interrupt Priorities ...................................................................................6-13
6.5.3 Determining the Source of an I nterrupt ...................................................................6-15
6.6 INITIALIZING THE PTS CONTROL BLOCKS ............................................................. 6-17
6.6.1 Specifying the PTS Count ....................................................................................... 6-18
6.6.2 Selecting the PTS Mode .................................................... .....................................6-19
6.6.3 Single Transfer Mode ..............................................................................................6-20
6.6.4 Block Transfer Mode ...............................................................................................6-23
6.6.5 PWM Modes ...........................................................................................................6-26
6.6.5.1 PWM Toggle Mode Example .............................................................................6-27
6.6.5.2 PWM Remap Mode Example .............................................................................6-32
CHAPTER 7
I/O PORTS
7.1 I/O PORTS OVERVIEW ................................................................................................ 7-1
7.2 BIDIRECTIONAL PORTS 1–4 . ...................................................................................... 7-1
7.2.1 Bidirectional Port Operation ......................................................................................7-3
7.2.2 Bidirectional Port Pin Configurations ............ .......... ........ ....... ....... ....... .......... ....... ..... 7-7
7.2.3 Bidirectional Port Pin Configuration Example ...........................................................7-8
7.2.4 Bidirectional Port Considerations ..............................................................................7-9
7.2.5 Design Considerations for External Interrupt Inputs ...............................................7-11
7.3 EPORT ........................................................................................................................ 7-11
7.3.1 EPORT Operation ...................................................................................................7-12
7.3.1.1 Reset ............................................................ ....................................... ...............7-14
7.3.1.2 Output Enable ....................................................................................................7-14
7.3.1.3 Complementary Output Mode ............................................................................7-14
vi
CONTENTS
7.3.1.4 Open-drain Output Mode ...................................................................................7-14
7.3.1.5 Input Mode ................................................................................... .. ....................7-16
7.3.2 Configuring EPORT Pins .................................................................. ......................7-17
7.3.2.1 Configuring EPORT Pins for Extended-address Functions ................................7-17
7.3.2.2 Configuring EPORT Pins for I/O ........................................................................7-17
7.3.3 EPORT Considerations ....................................................................... ....................7-18
7.3.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold .............7-18
7.3.3.2 EP_REG Settings for Pins Configured as Extended-address Signals ...............7-18
7.3.3.3 EPORT Status During Instruction Execution ......................................................7-18
7.3.3.4 Design Considerations .......................................................................................7-19
CHAPTER 8
SERIAL I/O (SIO) PORT
8.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW................................................... 8-1
8.2 SERIAL I/O PORT SIGNALS AND REGISTERS. ......................................................... 8-2
8.3 SERIAL PORT MODES................................................................................................. 8-4
8.3.1 Synchronous Mode (Mode 0) ....................................................................................8-4
8.3.2 Asynchronous Modes (Modes 1, 2, and 3) ...............................................................8-5
8.3.2.1 Mode 1 .................................................................................................................8-6
8.3.2.2 Mode 2 .................................................................................................................8-7
8.3.2.3 Mode 3 .................................................................................................................8-7
8.3.2.4 Mode 2 and 3 Timings ..........................................................................................8-7
8.3.2.5 Multiprocessor Communications . .........................................................................8-8
8.4 PROGRAMMING THE SERIAL PORT.......................................................................... 8-8
8.4.1 Configuring the Serial Port Pins ........................ .......... ............ ............ .......... ............8-8
8.4.2 Programming the Control Register ............................................................................8-8
8.4.3 Programming the Baud Rate and Clock Source .......................................................8-8
8.4.4 Enabling the Serial Port Interrupts ...................................................... ............... ..... 8 -13
8.4.5 Determining Serial Port Status .... ............................................................................8-13
CHAPTER 9
PULSE-WIDTH MODULATOR
9.1 PWM FUNCTIONAL OVERVIEW.................................................................................. 9-1
9.2 PWM SIGNALS AND REGISTERS............................................................................... 9-2
9.3 PWM OPERATION . ....................................................................................................... 9-3
9.4 PROGRAMMING THE FREQUENCY AND PERIOD.................................................... 9-5
9.5 PROGRAMMING THE DUTY CYCLE........................................................................... 9-7
9.5.1 Sample Calculations .................................................................................................9-9
9.5.2 Enabling the PWM Outputs ......... ........................................................ ...................... 9-9
9.5.3 Generating Analog Outputs ......................................................................................9-9
CHAPTER 10
EVENT PROCESSOR ARRAY (EPA)
10.1 EPA FUNCTIONAL OVERVIEW ................................................................................. 10-1
vii
8XC196NP, 80C196NU USER ’S MANUAL
10.2 EPA AND TIMER/COUNTER SIGNALS AND REGI STERS ....................................... 10-2
10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 10-5
10.3.1 Cascade Mode (Timer 2 Only) .......................... ..... ..... ..... .......................................10-6
10.3.2 Quadrature Clocking Mode .....................................................................................10-6
10.4 EPA CHANNEL FUNCTIONAL OVERVIEW............................................................... 10-8
10.4.1 Operating in Capture Mode .....................................................................................10-9
10.4.1.1 EPA Overruns ..................................................................................................10-11
10.4.1.2 Preventing EPA Overruns ................................................................................10-12
10.4.2 Operating in Compare Mode .................................................................................10-12
10.4.2.1 Generating a Low-speed PWM Output ............................................................10-12
10.4.2.2 Generating a Medium-speed PWM Output .............................. ....... ..... ..... ......10-13
10.4.2.3 Generating a High-speed PWM Output ...........................................................10-14
10.4.2.4 Generating the Highest-speed PWM Output ....................................................10-15
10.5 PROGRAMMING THE EPA AND TIMER/COUNTERS............................................. 10-15
10.5.1 Configuring the EPA and Timer/Counter Port Pins ...............................................10-15
10.5.2 Programming the Timers .......................................................................................10-15
10.5.3 Programming the Capture/Compare Channels .....................................................10-18
10.6 ENABLING THE EPA INTERRUPTS........................................................................ 10-22
10.7 DETERMINING EVENT STATUS.............................................................................. 10-22
10.7.1 Using Software to Service the Multiplexed Overrun Interrupts .............................10-23
10.8 PROGRAMMING EXAMPLES FOR EPA CHANNELS............................................. 10-24
10.8.1 EPA Compare Event Program ..............................................................................10-24
10.8.2 EPA Capture Event Program ................................................................................10-25
10.8.3 EPA PWM Output Program ..................................................................................10-26
CHAPTER 11
MINIMUM HARDWARE CONSIDERATIONS
11.1 MINIMUM CONNECTIONS ......................................................................................... 11-1
11.1.1 Unused Inputs .........................................................................................................11-2
11.1.2 I/O Port Pin Connections ........................................................................................11-2
11.2 APPLYING AND REMOVING POWER ....................................................................... 11-4
11.3 NOISE PROTECTION TIPS. ....................................................................................... 11-4
11.4 THE ON-CHIP OSCILLATOR CIRCUITRY ............................................................... .. 11-5
11.5 USING AN EXTERNAL CLOCK SOURCE.................................................................. 11-7
11.6 RESETTING THE DEVICE.......................................................................................... 11-8
11.6.1 Generating an External Reset .................................................................................11-9
11.6.2 Issuing the Reset (RST) Instruction ......................................................................11-11
11.6.3 Issuing an Illegal IDLPD Key Operand .................................................................11-11
CHAPTER 12
SPECIAL OPERATING MODES
12.1 SPECIAL OPERATING MODE SIGNA LS AND REGI STERS..................................... 12-1
12.2 REDUCING POWER CONSUMPTION....................................................................... 1 2-3
viii
CONTENTS
12.3 IDLE MODE................................................................................................................. 12-5
12.4 STANDBY MODE (80C196NU ONLY)........................................................................ 12-6
12.4.1 Enabling and Disabling Standby Mode . ..................................................................12-6
12.4.2 Entering Standby Mode ..........................................................................................12-6
12.4.3 Exiting Stan dby Mode .................... ....... ....... .......... .......... ....... .......... ....... ........ .......12-7
12.5 POWERDOWN MODE................................................................................................ 12-7
12.5.1 Enabling and Disabling Powerdown Mode ..............................................................12-7
12.5.2 Entering Powerdown Mode .....................................................................................12-7
12.5.3 Exiting Powerdown Mode .......................................................................................12-8
12.5.3.1 Generating a Hardware Reset .... .......................................................................12-8
12.5.3.2 Asserting an External Interrupt Signal ................................................................12-8
12.5.3.3 Selecting C
.....................................................................................................12-10
1
12.6 ONCE MODE............................................................................................................. 12-12
12.7 RESERVED TEST MODES (80C196NU ONLY)....................................................... 12-12
CHAPTER 13
INTERFACING WITH EXTERNAL MEMORY
13.1 INTERNAL AND EXTERNAL ADDRESSES............................................................... 13-1
13.2 EXTERNAL MEMORY INTERFACE SIGNALS........................................................... 13-2
13.3 THE CHIP-SELECT UNIT............................................................................................ 1 3-5
13.3.1 Defining Chip-select Address Ranges ....................................................................13-7
13.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing ....................................13-10
13.3.3 Chip-select Unit Initial Conditions ............................... ..........................................13-11
13.3.4 Initializing the Chip-select Registers ........................................................ ............. 13-11
13.3.5 Example of a Chip-select Setup ............................................................................13-12
13.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES ....... 13-14
13.5 BUS WIDTH AND MULTIPLEXING........................................................................... 13-18
13.5.1 A 16-bit Example System ......................................................................................13-21
13.5.2 16-bit Bus Timings ................................ ...................... ................. ...................... ... 13-22
13.5.3 8-bit Bus Timings ..................................................................................................13-24
13.5.4 Comparison of Multiplexed and Demultiplexed Buses ..........................................13-26
13.6 WAIT STATES (READY CONTROL)......................................................................... 13-26
13.7 BUS-HOLD PROTOCOL........................................................................................... 13-30
13.7.1 Enabling the Bus-hold Protocol .............................................................................13-32
13.7.2 Disabling the Bus-hold Protocol ............................................................................13-32
13.7.3 Hold Latency .........................................................................................................13-32
13.7.4 R egai ni ng Bu s Control ....... .. ..... .. ..... ..... ... .... ... .. ..... ..... ... .... ... ..... .. ..... .. ..... ... ..... .. ... 13-33
13.8 WRITE-CONTROL MODES...................................................................................... 13-33
13.9 SYSTEM BUS AC TIMING SPECIFICATIONS......................................................... 13-36
13.9.1 Deferred Bus-cycle Mode (80C196NU Only) ........................................................13-40
13.9.2 Explanation of AC Symbols ..................................................................................13-42
13.9.3 AC Timing Definitions ...........................................................................................13-42
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8XC196NP, 80C196NU USER ’S MANUAL
APPENDIX A
INSTRUCTION SET REFERENCE
APPENDIX B
SIGNAL DESCRIPTIONS
B.1 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. B-1
B.2 SIGNAL DESCRIPTIONS............................................................................................. B-6
B.3 DEFAULT CONDITIONS............................................................................................ B-13
APPENDIX C
REGISTERS
GLOSSARY
INDEX
x
CONTENTS
FIGURES
Figure Page
2-1 8XC196NP and 80C196NU Block Diagram.................................................................2-2
2-2 Block Diagram of the Core ...........................................................................................2-3
2-3 Clock Circuitry (8XC196NP)......................................................................................... 2-7
2-4 Clock Circuitry (80C196NU).........................................................................................2-8
2-5 Internal Clock Phases ..................................................................................................2-9
2-6 Effect of Clock Mode on CLKOUT Frequency............................................................2-10
3-1 Accumulator (ACC_0
3-2 Accumulator Control and Status (ACC_STAT) Register..............................................3-5
5-1 16-Mbyte Address Space.............................................................................................5-2
5-2 Pages FFH and 00H.....................................................................................................5-3
5-3 Register File Memory Map .............................. ............................................ ...............5-10
5-4 Windowing..................................................................................................................5-13
5-5 Window Selection (WSR) Register.............................................................................5-14
5-6 Window Selection 1 (W SR1) Register........................................................................5-15
5-7 The 24-bit Program Counter.......................... ....... ............... ............ ....... ............... ..... 5-23
5-8 Formation of Extended and Nonextended Addresses................................................5-24
5-9 A 64-Kbyte System With an 8-bit Bu s ........................................................................5-27
5-10 A 64-Kbyte System with Additional Data Storage ......................................................5-29
5-11 Example System Using the 1-Mbyte Mode ................................................................5-31
6-1 Flow Diagram for PTS and Standard Interrupts ...........................................................6-2
6-2 Standard Interrupt Response Time..............................................................................6-9
6-3 PTS Interrupt Response Time......................................................................................6-9
6-4 PTS Select (PTSSEL) Register...... ............................................................................6-11
6-5 Interrupt Mask (INT_MASK) Register.........................................................................6-12
6-6 Interrupt Mask 1 (INT_MASK1) Register......................................... ................. .......... 6-13
6-7 Interrupt Pending (INT_PEND) Register .. .................................................................. 6-16
6-8 Interrupt Pending 1 (INT_PEND1) Register ...............................................................6-17
6-9 PTS Control Blocks ....................................................................................................6-18
6-10 PTS Service ( PTSSRV) Register...............................................................................6-19
6-11 PTS Mode Selection Bi ts (PTSCON Bits 7:5) ............................................................6-20
6-12 PTS Control Block — Single Transfer Mode..............................................................6-21
6-13 PTS Control Block — Block Transfer Mode...............................................................6-24
6-14 A Generic PWM Waveform ................................................. .......................................6-27
6-15 PTS Control Block — PWM Toggle Mode .................................................................. 6-29
6-16 EPA and PTS Operations for the PWM Toggle Mode Example.................................6- 31
6-17 PTS Contr ol Block — PWM Remap Mode.................................................................6-34
6-18 EPA and PTS Operations for the PWM Remap Mode Example................................6-36
7-1 Bidirectional Port Structure...........................................................................................7-5
7-2 EPORT Block Diagram...............................................................................................7-13
7-3 EPORT Structure .......................................................................................................7-15
8-1 SIO Block Diagram .......................................................................................................8-1
8-2 Typical Shift Register Circuit for Mode 0.. ................. ...................... ...................... ....... 8-4
8-3 Mode 0 Timing.............................. .. .......... ....... ..... ..... .......... .. ..... .......... .. .......... ..... .. .....8-5
8-4 Serial Port Frames for Mode 1 .....................................................................................8-6
x
) Register ........................................... .......................................3-4
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8XC196NP, 80C196NU USER ’S MANUAL
FIGURES
Figure Page
8-5 Serial Port Frames in Mode 2 and 3.............................................................................8-7
8-6 Serial Port Control (SP_CON) Register........................................................................ 8-9
8-7 Serial Port Baud Rate (SP_BAUD) Register..............................................................8-11
8-8 Serial Port Status (SP_STATUS) Register ............................ ..................................... 8-14
9-1 PWM Block Diagram (8XC196NP Only).......................................................................9-1
9-2 PWM Block Diagram (80C196NU Only).......................................................................9-2
9-3 PWM Output Waveforms .. ..................................................... ....................................... 9-5
9-4 Control (CON_REG0) Register ....................................................................................9-7
9-5 PWM Control (PW M
9-6 D/A Buffer Block Diagram...........................................................................................9-10
9-7 PWM to Analog Conversion Circuitry.........................................................................9-10
10-1 EPA Block Diagram....................................................................................................10-2
10-2 EPA Timer/Counters ..................................................................................................10-5
10-3 Quadrature Mode Interface................................................................................... .....1 0-7
10-4 Quadrature Mode Timing and Count..........................................................................10-8
10-5 A Single EPA Capture/Compare Channel..................................................................10-9
10-6 EPA Simplifie d Input-capture Structure....................................................................10-10
10-7 Valid EPA Input Events............................................................................................10-10
10-8 Timer 1 Control (T1CONTROL) Register .................................................................10-16
10-9 Timer 2 Control (T2CONTROL) Register .................................................................10-17
10-10 EPA Control (EPA
10-11 EPA Interrupt Mask (EPA_MASK) Register.............................................................10-22
10-12 EPA Interrupt Pending (EPA_PEND) Register.........................................................10-23
11-1 Minimum Hardware Connections...............................................................................11-3
11-2 Power and Return Connections .................................................................................11-4
11-3 On-chip Oscillator Circuit................................................ ..... .......................................11-5
11-4 External Crystal Connections.....................................................................................11-6
11-5 External Clock Connections .......................................................................................11-7
11-6 External Clock Drive Waveforms................................................................................11-7
11-7 Reset Timing Sequence.............................................................................................11-8
11-8 Internal Reset Circuitry................... .......... ....... ..... .......... ..... ....... ..... ....... ..... .......... .. ...11-9
11-9 Minim um Reset Circuit .............................................................................................11-10
11-10 Example System Reset Circuit.................................................................................11-10
12-1 Clock Control During Power-saving Modes (8XC196NP) ..........................................1 2-4
12-2 Clock Control During Power-saving Modes (80C196NU)...........................................12-5
12-3 Power-up and Powerdown Sequence When Using an External Interrupt..................12-9
12-4 External RC Circuit........................................ .............................................................12-9
12-5 Typical Voltage on the RPD Pin While Exiting Powerdown.....................................12-11
13-1 Calculation of a Chip-select Output............................................................................13-6
13-2 Ad dress Compare (ADDRCOM
13-3 Address Mask (ADDRMSK
13-4 Bus Control (BUSCON
13-5 Example System for Setting Up Chip-s elect Outputs...............................................13-13
13-6 Chip Configuration 0 (CCR0) Register .....................................................................13-15
x
_CONTROL) Register................................................................9-8
x
_CON) Registers .......................................................................10-19
x
) Register ................................................................13-7
x
) Regi st er ........ .. ....... ........ .. ....... ... ....... ....... ... ....... ... .......13-8
x
) Register............................................................................13-10
xii
CONTENTS
FIGURES
Figure Page
13-7 Chip Configuration 1 (CCR1) Register .....................................................................13-16
13-8 Multiplexing and Bus Width Options.........................................................................13-19
13-9 Bus Activit y for F our Types of Buses........................................................................13-20
13-10 1 6-bit External Devices in Demultiplexed Mode... ....................................................13-22
13-11 Timings for Multiplexed and Demultiplexed 16-bit Buses (8XC196NP) ...................13-23
13-12 Timings for Multiplexed and Demultiplexed 8-bit Buses (8XC196NP) .....................13-25
13-13 READY Tim ing Diagram — Multiplexed Mode.........................................................13-28
13-14 READY Timing Diagram — Demultiplexed Mode (8XC196NP). ..............................13-29
13-15 READY Timing Diagram — Demultiplexed Mode (80C196NU). ..............................13-30
13-16 HOLD#, HLDA# Timing ............................................................................................13-31
13-17 Write-control Signal Waveforms...............................................................................13-34
13-18 Decoding WRL# and WRH#.....................................................................................13-35
13-19 A System with 8-bit and 16-bit Buses.......................................................................13-36
13-20 Multiplexed System Bus Timing (8XC196NP).......................................................... 13-37
13-21 Multiplexed System Bus Timing (80C196NU)..........................................................13-38
13-22 Demulti ple xed System Bus Timing (8XC196NP).....................................................13-39
13-23 Demulti plexed System Bus Timing (80C196NU).................................... ..................13-40
13-24 Deferr e d Bus-cycle Mode Timing Diagram (80C196NU) .........................................13-41
B-1 8XC196NP 100-lead SQFP Package..........................................................................B-2
B-2 8XC196NP 100-lead QFP Package............................................................................ B-3
B-3 80C196NU 100-lead SQFP Package..........................................................................B-4
B-4 80C196NU 100-lead QFP Package............................................................................B-5
xiii
8XC196NP, 80C196NU USER ’S MANUAL
TABLES
Table Page
1-1 Handbooks and Product Information . .. ..... ..... ....... ..... ..... ....... ..... ..... ....... ..... ..... ..... .......1-6
1-2 Application Notes, Application Briefs, and Article Reprints ..........................................1-6
1-3 MCS
1-4 MCS
1-5 MCS
2-1 Features of the 8XC196NP and 80C196NU.................................................................2-2
2-2 State Times at Various Frequencies ............................................................................2-9
2-3 Relationships Between Input Frequency, Clock Multiplier, and State Times.............2-10
3-1 Multiply/Accumulate Example Code.............................................................................3-2
3-2 Effect of SME and FME Bit Combinations....................................................................3-6
4-1 Operand Type Definitions.............................................................................................4-1
4-2 Equivalent Operand Types for Assembly and C Programming Languages.................4-2
4-3 Definition of Temporary Registers................................................................................4-7
5-1 8XC196NP and 80C196NU Memory Map....................................................................5-4
5-2 Program Memory Access for the 83C196NP ............................................................... 5-5
5-3 8XC196NP and 80C196NU Special-purpose Memory Addresses...............................5-6
5-4 Special-purpose Memory Access for the 83C196NP...................................................5-6
5-5 Peripheral SFRs...........................................................................................................5-8
5-6 Register File Memory Addresses ...............................................................................5-11
5-7 CPU SFRs..................................................................................................................5-12
5-8 Selecting a Window of Peripheral SFRs..................................................................... 5-15
5-9 Selecting a Window of the Upper Register File.. ........................................................5-15
5-10 Windows.....................................................................................................................5-17
5-11 Windowed Base Addresses .......................................................................................5-18
5-12 Memory Map for the System in Figure 5-9.. ............................................................ ...5 -28
5-13 Memory Map for the System in Figure 5-10...............................................................5-30
5-14 Memory Map for the System in Figure 5-11...............................................................5-32
6-1 Interrupt Signals .............................................. ............................................................. 6-3
6-2 Interrupt and PTS Control and Status Registers.......................................................... 6-3
6-3 Interrupt Sources, Ve ctors, and Priorities.................. ............ .......... ............ ............ ..... 6-5
6-4 Execution Times for PTS Cycles............................................................ ....................6-10
6-5 Single Transfer Mode PTSCB....................................................................................6-23
6-6 Block Transfer Mode PTSCB.....................................................................................6-23
6-7 Comparison of PWM Modes.......................................................................................6-26
6-8 PWM Toggle Mode PTSCB........................................................................................6-28
6-9 PWM Remap Mode PTSCB.......................................................................................6-33
7-1 Device I/O Ports ...................... ....... ..... ........ .... ........ ....... ..... ....... ..... ....... ..... ........ .... ..... 7- 1
7-2 Bidirectional Port Pins .................. ........................................................................... .....7-2
7-3 Bidirectional Port Control and Status Registers ... ........................................................7-3
7-4 Logic Table for Bidire ctional Ports in I/O Mode............................................................7-6
7-5 Logic Table for Bidire ctional Ports in Special-function Mode .......................................7-6
7-6 Control Register Valu es for Each Configuration. ..........................................................7-8
7-7 Port Configuration Example ......................................................................................... 7-8
7-8 Port Pin States After Reset and After Example Code Execution..................................7-9
®
96 Microcontroller Datasheets (Commercial/Express)......................................1-7
®
96 Microcontroller Datasheets (Automotive).....................................................1-7
®
96 Microcontroller Quick References. ...............................................................1-8
xiv
CONTENTS
TABLES
Table Page
7-9 EPORT Pins...............................................................................................................7-11
7-10 EPORT Contr ol and Status Registers........................................................................7-12
7-11 L ogic Table for EPORT in I/O Mode...........................................................................7-16
7-12 L ogic Table for EPORT in Address Mode ..... ...................... ................... ................. ...7 -16
7-13 Co nfiguratio n Register Settings for EPORT Pins.......................................................7-17
8-1 Serial Port Signals........................................................................................................ 8-2
8-2 Serial Port Control and Status Registers......................................................................8-2
8-3 SP_BAUD Values When Using the Internal Clock at 25 MHz....................................8-12
8-4 SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only) ......8-13
9-1 PWM Signals................................................................................................................9-2
9-2 PWM Control and Status Registers ........................................................ ...................... 9-3
9-3 PWM Output Frequencies (8XC196NP)....................................................................... 9-6
9-4 PWM Output Frequencies (80C196NU) .......................................................................9-6
9-5 PWM Output Alternate Functions........................................................... ...................... 9-9
10-1 EPA and Timer/Counter Signals.................................................................................10-2
10-2 EPA Control and Status Registers .............................................................................10-3
10-3 Quadrature Mode Truth Table....................................................................................10-7
10-4 Action Taken when a Valid Edge Occurs.................................................................10-11
10-5 E xample Co ntrol Register Settings and EPA Operations.........................................10-18
11-1 Minim um Required Signals.........................................................................................1 1-1
11-2 I/O Port Configuration Guide ......................................................................................11-2
12-1 Operating Mode Control Signals ................................................................................1 2-1
12-2 Operati ng Mode Control and Status Registers...........................................................12-2
12-3 80C196NU Clock Modes..........................................................................................12-13
13-1 E xample of Internal and External Addresses.............................................................13-1
13-2 External Memory Interface Signals.............................................................................13-2
13-3 Chip-select Registers............................................................................................ .. ...13-6
13-4 ADDRCOM
13-5 ADDRMSK
13-6 Base Addresses for Several Sizes of the Address Range.........................................13-9
13-7 BUSCON
13-8 BUSCON
13-9 Results for the Chip-select Example........................................................................13-14
13-10 Comparison of AC Timi ngs for Demultiplexed and Multiplexed 16-bit Buses ..........13-26
13-11 READY Signal Timing Definitions........................................................... ................. .13-27
13-12 HOLD#, HLDA# Timing Definitions ..........................................................................13-31
13-13 Maximum Hold Latency............................................................................................13-33
13-14 Write Signals for Standard and Write Strobe Modes ...... ............ ............ .......... ........ 13-34
13-15 AC Timing Symbol Definitions..................................................................................13-42
13-16 AC Timing Definitions...............................................................................................13-42
A-1 Opcode Map (Left Half)......................................................... ...................... ................ A-2
A-1 Opcode Map (Right Half).. ...................................................................... ..................... A-3
A-2 Processor Status Word (PSW) Flags.......................................................................... A-4
A-3 Effect of PSW Flags or Specified Conditions o n Conditional Jump Instructions.........A-5
x
Addresses and Reset Values................................................................13-7
x
Addresses and Reset Values................................................................13-8
x
Addresses and Reset Values.................................................................13-11
x
Registers for the Example System.........................................................13-13
xv
8XC196NP, 80C196NU USER ’S MANUAL
TABLES
Table Page
A-4 PSW Flag Setting Symbols .........................................................................................A-5
A-5 Operand Variables ...................................................................................................... A-6
A-6 Instructi on Set ........ ....... ..... ..... ....... ..... ..... ....... ..... ..... .......... .. ..... .......... .. ..... .......... .. .... A-7
A-7 Instructi on Opcodes ..................................................................................................A-47
A-8 Instruction Lengths and Hexadecimal Opcodes........................................................A-53
A-9 Instruction Executio n Times (in State Times)............................................................ A-60
B-1 8XC196NP and 80C196NU Signals Arranged by Function......................................... B-1
B-2 Description of Columns of Table B-3... ........................................................................B-6
B-3 Signal Descriptions...................................................................................................... B-6
B-4 Definition of Status Symbols .....................................................................................B-13
B-5 8XC196NP and 80C196NU Pin Status..................................................................... B-13
C-1 Module s and Related Registers.................................................................................. C- 1
C-2 Register Name, Address, and Reset Status............................................................ ....C-2
C-3 ACC_0
C-4 Effect of SME and FME Bit Combinations...................................................................C-7
C-5 ADDRCOM
C-6 ADDRMSK
C-7 BUSCON
C-8 EPA
C-9 EPA
C-10 P
C-11 P
C-12 Special-function Signals for Ports 1–4...... ..... ..... ..... ..... ..... .... ..... ..... ..... ....... ..... ..... .. ..C-31
C-13 P
C-14 P
C-15 PWM
C-16 SP_BAUD Values When Using the Internal Clock at 25 MHz...................................C-43
C-17 TIMER
C-18 WSR Settings and Direct Addresses for Windowable SFRs.....................................C-49
C-19 WSR1 Settings and Direct Addresses for Windowable SFRs................................... C-52
x
Addresses and Reset Values........................................................................C-5
x
Addresses and Reset Values.................................................................C-8
x
Addresses and Reset Values.................................................................C-9
x
Addresses and Reset Values..................................................................C-10
x
_CON Addresses and Reset Values................................................................C-23
x
_TIME Addresses and Reset Values................................................................C-24
x
_DIR Addresses and Reset Values.......................................................................C-30
x
_MODE Addresses and Reset Values..................................................................C-31
x
_PIN Addresses and Reset Values.......................................................................C-32
x
_REG Addresses and Reset Values.....................................................................C-33
x
_CONTROL Addresses and Reset Values.....................................................C-38
x
Addresses and Reset Values......................................................................C-48
xvi
Guide to This Manual
1
CHAPT ER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC196NP and 80C196NU embedded microcontrollers. It is intended
for use by both software and hardware designers familiar with the principles of microcontrollers.
This chapter describes w hat you’ll find in this man ual, lists other documents tha t ma y be useful,
and explains how to access the support services we provide to help you complete your design.
1.1 MANUAL CONTENTS
This manual contai ns several chapters and appen dixes, a glossary, and an index. This chapter,
Chapter 1, provides an ov e rview of the manua l. Thi s section su m mariz es the conte nts of the remaining chapters and appendixes. The remainder of this chapter describes notational conventions
and terminology used throughout the manual, provides references to related documentation, describes custome r support services, and explains how to access information and assi stance .
Chapter 2 — Architectural Overvi ew — provides an over view of the device hardware. It describes the core, internal timing, int ernal periphera ls, and special operati ng modes.
Chapter 3 — Advanced Math Features — describes the advanced mathematical features of the
80C196NU. The 80C19 6NU is the first m ember of the MCS
corporate enhanced 16-bit multiplication instructions for performing multiply-accumulate operations and a dedicated, 32-bit accumulator register for storing the results of these operations. The
accumulator and the enhanc ed ins tructions combi ne to decre ase the amount o f time required to
perform multiply-accumulate operati ons. The instructions a nd accumulat or support signed and
unsigned integers as wel l as signed fractional data.
Chapter 4 — Programming Considerations — provides an overview of the instruction set, describes general standards a nd conventions, and defines the operand types and addressing modes
supported by the MCS
tion set, see Appendix A.)
Chapter 5 — Me m ory Par titions — describe s the ad d ressable me mory spa ce of the device . It
describes the memory partitions, explains how to use windows to increase the amount of memory
that can be accessed with direct addressing, and provides exam ples of memo ry configurations.
Chapter 6 — Standard and PTS Interrupts — describes the interrupt control circuitry, priority
scheme, and timing for standard and perip heral transaction server (PTS) inte rrupts. It also explains interrupt programming and control.
Chapter 7 — I/O Ports — describes the input/out put ports and explains how to configure the
ports for input, output, or special functions.
®
96 microcontroller family . (For additional information about the instruc-
®
96 microcontroller fam ily to in-
1-1
8XC196NP, 80C196NU USER’S MANUAL
Chapter 8 — Serial I/O (SIO) Port — describes the asynchronous/synchronous serial I/O (SIO)
port and expla ins how to program it.
Chapter 9 —Pulse-width Modulator — provides a functional overview of the pulse width modulator (PWM) modules, descri bes how to program them, and provides sample circuitry for con verting the PWM outputs to analog signals.
Chapter 10 — Eve nt Processor Array (E PA) — de scribes the event processor array, a timer/counter-based, high-speed input/output u nit. It de scri bes t he time r/c ounters and explains h o w
to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs.
Chapter 11 — Minimum Hardware Considerations — describes options for providing the basic requirements for devi ce operat ion w ithin a system , discuss es other hardware considerations,
and describes device reset o ptions.
Chapter 12 — Spec ial Operating Modes — provides an overview of the idle, powerdown,
standby, and on-circuit emulation (ONCE) modes and describes how to enter and exit each mode.
Chapter 13 — Interfacing with External Memory — lists the external memory signals and describes the registers that control the external memory interface. It discusses the chip selects, multiplexed and demultiplexed bus modes, bus width and memory configurations, the bus-hold
protocol, write-control modes, and internal wait states and ready control. Finally, it provides timing informat ion for the system bus.
Appendix A — Instruction Set Reference — provides reference information for the instruction
set. It describes each instruction; defines the processor sta tus word (PSW) flags; shows the relationships between instructions and PSW flags; and lists hexadecimal opcodes, instruction
lengths, and execution times. (For additional information about the instruction set, see Chapter 4,
“Programming Consideratio ns.”)
Appendix B — Signal Descr iptions — provides referenc e information for the device pins, including descriptions of the pin functions, reset status of the I/O and control pins, and package pin
assignments.
Appendix C — Re gisters — provides a compilation of all device special-function registers
(SFRs) arranged alphabeti cally by register mnemonic . It also includes tables that list the windowed direct addresses for all SFRs in each possible window.
Glossary — define s terms with spec ial me aning used th roughout this manual.
Index — lists key topics with page number references.
1-2
GUIDE TO THIS MANUAL
1.2 N O TATIO NAL CONV ENTI ONS AND TERMINOLOGY
The following notations an d terminol ogy are used throughout this manual. The Glossary defines
other terms with special meanings.
# The pound symbol (#) has either of two meanings, depending on the
context. When used wi th a signal name, the symbol means that the
signal is active low. When used in an instruction, the symbol prefixes
an immediate value in immediate addressing mode.
addresses In this manual, both internal and external addresses use the number
of hexadecimal digits that correspond with the number of available
address lines. For example, the highe st possible internal address i s
shown as FFFFFFH, while the highest possible external address is
shown as FFFFFH. When w riting code, use the appropriate address
conventions for the software tool you are using. (In general,
assemblers require a zero preceding an alphabetic hexadecimal
character and an “H” following any hexadecimal value, so FFFFFFH
must be written as 0FF FFFFH. ANSI ‘C’ compilers require a z ero
plus an “x” precedin g a hexadecimal value, so FFFFFFH must be
written as 0xFFFFFF.) Consult the manual for your assembler or
compiler to determine its specific requirement s.
assert and deassert The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active
polarity (low or high) is defined by the signal name. Active-low
signals are designated by a pound symbol (#) suffix; active-high
signals have no suffix. To assert RD# is to drive it low; to assert ALE
is to drive it high; to deassert RD# is to drive it high; to deassert ALE
is to drive it low.
clear and set The terms clear and set refer to the val ue of a bit or the act of giving
it a value. If a bit is c lear, it s val ue is “0”; cleari ng a bit gi ves it a “0”
value. If a bit is set, its value is “1”; settin g a bit gives it a “1” value.
f Lowercase “f” represents the internal operating frequency. See
“Internal Timing” on page 2-7 for details.
instructions Instruction mnem onics are shown in upper case to av oid confusion.
In general, you may use either upper case or lower case when
programming. Consult the manual for your assembl er or compiler to
determine its specific req uirem ent s.
1-3
8XC196NP, 80C196NU USER’S MANUAL
italics Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible
meanings.
Variables in registers and signal names are commonly repres ented by
x and y, where x represents the first variable and y represents the
second variable . For example, in register P x_MODE.y, x represent s
the variable that identifies the specific port associated with the
register, and y represents the register bit variable (7:0 or 15:0).
Variables must be replace d with the correct values when configuring
or programming regi sters or ident ifyi ng signals.
numbers Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are
represented by t heir customa ry notations. (That is, 255 is a decimal
number and 1111 1111 is a binary number. In some cases, the letter B
is appended to binary numbers for clarity.)
register bits Bit locatio ns are indexed by 7:0 (or 15:0), where bit 0 is the least-
significant bit and bit 7 (or 15) is the most-significant bit. An
individual bit is represented by the register name, followed by a
period and the bit number. For example, WSR.7 is bit 7 of the
window selection register. In some discuss ions, bit names are used.
register names Register mnemonics are shown in upper case. For example, TIMER2
is the timer 2 register; timer 2 is the timer . A register name containing
a lowercase italic character represents more than one register. For
example, the x in Px_REG indicate s that the register name re fers to
any of the p ort data registers.
reserved bits Certain bits are described a s reserved bits. In illustrat ions, reserved
bits are indicated with a dash (—). These bits are not used in this
device, but they may be used in future implementations. To help
ensure that a current software design is compatible with future implementations, rese rved bits should be c leared (given a value of “0”) or
left in thei r de fault states, unl es s ot herwis e not ed. D o not rel y o n the
values of reserved bits; conside r them undefin ed.
signal names Signal names are shown in upper case. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number. For example, the EPA signals are named
EPA0, EPA1, EPA2, etc. Port pins a re repres ente d by t he p ort ab breviation, a period, a nd the pin number (e.g., P1.0, P 1.1); a range of
pins is represented by Px.y:z (e.g., P1.4:0 represents five port pins:
P1.4, P1.3, P1.2, P1.1, P1.0). A pound symbol (#) appended to a
signal name identifies an active-low signal.
1-4
GUIDE TO THIS MANUAL
t Lowercase “t” represents the internal operating period. See “Internal
Timing” on page 2-7 for details.
units of measure The following abbreviations are used to represent units of measure:
A amps, ampere s
DCV direct curre nt volts
Kbytes kilobytes
kHz kilohertz
kΩ kilo-ohms
mA milliamps, milliamperes
Mbytes megabytes
MHz megahertz
ms milliseconds
mW milliwatts
ns nanoseconds
pF picofarads
W watts
V volts
µA microamps, microam peres
µF microfarads
µs microseconds
µW microwatts
X Uppercase X (no italics) represents an unknown value or an
irrelevant (“don ’t care”) state o r condition. The val ue may be eit her
binary or hexadecimal, depending on the context. For example,
2XAFH (hex) indicates that bits 11:8 are unknown; 10XXB (binary)
indicates that the two least-significant bits are unknown.
1.3 RELATED DOCUMENTS
The tables in this section list additional documents that you may find useful in designing systems
incorporating MCS 96 microcontrollers. These are not comprehensive lists, but are a representative sample of relevant documents. For a complete list of available printed documents, please order the literature catalog (order number 210621). To order documents, please call the Intel
literature center for your area (telephone numbers are listed on page 1-11).
Intel’s ApBUILDER software, hypertext manuals and datasheets , and electronic versions of application notes and code examples are also available from the BBS (see “Bulletin Board System
(BBS)” on page 1- 9). New inform ation is available first from FaxBa ck and the BB S. Refer to
“Electronic Support Systems” on page 1-8 for details.
1-5
8XC196NP, 80C196NU USER’S MANUAL
Table 1-1. Handbooks and Product Information
Title and Description Order Number
Intel Embedded Quick Reference Guide
Solution s for Embedd ed Appl icat io ns Guide
Data on Demand
Data on Demand
Complete set of Intel handbooks on CD-ROM.
Handboo k Set
Complete set of Intel’s product line handbooks. Contains datasheets, application
notes, article reprints and other desig n informatio n on microprocessors, peripherals, embedded controllers, memory components, single-board computers,
microcommunications, software development tools, and operating systems.
Automotive Products
Application notes and article reprints on topics including the MCS 51 and MCS 96
microcon trol le r s. Docu men t s in this handb ook discuss hardware and software
implementations and present helpful design techniques.
Embedded Applications
Datasheets, architecture descriptions, and application notes on topics including
flash memor y device s, netwo rkin g chips, an d MCS 51 and MCS 96 microc ontrollers. Documents in this handbook discuss hardware and software implementations and present helpful design techniques.
Embedded Microcontrollers
Datasheets and architecture descriptions for Intel’s three industry-standard microcontrollers, the MCS 48, MCS 51, and MCS 96 microcontrollers.
Peripheral Components
Comprehensive information on Intel’s peripheral components, including
datasheets, application notes, and technical briefs.
Flas h Memory
A collection of datasheets and application notes devoted to techniques and
information to help design semiconductor memory into an application or system.
Packaging
Detailed information on the manufacturing, applications, and attributes of a variety
of semiconductor packages.
Development Tools Handbook
Information on third-party hardware and software tools that support Intel’s
embedded microcontrollers.
†
Included in handbook set (order num be r 231003)
fact sheet 240952
annual subscription (6 issues; Windows* version)
— ha ndbooks and product overview
†
†
(2 volume set)
†
handbook (2 volume set)
†
†
†
272439
240691
240897
231003
231792
270648
270646
296467
210830
240800
272326
AB-71,
AP-125,
AP-155,
AR-375,
AP-406,
†
Included in
††
Included in
†††
Included in
1-6
Table 1-2. Application Notes, Application Briefs, and Article Reprints
Title Order Number
Using the SIO on the 8XC196MH
Design Microcontroller Systems for Electrically Noisy Environments
Oscillators for Microcontrollers
Motor Controllers Take the Single-Chip Route
MCS® 96 Analog Acquisition Primer
Automotive Products
Embedded Applications
Automotive Products
(application brief) 272594
†††
†††
(article reprin t) 270056
†††
handbook (order number 231792)
handbook (order number 270648)
and
Embedded Applications
handbooks
210313
230659
270365
GUIDE TO THIS MANUAL
Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued)
Title Order Number
AP-445,
AP-449,
8XC196KR Peripherals: A User’s Point of View
A Comparison of the Event Processor Array (EPA) and High Speed
Input/Output (HSIO) Unit
AP-475,
Using the 8XC196NT
AP-477,
AP-483,
AP-700,
AP-711,
AP-715,
†
††
†††
Low Voltage Embedded Design
Application Examples Using the 8XC196MC/MD Microcontroller
Intel Fuzzy Logic Tool Simplifies ABS Design
EMI Design Techniques for Microcon tro llers in Auto mo ti ve Appl icat io ns
Interfacing an I2C Serial EEPROM to an MCS® 96 Microcontroller
Included in
Included in
Included in
Automotive Products
Embedded Applications
Automotive Products
†
††
††
handbook (order number 231792)
handbook (order number 270648)
and
Embedded Applications
†
†
handbooks
Table 1-3. MCS® 96 Microcontroller Datasheets (Commercial/Express)
Title Order Number
8XC196KR/K Q/JR/ JQ Commercia l/E xpress CHMOS Micro co ntrolle r
8XC196KT Com mercia l CHMOS Microcontro ller
†
87C196KT /87C1 96 KS 20 MHz Advan ced 16-Bit CHMOS Micro co ntrol ler
8XC196MC Industrial Motor Control Microcontroller
†
87C196M D Industrial Motor Control CHMOS Microcontro ll er
8XC196NP Commercial CHMOS 16-Bit Microcontroller
†
8XC196NT CHMOS Microcontroller with 1-Mbyte Linear Address Space
80C196NU Commercial CHMOS 16-Bit Microcontroller
†
Included in
Embedded Microcontro llers
handbook (order number 270646)
†
†
†
†
270873
270968
272315
272324
272282
272595
272324
272680
270912
272266
272513
272323
270946
272459
272267
272644
Table 1-4. MCS® 96 Microcont rol ler Datasheets (Automotive)
Title and Description Order Number
87C196CA/87C196CB 20 MH z Advanced 16-Bi t CHMO S Micro con troller with
Integrated CAN 2.0
87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller
87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller
87C196KR/KQ, 87C196JV/JT, 87C196JR/JQ Advanced 16-Bit CHMOS
Microcontroller
87C196KT/87C196KS Advanced 16-Bit CHMOS Microcontroller
87C196KT/KS 20 MHz Advanced 16-Bit CHMOS Microcontroller
†
Included in
Automotive Products
†
†
†
†
†
†
handbook (order number 231792)
272405
272529
272580
270827
270999
272513
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8XC196NP, 80C196NU USER’S MANUAL
Table 1-5. MCS® 96 Microcontroller Quick References
Title and Description Order Number
8XC196KR Quick Reference
8XC196KT Quick Reference
8XC196MC Quick Reference
8XC196NP Quick Reference
8XC196NT Quick Reference
(includes the JQ, JR, KQ, KR) 272113
272269
272114
272466
272270
1-8
GUIDE TO THIS MANUAL
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8XC196NP, 80C196NU USER’S MANUAL
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1-10
GUIDE TO THIS MANUAL
1.4.4 World Wide Web
We offer a variety of information through the W or ld Wide W eb (URL:http://www.intel.com/). Select “Embedded Design Products” from the Intel home page.
1.5 TECHNICAL SUPPO RT
In the U.S. and Canada, technical support representatives are availabl e to answer your questions
between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice
telephone number and indicate whether you prefer a response b y phone or by fax). Outside the
U.S. and Canada, please contac t your local distribut or.
1-800-628-8686 U.S. and Canada
916-356-7599 U.S. and Canada
916-356-6100 (fax) U.S. and Canada
1.6 PRODUCT LITER AT URE
You can order product literature from the following Intel literature centers.
1-800-468-8118, ext. 283 U.S. and Canada
708-296-9333 U.S. (from overseas)
44(0)1793-431155 Europe (U.K.)
44(0)1793-421333 Germany
44(0)1793-421777 France
81(0)120-47-88-32 Japan (fax only)
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