Intel 87C196CA, 8XC196Kx, 8XC196Jx, 8XC196Lx User Manual

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8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual

August 2004

Order Number: 272973-003

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The 8XC196Lx, 8XC196Kx, 8XC196Jx and 87C196CA microprocessors may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.

Copyright © Intel Corporation, 2004

*Third-party brands and names are the property of their respective owners.

 

CONTENTS

CHAPTER 1

 

GUIDE TO THIS MANUAL

 

1.1

MANUAL CONTENTS ...................................................................................................

1-1

1.2

RELATED DOCUMENTS ..............................................................................................

1-2

CHAPTER 2

 

ARCHITECTURAL OVERVIEW

 

2.1

MICROCONTROLLER FEATURES ..............................................................................

2-1

2.2

BLOCK DIAGRAM.........................................................................................................

2-2

2.3

INTERNAL TIMING........................................................................................................

2-2

2.4

EXTERNAL TIMING ......................................................................................................

2-5

2.5

INTERNAL PERIPHERALS ...........................................................................................

2-6

2.5.1

I/O Ports ....................................................................................................................

2-7

2.5.2 Synchronous Serial I/O Port .....................................................................................

2-7

2.5.3

Event Processor Array ..............................................................................................

2-7

2.5.4

J1850 Communications Controller ............................................................................

2-7

2.6

DESIGN CONSIDERATIONS........................................................................................

2-7

CHAPTER 3

 

ADDRESS SPACE

 

3.1

ADDRESS PARTITIONS ...............................................................................................

3-1

3.2

REGISTER FILE............................................................................................................

3-2

3.3

PERIPHERAL SPECIAL-FUNCTION REGISTERS ......................................................

3-4

3.4

WINDOWING.................................................................................................................

3-6

CHAPTER 4

 

STANDARD AND PTS INTERRUPTS

 

4.1

INTERRUPT SOURCES, VECTORS, AND PRIORITIES .............................................

4-1

4.2

INTERRUPT REGISTERS.............................................................................................

4-2

4.2.1

Interrupt Mask Registers ...........................................................................................

4-3

4.2.2

Interrupt Pending Registers ......................................................................................

4-4

4.2.3 Peripheral Transaction Server Registers ..................................................................

4-6

CHAPTER 5

 

I/O PORTS

 

5.1

I/O PORTS OVERVIEW ................................................................................................

5-1

5.2

INTERNAL STRUCTURE FOR PORTS 1, 2, 5, AND 6 (BIDIRECTIONAL PORTS) ....

5-1

5.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports) ................................................

5-3

5.2.2 Special Bidirectional Port Considerations .................................................................

5-4

5.3

INTERNAL STRUCTURE FOR PORTS 3 AND 4 (ADDRESS/DATA BUS)..................

5-5

iii

8XC196LX SUPPLEMENT

 

CHAPTER 6

 

SYNCHRONOUS SERIAL I/O PORT

 

6.1 SSIO 0 CLOCK REGISTER...........................................................................................

6-1

6.2 SSIO 1 CLOCK REGISTER...........................................................................................

6-2

CHAPTER 7

 

EVENT PROCESSOR ARRAY

 

7.1

EPA FUNCTIONAL OVERVIEW ...................................................................................

7-1

7.1.1

 

EPA Mask Registers .................................................................................................

7-4

7.1.2

 

EPA Pending Registers ............................................................................................

7-5

7.1.3 EPA Interrupt Priority Vector Register .......................................................................

7-6

CHAPTER 8

 

J1850 COMMUNICATIONS CONTROLLER

 

8.1

J1850 FUNCTIONAL OVERVIEW.................................................................................

8-1

8.2 J1850 CONTROLLER SIGNALS AND REGISTERS.....................................................

8-3

8.3

J1850 CONTROLLER OPERATION .............................................................................

8-4

8.3.1

 

Control State Machine ..............................................................................................

8-4

8.3.1.1 Cyclic Redundancy Check Generator ..................................................................

8-4

8.3.1.2

Bus Contention .....................................................................................................

8-5

8.3.1.3

Bit Arbitration ........................................................................................................

8-5

8.3.1.4

Error Detection .....................................................................................................

8-5

8.3.2 Symbol Synchronization and Timing Circuitry ...........................................................

8-5

8.3.2.1

Clock Prescaler ....................................................................................................

8-6

8.3.2.2

Digital Filter ..........................................................................................................

8-6

8.3.2.3

Delay Compensation ............................................................................................

8-6

8.3.2.4 Symbol Encoding and Decoding ..........................................................................

8-6

8.3.3

 

Bit Arbitration Example .............................................................................................

8-7

8.4

MESSAGE FRAMES .....................................................................................................

8-8

8.4.1

 

Standard Messaging .................................................................................................

8-9

8.4.1.1

Header .................................................................................................................

8-9

8.4.1.2

CRC Byte .............................................................................................................

8-9

8.4.1.3

Normalization Bit ..................................................................................................

8-9

8.4.1.4 Start and End Message Frame Symbols ............................................................

8-10

8.4.2

 

In-frame Response Messaging ...............................................................................

8-12

8.4.2.1 IFR Messaging Type 1: Single Byte, Single Responder ....................................

8-12

8.4.2.2 IFR Messaging Type 2: Single Byte, Multiple Responders ................................

8-12

8.4.2.3 IFR Messaging Type 3: Multiple Bytes, Single Responder ................................

8-13

8.5 TRANSMITTING AND RECEIVING MESSAGES .......................................................

8-13

8.5.1

 

Transmitting Messages ...........................................................................................

8-13

8.5.2

 

Receiving Messages ...............................................................................................

8-15

8.5.3

 

IFR Messages .........................................................................................................

8-16

iv

 

 

CONTENTS

8.6

PROGRAMMING THE J1850 CONTROLLER ............................................................

8-16

8.6.1 Programming the J1850 Command (J_CMD) Register ..........................................

8-16

8.6.2 Programming the J1850 Configuration (J_CFG) Register ......................................

8-18

8.6.3 Programming the J1850 Delay Compensation (J_DLY) Register ...........................

8-19

8.6.4 Programming the J1850 Status (J_STAT) Register ................................................

8-21

CHAPTER 9

 

MINIMUM HARDWARE CONSIDERATIONS

 

9.1

IDENTIFYING THE RESET SOURCE...........................................................................

9-1

9.2

DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD .......................................

9-2

CHAPTER 10

 

SPECIAL OPERATING MODES

 

10.1

INTERNAL TIMING......................................................................................................

10-1

10.2

ENTERING AND EXITING ONCE MODE ...................................................................

10-2

CHAPTER 11

 

PROGRAMMING THE NONVOLATILE MEMORY

 

11.1

SIGNATURE WORD AND PROGRAMMING VOLTAGE VALUES.............................

11-1

11.2

OTPROM ADDRESS MAP ..........................................................................................

11-1

11.3

SLAVE PROGRAMMING CIRCUIT AND ADDRESS MAP .........................................

11-2

11.4

SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP.............................

11-4

APPENDIX A

 

SIGNAL DESCRIPTIONS

 

A.1

FUNCTIONAL GROUPINGS OF SIGNALS .................................................................

A-1

A.2

DEFAULT CONDITIONS ..............................................................................................

A-7

GLOSSARY

v

8XC196LX SUPPLEMENT

FIGURES

Figure

 

Page

2-1

8XC196Lx Block Diagram ............................................................................................

2-2

2-2

Clock Circuitry (87C196LA, LB Only) ...........................................................................

2-3

2-3

Internal Clock Phases (Assumes PLL is Bypassed).....................................................

2-4

2-4

Effect of Clock Mode on Internal CLKOUT Frequency.................................................

2-5

2-5

Unerasable PROM 1 (USFR1) Register (LA, LB Only) ................................................

2-6

3-1

Register File Address Map ...........................................................................................

3-3

4-1

Interrupt Mask (INT_MASK) Register...........................................................................

4-3

4-2

Interrupt Mask 1 (INT_MASK1) Register......................................................................

4-4

4-3

Interrupt Pending (INT_PEND) Register ......................................................................

4-5

4-4

Interrupt Pending 1 (INT_PEND1) Register .................................................................

4-6

4-5

PTS Select (PTSSEL) Register....................................................................................

4-7

4-6

PTS Service (PTSSRV) Register .................................................................................

4-8

5-1

Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only) .......................................

5-3

5-2

Ports 3 and 4 Internal Structure (87C196LA, LB Only) ................................................

5-6

6-1

SSIO 0 Clock (SSIO0_CLK) Register...........................................................................

6-1

6-2

SSIO 1 Clock (SSIO1_CLK) Register...........................................................................

6-2

7-1

EPA Block Diagram (87C196LA, LB Only)...................................................................

7-2

7-2

EPA Block Diagram (83C196LD Only).........................................................................

7-3

7-3

EPA Interrupt Mask (EPA_MASK) Register .................................................................

7-4

7-4

EPA Interrupt Mask 1 (EPA_MASK1) Register ............................................................

7-4

7-5

EPA Interrupt Pending (EPA_PEND) Register.............................................................

7-5

7-6

EPA Interrupt Pending 1 (EPA_PEND1) Register........................................................

7-5

7-7

EPA Interrupt Priority Vector Register (EPAIPV)..........................................................

7-6

8-1

Integrated J1850 Communications Protocol Solution...................................................

8-1

8-2

J1850 Communications Controller Block Diagram .......................................................

8-2

8-3

Huntzicker Symbol Definition for J1850........................................................................

8-7

8-4

Typical VPW Waveform................................................................................................

8-7

8-5

Bit Arbitration Example .................................................................................................

8-8

8-6

J1850 Message Frames...............................................................................................

8-9

8-7

Huntzicker Symbol Definition for the Normalization Bit ..............................................

8-10

8-8

Definition for Start and End of Frame Symbols ..........................................................

8-11

8-9

IFR Type 1 Message Frame.......................................................................................

8-12

8-10

IFR Type 2 Message Frame.......................................................................................

8-13

8-11

IFR Type 3 Message Frame.......................................................................................

8-13

8-13

J1850 Transmit Message Structure............................................................................

8-14

8-12

J1850 Transmitter (J_TX) Register ............................................................................

8-14

8-15

J1850 Receive Message Structure.............................................................................

8-15

8-14

J1850 Receiver (J_RX) Register................................................................................

8-15

8-16

J1850 Command (J_CMD) Register ..........................................................................

8-17

8-17

J1850 Configuration (J_CFG) Register ......................................................................

8-18

8-18

J1850 Delay (J_DLY) Register ...................................................................................

8-20

8-19

J1850 Status (J_STAT) Register................................................................................

8-21

9-1

Reset Source (RSTSRC) Register ...............................................................................

9-1

10-1

Clock Circuitry (87C196LA, LB Only) .........................................................................

10-2

vi

 

 

CONTENTS

 

FIGURES

 

Figure

 

Page

11-1

Slave Programming Circuit.........................................................................................

11-3

11-2

Serial Port Programming Circuit .................................................................................

11-4

A-1

87C196LA 52-pin PLCC Package ...............................................................................

A-3

A-2

87C196LB 52-pin PLCC Package ...............................................................................

A-5

A-3

83C196LD 52-pin PLCC Package...............................................................................

A-7

vii

8XC196LX SUPPLEMENT

TABLES

Table

 

Page

1-1

Related Documents ......................................................................................................

1-2

2-1

Features of the 8XC196Lx and 8XC196Kx Product Famiies .......................................

2-1

2-2

State Times at Various Frequencies ............................................................................

2-4

2-3

Relationships Between Input Frequency, Clock Multiplier, and State Times ...............

2-5

2-4

UPROM Programming Values and Locations ..............................................................

2-6

3-1

Address Map ................................................................................................................

3-1

3-2

Register File Memory Addresses .................................................................................

3-3

3-3

8XC196Lx Peripheral SFRs .........................................................................................

3-4

3-4

Windows .......................................................................................................................

3-6

4-1

Interrupt Sources, Vectors, and Priorities.....................................................................

4-2

5-1

Microcontroller Ports.....................................................................................................

5-1

7-1

EPA Channels ..............................................................................................................

7-1

7-2

EPA Interrupt Priority Vectors.......................................................................................

7-6

8-1

J1850 Controller Signals ..............................................................................................

8-3

8-2

Control and Status Registers .......................................................................................

8-3

8-3

Relationships Between Input Frequency, PLL, and Prescaler Bits ..............................

8-6

8-4

Huntzicker Symbol Timing Characteristics .................................................................

8-11

11-1

Signature Word and Programming Voltage Values....................................................

11-1

11-2

87C196LA, LB OTPROM Address Map .....................................................................

11-2

11-3

Slave Programming Mode Address Map....................................................................

11-3

11-4

Serial Port Programming Mode Address Map ............................................................

11-5

A-1

87C196LA Signals Arranged by Functional Categories ..............................................

A-2

A-2

87C196LB Signals Arranged by Functional Categories ..............................................

A-4

A-3

83C196LD Signals Arranged by Functional Categories ..............................................

A-6

A-4

Definition of Status Symbols .......................................................................................

A-7

A-5

87C196LA, LB Default Signal Conditions....................................................................

A-8

A-6

83C196LD Default Signal Conditions ..........................................................................

A-9

viii

1

Guide to This Manual

CHAPTER 1

GUIDE TO THIS MANUAL

This document is a supplement to the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual. It describes the differences between the 8XC196Lx and the 8XC196Kx family of microcontrollers. For information not found in this supplement, please consult the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual (order number 272258) or the 8XC196Lx datasheets listed in the “Related Documents” section of this chapter.

1.1MANUAL CONTENTS

This supplement contains several chapters, an appendix, a glossary, and an index. This chapter, Chapter 1, provides an overview of the supplement. This section summarizes the contents of the remaining chapters and appendixes. The remainder of this chapter provides references to related documentation.

Chapter 2 Architectural Overview — compares the features of the 8XC196Lx microcontroller family with those of the 8XC196Kx microcontroller family and describes the 87C196LA, LB internal clock circuitry.

Chapter 3 Address Space — describes the addressable memory space of the 52-pin 8XC196Lx, lists the peripheral special-function registers (SFRs), and provides tables of WSR values for windowing higher memory into the lower register file for direct access.

Chapter 4 Standard and PTS Interrupts — describes the additional interrupts for the 87C196LB’s J1850 communications controller peripheral and the SFRs that support those interrupts.

Chapter 5 — I/O Ports — state from a “logic 1” to

describes the port differences and explains the change in the port reset a “logic 0” on the 87C196LA, LB.

Chapter 6 — Synchronous Serial I/O Port —

describes the enhanced synchronous serial I/O

(SSIO) port and explains how to program the two additional peripheral SFRs.

Chapter 7 — Event Processor Array —

describes the event processor array channel differenc-

es.

 

 

Chapter 8 — J1850 Communications Controller — describes the 87C196LB’s integrated J1850 controller and explains how to configure it.

Chapter 9 — Minimum Hardware Considerations — describes device reset options through the reset source register, and discusses hardware design considerations.

Chapter 10 Special Operating Modes — illustrates the internal clock control circuitry of the 87C196LA, LB and describes how to enter and exit on-circuit emulation (ONCE) mode.

Chapter 11 — Programming the Nonvolatile Memory — describes the memory maps and recommended circuits to support programming of the 87C196LA, LB’s 24 Kbytes of OTPROM.

1-1

8XC196LX SUPPLEMENT

Appendix A Signal Descriptions — provides reference information for the 8XC196Lx device pins, including descriptions of the pin functions, reset status of the I/O and control pins, and package pin assignments.

Glossary — defines terms with special meaning used throughout this supplement.

Index — lists key topics with page number references.

1.2RELATED DOCUMENTS

Table 1-1 lists additional documents that you may find useful in designing systems incorporating the 8XC196Lx microcontrollers.

Table 1-1. Related Documents

Title and Description

Order Number

 

 

8XC196Kx, 8XC196Jx, 87C196CA Microcontroller Family User’s Manual

272258

87C196LA-20 MHz CHMOS 16-Bit Microcontroller Automotive datasheet

272806

87C196LB-20 MHz CHMOS 16-Bit Microcontroller Automotive datasheet

272807

83C196LD CHMOS 16-Bit Microcontroller Automotive datasheet

272805

1-2

2

Architectural

Overview

CHAPTER 2

ARCHITECTURAL OVERVIEW

This chapter describes architectural differences between the 8XC196Lx (87C196LA, 87C196LB, and 83C196LD) and the 8XC196Kx (8XC196Kx, 8XC196Jx, and 87C196CA) microcontroller families. Both the 8XC196Lx and the 8XC196Kx are designed for high-speed calculations and fast I/O, and share a common architecture and instruction set with few deviations. This chapter provides a high-level overview of the deviations between the two families.

NOTE

This supplement describes two product families within the MCS® 96 microcontroller family. For brevity, the name 8XC196Lx is used when the discussion applies to all three Lx controllers. Likewise, the name 8XC196Kx is used when the discussion applies to all the Kx, Jx, and CA controllers.

2.1MICROCONTROLLER FEATURES

Table 2-1 lists the features of the 8XC196Lx and the 8XC196Kx.

Table 2-1. Features of the 8XC196Lx and 8XC196Kx Product Famiies

 

 

OTPROM/

Register

Code

I/O

EPA

SIO/

 

 

 

Ext.

Device

Pins

EPROM/

SSIO

A/D

CAN

J1850

Interrupt

RAM (2)

RAM

Pins

Pins

 

 

ROM (1)

Ports

 

 

 

Pins

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

87C196LA

52

24 K

768

41

6

3

6

1

 

 

 

 

 

 

 

 

 

 

 

 

87C196LB

52

24 K

768

41

6

3

6

1

1

 

 

 

 

 

 

 

 

 

 

 

 

83C196LD

52

16 K

384

41

6

3

1

 

 

 

 

 

 

 

 

 

 

 

 

8XC196JV

52

48 K

1536

512

41

6

3

6

1

 

 

 

 

 

 

 

 

 

 

 

 

8XC196KT

68

32 K

1024

512

56

10

3

8

2

 

 

 

 

 

 

 

 

 

 

 

 

8XC196JT

52

32 K

1024

512

41

6

3

6

1

 

 

 

 

 

 

 

 

 

 

 

 

87C196CA

68

32 K

1024

256

51

6

3

6

1

2

 

 

 

 

 

 

 

 

 

 

 

 

8XC196KR

68

16 K

512

256

56

10

3

8

2

 

 

 

 

 

 

 

 

 

 

 

 

8XC196JR

52

16 K

512

256

41

6

3

6

1

 

 

 

 

 

 

 

 

 

 

 

 

NOTES:

1.Optional. The second character of the device name indicates the presence and type of nonvolatile memory. 80C196xx = none; 83C196xx = ROM; 87C196xx = OTPROM or EPROM.

2.Register RAM amounts include the 24 bytes allocated to core SFRs and the stack pointer.

2-1

8XC196LX SUPPLEMENT

2.2BLOCK DIAGRAM

Figure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller. Observe that the slave port peripheral does not exist on the 8XC196Lx.

 

 

 

 

 

 

 

 

Core

Optional

 

Interrupt

 

 

(CPU, Memory

ROM/

 

 

 

 

Controller

 

 

Controller)

OTPROM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Peripheral

 

 

Clock and

 

Optional

 

 

 

 

Code/Data

 

Transaction

 

 

Power Mgmt.

 

 

 

 

 

RAM

 

Server

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

SIO

SSIO

EPA

A/D

WDT

J1850

Note:

The J1850 peripheral is unique to the 87C196LB device.

The A/D peripheral is unique to the 87C196LA, LB devices.

A5253-01

Figure 2-1. 8XC196Lx Block Diagram

2.3INTERNAL TIMING

The 87C196LA, LB clock circuitry (Figure 2-2) implements a phase-locked loop and clock multiplier circuitry, which can substantially increase the CPU clock rate while using a lower-frequen- cy input clock. The clock circuitry accepts an input clock signal on XTAL1 provided by an external crystal or oscillator. Depending on the value of the PLLEN pin, this frequency is routed either through the phase-locked loop and multiplier or directly to the divide-by-two circuit. The multiplier circuitry can double the input frequency (FXTAL1) before the frequency (f) reaches the divide-by-two circuitry. The clock generators accept the divided input frequency (f/2) from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2. These signals are active when high.

NOTE

This manual uses lowercase “f” to represent the internal clock frequency. For

the 87C196LA and LB, f is equal to either FXTAL1 or 2FXTAL1, depending on the clock multiplier mode, which is controlled by the PLLEN input pin.

2-2

ARCHITECTURAL OVERVIEW

FXTAL1

XTAL1

XTAL2

Disable Oscillator (Powerdown)

 

 

 

 

Disable

Phase

 

 

Filter

 

 

 

 

 

PLL

 

 

 

 

 

 

 

Comparator

 

 

 

 

(Powerdown)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Phase-locked

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Oscillator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

XTAL1

XTAL1

 

 

 

 

PLLEN

 

Phase-locked Loop

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Multiplier

F

2F

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disable Clock Input (Powerdown)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Divide by two

 

 

 

 

 

 

 

 

 

 

 

 

Circuit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f/2

 

To reset logic

 

 

Disable Clocks (Idle, Powerdown)

Clock

Clock

CPU Clocks (PH1, PH2)

Failure

 

Generators

 

Detection

Peripheral Clocks (PH1, PH2)

 

 

 

f/2

 

 

Programmable

 

OSC

Divider

 

 

(CLK1:0)

 

 

 

 

0

 

 

CLKOUT

 

 

1

 

 

Disable Clocks (Powerdown)

 

 

A5290-01

Figure 2-2. Clock Circuitry (87C196LA, LB Only)

The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-3). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibility in power management. It also outputs the CLKOUT signal on the CLKOUT pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal. This delay varies with temperature and voltage.

2-3

8XC196LX SUPPLEMENT

XTAL1

t t

1 State Time

 

1 State Time

 

PH1

PH2

CLKOUT

Phase 1

Phase 2

Phase 1

Phase 2

A0805-01

Figure 2-3. Internal Clock Phases (Assumes PLL is Bypassed)

The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies.

Table 2-2. State Times at Various Frequencies

f

 

(Frequency Input to the

State Time

Divide-by-two Circuit)

 

 

 

8 MHz

250 ns

 

 

12 MHz

167 ns

 

 

16 MHz

125 ns

 

 

20 MHz

100 ns

 

 

The following formulas calculate the frequency of PH1 and PH2, the duration of a state time, and the duration of a clock period (t).

f

2

1

PH1 (in MHz) = -- = PH2

State Time (in µs) = --

t = --

2

f

f

Because the device can operate at many frequencies, this manual defines time requirements (such as instruction execution times) in terms of state times rather than specific measurements. Datasheets list AC characteristics in terms of clock periods (t; sometimes called Tosc).

Figure 2-4 illustrates the timing relationships between the input frequency (FXTAL1), the operating frequency (f), and the CLKOUT signal with each PLLEN pin configuration. Table 2-3 details the relationships between the input frequency (FXTAL1), the PLLEN pin, the operating frequency (f), the clock period (t), and state times.

2-4

ARCHITECTURAL OVERVIEW

 

TXHCH

XTAL1

 

(16 MHz)

 

f

 

PLLEN = 0

t = 62.5ns

Internal

 

CLKOUT

 

f

 

PLLEN = 1

t = 31.25ns

Internal

 

CLKOUT

 

 

A3376-01

Figure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency

Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times

FXTAL1

PLLEN

Multiplier

f

t

State Time

(Frequency

(Input Frequency to

(Clock

on XTAL1)

 

 

the Divide-by-two Circuit)

Period)

 

 

 

 

 

 

 

4 MHz

0

1

4 MHz

250 ns

500 ns

8 MHz

0

1

8 MHz

125 ns

250 ns

12 MHz

0

1

12 MHz

83.5 ns

167 ns

16 MHz

0

1

16 MHz

62.5 ns

125 ns

20 MHz

0

1

20 MHz

50 ns

100 ns

4 MHz

1

2

8 MHz

125 ns

250 ns

8 MHz

1

2

16 MHz

62.5 ns

125 ns

10 MHz

1

2

20 MHz

50 ns

100 ns

2.4EXTERNAL TIMING

You can control the output frequency on the CLKOUT pin by programming two uneraseable PROM bits. Figure 2-5 illustrates the read-only USFR1, which reflects the state of the unerasable PROM bits. You can select one of three frequencies: f/2, f/4, or f/8. As Figure 2-2 on page 2-3 shows, the configurable divider accepts the output of the clock generators (f/2) and further divides that frequency to produce the desired output frequency. The CLK1:0 bits control the divisor (divide f/2 by either 1, 2, or 4).

2-5

8XC196LX SUPPLEMENT

USFR1 (read only)

Address:

1FF2H

 

Reset State:

XXH

The UPROM special-function register 1 (USFR1) reflects the status of unerasable, programmable read-only memory (UPROM) locations. This read-only register reflects the status of two bits that control the output frequency on CLKOUT.

7

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

CLK1

CLK0

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Bit

 

 

 

 

 

 

Function

 

 

Number

Mnemonic

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7:2

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1:0

CLK1:0

CLKOUT Control

 

 

 

 

 

 

 

 

These bits reflect the programmed frequency of the CLKOUT signal:

 

 

CLK1 CLK0

 

 

 

 

 

 

 

 

 

0

0

 

divide by 1 (CLKOUT = f/2)

 

 

 

 

0

1

 

divide by 2 (CLKOUT = f/4)

 

 

 

 

1

0

 

divide by 4 (CLKOUT = f/8)

 

 

 

 

1

1

 

divide by 1 (CLKOUT = f/2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 2-5. Unerasable PROM 1 (USFR1) Register (LA, LB Only)

To program these bits, write the correct value to the locations shown in Table 2-4 using slave programming mode. During normal operation, you can determine the values of these bits by reading the UPROM SFR (Figure 2-5).

You can verify a UPROM bit to make sure it programmed, but you cannot erase it. For this reason, Intel cannot test the bits before shipment. However, Intel does test the features that the UPROM bits enable, so the only undetectable defects are (unlikely) defects within the UPROM cells themselves.

Table 2-4. UPROM Programming Values and Locations

To set this bit

Write this value

To this location

 

 

 

CLK0

0001H

0768H

 

 

 

CLK1

0002H

0728H

 

 

 

2.5INTERNAL PERIPHERALS

The internal peripheral modules provide special functions for a variety of applications. This section provides a brief description of the peripherals that differ between the 8XC196Lx and the 8XC196Kx families.

2-6

ARCHITECTURAL OVERVIEW

2.5.1I/O Ports

The I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, on the 87C196LA and LB the reset state level of all 41 general-purpose I/O pins has changed from a weak logic “1” (wk1) to a weak logic “0” (wk0).

2.5.2Synchronous Serial I/O Port

The synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing two new special function registers (SSIO0_CLK and SSIO1_CLK) that allow you to select the operating mode and configure the phase and polarity of the serial clock signals.

2.5.3Event Processor Array

The 8XC196Lx’s event processor array (EPA) is functionally identical to that of the 8XC196Jx, except that it has only two EPA capture/compare channels without pins instead of four. In addition the LD has no compare-only channels.

2.5.4J1850 Communications Controller

The 87C196LB microcontroller has a peripheral not found on the 8XC196Kx microcontrollers or any other Lx microcontroller, the J1850 peripheral. The J1850 communications controller manages communications between multiple network nodes. This integrated peripheral supports the 10.4 Kb/s VPW (variable pulse-width) medium-speed, class B, in-vehicle network protocol. It also supports both the standard and in-frame response (IFR) message framing as specified by the

Society of Automotive Engineering (SAE) J1850 (revised May 1994) technical standards.

2.6DESIGN CONSIDERATIONS

With the exception of a few new multiplexed functions, the 8XC196Lx microcontrollers are pin compatible with the 8XC196Jx microcontrollers. The 8XC196Jx microcontrollers are 52-lead versions of 8XC196Kx microcontrollers. For registers that are implemented in both the 8XC196Lx and the 8XC196Jx, configure the 8XC196Lx register as you would for the 8XC196Jx unless differences are noted in this supplement.

2-7

3

Address Space

CHAPTER 3

ADDRESS SPACE

This chapter describes the differences in the address space of the 8XC196Lx from that of the 8XC196Kx.

3.1ADDRESS PARTITIONS

Table 3-1 is an address map of the 8XC196Lx and 8XC196Kx microcontroller family members.

Table 3-1. Address Map

 

Device and Hex Address Range

 

 

 

 

 

 

 

 

 

 

 

 

 

Addressing

CA

KRJR,

LD

LBLA,

 

KTJT,

 

JV

Description

 

 

Modes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FFFF

FFFF

FFFF

FFFF

 

FFFF

 

FFFF

External device (memory

Indirect or

 

 

or I/O) connected to

A000

6000

6000

8000

 

A000

 

E000

indexed

 

 

address/data bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program memory

 

9FFF

5FFF

5FFF

7FFF

 

9FFF

 

DFFF

(internal nonvolatile or

Indirect or

2080

2080

2080

2080

 

2080

 

2080

external memory); see

indexed

 

 

 

 

 

 

 

 

Note 1

 

207F

207F

207F

207F

 

207F

 

207F

Special-purpose memory

Indirect or

 

 

(internal nonvolatile or

2000

2000

2000

2000

 

2000

 

2000

indexed

 

 

external memory)

 

 

 

 

 

 

 

 

 

1FFF

1FFF

1FFF

1FFF

 

1FFF

 

1FFF

Memory-mapped SFRs

Indirect or

1FE0

1FE0

1FE0

1FE0

 

1FE0

 

1FE0

indexed

 

 

 

 

 

 

 

 

 

 

 

Peripheral SFRs

Indirect,

1FDF

1FDF

1FDF

1FDF

 

1FDF

 

1FDF

indexed, or

 

 

(Includes J1850 SFRs on

1F00

1F00

1F00

1F00

 

1F00

 

1F00

windowed

 

 

87C196LB)

 

 

 

 

 

 

 

 

direct

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Indirect,

1EFF

 

CAN

SFRs

indexed, or

1E00

 

windowed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

direct

 

 

 

 

 

 

 

 

External device (memory

 

1DFF

1EFF

1EFF

1EFF

 

1EFF

 

1EFF

or I/O) connected to

Indirect or

 

 

address/data bus;

1C00

1C00

1C00

0300

 

1C00

 

1E00

indexed

 

 

(future SFR expansion;

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

see Note 2)

 

 

 

 

 

 

 

 

 

 

Indirect,

 

1DFF

Register RAM

indexed, or

 

1C00

windowed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

direct

NOTES:

1.After a reset, the device fetches its first instruction from 2080H.

2.The content or function of these locations may change in future device revisions, in which case a program that relies on a location in this range might not function properly.

3-1

8XC196LX SUPPLEMENT

Table 3-1. Address Map (Continued)

 

Device and Hex Address Range

 

 

 

 

 

 

 

 

 

 

Addressing

CA

KRJR,

LD

LBLA,

KTJT,

JV

Description

Modes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1BFF

1BFF

1BFF

 

1BFF

1BFF

External device (memory

Indirect or

or I/O) connected to

0500

0500

0600

0600

0600

indexed

 

address/data bus

 

 

 

 

 

 

 

04FF

04FF

05FF

05FF

Internal code or data RAM

Indirect or

0400

0400

0400

0400

indexed

 

 

 

 

03FF

05FF

 

 

 

External device (memory

Indirect or

or I/O) connected to

0200

0180

indexed

 

 

 

 

address/data bus

 

 

 

 

 

 

 

 

 

 

 

 

 

Upper register file

Indirect,

03FF

01FF

017F

02FF

03FF

03FF

indexed, or

(general-purpose register

0100

0100

0100

0100

0100

0100

windowed

RAM)

 

 

 

 

 

 

direct

 

 

 

 

 

 

 

00FF

00FF

00FF

00FF

00FF

00FF

Lower register file

Direct,

(register RAM, stack

indirect, or

0000

0000

0000

0000

0000

0000

pointer, and CPU SFRs)

indexed

 

 

 

 

 

 

NOTES:

1.After a reset, the device fetches its first instruction from 2080H.

2.The content or function of these locations may change in future device revisions, in which case a program that relies on a location in this range might not function properly.

3.2REGISTER FILE

Figure 3-1 compares the register file addresses of the 8XC196Lx and 8XC196Kx. The register file in Figure 3-1 is divided into an upper register file and a lower register file. The upper register file consists of general-purpose register RAM. The lower register file contains general-purpose register RAM along with the stack pointer (SP) and the CPU special-function registers (SFRs).

Table 3-2 lists the register file memory addresses. The RALU accesses the lower register file directly, without the use of the memory controller. It also accesses a windowed location directly (see “Windowing” on page 3-6). The upper register file and the peripheral SFRs can be windowed. Registers in the lower register file and registers being windowed can be accessed with register-direct addressing.

NOTE

The register file must not contain code. An attempt to execute an instruction from a location in the register file causes the memory controller to fetch the instruction from external memory.

3-2

ADDRESS SPACE

 

 

 

 

 

 

 

 

 

 

 

 

 

Address

 

 

 

 

 

 

 

 

 

 

 

 

 

03FFH

 

 

 

 

 

 

 

 

 

 

 

 

 

(CA, JT, JV, KT)

 

 

 

 

 

 

 

 

 

 

 

General-purpose

 

 

 

 

 

 

 

 

 

 

 

 

 

Register RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

02FFH (LA, LB)

 

 

 

 

 

 

 

 

 

 

 

 

 

01FFH (JR, KR)

 

 

 

 

 

 

 

 

 

 

 

 

 

017FH (LD)

 

 

Address

 

 

 

 

 

 

 

 

0100H

 

 

 

03FFH

 

 

 

 

 

 

General-purpose

00FFH

 

 

 

Upper

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0100H

Register File

 

 

 

Register RAM

001AH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Stack Pointer

0019H

 

 

 

00FFH

 

 

 

 

 

 

 

 

 

Lower

 

 

 

 

 

0018H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register File

 

 

 

CPU SFRs

0017H

 

 

 

0000H

 

 

 

0000H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5260-01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 3-1. Register File Address Map

 

 

 

 

 

 

 

Table 3-2. Register File Memory Addresses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device and Hex Address Range

 

 

Description

 

Addressing Modes

 

 

 

 

 

 

 

 

 

 

 

 

 

JV

 

CA,JT,KT

LA, LB

JR, KR

 

LD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1DFF

 

Register RAM

 

Indirect, indexed, or

1C00

 

 

windowed direct

 

 

 

 

 

 

 

 

 

 

 

 

03FF

 

03FF

02FF

01FF

 

017F

Upper register file (register RAM)

 

Indirect, indexed, or

0100

 

0100

 

0100

0100

 

0100

 

windowed direct

 

 

 

 

 

 

 

00FF

 

00FF

00FF

00FF

 

00FF

Lower register file (register RAM)

 

Direct, indirect, or

001A

 

001A

001A

001A

 

001A

 

indexed

 

 

 

 

 

 

0019

 

0019

 

0019

0019

 

0019

Lower register file (stack pointer)

 

Direct, indirect, or

0018

 

0018

 

0018

0018

 

0018

 

indexed

 

 

 

 

 

 

 

0017

 

0017

 

0017

0017

 

0017

Lower register file (CPU SFRs)

 

Direct, indirect, or

0000

 

0000

 

0000

0000

 

0000

 

indexed

 

 

 

 

 

 

 

3-3

8XC196LX SUPPLEMENT

3.3PERIPHERAL SPECIAL-FUNCTION REGISTERS

Table 3-3 lists the peripheral SFR addresses. Highlighted addresses are unique to the 8XC196Lx.

Table 3-3. 8XC196Lx Peripheral SFRs

Ports 3, 4, 5, and UPROM SFRs

Address

High (Odd) Byte

Low (Even) Byte

1FFEH

P4_PIN

P3_PIN

1FFCH

P4_REG

P3_REG

1FFAH

SLP_CON

SLP_CMD

1FF8H

Reserved

SLP_STAT

1FF6H

P5_PIN

USFR

1FF4H

P5_REG

P34_DRV

1FF2H

P5_DIR

USFR1 (LA, LB)

1FF0H

P5_MODE

Reserved

1FEEH

Reserved

Reserved

1FECH

Reserved

Reserved

1FEAH

Reserved

Reserved

1FE8H

Reserved

Reserved

1FE6H

Reserved

Reserved

1FE4H

Reserved

Reserved

1FE2H

Reserved

Reserved

1FE0H

Reserved

Reserved

Must be addressed as a word.

Ports 0, 1, 2, and 6 SFRs

Address

High (Odd) Byte

Low (Even) Byte

1FDEH

Reserved

Reserved

1FDCH

Reserved

Reserved

1FDAH

Reserved

P0_PIN

1FD8H

Reserved

Reserved

1FD6H

P6_PIN

P1_PIN

1FD4H

P6_REG

P1_REG

1FD2H

P6_DIR

P1_DIR

1FD0H

P6_MODE

P1_MODE

1FCEH

P2_PIN

Reserved

1FCCH

P2_REG

Reserved

1FCAH

P2_DIR

Reserved

1FC8H

P2_MODE

Reserved

1FC6H

Reserved

Reserved

1FC4H

Reserved

Reserved

1FC2H

Reserved

Reserved

1FC0H

Reserved

Reserved

3-4

ADDRESS SPACE

Table 3-3. 8XC196Lx Peripheral SFRs (Continued)

SIO and SSIO SFRs

Address

High (Odd) Byte

Low (Even) Byte

1FBEH

Reserved

Reserved

1FBCH

SP_BAUD (H)

SP_BAUD (L)

1FBAH

SP_CON

SBUF_TX

1FB8H

SP_STATUS

SBUF_RX

1FB6H

SSIO1_CLK

Reserved

1FB4H

SSIO0_CLK

SSIO_BAUD

1FB2H

SSIO1_CON

SSIO1_BUF

1FB0H

SSIO0_CON

SSIO0_BUF

 

A/D SFRs (LA, LB Only)

Address

High (Odd) Byte

Low (Even) Byte

1FAEH

AD_TIME

AD_TEST

1FACH

Reserved

AD_COMMAND

1FAAH

AD_RESULT (H)

AD_RESULT (L)

 

EPA Interrupt SFRs

Address

High (Odd) Byte

Low (Even) Byte

1FA8H

Reserved

EPAIPV

1FA6H

Reserved

EPA_PEND1

1FA4H

Reserved

EPA_MASK1

1FA2H

EPA_PEND (H)

EPA_PEND (L)

1FA0H

EPA_MASK (H)

EPA_MASK (L)

Timer 1, Timer 2, and EPA SFRs

Address

High (Odd) Byte

Low (Even) Byte

1F9EH

TIMER2 (H)

TIMER2 (L)

1F9CH

Reserved

T2CONTROL

1F9AH

TIMER1 (H)

TIMER1 (L)

1F98H

Reserved

T1CONTROL

1F96H

Reserved

Reserved

1F94H

Reserved

Reserved

1F92H

Reserved

RST_SRC

1F90H

Reserved

Reserved

 

EPA SFRs

 

Address

High (Odd) Byte

Low (Even) Byte

1F8EH

COMP1_TIME (H)

COMP1_TIME (L)

1F8CH

Reserved

COMP1_CON

1F8AH

COMP0_TIME (H)

COMP0_TIME (L)

1F88H

Reserved

COMP0_CON

1F86H

EPA9_TIME (H)

EPA9_TIME (L)

1F84H

Reserved

EPA9_CON

1F82H

EPA8_TIME (H)

EPA8_TIME (L)

1F80H

Reserved

EPA8_CON

Must be addressed as a word.

EPA SFRs (Continued)

Address

High (Odd) Byte

Low (Even) Byte

1F7EH

EPA7_TIME (H)

EPA7_TIME (L)

1F7CH

Reserved

EPA7_CON

1F7AH

EPA6_TIME (H)

EPA6_TIME (L)

1F78H

Reserved

EPA6_CON

1F76H

EPA5_TIME (H)

EPA5_TIME (L)

1F74H

Reserved

EPA5_CON

1F72H

EPA4_TIME (H)

EPA4_TIME (L)

1F70H

Reserved

EPA4_CON

1F6EH

EPA3_TIME (H)

EPA3_TIME (L)

1F6CH

EPA3_CON (H)

EPA3_CON (L)

1F6AH

EPA2_TIME (H)

EPA2_TIME (L)

1F68H

Reserved

EPA2_CON

1F66H

EPA1_TIME (H)

EPA1_TIME (L)

1F64H

EPA1_CON (H)

EPA1_CON (L)

1F62H

EPA0_TIME (H)

EPA0_TIME (L)

1F60H

Reserved

EPA0_CON

 

J1850 SFRs (LB Only)

Address

High (Odd) Byte

Low (Even) Byte

1F5EH

Reserved

Reserved

1F5CH

Reserved

Reserved

1F5AH

Reserved

Reserved

1F58H

Reserved

J_DLY

1F56H

Reserved

Reserved

1F54H

Reserved

J_CFG

1F52H

J_STAT

J_RX

1F50H

J_CMD

J_TX

3-5

8XC196LX SUPPLEMENT

3.4WINDOWING

Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into the lower register file. The window selection register (WSR) selects a 32-, 64or 128-byte segment of higher memory to be windowed into the top of the lower register file space. Table 3-4 lists the WSR values for windowing the upper register file for both the 8XC196Lx and 8XC196Kx.

Table 3-4. Windows

 

 

WSR Value

WSR Value

WSR Value for

Base

 

128-byte

 

for 32-byte Window

for 64-byte Window

Address

 

Window

 

(00E0–00FFH)

(00C0–00FFH)

 

 

(0080–00FFH)

 

 

 

 

 

 

 

 

 

Peripheral SFRs

 

 

 

 

 

 

 

1FE0H

 

7FH (Note)

 

 

1FC0H

 

7EH

3FH (Note)

 

1FA0H

 

7DH

 

 

1F80H

 

7CH

3EH

1FH (Note)

1F60H

 

7BH

 

 

1F40H

 

7AH

3DH

 

1F20H

 

79H

 

 

1F00H

 

78H

3CH

1EH

CAN Peripheral SFRs (87C196CA Only)

 

 

 

 

 

 

1EE0H

 

77H

 

 

1EC0H

 

76H

3BH

 

1EA0H

 

75H

 

 

1E80H

 

74H

3AH

1DH

1E60H

 

73H

 

 

1E40H

 

72H

39H

 

1E20H

 

71H

 

 

1E00H

 

70H

38H

1CH

Register RAM (87C196JV Only)

 

 

 

 

 

 

1DE0H

 

6FH

 

 

1DC0H

 

6EH

37H

 

1DA0H

 

6DH

 

 

1D80H

 

6CH

36H

1BH

1D60H

 

6BH

 

 

1D40H

 

6AH

35H

 

1D20H

 

69H

 

 

1D00H

 

68H

34H

1AH

NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a window. Reading these locations through a window returns FFH; writing these locations through a window has no effect.

3-6

 

 

 

 

ADDRESS SPACE

 

Table 3-4. Windows (Continued)

 

 

 

 

 

 

 

 

 

WSR Value

 

WSR Value

WSR Value for

 

Base

 

128-byte

 

for 32-byte Window

 

for 64-byte Window

 

Address

 

Window

 

(00E0–00FFH)

 

(00C0–00FFH)

 

 

 

(0080–00FFH)

 

 

 

 

 

 

 

 

 

 

 

 

Register RAM (87C196JV Only; Continued)

 

 

 

 

 

 

 

 

 

1CE0H

67H

 

 

 

 

1CC0H

66H

 

33H

 

 

1CA0H

65H

 

 

 

 

1C80H

64H

 

32H

19H

 

1C60H

63H

 

 

 

 

1C40H

62H

 

31H

 

 

1C20H

61H

 

 

 

 

1C00H

60H

 

30H

18H

 

Upper Register File (CA, JT, JV, KT)

 

 

 

 

 

 

 

 

 

03E0H

5FH

 

 

 

 

03C0H

5EH

 

2FH

 

 

03A0H

5DH

 

 

 

 

0380H

5CH

 

2EH

17H

 

0360H

5BH

 

 

 

 

0340H

5AH

 

2DH

 

 

0320H

59H

 

 

 

 

0300H

58H

 

2CH

16H

 

Upper Register File (CA, JT, JV, KT, LA, LB)

 

 

 

 

 

 

 

 

 

02E0H

57H

 

 

 

 

02C0H

56H

 

2BH

 

 

02A0H

55H

 

 

 

 

0280H

54H

 

2AH

15H

 

0260H

53H

 

 

 

 

0240H

52H

 

29H

 

 

0220H

51H

 

 

 

 

0200H

50H

 

28H

14H

 

Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB)

 

 

 

 

 

 

 

 

 

01E0H

4FH

 

 

 

 

01C0H

4EH

 

27H

 

 

01A0H

4DH

 

 

 

 

0180H

4CH

 

26H

13H

 

NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a window. Reading these locations through a window returns FFH; writing these locations through a window has no effect.

3-7

8XC196LX SUPPLEMENT

Table 3-4. Windows (Continued)

 

WSR Value

WSR Value

WSR Value for

Base

128-byte

for 32-byte Window

for 64-byte Window

Address

Window

(00E0–00FFH)

(00C0–00FFH)

 

(0080–00FFH)

 

 

 

 

 

 

 

Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB, LD)

 

 

 

 

 

0160H

4BH

 

 

0140H

4AH

25H

 

0120H

49H

 

 

0100H

48H

24H

12H

NOTE: Locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be accessed through a window. Reading these locations through a window returns FFH; writing these locations through a window has no effect.

3-8

4

Standard and PTS

Interrupts

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