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8XC196MC
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Intel 8XC196MH, 8XC196MC, 8XC196MD User Manual

8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual
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Please fax this f orm to (602)554-7436 or mail it to
Marcia Bethel, Glenn Dotson, Robin Manelis, and Sue Ranta Technical Information Developers Intel Corpor ation, Mail Stop CH6-224 5000 W. Chandl er Blv d. Chandler, AZ 85226
-2
8XC196MC,
8XC196MD, 8XC196MH
Microcontrol ler
User’s Manual
August 2004 Order Number 272181-003
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyrig ht, for sale and use of Intel products except as provided in Intel’s Terms and Conditi on s of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation. Intel Corporation and Intel’s FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products. *Other brands and names are the property of their respective owners. Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
© INTEL CORPORATION, 1996
CONTENT
CHAPTER 1
TO THIS MANUAL
GUIDE
1.
1 MANUAL CONTENTS ................................................................................................... 1-1
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
1.
3 RELATED DOCUMENTS .............................................................................................. 1-5
1.
4 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-8
4 World Wide Web .....................................................................................................1-11
1.4.
1.
5 TECHNICAL SUPPORT .............................................................................................. 1-11
1.
6 PRODUCT LITERATURE ............................................................................................ 1-11
CHAPTER 2
ARCHITECTURAL
2.
1 TYPICAL APPLICATIONS ............................................................................................. 2-1
2.
2 MICROCONTROLLER FEATURES .............................................................................. 2-1
2.
3 FUNCTIONAL OVERVIEW............................................................................................ 2-2
1 CPU Control ..............................................................................................................2-4
2.3.
2.3.
2 Register File ..............................................................................................................2-4
2.3.
3 Register Arithmetic-logic Unit (RALU) .......................................................................2-4
1 Code Execution ....................................................................................................2-5
2.3.3.
2 Instruction Format ................................................................................................2-5
2.3.3.
2.3.
4 Memory Interface Unit ...............................................................................................2-6
2.3.
5 Interrupt Service ........................................................................................................2-6
2.
4 INTERNAL TIMING........................................................................................................ 2-7
2.
5 INTERNAL PERIPHERALS ........................................................................................... 2-8
2.5.
1 I/O Ports ....................................................................................................................2-9
2.5.
2 Serial I/O (SIO) Port ..................................................................................................2-9
2.5.
3 Event Processor Array (EPA) and Timer/Counters .................................................2-10
2.5.
4 Pulse-width Modulator (PWM) ................................................................................2-10
2.5.
5 Frequency Generator ..............................................................................................2-10
2.5.
6 Waveform Generator ..............................................................................................2-10
2.5.
7 Analog-to-digital Converter .....................................................................................2-11
2.5.
8 Watchdog Timer ......................................................................................................2-11
2.
6 SPECIAL OPERATING MODES ................................................................................. 2-11
2.6.
1 Reducing Power Consumption ...............................................................................2-11
2.6.
2 Testing the Printed Circuit Board ............................................................................2-11
2.6.
3 Programming the Nonvolatile Memory ....................................................................2-12
OVERVIEW
S
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8XC196MC, MD, MH USER’S MANUAL
CHAPTER 3
PROGRAMMING CONSIDERATIONS
3.1 OVERVIEW OF THE INSTRUCTION SET.................................................................... 3-1
3.1.1 BIT Operands ............................................................................................................3-2
3.1.2 BYTE Operands ........................................................................................................3-2
3.1.3 SHORT-INTEGER Operands ....................................................................................3-2
3.1.4 WORD Operands ......................................................................................................3-2
3.1.5 INTEGER Operands .................................................................................................3-3
3.1.6 DOUBLE-WORD Operands ......................................................................................3-3
3.1.7 LONG-INTEGER Operands ......................................................................................3-4
3.1.8 Converting Operands ................................................................................................3-4
3.1.9 Conditional Jumps ....................................................................................................3-4
3.1.10 Floating Point Operations .........................................................................................3-4
3.2 ADDRESSING MODES . ................................................................................................ 3-5
3.2.1 Direct Addressing ......................................................................................................3-6
3.2.2 Immediate Addressing ..............................................................................................3-6
3.2.3 Indirect Addressing ...................................................................................................3-6
3.2.3.1 Indirect Addressing with Autoincrement ...............................................................3-7
3.2.3.2 Indirect Addressing with the Stack Pointer ........................................................... 3-7
3.2.4 Indexed Addressing ..................................................................................................3-7
3.2.4.1 Short-indexed Addressing ....................................................................................3-7
3.2.4.2 Long-indexed Addressing .................................................................................... 3-8
3.2.4.3 Zero-indexed Addressing .....................................................................................3-8
3.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS.................................. 3-9
3.3.1 Direct Addressing ......................................................................................................3-9
3.3.2 Indexed Addressing ..................................................................................................3-9
3.4 SOFTWARE STANDARDS AND CONVENTIONS ....................................................... 3-9
3.4.1 Using Registers .........................................................................................................3-9
3.4.2 Addressing 32-bit Operands ...................................................................................3-10
3.4.3 Linking Subroutines ................................................................................................3-10
3.5 SOFTWARE PROTECTION FEATURES AND GUIDELINES .................................... 3-11
CHAPTER 4
MEMORY PARTITIONS
4.1 MEMORY PARTITIONS................................................................................................ 4-1
4.1.1 External Devices (Memory or I/O) .............................................................................4-1
4.1.2 Program and Special-purpose Memory ....................................................................4-1
4.1.3 Program Memory ......................................................................................................4-2
4.1.4 Special-purpose Memory ..........................................................................................4-3
4.1.4.1 Reserved Memory Locations ...............................................................................4-3
4.1.4.2 Interrupt and PTS Vectors .................................................................................... 4-3
4.1.4.3 Security Key .........................................................................................................4-4
4.1.4.4 Chip Configuration Bytes (CCBs) .........................................................................4-4
4.1.5 Special-function Registers (SFRs) ............................................................................ 4-4
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CONTENTS
4.1.5.1 Memory-mapped SFRs ........................................................................................4-5
4.1.5.2 Peripheral SFRs ...................................................................................................4-5
4.1.6 Register File ..............................................................................................................4-9
4.1.6.1 General-purpose Register RAM .........................................................................4-10
4.1.6.2 Stack Pointer (SP) ..............................................................................................4-10
4.1.6.3 CPU Special-function Registers (SFRs) .. ...........................................................4-11
4.2 WINDOWING............................................................................................................... 4-12
4.2.1 Selecting a Window ................................................................................................4-13
4.2.2 Addressing a Location Through a Window ............................................................. 4-14
4.2.2.1 32-byte Windowing Example ..............................................................................4-16
4.2.2.2 64-byte Windowing Example ..............................................................................4-16
4.2.2.3 128-byte Windowing Example ............................................................................4-16
4.2.2.4 Unsupported Locations Windowing Example .....................................................4-16
4.2.2.5 Using the Linker Locator to Set Up a Window ....................................................4-17
4.2.3 Windowing and Addressing Modes .........................................................................4-19
CHAPTER 5
STANDARD AND PTS INTERRUPTS
5.1 OVERVIEW OF INTERRUPTS............. ......................................................................... 5-1
5.2 INTERRUPT SIGNALS AND REGISTERS ................................................................... 5-3
5.3 INTERRUPT SOURCES AND PRIORITIES.................................................................. 5-4
5.3.1 Special Interrupts ......................................................................................................5-6
5.3.1.1 Unimplemented Opcode ......................................................................................5-6
5.3.1.2 Software Trap .......................................................................................................5-6
5.3.1.3 NMI .......................................................... ............................................................. 5-6
5.3.2 External Interrupt Pin ................................................................................................5-6
5.3.3 Multiplexed Interrupt Sources ..... ................. ...................... ................. ................. .....5-7
5.3.4 End-of-PTS Interrupts ...............................................................................................5-9
5.4 INTERRUPT LATENCY................................................................................................. 5-9
5.4.1 Situations that Increase Interrupt Latency ................................................................ 5-9
5.4.2 Calculating Latency .................................................................................................5-10
5.4.2.1 Standard Interrupt Latency ................... .. ............................................................5-10
5.4.2.2 PTS Interrupt Laten cy ........................................................................................5-11
5.5 PROGRAMMING THE INTERRUPTS......................................................................... 5-12
5.5.1 Modifying Interrupt Priorities ....................................... ....................................... .....5-18
5.5.2 Determining the Source of an I nterrupt ................................................................... 5-20
5.6 INITIALIZING THE PTS CONTROL BLOCKS ............................................................. 5-24
5.6.1 Specifying the PTS Count .......................................................................................5-25
5.6.2 Selecting the PTS Mode .........................................................................................5-27
5.6.3 Single Transfer Mode ..............................................................................................5-27
5.6.4 Block Transfer Mode ...............................................................................................5-30
5.6.5 A/D Scan Mode .......................................................................................................5-32
5.6.5.1 A/D Scan Mode Cycles ......................................................................................5-35
5.6.5.2 A/D Scan Mode Example 1 ................................................................................5-35
5.6.5.3 A/D Scan Mode Example 2 ................................................................................5-37
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8XC196MC, MD, MH USER’S MANUAL
5.6.6 Serial I/O Modes .....................................................................................................5-37
5.6.6.1 Synchronous SIO Transmit Mode Example .......................................................5-43
5.6.6.2 Synchronous SIO Receive Mode Example ........................................................ 5-47
5.6.6.3 Asynchronous SIO Transmit Mode Example .....................................................5-50
5.6.6.4 Asynchronous SIO Receive Mode Example ......................................................5-55
CHAPTER 6
I/O PORTS
6.1 I/O PORTS OVERVIEW ................................................................................................ 6-1
6.2 INPUT-ONLY PORTS 1 (MC, MD ONLY) AND 0.......................................................... 6-2
6.2.1 Standard Input-only Port Operation ..........................................................................6-3
6.2.2 Standard Input-only Port Considerations ..................................................................6-4
6.3 BIDIRECTIONAL PORTS 1 (MH ONLY), 2, 5, AND 7 (MD ONLY)............................... 6-4
6.3.1 Bidirectional Port Operation ......................................................................................6-6
6.3.2 Bidirectional Port Pin Configurations ............ .......... ........ ....... ....... ....... .......... ....... ..... 6-9
6.3.3 Bidirectional Port Pin Configuration Example .........................................................6-11
6.3.4 Bidirectional Port Considerations ............................................................................6-12
6.4 BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)...................................... 6-14
6.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation .....................................6- 15
6.4.2 Using Ports 3 and 4 as I/O . .. ................. ............ ................. ............... ............ ..........6-16
6.4.3 Design Considerations for Ports 3 and 4 .......... .......... ....... .......... ..... ....... .......... .....6-16
6.5 STANDARD OUTPUT-ONLY PORT 6 ....................................................................... 6-16
6.5.1 Output-only Port Operation .....................................................................................6-17
6.5.2 Configuring Output-only Port Pins ..........................................................................6-17
CHAPTER 7
SERIAL I/O (SIO) PORT
7.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW................................................... 7-1
7.2 SERIAL I/O PORT SIGNALS AND REGISTERS.......................................................... 7-2
7.3 SERIAL PORT MODES................................................................................................. 7-4
7.3.1 Synchronous Modes (Modes 0 and 4) ...................................................................... 7-5
7.3.1.1 Mode 0 . ................................................................................................................7-5
7.3.1.2 Mode 4 . ................................................................................................................7-6
7.3.2 Asynchronous Modes (Modes 1, 2, and 3) ............................................................... 7-7
7.3.2.1 Mode 1 . ................................................................................................................7-7
7.3.2.2 Mode 2 . ................................................................................................................7-8
7.3.2.3 Mode 3 . ................................................................................................................7-9
7.3.2.4 Mode 2 and 3 Timings ..........................................................................................7-9
7.3.2.5 Multiprocessor Communications ..........................................................................7-9
7.4 PROGRAMMING THE SERIAL PORT........................................................................ 7-10
7.4.1 Configuring the Serial Port Pins ....................................... ................... ................. ...7-10
7.4.2 Programming the Control Register ..........................................................................7-10
7.4.3 Programming the Baud Rate and Clock Source .....................................................7-12
7.4.4 Enabling the Serial Port Interrupts .......................................... ............ ................. ... 7- 14
vi
CONTENTS
7.4.5 Determining Serial Port Status ................................................................................7-15
CHAPTER 8
FREQUENCY GENERATOR
8.1 FUNCTIONAL OVERVIEW............................................................................................ 8-1
8.2 PROGRAMMING THE FREQUENCY GENERATOR ................................................... 8-3
8.2.1 Configuring the Output ..............................................................................................8-3
8.2.2 Programming the Frequency ....................................................................................8-3
8.2.3 Determining the Current Value of the Down-counter ................................................ 8-4
8.3 APPLICATION EXAMPLE............................................................................................. 8-4
CHAPTER 9
WAVEFORM GENERATOR
9.1 WAVEFORM GENERATOR FUNCTIONAL OVERVIEW.............................................. 9-1
9.2 WAVEFORM GENERATOR SIGNALS AND REGISTERS........................................... 9-3
9.3 WAVEFORM GENERATOR OPERATION.................................................................... 9-4
9.3.1 Timebase Generator .................................................................................................9-4
9.3.2 Phase Driver Channels .............................................................................................9-5
9.3.3 Control and Protection Circuitry ................... .......... ............ ............... ....... ............ ..... 9-5
9.3.4 Register Buffering and Synchronization .................................................................... 9-6
9.3.5 Operating Modes ......................................................................................................9-7
9.3.5.1 Center-aligned Modes ..........................................................................................9-9
9.3.5.2 Edge-Aligned Modes ..........................................................................................9-10
9.4 PROGRAMMING THE WAVEFORM GENERATOR................................................... 9-12
9.4.1 Configuring the Outputs ..........................................................................................9-12
9.4.2 Controlling the Protection Circuitry and EXTINT Interrupt Generation .................... 9 -15
9.4.3 Specifying the Carrier Period and Duty Cycle ................................... ......................9-16
9.4.4 Specifying the Operating Mode and Dead Time and Starting the Counter .............9-17
9.5 DETERMINING THE WAVEFORM GENERATOR’S STATUS................................... 9-19
9.6 ENABLING THE WAVEFORM GENERATOR INTERRUPTS..................................... 9-19
9.7 DESIGN CONSIDERATIONS...................................................................................... 9-20
9.7.1 Dead Time and Duty Cycle .....................................................................................9-20
9.7.2 EXTINT Interrupts and Protection Circuitry ........................ ................. ............... ..... 9-21
9.8 PROGRAMMING EXAMPLE....................................................................................... 9-21
CHAPTER 10
PULSE-WIDTH MODULATOR
10.1 PWM FUNCTIONAL OVERVIEW................................................................................ 10-1
10.2 PWM SIGNALS AND REGISTERS............................................................................. 10-2
10.3 PWM OPERATION...................................................................................................... 10-3
10.4 PROGRAMMING THE FREQUENCY AND PERIOD.................................................. 10-4
10.5 PROGRAMMING THE DUTY CYCLE......................................................................... 10-6
10.5.1 Sample Calculations ...............................................................................................10-7
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8XC196MC, MD, MH USER’S MANUAL
10.5.2 Reading the Current Value of the Down-counter ....................................................10-7
10.5.3 Enabling the PWM Outputs .......................... ........................................................ ... 1 0-8
10.5.4 Generating Analog Outputs ..................................................................................10-10
CHAPTER 11
EVENT PROCESSOR ARRAY (EPA)
11.1 EPA FUNCTIONAL OVERVIEW ................................................................................. 11-1
11.2 EPA AND TIMER/COUNTER SIGNALS AND REGI STERS ....................................... 11-2
11.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 11-5
11.3.1 Cascade Mode (Timer 2 Only) ............................... ................................................. 11-7
11.3.2 Quadrature Clocking Modes ...................................................................................11-7
11.4 EPA CHANNEL FUNCTIONAL OVERVIEW............................................................... 11-9
11.4.1 Operating in Capture Mode ...................................................................................11-10
11.4.1.1 EPA Overruns ..................................................................................................11-12
11.4.1.2 Preventing EPA Overruns ................................................................................11-13
11.4.2 Operating in Compare Mode .................................................................................11-13
11.4.2.1 Generating a Low-speed PWM Output ............................................................11-13
11.4.2.2 Generating the Highest-speed PWM Output ....................................................11-14
11.5 PROGRAMMING THE EPA AND TIMER/COUNTERS............................................. 11-15
11.5.1 Configuring the EPA and Timer/Counter Signals ..................................................11-15
11.5.2 Programming the Timers .......................................................................................11-15
11.5.3 Programming the Capture/Compare Channels .....................................................11-18
11.5.4 Programming the Compare-only Channels ...........................................................11-22
11.6 ENABLING THE EPA INTERRUPTS........................................................................ 11-23
11.7 DETERMINING EVENT STATUS.............................................................................. 11-24
CHAPTER 12
ANALOG-TO-DIGITAL (A/D) CONVERTER
12.1 A/D CONVERTER FUNCTIONAL OVERVIEW........................................................... 12-1
12.2 A/D CONVERTER SIGNALS AND REGISTERS ........................................................ 12-2
12.3 A/D CONVERTER OPERATION................................................................................. 12-3
12.4 PROGRAMMING THE A/D CONVERTER. ................................................................. 12-4
12.4.1 Programming the A/D Test Register .......................................................................12-5
12.4.2 Programming the A/D Result Register (for Threshold Detection Only) ...................12-5
12.4.3 Programming the A/D Time Register ......................................................................12-6
12.4.4 Programming the A/D Command Register ..............................................................12-7
12.4.5 Enablin g the A/D Interr upt .. .. ....... ..... ..... ....... ..... ..... ........ .... ..... ........ .... ..... ........ .... ... 12-8
12.5 DETERMINING A/D STATUS AND CONVERSION RESULTS.................................. 12-9
12.6 DESIGN CONSIDERATIONS.................................................................................... 12-10
12.6.1 Designing External Interface Circuitry . ............................... ................................... 12-10
12.6.1.1 Minimizing the Effect of High Input Source Resistance ....................................12-11
12.6.1.2 Suggested A/D Input Circuit .............................................................................12-12
12.6.1.3 Analog Ground and Reference Voltages .........................................................12-12
viii
CONTENTS
12.6.1.4 Using Mixed Analog and Digital Inputs ............................................................12-13
12.6.2 Understanding A/D Conversion Errors ..................................................................12-13
CHAPTER 13
MINIMUM HARDWARE CONSIDERATIONS
13.1 MINIMUM CONNECTIONS ......................................................................................... 13-1
13.1.1 Unused Inputs .........................................................................................................13-2
13.1.2 I/O Port Pin Connections ........................................................................................13-2
13.2 APPLYING AND REMOVING POWER ....................................................................... 13-4
13.3 NOISE PROTECTION TIPS........................................................................................ 13-4
13.4 THE ON-CHIP OSCILLATOR CIRCUITRY ................................................................. 13-5
13.5 USING AN EXTERNAL CLOCK SOURCE.................................................................. 13-7
13.6 RESETTING THE DEVICE.......................................................................................... 13-8
13.6.1 Generating an External Reset ...............................................................................13-10
13.6.2 Issuing the Reset (RST) Instruction ......................................................................13-12
13.6.3 Issuing an Illegal IDLPD Key Operand .................................................................13-12
13.6.4 Generating Wait States . ....... ............ .......... ............ ............ ............... ....... ............ . 13-12
13.6.5 Enabling the Watchdog Timer ...............................................................................13-12
CHAPTER 14
SPECIAL OPERATING MODES
14.1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS..................................... 14-1
14.2 REDUCING POWER CONSUMPTION....................................................................... 14-3
14.3 IDLE MODE ............................................................................................................... .. 14-4
14.4 POWERDOWN MODE ................................................................................................ 14-5
14.4.1 Enabling and Disabling Powerdown Mode ..............................................................14-5
14.4.2 Entering Powerdown Mode .....................................................................................14-6
14.4.3 Exiting Powerdown Mode .......................................................................................14-6
14.4.3.1 Driving the V
Pin Low ......................................................................................14-6
pp
14.4.3.2 Generating a Hardware Reset ...........................................................................14-6
14.4.3.3 Asserting the External Interrupt Signal ...............................................................14-7
14.4.3.4 Selecting R
and C1 ...........................................................................................14-8
1
14.5 ONCE MODE............................................................................................................. 14-10
14.6 RESERVED TEST MODES....................................................................................... 14-11
CHAPTER 15
INTERFACING WITH EXTERNAL MEMORY
15.1 EXTERNAL MEMORY INTERFACE SIGNALS AND REGISTERS............................ 15-1
15.2 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES ......... 15-5
15.3 BUS WIDTH AND MULTIPLEXING........................................................................... 15-10
15.3.1 Timing Requirements for BUSWIDTH ...................................................................15-13
15.3.2 16-bit Bus Timings ...................... ................. ...................... ................. .................. 15-14
15.3.3 8-bit Bus Timings ..................................................................................................15-16
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8XC196MC, MD, MH USER’S MANUAL
15.4 WAIT STATES (READY CONTROL)......................................................................... 15-17
15.5 BUS-CONTROL MODES........................................................................................... 15-21
15.5.1 Standard Bus-control Mode ..................................................................................15-22
15.5.2 Write Strobe Mode ... ........................................................................... .................. 15-25
15.5.3 Address Valid Strobe Mode ..................................................................................15-27
15.5.4 Address Valid with Write Strobe Mode ............... ...................................................15-30
15.6 SYSTEM BUS AC TIMING SPECIFICATIONS......................................................... 15-31
15.6.1 Explanation of AC Symbols . .................................................................................15-33
15.6.2 AC Timing Definitions ...........................................................................................15-33
CHAPTER 16
PROGRAMMING THE NONVOLATILE MEMORY
16.1 PROGRAMMING METHODS...................................................................................... 16-1
16.2 OTPROM MEMORY MAP ........................................................................................... 16-2
16.3 SECURITY FEATURES............................................................................................... 16-3
16.3.1 Controlling Access to Internal Memory ...................................................................16-3
16.3.1.1 Controlling Access to the OTPROM During Normal Operation .... ......................1 6-4
16.3.1.2 Controlling Access to the OTPROM During Programming Modes .....................16-4
16.3.2 Controlling Fetches from External Memory .............................................................16-6
16.4 PROGRAMMING PULSE WIDTH ............................................................................... 16-8
16.5 MODIFIED QUICK-PULSE ALGORITHM.................................................................... 16-9
16.6 PROGRAMMING MODE PINS.................................................................................. 16-11
16.7 ENTERING PROGRAMMING MODES..................................................................... 16-13
16.7.1 Selecting the Programming Mode .........................................................................16-13
16.7.2 Power-up and Power-down Sequences ................................................................16-14
16.7.2.1 Power-up Sequence .........................................................................................16-14
16.7.2.2 Power-down Sequence ....................................................................................16-14
16.8 SLAVE PROGRAMMING MODE............................................................................... 16-15
16.8.1 Reading the Signature Word and Programming Voltages ....................................16-15
16.8.2 Slave Programming Circuit and Memory Map ......................................................16-16
16.8.3 Operating Environment .........................................................................................16-17
16.8.4 Slave Programming Routines . ..............................................................................16-19
16.8.5 Timing Mnemonics ................................................................................................16-24
16.9 AUTO PROGRAMMING MODE ................................................................................ 16-25
16.9.1 Auto Programming Circuit and Memory Map ........................................................16-25
16.9.2 Operating Environment .........................................................................................16-27
16.9.3 Auto Programming Routine ...................................................................................16-27
16.9.4 Auto Programming Procedure ..............................................................................16-29
16.9.5 ROM-dump Mode .................................................................................................16-30
16.10 PCCB AND UPROM PROGRAMMING (8XC196MH ONLY).................................... 16-30
16.11 RUN-TIME PROGRAMMING .................................................................................... 16-32
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CONTENTS
APPENDIX A
INSTRUCTION SET REFERENCE
APPENDIX B
SIGNAL DESCRIPTIONS
B.1 SIGNAL NAME CHANGES. .......................................................................................... B-1
B.2 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. B-1
B.3 SIGNAL DESCRIPTIONS........................................................................................... B-12
B.4 DEFAULT CONDITIONS............................................................................................ B-22
APPENDIX C
REGISTERS
GLOSSARY
INDEX
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8XC196MC, MD, MH USER’S MANUAL
FIGURES
Figure Page
2-1 8XC196M
2-2 Block Diagram of the Core...........................................................................................2-3
2-3 Clock Circuitry . .............................................................................................................2-7
2-4 Internal Clock Phases ..................................................................................................2-8
4-1 Regi ster File Memory Map ............. .......................................... ....................................4-9
4-2 Windowing..................................................................................................................4-12
4-3 Window Selection (WSR) Register.............................................................................4-13
5-1 Flow Diagram for PTS and Standard Interrupts ...........................................................5-2
5-2 Waveform Generator Protection Circuitry.................. .......... ....... ........ ....... ....... ....... ..... 5-7
5-3 Flow Diagram for t he OVRTM Interrupt........................................................................5-8
5-4 Standard Interrupt Response Time.................................. .......................... ................5-11
5-5 PTS Interrupt Response Time....................................................................................5-11
5-6 PTS Select (PTSSEL) Register.................................................................................. 5-14
5-7 Interrupt Ma sk (INT_MASK) Register .............. ........................................................... 5-15
5-8 Interrupt Ma sk 1 (INT_MASK1) Register......................................... ...................... ..... 5-16
5-9 Peripheral Interrupt Ma sk (PI_MASK) Register...................................... ................. ... 5-17
5-10 Inter rupt Pending (INT_PEND) Register ....................................................................5-21
5-11 Inter rupt Pending 1 (INT_PEND1) Register ...............................................................5-22
5-12 Peripheral Inter rupt Pending (PI_PEND) Register .....................................................5-23
5-13 PTS Control Blocks ....................................................................................................5-25
5-14 PTS Service ( PTSSRV) Register ...............................................................................5-26
5-15 PTS Mode Selection Bi ts (PTSCON Bits 7:5) ............................................................5-27
5-16 PTS Control Block — Single Transfer Mode..............................................................5-28
5-17 PTS Control Block — Block Transfer Mode...............................................................5-31
5-18 PTS Control Block – A/D Scan Mode.........................................................................5-33
5-19 PTS Control Block 1 – Serial I/O Mode......................................................................5-38
5-20 PTS Control Block 2 – Serial I/O Mode......................................................................5-41
5-21 Synchronous SIO Transmit Mode Timing...................................................................5-43
5-22 Synchronous SIO Transmit Mode — End-of-PTS Interrupt Routine Flowchart..........5-46
5-23 Synchronous SIO Receive Timing..............................................................................5-47
5-24 Synchronous SIO Receive Mode — End-of-PTS Interr upt Routine Flowchart...........5-50
5-25 Asynchronous SIO Transmit Timing...........................................................................5-51
5-26 Asynchronous SIO Transmit Mode — End-of-PTS I nterrupt Routine Flowchart ........5-54
5-27 Asynchronous SIO Receive Timing............................................................................5-55
5-28 Asynchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart.........5-58
6-1 Standard Input-only Port Structure...............................................................................6-3
6-2 Bidirectional Port Structure...........................................................................................6-8
6-3 Address/Data Bus (Ports 3 and 4) Structure..............................................................6-15
6-4 Output-only Port .........................................................................................................6-18
6-5 Port 6 Output Configuration (WG_OUTPUT) Register... ............................................ 6-18
7-1 SIO Block Diagram . ......................................................................................................7-1
7-2 Typical Shift Register Circuit for Mode 0.......................................................... ............ 7-5
7-3 Mode 0 Timing.......................................... ....... ..... ..... .......... .. .......... ..... .. .......... ..... .. .....7-6
7-4 Serial Port Frames for Mode 1 ............................................ .........................................7-8
x
Block Diagram ................................................................... ........................2-3
xii
CONTENTS
FIGURES
Figure Page
7-5 Serial Port Frames in Mode 2 and 3.............................................................................7-9
7-6 Serial Port Control (SP 7-7 Serial Port 7-8 Serial Port Status
8-1 Frequency Generator Block Diagram...........................................................................8-1
8-2 Frequency (FREQ_GEN) Register...............................................................................8-3
8-3 Frequency Generator Count (FREQ_CNT) Register....................................................8-4
8-4 Infrared Remote Control Ap plication Block Diagram.................................................... 8-5
8-5 Data Encoding Example...............................................................................................8-5
9-1 Waveform Generator Block Diagram............................................................................9-2
9-2 Dead-time Generator Circuitry........ ........ ....... ..... ....... ..... ....... ..... ........ .... ........ ....... ..... .. 9-5
9-3 Protection Circuit ry ............. ............ .......... ............ ............... ............ ....... ............... ....... 9-6
9-4 Center-aligned Modes — Counter Operation............................................................... 9-9
9-5 Center-aligned Modes — Output Operation...............................................................9-10
9-6 Edge-aligned Modes — Counter Operation...............................................................9-11
9-7 Edge-aligned Modes — Output Operation .................................................................9-11
9-8 WG Output Configuration (WG_OU TPUT) Register ..................................................9-13
9-9 Waveform Generator Protection (WG_PROTECT) Register......................................9-15
9-10 Waveform Generator Reload (WG_RELOAD) Register.............................................9-16
9-11 Phase Compare (WG _CO MP
9-12 Waveform Generator Control (WG_CONTROL) Register. ...................................... ...9 -18
9-13 Waveform Generator Counter (WG_COUNTER) Register ........................................9-19
9-14 Effect of Dead Time on Duty Cycle............................................................................9-20
10-1 PWM Block Diagram ..................................................................................................10-2
10-2 PWM Output Wa veforms......................................................................................... ...1 0-4
10-3 PWM P eriod (PWM_PERIOD) R egister. ................................................ .................... 10-6
10-4 PWM Control (PWM
10-5 PWM C ount (PWM_COUNT) Register.......................................................................10-8
10-6 Waveform Generator Output Configuration (WG_OUTPUT) Register.......................10-9
10-7 D/A Buffer Block Diagram.........................................................................................10-10
10-8 PWM to Analog Conversion Circuitry.......................................................................10-10
11-1 EPA Block Diagram....................................................................................................11-2
11-2 EPA Timer/Counters ..................................................................................................11-6
11-3 Quadrature Mode Interface........................................................................................11-8
11-4 Quadrature Mode Timing and Count..........................................................................11-9
11-5 A Single EPA Capture/Compare Channel................................................................11-10
11-6 EPA Simplifie d Input-capture Structure....................................................................11-11
11-7 Valid EPA Input Events............................................................................................11-11
11-8 Timer 1 Control (T1CONTROL) Register.................................................................11-16
11-9 Timer 2 Control (T2CONTROL) Register.................................................................11-17
11-10 EPA Control (EPA 11-11 EPA Compare Control (COMP
12-1 A/D C onverter Block Diagram . .............................................. ..................................... 1 2-1
12-2 A/D Test (AD_TEST) Register. ................................................................................ ...1 2-5
x
Baud Rate (SPx_BAUD) Register.........................................................7-12
x
_CON) Register....................................................................7-10
(SPx_STATUS) Register...............................................................7-15
x
) Register............................................... ....................9-17
x
_CONTROL) Register..............................................................10-7
x
_CON) Registers .......................................................................11-19
x
_CON) Registers....................................................11-22
xiii
8XC196MC, MD, MH USER’S MANUAL
FIGURES
Figure Page
12-3 A/D R esult (AD_RESULT) Register — Write Format............... ..... .. ..... ..... ..... .. ..... .....12-6
12-4 A/D Time (A D_TIME) Register ....... ...................... ...................... ...................... .......... 1 2-7
12-5 A/D C ommand (AD_COMMAND) Register ................................................................12-8
12-6 A/D R esult (AD_RESULT) Register — Read Format.................................................1 2-9
12-7 Idealized A/D Sampling Circuitry..............................................................................12-10
12-8 Suggested A/D Input Circuit.....................................................................................12-12
12-9 Ideal A/D Conversion Characteristic.........................................................................12-15
12-10 Actual and Ideal A/D Conversion Characteristics.....................................................12-16
12-11 T erminal-based A/D Conversion Characteristic.......................................................12-18
13-1 Minimum Hardware Connections ...............................................................................13-3
13-2 Power and Return Connections .................................................................................13-4
13-3 On-chip Oscillator Circuit............................................................................................13-5
13-4 External Crystal Connections.....................................................................................13-6
13-5 External Clock Connections .......................................................................................13-7
13-6 External Clock Drive Waveforms................................................................................13-7
13-7 Reset Timing Sequence.............................................................................................13-8
13-8 General Configuration Register (GEN_CON)............................................................13-9
13-9 Internal Reset Circuitry................... ....................................... ................. ..................13-10
13-10 Minimum Reset Circuit .............................................................................................13-11
13-11 E xample of a System Reset Circuit..........................................................................13-11
14-1 Clock Control During Power-saving Modes ................................................................14-4
14-2 Power-up and Power-down Sequence When Using an External Interrupt.................14-7
14-3 External RC Circuit.....................................................................................................14-8
14-4 Typical Voltage on the V
15-1 Chip Configuration 0 (CCR0) Register.......................................................................15-7
15-2 Chip Configuration 1 (CCR1) Register.......................................................................15-9
15-3 Multiplexing and Bus Width Options.........................................................................15-11
15-4 BUSWID TH Timing Diagram (8XC196MC, MD) ......................................................15-12
15-5 BUSWID TH Timing Diagram (8XC196MH)..............................................................15-12
15-6 Timings for 16-bit Buses...........................................................................................15-15
15-7 Timings for 8-bit Buses.............................................................................................15-17
15-8 READY Timing Diagram — One Wait State (8XC196MC, MD)...............................15-19
15-9 READY Timing Diagram — One Wait State (8XC196MH).......................................15-20
15-10 Standard Bus Control...............................................................................................15-22
15-11 Decoding WRL# and WRH#.....................................................................................15-22
15-12 8-bit System with Flash and RAM ............................................................................15-23
15-13 16-bit S yst em with Dynamic Bus Width....................................................................15-24
15-14 Wr ite Strobe Mode ...................................................................................................15-25
15-15 16-bit System with Writes to Byte-wide RAMs .........................................................15-26
15-16 Address Valid Strobe Mode ......................................................................................15-27
15-17 Comparison of ALE and ADV# Bus Cycles ..............................................................15-27
15-18 8-bit System with Flash ............................................................................................15-28
15-19 16-bit System with EPROM...................................................................................... 15-29
15-20 Timings of Address Valid with Write Strobe Mode...................................................15-30
Pin While Exiting Powerdown.........................................14-9
PP
xiv
CONTENTS
FIGURES
Figure Page
15-21 16-bit S yst em with RAM ... ..... .. ..... .. ..... ... ..... .. ..... .. ..... ..... ... .... ... .. ..... ..... .. ..... ... ..... .. ...15-31
15-22 System Bus Timing ..................................................................................................15-32
16-1 U nerasable PROM (USFR) Register ... .......................................................................16-7
16-2 Programmi n g Pulse Width (PPW) Re gister................................................................16-8
16-3 Modifi ed Quick-pulse Algorithm .... ............................................................................16-10
16-4 Pin Functions in Programming Modes......................................................................16-11
16-5 Slave Programming Circuit.......................................................................................16-16
16-6 Chip Configuration Registers (CCRs).......................................................................16-18
16-7 Address/Command Decoding Routine.....................................................................16-20
16-8 Program Word R outine .............................................................................................16-21
16-9 Program Word Wa veform . ........................................................................................16-22
16-10 Dump Word Routine.................................................................................................16-23
16-11 Dump Word Waveform.............................................................................................16-24
16-12 Auto Programming Circuit ........................................................................................ 16-26
16-13 Auto Programming Routine......................................................................................16-28
16-14 PCCB and UPROM Programming Circuit ................................................................16-31
16-15 Ru n-time Progr amming Code Example....................................................................16-33
B-1 8XC196MC 64-lead Shrink DIP (SDIP) Package........................................................B-3
B-2 8XC196MC 84-lead PLCC Package...........................................................................B-4
B-3 8XC196MC 80-lead Shrink EIAJ/QFP Package..........................................................B-5
B-4 8XC196MD 84-lead PLCC Package...........................................................................B-7
B-5 8XC196MD 80-lead Shrink EIAJ/QFP Package..........................................................B-8
B-6 8XC196MH 64-lead Shrink DIP (SDIP) Package......................................................B-10
B-7 8XC196MH 84-lead PLCC Package. ........................................................................B-11
B-8 8XC196MH 80-lead Shrink EIAJ/QFP Package........................................................B-12
xv
8XC196MC, MD, MH USER’S MANUAL
TABLES
Table Page
1-1 Handbooks and Product Information..................................... ..... ..... ....... ..... ..... ..... .......1-6
1-2 Application Notes, Application Briefs, and Article Repr ints .......................................... 1-6
1-3 MCS 1-4 MCS 1-5 MCS
2-1 Features of the 8XC196Mx Product Family..................................................................2-2
2-2 State Times at Various Frequencies............................................................................2-8
3-1 Operand Type Definitions............................................................................................. 3-1
3-2 Equivalent Operand Types for Assembly and C Programming Languages.................3-2
3-3 Definition of Temporary Registers................................................................................3-6
4-1 Memory Map .. .............................................................................................................4-2
4-2 Special-purpose Memory Addresses............................................................................4-3
4-3 Memory-mapped SFRs ................................................................................................4-5
4-4 Peripheral SFRs — 8XC196MC...................................................................................4-6
4-5 Peripheral SFRs — 8XC196MD...................................................................................4-7
4-6 Peripheral SFRs — 8XC196MH...................................................................................4-8
4-7 Register File Memory Addresses ..............................................................................4-10
4-8 CPU SFRs..................................................................................................................4-11
4-9 Selecting a Window of Peripheral SFRs.....................................................................4-13
4-10 Selecting a Window of the Upper Register File..........................................................4-14
4-11 Windows.....................................................................................................................4-15
4-12 Windowed Base Addresses .......................................................................................4-15
5-1 Interrupt Signals ...........................................................................................................5-3
5-2 Interrupt and PTS Control and Status Registers.............................................. ............ 5-3
5-3 Interrupt S ources, Vectors, and Prioriti es.................. ............ ............... ....... ............ ..... 5-5
5-4 Execution Times for PTS Cycles................................................................................5-12
5-5 Single Transfer Mode PTSCB....................................................................................5-30
5-6 Block Transfer Mode PTSCB.....................................................................................5-30
5-7 A/D Scan Mode Command/Data Table......................................................................5-34
5-8 Command/Data Table (Example 1)............................................................................5-36
5-9 A/D Scan Mode PTSCB (Example 1).........................................................................5-36
5-10 Command/Data Table (Example 2)............................................................................5-37
5-11 A/D Scan Mode PTSCB (Example 2).........................................................................5-37
5-13 SSIO Transmit Mode PTSCBs...................................................................................5-45
5-14 SSIO Receive Mode PTSCBs. ...................................................................................5-48
5-15 ASIO Transmit Mode PTSCBs...................................................................................5-52
5-16 ASIO Receive Mode PTSCBs. ...................................................................................5-56
6-1 Device I/O Ports ............... ....... ..... ....... ..... ....... ..... ........ ....... ..... ....... ..... ....... ..... ....... .....6-1
6-2 Standard Input-only Port Pins ......................................................................................6-2
6-3 Input-only Port Registers..............................................................................................6-3
6-4 Bidirectional Port Pins ........................................................... ..... ..... ..... .. ..... ..... ..... .......6-5
6-5 Bidirectional Port Control and Status Registers ..................................... ......................6-6
6-6 Logic Table for Bidire ctional Ports in I/O Mode ............................................................6-9
6-7 Logic Table for Bidire ctional Ports in Special-function M od e .......................................6-9
®
96 Microcontroller Datasheets (Commercial/Express)......................................1-7
®
96 Microcontroller Datasheets (Automotive).....................................................1-7
®
96 Microcontroller Quick References................................................................1-8
xvi
CONTENTS
TABLES
Table Page
6-8 Control Register V alues for Each Configuration .........................................................6-11
6-9 Port Configuration Example .......................................................................................6-11
6-10 Port Pin States After Reset and After Example Code Execution................................ 6-12
6-11 Ports 3 and 4 Pins......................................................................................................6-14
6-12 Ports 3 and 4 Control and Status Registers...............................................................6-14
6-13 L ogic T able for Ports 3 and 4 as Open-drain I/O................................................... ..... 6 -16
6-14 Standard Output-only Port Pins..................................................................................6-17
6-15 Output-only Port Control Register ................................................... ............ ............ ... 6-17
7-1 Serial Port Signals................................................................. ....................................... 7-2
7-2 Serial Port Control and Status R egisters.............. ........................................................7-2
7-3 SP
8-1 Frequency Generator Signal ........................................................................................8-2
8-2 Frequency Generator Control and Status Registers...................................................8-2
9-1 Waveform Generator Signals .......................................................................................9-3
9-2 Waveform Generator Control and Status Registers....................................................9-3
9-3 Operation in Center-aligned and Edge-aligned Modes ................................................ 9-8
9-4 Register Updates..........................................................................................................9-8
9-5 Output Configuration .................................................................................................. 9-12
10-1 PWM Signals..............................................................................................................10-2
10-2 PWM C ontrol and Status Registers............................................................................1 0-3
10-3 PWM Output Fre quencies (F
10-4 PWM Output Alternat e Functions...............................................................................10-8
11-1 EPA Channels............................................................................................................1 1-1
11-2 EPA and Timer/Counter Signals.................................................................................11-2
11-3 EPA Control and Status Registers .............................................................................11-3
11-4 Quadrature Mode Truth Table....................................................................................11-8
11-5 Action Taken When a Valid Ed ge Oc curs ................................................................11-12
11-6 E xample EPA Control Register Sett ings for Channels 1, 3, or 5..............................11-18
12-1 A/D C onverter Pins................................... ................. ...................... ...................... ..... 1 2-2
12-2 A/D C ontrol and Status Registers.................. ................. ...................... ................... ... 12-2
13-1 Minim um Required Signals.........................................................................................13-1
13-2 I/O Port Configuration Guide......................................................................................13-2
13-3 Selecting the Watchdog Reset Interval (8XC196MH only)......................................13-13
14-1 Operating Mode Control Signals ................................................................................14-1
14-2 Operati ng Mode Control and Status Registers...........................................................1 4-2
15-1 External Memory Interface Signals.............................................................................15-1
15-2 External Memory Interface Registers .........................................................................15-4
15-3 Register Settings for Configuring External Memory Interface Signals........................15-5
15-4 BUSWID TH Signal Timing Definitions. .....................................................................15-13
15-5 READY Signal Timing Definitions.............................................................................15-20
15-6 B us-control Modes ...................................................................................................15-21
15-7 AC Timing Symbol Definitions..................................................................................15-33
15-8 External Memory Systems Must Meet These Specifications....................................15-33
15-9 Microcontrol ler M eets These Specifications .............................................................15-34
x
_BAUD Values When Using XTAL1 at 16 MHz...................................................7-14
)............. ........................... ...................... .................10-5
PWM
xvii
8XC196MC, MD, MH USER’S MANUAL
TABLES
Table Page
16-1 87C196M
16-2 Memory Protection for Normal Operating Mode.........................................................16-4
16-3 Memory Protection Options for Programming Modes ................................................16-5
16-4 UPROM Programming Values and Locations for Slave Mode...................................16-7
16-5 Example PPW_VALUE Calculations..........................................................................16-9
16-6 Pin Descriptions .......................................................................................................16-11
16-7 PMODE Values ........................................................................................................16-13
16-8 Device Signature Word and Programming Voltages................................................16-16
16-9 Slave Programming Mode Memory Map..................................................................16-17
16-10 Timing Mnemonics...................................................................................................16-24
16-11 8XC196MC/MD Auto Programming Memory Map . .................................................16-27
16-12 8XC196MH Auto Programming Memory Map.........................................................16-27
16-13 PCCB and UPROM Programming Values...............................................................16-32
A-1 Opcode Map (Left Half)......................................................... ................. ..................... A-2
A-1 Opcode Map (Right Half)................ ......................................................................... .... A-3
A-2 Processor Status Word (PSW) Flags.......................................................................... A-4
A-3 Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions......... A-5
A-4 PSW Flag Setting Symbols .........................................................................................A-5
A-5 Operand Variables ......................................................................................................A-6
A-6 Instructio n Set ... ........ .... ..... ........ .... ..... ........ .... ..... ........ ....... .. ........ ....... .. ........ ....... .. .... A-7
A-7 Instructio n Opcodes .................................................................................................. A-41
A-8 Instruction Lengths and Hexadecimal Opcodes........................................................A-47
A-9 Instruction Executio n Times (in State Times)............................................................ A-52
B-1 Signal Name Changes ................................................................................................ B-1
B-2 8XC196MC Signals Arranged by Functional Categories............................................. B-2
B-3 8XC196MD Signals Arranged by Functional Categories............................................. B-6
B-4 8XC196MH Signals Arranged by Functional Categories............................................. B-9
B-5 Description of Columns of Table B-6......................................................................... B-13
B-6 Signal Descriptions....................................................................................................B-13
B-7 Definition of Status Symbols .....................................................................................B-23
B-8 8XC196MC and MD Default Signal Conditions.........................................................B-23
B-9 8XC196MH Default Signal Conditions.......................................................................B-25
C-1 Modules and Related Registers..................................................................................C-1
C-2 Register Name, Address, and Reset Status................................................................C-2
C-3 COMP C-4 EPA C-5 EPA C-6 P C-7 P
C-8 Special-function Signals for Ports 1, 2, 5, 6............... ..... ..... .. ........ ..... .... ..... ..... ..... .... C-32
C-9 P C-10 P
C-11 Output Configurati on .................................................................................................C-65
C-12 WSR Settings and Direct Addresses for Windowable SFRs.....................................C-68
x x
x x
x
OTPROM Memory Map ...................... ....................................................16-3
x
_TIME Addresses and Reset Values............................................................C-17
x
_CON Addresses and Reset Values................................................................C-20
x
_TIME Addresses and Reset Values................................................................C-21
_DIR Addresses and Reset Values.......................................................................C-30
_MODE Addresses and Reset Values..................................................................C-31
_PIN Addresses and Reset Values.......................................................................C-33
_REG Addresses and Reset Values.....................................................................C-34
xviii
Guide to This Manual
1
CHAPT ER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC1 96MC, 8XC196M D, and 8XC196M H embedded microcontrol­lers. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you com­plete your design.

1.1 MANUAL CONTENTS

This manual contai ns several chapters and appen dixes, a glossary, and an index. Thi s chapter, Chapter 1, provides an ov e rview of the manua l. Thi s section su m mariz es the conte nts of the re­maining chapters and appendixes. The remainder of this chapter describes notational conventions and terminology used throughout the manual, provides refere nc es to re late d doc ument ation, de­scribes custome r support services, and explains how to access information and assi stance .
Chapter 2 — Architectural Overvi ew — provides an over view of the device hardware. It de­scribes the core, internal timing, int ernal periphera ls, and special operati ng modes.
Chapter 3 — Programming Considerations — provides an overview of the instruction set, de­scribes general standards a nd conventions, and defines the ope rand types and addres sing mode s supported by the MCS tion set, see Appendix A.)
®
96 microcontroller family . (For additional information about the instruc-
Chapter 4 — Me m ory Par titions — describe s the a d dressa ble memory spa ce of the devi ce. It describes the mem ory partitions and explains how to use win dows to increa se the amount of memory that can be accessed with register-direct instructions.
Chapter 5 — Standard and PTS Interrupts — describes the interrupt control circuitry , priority scheme, and timing for standard and perip heral transaction server (PTS) inter rupts. It also ex­plains interrupt programming and control.
Chapter 6 — I/O Ports — describes the input/out put ports and explains how to configure the ports for input, output, or special functions.
Chapter 7 — Serial I/O (SIO) Port — describes the 8XC196M H ’s asynchronous/synchronous serial I/O (SIO) port and explains how to program it.
Chapter 8 — Frequency Generator — describes the 8XC196MD’s frequency generator and ex­plains how to configure it. For additional information and application examples, consult AP-483, Application Examples Usi ng the 8XC196MC / MD Mic rocontroller (order number 272282).
1-1
8XC196MC, MD, MH USER’S MANUAL
Chapter 9 — Waveform Generator — describes the waveform gene rator and expl ains h ow to configure it. For additional information and application examples, consult AP-483, Application Examples Using the 8XC196MC/MD Microcontroller (order number 272282).
Chapter 10 — Pulse-wi dth Modulat or — provides a funct ional overview of the pulse width modulator (PWM) mo dules, describes how to program them, and provides sample circuitry f or converting the PWM outputs to anal o g signals.
Chapter 11 — Event Processor Array (EPA) — describes the eve nt processor array, a tim­er/counter-based, high-speed input/outp ut u nit. It de scri bes t he timer/counters a n d expla ins h ow to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs .
Chapter 12 — Anal og-to-digital (A/D) Converter — provides an overview of the analog-to­digital (A/D) converter and describes how to program the converter, read the conversion results, and interface with external circuitry.
Chapter 13 — Minimum Hardware Considerations — describes options for providing the ba­sic requirements for devi ce operat ion w ithin a system , discuss es other hardware considerati ons, and describes device reset o ptions.
Chapter 14 — Spec ial Operating Modes — provides an overview of the idle, powerdown, and on-circuit emulation (ONCE ) modes and describes how to enter and exit each mode.
Chapter 15 — Interfacing with External Memory — lists the external memory signals and de­scribes the registers tha t control the exte rnal memory interface. It discusses the bus width and memory configurations, the bus-hold protocol, write-control modes, and internal wait states and ready control. Finall y, it provides timing information for the system bus.
Chapter 16 — Programming the Nonvolatile Memory — provides recommended circuits, the corresponding memory maps, and flow diagrams. It also provides procedures for auto program­ming.
Appendix A — Instruction Set Reference — provides reference information for the instruction set. It describes each instruction; defines the processor sta tus word (PSW) flags; shows the rela­tionships between instructions and PSW flags; and lists hexadecimal opcodes, instruction lengths, and execution times. (For additional information about the instruction set, see Chapter 3, “Programming Consideratio ns.”)
Appendix B — Signal Descr iptions — provides referenc e information for the device pins, in­cluding descriptions of the pin functions, reset status of the I/O and control pins, and package pin assignments.
1-2
GUIDE TO THIS MANUAL
Appendix C — Re gisters — provides a compilation of all device special-function registers (SFRs) arranged alphabeti cally by register mnemonic . It also includes tables that list the win­dowed direct addresses for all SFRs in each possible window.
Glossary — define s terms with spec ial me aning used th roughout this manual.
Index — lists key topics with page number references.

1.2 NOTATIONAL CONV ENTI ONS AND TERMINOLOGY

The following notations an d terminol ogy are used throughout this manual. The Glossary defines other terms with special meanings.
# The pound symbol (#) has either of two meanings, depending on the
context. When used wi th a signal name, the symbol means that the signal is active low. When used in an instruction, the symbol prefixes an immediate value in immediate addressing mode.
assert and deassert The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active polarity (low or high) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To assert RD# is to drive it low; to assert ALE is to drive it high; to deassert RD# is to drive it high; to deassert ALE is to drive it low.
clear and set The terms clear and set refer to the value of a bit or the act of giving
it a value. If a bit is c lear, its val ue is “0”; cleari ng a bit gives it a “0” value. If a bit is set, its value is “1”; settin g a bit gives it a “1” value.
instructions Instruction mnem onics are shown in upper case to av oid confusion.
In general, you may use either upper case or lower case when programming. Consult the manual for your assembl er or compiler to determine its specific req uirem ent s.
italics Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible meanings.
Vari able s in regist ers and signal names are commonly represente d by x and y, where x represents the first variable and y represents the second variable . For example, in register P x_MODE.y, x represents the variable that identifies the specific port associated with the register, and y represents the register bit variable (7:0 or 15:0). Vari ables must be replaced with the correct values when configuring or programming regi sters or ident ifyi ng signals.
1-3
8XC196MC, MD, MH USER’S MANUAL
numbers Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are represented by t heir customa ry notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is appended to binary numbers for clarity.)
register bits Bit locations are indexed by 7:0 (or 15:0), where bit 0 is the least-
significant bit and bit 7 (or 15) is the most-significant bit. An individual bit is represented by the register name, followed by a period and the bit number. For example, WSR.7 is bit 7 of the window selection register. In some discuss ions, bit names are used.
register names Register mnemonics are shown in upper case. For example, TIMER2
is the timer 2 register; timer 2 is the timer. A register name containing a lowercase italic character represents more than one register. For example, the x in Px_REG indicate s that the register name re fers to any of the p ort data registers.
reserved bits Certain bits are described a s reserved bits. In illustrat ions, reserved
bits are indicated with a dash (—). These bits are not used in this device, but they may be used in future implementations. To help ensure that a current software design is compatible with future imple­mentations, rese rved bits should be c leared (given a value of “0”) or left in thei r de fault states, unles s ot he rwis e not ed. Do not rel y o n the values of reserved bits; conside r them undefin ed.
signal names Signal names are shown in upper case. When several signals share a
common name, an individual signal is represented by the signal name followed by a number. For example, the EPA signals are named EPA0, EPA1, EPA2, etc. Port pins are represente d by t he p ort ab bre­viation, a period, a nd the pin number (e.g., P1.0, P 1.1); a range of pins is represented by Px.y:z (e.g., P1.4:0 represents five port pins: P1.4, P1.3, P1.2, P1.1, P1.0). A pound symbol (#) appended to a signal name identifies an active-low signal.
1-4
GUIDE TO THIS MANUAL
units of measure The following abbreviations are used to represent units of measure:
A amps, amperes DCV direct current volts
ytes kilobytes
Kb
z kilohertz
kH kΩ kilo-ohms mA milliamps, milliamperes Mbytes megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts
µA microamps, microamperes µF microfarads µs microseconds µW microwatts
X Uppercase X (no italics) represents an unknown value or an
elevant (“don’t care”) state or condition. The value may be either
irr
or hexadecimal, depending on the context. For example,
binary 2XAFH ind
(hex) indicates that bits 11:8 are unknown; 10XXB (binary)
icates that the two least-significant bits are unknown.

1.3 RELATED DOCUMENTS

The tables in this section list additional documents that you may find useful in designing systems
corporating MCS 96 microcontrollers. These are not comprehensive lists, but are a representa-
in tive sample of relevant documents. For a complete list of available printed documents, please or-
the literature catalog (order number 210621). To order documents, please call the Intel
der literature center for your area (telephone numbers are listed on page 1-11).
1-5
8XC196MC, MD, MH USER’S MANUAL

Table 1-1. Handbooks and Product Information

Title and Description Order Number
Intel Embedded Quick Reference Guide Solution s for Embedd ed Appl icat io ns Guide Data on Dema nd Data on Dema nd
Complete set of Intel handbooks on CD-ROM.
Handboo k Set
Complete set of Intel’s product line handbooks. Contains datasheets, application notes, article reprints and other desig n informatio n on microprocessors, periph­erals, embedded controllers, memory components, single-board computers, microcommunications, software development tools, and operating systems.
Automotive Products
Application notes and article reprints on topics including the MCS 51 and MCS 96 microcon trol le r s. Docu men t s in this handb ook discuss hardware and software implementations and present helpful design techniques.
Embedded A pplications
Datasheets, architecture descriptions, and application notes on topics including flash memor y device s, netwo rkin g chips, an d MCS 51 and MCS 96 microc on­trollers. Documents in this handbook discuss hardware and software implementa­tions and present helpful design techniques.
Embedded Microcontrollers
Datasheets and architecture descriptions for Intel’s three industry-standard micro­controllers, the MCS 48, MCS 51, and MCS 96 microcontrollers.
Peripheral Components
Comprehensive information on Intel’s peripheral components, including datasheets, application notes, and technical briefs.
Flas h Memory
A collection of datasheets and application notes devoted to techniques and information to help design semiconductor memory into an application or system.
Packaging
Detailed information on the manufacturing, applications, and attributes of a variety of semiconductor packages.
Development Tools Handbook
Information on third-party hardware and software tools that support Intel’s embedded microcontrollers.
†
Included in handbook set (order num be r 231003)
fact sheet 240952 annual subscription (6 issues; Windows* version)
— ha ndbooks and product overview
†
†
(2 volume set)
†
handbook (2 volume set)
†
†
†
272439 240691
240897
231003
231792
270648
270646
296467
210830
240800
272326
AB-71, AP-125, AP-155, AR-375,
†
Included in
††
Included in
†††
Included in
1-6

Table 1-2. Application Notes, Application Briefs, and Article Reprints

Title Order Number
Using the SIO on the 8XC196MH
Designing Microcontroller Systems for Electrically Noisy Environments Oscillators for Microcontrollers
Motor Controllers Take the Single-Chip Route
Automotive Products
Embedded Applications
Automotive Products
(application brief) 272594
†††
†††
(article reprin t) 270056
handbook (order number 231792)
handbook (order number 270648)
and
Embedded Applications
handbooks
210313 230659
GUIDE TO THIS MANUAL
Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued)
Title Order Number
AP-406, AP-445, AP-449,
MCS® 96 Analog Acquisition Primer 8XC196KR Peripherals: A User’s Point of View A Comparison of the Event Processor Array (EPA) and High Speed
Input/Output (HSIO) Unit
AP-475,
Using the 8XC196NT
AP-477, AP-483, AP-700, AP-711, AP-715,
† †† †††
Low Voltage Embedded Design Application Examples Using the 8XC196MC/MD Microcontroller Intel Fuzzy Logic Tool Simplifies ABS Design EMI Design Techniques for Microcon tro llers in Auto mo ti ve Appl icat io ns Interfacing an I2C Serial EEPROM to an MCS® 96 Microcontroller
Included in
Included in
Included in
Automotive Products
Embedded Applications
Automotive Products
†
††
handbook (order number 231792)
and
†††
†
††
†
handbook (order number 270648)
Embedded Applications
handbooks

Table 1-3. MCS® 96 Microcontroller Datasheets (Commercial/Express)

Title Order Number
8XC196KR/K Q/JR/ JQ Commercia l/E xpress CHMOS Micro co ntrolle r 8XC196KT Com mercia l CHMOS Microcontro ller
†
87C196KT /87C1 96 KS 20 MHz Advan ced 16-Bit CHMOS Micro co ntrol ler 8XC196MC Industrial Motor Control Microcontroller
†
87C196M D Industrial Motor Control CHMOS Microcon tro ller 8XC196NP Commercial CHMOS 16-Bit Microcontroller
†
8XC196NT CHMOS Microcontroller with 1-Mbyte Linear Address Space 80C196NU Commercial CHMOS 16-Bit Microcontroller
†
Included in
Embedded Microcontro llers
handbook (order number 270646)
†
†
†
†
270365 270873 270968
272315 272324 272282 272595 272324 272680
270912 272266 272513 272323 270946 272459 272267 272644

Table 1-4. MCS® 96 Microcont rol ler Datasheets (Automotive)

Title and Description Order Number
87C196CA/87C196CB 20 MHz Adva nced 16-Bi t CHMOS Mi cro con tro lle r with
Integrated CAN 2.0 87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller 87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller 87C196KR/KQ, 87C196JV/JT, 87C196JR/JQ Advanced 16-Bit CHMOS
Microcontroller 87C196KT/87C196KS Advanced 16-Bit CHMOS Microcontroller 87C196KT/KS 20 MHz Advanced 16-Bit CHMOS Microcontroller
†
Included in
Automotive Products
†
† †
†
†
†
handbook (order number 231792)
272405
272529 272580 270827
270999 272513
1-7
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