How it Works
Intel
Loading...
8XC196MC
User Manual
579 pgs4.15 Mb0
Table of contents
Loading...

Intel 8XC196MH, 8XC196MC, 8XC196MD User Manual

Download
8XC196MC, 8XC196MD, 8XC196MH Microcontroller User’s Manual
We Value Your Opinion
Dear Intel Customer: We have updated the infor ma tion that was provided in the 1992 version of the 8XC196MC User’s
Does the manual contain the information that you need? If not, what’s missing?
What do you like the most about thi s manual?
What do you like t he least about this manual?
How would you rate the overall quality? (1=awful, 2=average, 3=better than average) ________ _
Name Title Company Address City, State or Country Zip Code or Postal Cod e Phone Fax Intel product s us ed Type of application
Please fax this f orm to (602)554-7436 or mail it to
Marcia Bethel, Glenn Dotson, Robin Manelis, and Sue Ranta Technical Information Developers Intel Corpor ation, Mail Stop CH6-224 5000 W. Chandl er Blv d. Chandler, AZ 85226
-2
8XC196MC,
8XC196MD, 8XC196MH
Microcontrol ler
User’s Manual
August 2004 Order Number 272181-003
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyrig ht, for sale and use of Intel products except as provided in Intel’s Terms and Conditi on s of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation. Intel Corporation and Intel’s FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products. *Other brands and names are the property of their respective owners. Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
© INTEL CORPORATION, 1996
CONTENT
CHAPTER 1
TO THIS MANUAL
GUIDE
1.
1 MANUAL CONTENTS ................................................................................................... 1-1
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
1.
3 RELATED DOCUMENTS .............................................................................................. 1-5
1.
4 ELECTRONIC SUPPORT SYSTEMS ........................................................................... 1-8
4 World Wide Web .....................................................................................................1-11
1.4.
1.
5 TECHNICAL SUPPORT .............................................................................................. 1-11
1.
6 PRODUCT LITERATURE ............................................................................................ 1-11
CHAPTER 2
ARCHITECTURAL
2.
1 TYPICAL APPLICATIONS ............................................................................................. 2-1
2.
2 MICROCONTROLLER FEATURES .............................................................................. 2-1
2.
3 FUNCTIONAL OVERVIEW............................................................................................ 2-2
1 CPU Control ..............................................................................................................2-4
2.3.
2.3.
2 Register File ..............................................................................................................2-4
2.3.
3 Register Arithmetic-logic Unit (RALU) .......................................................................2-4
1 Code Execution ....................................................................................................2-5
2.3.3.
2 Instruction Format ................................................................................................2-5
2.3.3.
2.3.
4 Memory Interface Unit ...............................................................................................2-6
2.3.
5 Interrupt Service ........................................................................................................2-6
2.
4 INTERNAL TIMING........................................................................................................ 2-7
2.
5 INTERNAL PERIPHERALS ........................................................................................... 2-8
2.5.
1 I/O Ports ....................................................................................................................2-9
2.5.
2 Serial I/O (SIO) Port ..................................................................................................2-9
2.5.
3 Event Processor Array (EPA) and Timer/Counters .................................................2-10
2.5.
4 Pulse-width Modulator (PWM) ................................................................................2-10
2.5.
5 Frequency Generator ..............................................................................................2-10
2.5.
6 Waveform Generator ..............................................................................................2-10
2.5.
7 Analog-to-digital Converter .....................................................................................2-11
2.5.
8 Watchdog Timer ......................................................................................................2-11
2.
6 SPECIAL OPERATING MODES ................................................................................. 2-11
2.6.
1 Reducing Power Consumption ...............................................................................2-11
2.6.
2 Testing the Printed Circuit Board ............................................................................2-11
2.6.
3 Programming the Nonvolatile Memory ....................................................................2-12
OVERVIEW
S
iii
8XC196MC, MD, MH USER’S MANUAL
CHAPTER 3
PROGRAMMING CONSIDERATIONS
3.1 OVERVIEW OF THE INSTRUCTION SET.................................................................... 3-1
3.1.1 BIT Operands ............................................................................................................3-2
3.1.2 BYTE Operands ........................................................................................................3-2
3.1.3 SHORT-INTEGER Operands ....................................................................................3-2
3.1.4 WORD Operands ......................................................................................................3-2
3.1.5 INTEGER Operands .................................................................................................3-3
3.1.6 DOUBLE-WORD Operands ......................................................................................3-3
3.1.7 LONG-INTEGER Operands ......................................................................................3-4
3.1.8 Converting Operands ................................................................................................3-4
3.1.9 Conditional Jumps ....................................................................................................3-4
3.1.10 Floating Point Operations .........................................................................................3-4
3.2 ADDRESSING MODES . ................................................................................................ 3-5
3.2.1 Direct Addressing ......................................................................................................3-6
3.2.2 Immediate Addressing ..............................................................................................3-6
3.2.3 Indirect Addressing ...................................................................................................3-6
3.2.3.1 Indirect Addressing with Autoincrement ...............................................................3-7
3.2.3.2 Indirect Addressing with the Stack Pointer ........................................................... 3-7
3.2.4 Indexed Addressing ..................................................................................................3-7
3.2.4.1 Short-indexed Addressing ....................................................................................3-7
3.2.4.2 Long-indexed Addressing .................................................................................... 3-8
3.2.4.3 Zero-indexed Addressing .....................................................................................3-8
3.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS.................................. 3-9
3.3.1 Direct Addressing ......................................................................................................3-9
3.3.2 Indexed Addressing ..................................................................................................3-9
3.4 SOFTWARE STANDARDS AND CONVENTIONS ....................................................... 3-9
3.4.1 Using Registers .........................................................................................................3-9
3.4.2 Addressing 32-bit Operands ...................................................................................3-10
3.4.3 Linking Subroutines ................................................................................................3-10
3.5 SOFTWARE PROTECTION FEATURES AND GUIDELINES .................................... 3-11
CHAPTER 4
MEMORY PARTITIONS
4.1 MEMORY PARTITIONS................................................................................................ 4-1
4.1.1 External Devices (Memory or I/O) .............................................................................4-1
4.1.2 Program and Special-purpose Memory ....................................................................4-1
4.1.3 Program Memory ......................................................................................................4-2
4.1.4 Special-purpose Memory ..........................................................................................4-3
4.1.4.1 Reserved Memory Locations ...............................................................................4-3
4.1.4.2 Interrupt and PTS Vectors .................................................................................... 4-3
4.1.4.3 Security Key .........................................................................................................4-4
4.1.4.4 Chip Configuration Bytes (CCBs) .........................................................................4-4
4.1.5 Special-function Registers (SFRs) ............................................................................ 4-4
iv
CONTENTS
4.1.5.1 Memory-mapped SFRs ........................................................................................4-5
4.1.5.2 Peripheral SFRs ...................................................................................................4-5
4.1.6 Register File ..............................................................................................................4-9
4.1.6.1 General-purpose Register RAM .........................................................................4-10
4.1.6.2 Stack Pointer (SP) ..............................................................................................4-10
4.1.6.3 CPU Special-function Registers (SFRs) .. ...........................................................4-11
4.2 WINDOWING............................................................................................................... 4-12
4.2.1 Selecting a Window ................................................................................................4-13
4.2.2 Addressing a Location Through a Window ............................................................. 4-14
4.2.2.1 32-byte Windowing Example ..............................................................................4-16
4.2.2.2 64-byte Windowing Example ..............................................................................4-16
4.2.2.3 128-byte Windowing Example ............................................................................4-16
4.2.2.4 Unsupported Locations Windowing Example .....................................................4-16
4.2.2.5 Using the Linker Locator to Set Up a Window ....................................................4-17
4.2.3 Windowing and Addressing Modes .........................................................................4-19
CHAPTER 5
STANDARD AND PTS INTERRUPTS
5.1 OVERVIEW OF INTERRUPTS............. ......................................................................... 5-1
5.2 INTERRUPT SIGNALS AND REGISTERS ................................................................... 5-3
5.3 INTERRUPT SOURCES AND PRIORITIES.................................................................. 5-4
5.3.1 Special Interrupts ......................................................................................................5-6
5.3.1.1 Unimplemented Opcode ......................................................................................5-6
5.3.1.2 Software Trap .......................................................................................................5-6
5.3.1.3 NMI .......................................................... ............................................................. 5-6
5.3.2 External Interrupt Pin ................................................................................................5-6
5.3.3 Multiplexed Interrupt Sources ..... ................. ...................... ................. ................. .....5-7
5.3.4 End-of-PTS Interrupts ...............................................................................................5-9
5.4 INTERRUPT LATENCY................................................................................................. 5-9
5.4.1 Situations that Increase Interrupt Latency ................................................................ 5-9
5.4.2 Calculating Latency .................................................................................................5-10
5.4.2.1 Standard Interrupt Latency ................... .. ............................................................5-10
5.4.2.2 PTS Interrupt Laten cy ........................................................................................5-11
5.5 PROGRAMMING THE INTERRUPTS......................................................................... 5-12
5.5.1 Modifying Interrupt Priorities ....................................... ....................................... .....5-18
5.5.2 Determining the Source of an I nterrupt ................................................................... 5-20
5.6 INITIALIZING THE PTS CONTROL BLOCKS ............................................................. 5-24
5.6.1 Specifying the PTS Count .......................................................................................5-25
5.6.2 Selecting the PTS Mode .........................................................................................5-27
5.6.3 Single Transfer Mode ..............................................................................................5-27
5.6.4 Block Transfer Mode ...............................................................................................5-30
5.6.5 A/D Scan Mode .......................................................................................................5-32
5.6.5.1 A/D Scan Mode Cycles ......................................................................................5-35
5.6.5.2 A/D Scan Mode Example 1 ................................................................................5-35
5.6.5.3 A/D Scan Mode Example 2 ................................................................................5-37
v
8XC196MC, MD, MH USER’S MANUAL
5.6.6 Serial I/O Modes .....................................................................................................5-37
5.6.6.1 Synchronous SIO Transmit Mode Example .......................................................5-43
5.6.6.2 Synchronous SIO Receive Mode Example ........................................................ 5-47
5.6.6.3 Asynchronous SIO Transmit Mode Example .....................................................5-50
5.6.6.4 Asynchronous SIO Receive Mode Example ......................................................5-55
CHAPTER 6
I/O PORTS
6.1 I/O PORTS OVERVIEW ................................................................................................ 6-1
6.2 INPUT-ONLY PORTS 1 (MC, MD ONLY) AND 0.......................................................... 6-2
6.2.1 Standard Input-only Port Operation ..........................................................................6-3
6.2.2 Standard Input-only Port Considerations ..................................................................6-4
6.3 BIDIRECTIONAL PORTS 1 (MH ONLY), 2, 5, AND 7 (MD ONLY)............................... 6-4
6.3.1 Bidirectional Port Operation ......................................................................................6-6
6.3.2 Bidirectional Port Pin Configurations ............ .......... ........ ....... ....... ....... .......... ....... ..... 6-9
6.3.3 Bidirectional Port Pin Configuration Example .........................................................6-11
6.3.4 Bidirectional Port Considerations ............................................................................6-12
6.4 BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)...................................... 6-14
6.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation .....................................6- 15
6.4.2 Using Ports 3 and 4 as I/O . .. ................. ............ ................. ............... ............ ..........6-16
6.4.3 Design Considerations for Ports 3 and 4 .......... .......... ....... .......... ..... ....... .......... .....6-16
6.5 STANDARD OUTPUT-ONLY PORT 6 ....................................................................... 6-16
6.5.1 Output-only Port Operation .....................................................................................6-17
6.5.2 Configuring Output-only Port Pins ..........................................................................6-17
CHAPTER 7
SERIAL I/O (SIO) PORT
7.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW................................................... 7-1
7.2 SERIAL I/O PORT SIGNALS AND REGISTERS.......................................................... 7-2
7.3 SERIAL PORT MODES................................................................................................. 7-4
7.3.1 Synchronous Modes (Modes 0 and 4) ...................................................................... 7-5
7.3.1.1 Mode 0 . ................................................................................................................7-5
7.3.1.2 Mode 4 . ................................................................................................................7-6
7.3.2 Asynchronous Modes (Modes 1, 2, and 3) ............................................................... 7-7
7.3.2.1 Mode 1 . ................................................................................................................7-7
7.3.2.2 Mode 2 . ................................................................................................................7-8
7.3.2.3 Mode 3 . ................................................................................................................7-9
7.3.2.4 Mode 2 and 3 Timings ..........................................................................................7-9
7.3.2.5 Multiprocessor Communications ..........................................................................7-9
7.4 PROGRAMMING THE SERIAL PORT........................................................................ 7-10
7.4.1 Configuring the Serial Port Pins ....................................... ................... ................. ...7-10
7.4.2 Programming the Control Register ..........................................................................7-10
7.4.3 Programming the Baud Rate and Clock Source .....................................................7-12
7.4.4 Enabling the Serial Port Interrupts .......................................... ............ ................. ... 7- 14
vi
CONTENTS
7.4.5 Determining Serial Port Status ................................................................................7-15
CHAPTER 8
FREQUENCY GENERATOR
8.1 FUNCTIONAL OVERVIEW............................................................................................ 8-1
8.2 PROGRAMMING THE FREQUENCY GENERATOR ................................................... 8-3
8.2.1 Configuring the Output ..............................................................................................8-3
8.2.2 Programming the Frequency ....................................................................................8-3
8.2.3 Determining the Current Value of the Down-counter ................................................ 8-4
8.3 APPLICATION EXAMPLE............................................................................................. 8-4
CHAPTER 9
WAVEFORM GENERATOR
9.1 WAVEFORM GENERATOR FUNCTIONAL OVERVIEW.............................................. 9-1
9.2 WAVEFORM GENERATOR SIGNALS AND REGISTERS........................................... 9-3
9.3 WAVEFORM GENERATOR OPERATION.................................................................... 9-4
9.3.1 Timebase Generator .................................................................................................9-4
9.3.2 Phase Driver Channels .............................................................................................9-5
9.3.3 Control and Protection Circuitry ................... .......... ............ ............... ....... ............ ..... 9-5
9.3.4 Register Buffering and Synchronization .................................................................... 9-6
9.3.5 Operating Modes ......................................................................................................9-7
9.3.5.1 Center-aligned Modes ..........................................................................................9-9
9.3.5.2 Edge-Aligned Modes ..........................................................................................9-10
9.4 PROGRAMMING THE WAVEFORM GENERATOR................................................... 9-12
9.4.1 Configuring the Outputs ..........................................................................................9-12
9.4.2 Controlling the Protection Circuitry and EXTINT Interrupt Generation .................... 9 -15
9.4.3 Specifying the Carrier Period and Duty Cycle ................................... ......................9-16
9.4.4 Specifying the Operating Mode and Dead Time and Starting the Counter .............9-17
9.5 DETERMINING THE WAVEFORM GENERATOR’S STATUS................................... 9-19
9.6 ENABLING THE WAVEFORM GENERATOR INTERRUPTS..................................... 9-19
9.7 DESIGN CONSIDERATIONS...................................................................................... 9-20
9.7.1 Dead Time and Duty Cycle .....................................................................................9-20
9.7.2 EXTINT Interrupts and Protection Circuitry ........................ ................. ............... ..... 9-21
9.8 PROGRAMMING EXAMPLE....................................................................................... 9-21
CHAPTER 10
PULSE-WIDTH MODULATOR
10.1 PWM FUNCTIONAL OVERVIEW................................................................................ 10-1
10.2 PWM SIGNALS AND REGISTERS............................................................................. 10-2
10.3 PWM OPERATION...................................................................................................... 10-3
10.4 PROGRAMMING THE FREQUENCY AND PERIOD.................................................. 10-4
10.5 PROGRAMMING THE DUTY CYCLE......................................................................... 10-6
10.5.1 Sample Calculations ...............................................................................................10-7
vii
8XC196MC, MD, MH USER’S MANUAL
10.5.2 Reading the Current Value of the Down-counter ....................................................10-7
10.5.3 Enabling the PWM Outputs .......................... ........................................................ ... 1 0-8
10.5.4 Generating Analog Outputs ..................................................................................10-10
CHAPTER 11
EVENT PROCESSOR ARRAY (EPA)
11.1 EPA FUNCTIONAL OVERVIEW ................................................................................. 11-1
11.2 EPA AND TIMER/COUNTER SIGNALS AND REGI STERS ....................................... 11-2
11.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 11-5
11.3.1 Cascade Mode (Timer 2 Only) ............................... ................................................. 11-7
11.3.2 Quadrature Clocking Modes ...................................................................................11-7
11.4 EPA CHANNEL FUNCTIONAL OVERVIEW............................................................... 11-9
11.4.1 Operating in Capture Mode ...................................................................................11-10
11.4.1.1 EPA Overruns ..................................................................................................11-12
11.4.1.2 Preventing EPA Overruns ................................................................................11-13
11.4.2 Operating in Compare Mode .................................................................................11-13
11.4.2.1 Generating a Low-speed PWM Output ............................................................11-13
11.4.2.2 Generating the Highest-speed PWM Output ....................................................11-14
11.5 PROGRAMMING THE EPA AND TIMER/COUNTERS............................................. 11-15
11.5.1 Configuring the EPA and Timer/Counter Signals ..................................................11-15
11.5.2 Programming the Timers .......................................................................................11-15
11.5.3 Programming the Capture/Compare Channels .....................................................11-18
11.5.4 Programming the Compare-only Channels ...........................................................11-22
11.6 ENABLING THE EPA INTERRUPTS........................................................................ 11-23
11.7 DETERMINING EVENT STATUS.............................................................................. 11-24
CHAPTER 12
ANALOG-TO-DIGITAL (A/D) CONVERTER
12.1 A/D CONVERTER FUNCTIONAL OVERVIEW........................................................... 12-1
12.2 A/D CONVERTER SIGNALS AND REGISTERS ........................................................ 12-2
12.3 A/D CONVERTER OPERATION................................................................................. 12-3
12.4 PROGRAMMING THE A/D CONVERTER. ................................................................. 12-4
12.4.1 Programming the A/D Test Register .......................................................................12-5
12.4.2 Programming the A/D Result Register (for Threshold Detection Only) ...................12-5
12.4.3 Programming the A/D Time Register ......................................................................12-6
12.4.4 Programming the A/D Command Register ..............................................................12-7
12.4.5 Enablin g the A/D Interr upt .. .. ....... ..... ..... ....... ..... ..... ........ .... ..... ........ .... ..... ........ .... ... 12-8
12.5 DETERMINING A/D STATUS AND CONVERSION RESULTS.................................. 12-9
12.6 DESIGN CONSIDERATIONS.................................................................................... 12-10
12.6.1 Designing External Interface Circuitry . ............................... ................................... 12-10
12.6.1.1 Minimizing the Effect of High Input Source Resistance ....................................12-11
12.6.1.2 Suggested A/D Input Circuit .............................................................................12-12
12.6.1.3 Analog Ground and Reference Voltages .........................................................12-12
viii
CONTENTS
12.6.1.4 Using Mixed Analog and Digital Inputs ............................................................12-13
12.6.2 Understanding A/D Conversion Errors ..................................................................12-13
CHAPTER 13
MINIMUM HARDWARE CONSIDERATIONS
13.1 MINIMUM CONNECTIONS ......................................................................................... 13-1
13.1.1 Unused Inputs .........................................................................................................13-2
13.1.2 I/O Port Pin Connections ........................................................................................13-2
13.2 APPLYING AND REMOVING POWER ....................................................................... 13-4
13.3 NOISE PROTECTION TIPS........................................................................................ 13-4
13.4 THE ON-CHIP OSCILLATOR CIRCUITRY ................................................................. 13-5
13.5 USING AN EXTERNAL CLOCK SOURCE.................................................................. 13-7
13.6 RESETTING THE DEVICE.......................................................................................... 13-8
13.6.1 Generating an External Reset ...............................................................................13-10
13.6.2 Issuing the Reset (RST) Instruction ......................................................................13-12
13.6.3 Issuing an Illegal IDLPD Key Operand .................................................................13-12
13.6.4 Generating Wait States . ....... ............ .......... ............ ............ ............... ....... ............ . 13-12
13.6.5 Enabling the Watchdog Timer ...............................................................................13-12
CHAPTER 14
SPECIAL OPERATING MODES
14.1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS..................................... 14-1
14.2 REDUCING POWER CONSUMPTION....................................................................... 14-3
14.3 IDLE MODE ............................................................................................................... .. 14-4
14.4 POWERDOWN MODE ................................................................................................ 14-5
14.4.1 Enabling and Disabling Powerdown Mode ..............................................................14-5
14.4.2 Entering Powerdown Mode .....................................................................................14-6
14.4.3 Exiting Powerdown Mode .......................................................................................14-6
14.4.3.1 Driving the V
Pin Low ......................................................................................14-6
pp
14.4.3.2 Generating a Hardware Reset ...........................................................................14-6
14.4.3.3 Asserting the External Interrupt Signal ...............................................................14-7
14.4.3.4 Selecting R
and C1 ...........................................................................................14-8
1
14.5 ONCE MODE............................................................................................................. 14-10
14.6 RESERVED TEST MODES....................................................................................... 14-11
CHAPTER 15
INTERFACING WITH EXTERNAL MEMORY
15.1 EXTERNAL MEMORY INTERFACE SIGNALS AND REGISTERS............................ 15-1
15.2 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES ......... 15-5
15.3 BUS WIDTH AND MULTIPLEXING........................................................................... 15-10
15.3.1 Timing Requirements for BUSWIDTH ...................................................................15-13
15.3.2 16-bit Bus Timings ...................... ................. ...................... ................. .................. 15-14
15.3.3 8-bit Bus Timings ..................................................................................................15-16
ix
8XC196MC, MD, MH USER’S MANUAL
15.4 WAIT STATES (READY CONTROL)......................................................................... 15-17
15.5 BUS-CONTROL MODES........................................................................................... 15-21
15.5.1 Standard Bus-control Mode ..................................................................................15-22
15.5.2 Write Strobe Mode ... ........................................................................... .................. 15-25
15.5.3 Address Valid Strobe Mode ..................................................................................15-27
15.5.4 Address Valid with Write Strobe Mode ............... ...................................................15-30
15.6 SYSTEM BUS AC TIMING SPECIFICATIONS......................................................... 15-31
15.6.1 Explanation of AC Symbols . .................................................................................15-33
15.6.2 AC Timing Definitions ...........................................................................................15-33
CHAPTER 16
PROGRAMMING THE NONVOLATILE MEMORY
16.1 PROGRAMMING METHODS...................................................................................... 16-1
16.2 OTPROM MEMORY MAP ........................................................................................... 16-2
16.3 SECURITY FEATURES............................................................................................... 16-3
16.3.1 Controlling Access to Internal Memory ...................................................................16-3
16.3.1.1 Controlling Access to the OTPROM During Normal Operation .... ......................1 6-4
16.3.1.2 Controlling Access to the OTPROM During Programming Modes .....................16-4
16.3.2 Controlling Fetches from External Memory .............................................................16-6
16.4 PROGRAMMING PULSE WIDTH ............................................................................... 16-8
16.5 MODIFIED QUICK-PULSE ALGORITHM.................................................................... 16-9
16.6 PROGRAMMING MODE PINS.................................................................................. 16-11
16.7 ENTERING PROGRAMMING MODES..................................................................... 16-13
16.7.1 Selecting the Programming Mode .........................................................................16-13
16.7.2 Power-up and Power-down Sequences ................................................................16-14
16.7.2.1 Power-up Sequence .........................................................................................16-14
16.7.2.2 Power-down Sequence ....................................................................................16-14
16.8 SLAVE PROGRAMMING MODE............................................................................... 16-15
16.8.1 Reading the Signature Word and Programming Voltages ....................................16-15
16.8.2 Slave Programming Circuit and Memory Map ......................................................16-16
16.8.3 Operating Environment .........................................................................................16-17
16.8.4 Slave Programming Routines . ..............................................................................16-19
16.8.5 Timing Mnemonics ................................................................................................16-24
16.9 AUTO PROGRAMMING MODE ................................................................................ 16-25
16.9.1 Auto Programming Circuit and Memory Map ........................................................16-25
16.9.2 Operating Environment .........................................................................................16-27
16.9.3 Auto Programming Routine ...................................................................................16-27
16.9.4 Auto Programming Procedure ..............................................................................16-29
16.9.5 ROM-dump Mode .................................................................................................16-30
16.10 PCCB AND UPROM PROGRAMMING (8XC196MH ONLY).................................... 16-30
16.11 RUN-TIME PROGRAMMING .................................................................................... 16-32
x
CONTENTS
APPENDIX A
INSTRUCTION SET REFERENCE
APPENDIX B
SIGNAL DESCRIPTIONS
B.1 SIGNAL NAME CHANGES. .......................................................................................... B-1
B.2 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. B-1
B.3 SIGNAL DESCRIPTIONS........................................................................................... B-12
B.4 DEFAULT CONDITIONS............................................................................................ B-22
APPENDIX C
REGISTERS
GLOSSARY
INDEX
xi
8XC196MC, MD, MH USER’S MANUAL
FIGURES
Figure Page
2-1 8XC196M
2-2 Block Diagram of the Core...........................................................................................2-3
2-3 Clock Circuitry . .............................................................................................................2-7
2-4 Internal Clock Phases ..................................................................................................2-8
4-1 Regi ster File Memory Map ............. .......................................... ....................................4-9
4-2 Windowing..................................................................................................................4-12
4-3 Window Selection (WSR) Register.............................................................................4-13
5-1 Flow Diagram for PTS and Standard Interrupts ...........................................................5-2
5-2 Waveform Generator Protection Circuitry.................. .......... ....... ........ ....... ....... ....... ..... 5-7
5-3 Flow Diagram for t he OVRTM Interrupt........................................................................5-8
5-4 Standard Interrupt Response Time.................................. .......................... ................5-11
5-5 PTS Interrupt Response Time....................................................................................5-11
5-6 PTS Select (PTSSEL) Register.................................................................................. 5-14
5-7 Interrupt Ma sk (INT_MASK) Register .............. ........................................................... 5-15
5-8 Interrupt Ma sk 1 (INT_MASK1) Register......................................... ...................... ..... 5-16
5-9 Peripheral Interrupt Ma sk (PI_MASK) Register...................................... ................. ... 5-17
5-10 Inter rupt Pending (INT_PEND) Register ....................................................................5-21
5-11 Inter rupt Pending 1 (INT_PEND1) Register ...............................................................5-22
5-12 Peripheral Inter rupt Pending (PI_PEND) Register .....................................................5-23
5-13 PTS Control Blocks ....................................................................................................5-25
5-14 PTS Service ( PTSSRV) Register ...............................................................................5-26
5-15 PTS Mode Selection Bi ts (PTSCON Bits 7:5) ............................................................5-27
5-16 PTS Control Block — Single Transfer Mode..............................................................5-28
5-17 PTS Control Block — Block Transfer Mode...............................................................5-31
5-18 PTS Control Block – A/D Scan Mode.........................................................................5-33
5-19 PTS Control Block 1 – Serial I/O Mode......................................................................5-38
5-20 PTS Control Block 2 – Serial I/O Mode......................................................................5-41
5-21 Synchronous SIO Transmit Mode Timing...................................................................5-43
5-22 Synchronous SIO Transmit Mode — End-of-PTS Interrupt Routine Flowchart..........5-46
5-23 Synchronous SIO Receive Timing..............................................................................5-47
5-24 Synchronous SIO Receive Mode — End-of-PTS Interr upt Routine Flowchart...........5-50
5-25 Asynchronous SIO Transmit Timing...........................................................................5-51
5-26 Asynchronous SIO Transmit Mode — End-of-PTS I nterrupt Routine Flowchart ........5-54
5-27 Asynchronous SIO Receive Timing............................................................................5-55
5-28 Asynchronous SIO Receive Mode — End-of-PTS Interrupt Routine Flowchart.........5-58
6-1 Standard Input-only Port Structure...............................................................................6-3
6-2 Bidirectional Port Structure...........................................................................................6-8
6-3 Address/Data Bus (Ports 3 and 4) Structure..............................................................6-15
6-4 Output-only Port .........................................................................................................6-18
6-5 Port 6 Output Configuration (WG_OUTPUT) Register... ............................................ 6-18
7-1 SIO Block Diagram . ......................................................................................................7-1
7-2 Typical Shift Register Circuit for Mode 0.......................................................... ............ 7-5
7-3 Mode 0 Timing.......................................... ....... ..... ..... .......... .. .......... ..... .. .......... ..... .. .....7-6
7-4 Serial Port Frames for Mode 1 ............................................ .........................................7-8
x
Block Diagram ................................................................... ........................2-3
xii
CONTENTS
FIGURES
Figure Page
7-5 Serial Port Frames in Mode 2 and 3.............................................................................7-9
7-6 Serial Port Control (SP 7-7 Serial Port 7-8 Serial Port Status
8-1 Frequency Generator Block Diagram...........................................................................8-1
8-2 Frequency (FREQ_GEN) Register...............................................................................8-3
8-3 Frequency Generator Count (FREQ_CNT) Register....................................................8-4
8-4 Infrared Remote Control Ap plication Block Diagram.................................................... 8-5
8-5 Data Encoding Example...............................................................................................8-5
9-1 Waveform Generator Block Diagram............................................................................9-2
9-2 Dead-time Generator Circuitry........ ........ ....... ..... ....... ..... ....... ..... ........ .... ........ ....... ..... .. 9-5
9-3 Protection Circuit ry ............. ............ .......... ............ ............... ............ ....... ............... ....... 9-6
9-4 Center-aligned Modes — Counter Operation............................................................... 9-9
9-5 Center-aligned Modes — Output Operation...............................................................9-10
9-6 Edge-aligned Modes — Counter Operation...............................................................9-11
9-7 Edge-aligned Modes — Output Operation .................................................................9-11
9-8 WG Output Configuration (WG_OU TPUT) Register ..................................................9-13
9-9 Waveform Generator Protection (WG_PROTECT) Register......................................9-15
9-10 Waveform Generator Reload (WG_RELOAD) Register.............................................9-16
9-11 Phase Compare (WG _CO MP
9-12 Waveform Generator Control (WG_CONTROL) Register. ...................................... ...9 -18
9-13 Waveform Generator Counter (WG_COUNTER) Register ........................................9-19
9-14 Effect of Dead Time on Duty Cycle............................................................................9-20
10-1 PWM Block Diagram ..................................................................................................10-2
10-2 PWM Output Wa veforms......................................................................................... ...1 0-4
10-3 PWM P eriod (PWM_PERIOD) R egister. ................................................ .................... 10-6
10-4 PWM Control (PWM
10-5 PWM C ount (PWM_COUNT) Register.......................................................................10-8
10-6 Waveform Generator Output Configuration (WG_OUTPUT) Register.......................10-9
10-7 D/A Buffer Block Diagram.........................................................................................10-10
10-8 PWM to Analog Conversion Circuitry.......................................................................10-10
11-1 EPA Block Diagram....................................................................................................11-2
11-2 EPA Timer/Counters ..................................................................................................11-6
11-3 Quadrature Mode Interface........................................................................................11-8
11-4 Quadrature Mode Timing and Count..........................................................................11-9
11-5 A Single EPA Capture/Compare Channel................................................................11-10
11-6 EPA Simplifie d Input-capture Structure....................................................................11-11
11-7 Valid EPA Input Events............................................................................................11-11
11-8 Timer 1 Control (T1CONTROL) Register.................................................................11-16
11-9 Timer 2 Control (T2CONTROL) Register.................................................................11-17
11-10 EPA Control (EPA 11-11 EPA Compare Control (COMP
12-1 A/D C onverter Block Diagram . .............................................. ..................................... 1 2-1
12-2 A/D Test (AD_TEST) Register. ................................................................................ ...1 2-5
x
Baud Rate (SPx_BAUD) Register.........................................................7-12
x
_CON) Register....................................................................7-10
(SPx_STATUS) Register...............................................................7-15
x
) Register............................................... ....................9-17
x
_CONTROL) Register..............................................................10-7
x
_CON) Registers .......................................................................11-19
x
_CON) Registers....................................................11-22
xiii
8XC196MC, MD, MH USER’S MANUAL
FIGURES
Figure Page
12-3 A/D R esult (AD_RESULT) Register — Write Format............... ..... .. ..... ..... ..... .. ..... .....12-6
12-4 A/D Time (A D_TIME) Register ....... ...................... ...................... ...................... .......... 1 2-7
12-5 A/D C ommand (AD_COMMAND) Register ................................................................12-8
12-6 A/D R esult (AD_RESULT) Register — Read Format.................................................1 2-9
12-7 Idealized A/D Sampling Circuitry..............................................................................12-10
12-8 Suggested A/D Input Circuit.....................................................................................12-12
12-9 Ideal A/D Conversion Characteristic.........................................................................12-15
12-10 Actual and Ideal A/D Conversion Characteristics.....................................................12-16
12-11 T erminal-based A/D Conversion Characteristic.......................................................12-18
13-1 Minimum Hardware Connections ...............................................................................13-3
13-2 Power and Return Connections .................................................................................13-4
13-3 On-chip Oscillator Circuit............................................................................................13-5
13-4 External Crystal Connections.....................................................................................13-6
13-5 External Clock Connections .......................................................................................13-7
13-6 External Clock Drive Waveforms................................................................................13-7
13-7 Reset Timing Sequence.............................................................................................13-8
13-8 General Configuration Register (GEN_CON)............................................................13-9
13-9 Internal Reset Circuitry................... ....................................... ................. ..................13-10
13-10 Minimum Reset Circuit .............................................................................................13-11
13-11 E xample of a System Reset Circuit..........................................................................13-11
14-1 Clock Control During Power-saving Modes ................................................................14-4
14-2 Power-up and Power-down Sequence When Using an External Interrupt.................14-7
14-3 External RC Circuit.....................................................................................................14-8
14-4 Typical Voltage on the V
15-1 Chip Configuration 0 (CCR0) Register.......................................................................15-7
15-2 Chip Configuration 1 (CCR1) Register.......................................................................15-9
15-3 Multiplexing and Bus Width Options.........................................................................15-11
15-4 BUSWID TH Timing Diagram (8XC196MC, MD) ......................................................15-12
15-5 BUSWID TH Timing Diagram (8XC196MH)..............................................................15-12
15-6 Timings for 16-bit Buses...........................................................................................15-15
15-7 Timings for 8-bit Buses.............................................................................................15-17
15-8 READY Timing Diagram — One Wait State (8XC196MC, MD)...............................15-19
15-9 READY Timing Diagram — One Wait State (8XC196MH).......................................15-20
15-10 Standard Bus Control...............................................................................................15-22
15-11 Decoding WRL# and WRH#.....................................................................................15-22
15-12 8-bit System with Flash and RAM ............................................................................15-23
15-13 16-bit S yst em with Dynamic Bus Width....................................................................15-24
15-14 Wr ite Strobe Mode ...................................................................................................15-25
15-15 16-bit System with Writes to Byte-wide RAMs .........................................................15-26
15-16 Address Valid Strobe Mode ......................................................................................15-27
15-17 Comparison of ALE and ADV# Bus Cycles ..............................................................15-27
15-18 8-bit System with Flash ............................................................................................15-28
15-19 16-bit System with EPROM...................................................................................... 15-29
15-20 Timings of Address Valid with Write Strobe Mode...................................................15-30
Pin While Exiting Powerdown.........................................14-9
PP
xiv
CONTENTS
FIGURES
Figure Page
15-21 16-bit S yst em with RAM ... ..... .. ..... .. ..... ... ..... .. ..... .. ..... ..... ... .... ... .. ..... ..... .. ..... ... ..... .. ...15-31
15-22 System Bus Timing ..................................................................................................15-32
16-1 U nerasable PROM (USFR) Register ... .......................................................................16-7
16-2 Programmi n g Pulse Width (PPW) Re gister................................................................16-8
16-3 Modifi ed Quick-pulse Algorithm .... ............................................................................16-10
16-4 Pin Functions in Programming Modes......................................................................16-11
16-5 Slave Programming Circuit.......................................................................................16-16
16-6 Chip Configuration Registers (CCRs).......................................................................16-18
16-7 Address/Command Decoding Routine.....................................................................16-20
16-8 Program Word R outine .............................................................................................16-21
16-9 Program Word Wa veform . ........................................................................................16-22
16-10 Dump Word Routine.................................................................................................16-23
16-11 Dump Word Waveform.............................................................................................16-24
16-12 Auto Programming Circuit ........................................................................................ 16-26
16-13 Auto Programming Routine......................................................................................16-28
16-14 PCCB and UPROM Programming Circuit ................................................................16-31
16-15 Ru n-time Progr amming Code Example....................................................................16-33
B-1 8XC196MC 64-lead Shrink DIP (SDIP) Package........................................................B-3
B-2 8XC196MC 84-lead PLCC Package...........................................................................B-4
B-3 8XC196MC 80-lead Shrink EIAJ/QFP Package..........................................................B-5
B-4 8XC196MD 84-lead PLCC Package...........................................................................B-7
B-5 8XC196MD 80-lead Shrink EIAJ/QFP Package..........................................................B-8
B-6 8XC196MH 64-lead Shrink DIP (SDIP) Package......................................................B-10
B-7 8XC196MH 84-lead PLCC Package. ........................................................................B-11
B-8 8XC196MH 80-lead Shrink EIAJ/QFP Package........................................................B-12
xv
8XC196MC, MD, MH USER’S MANUAL
TABLES
Table Page
1-1 Handbooks and Product Information..................................... ..... ..... ....... ..... ..... ..... .......1-6
1-2 Application Notes, Application Briefs, and Article Repr ints .......................................... 1-6
1-3 MCS 1-4 MCS 1-5 MCS
2-1 Features of the 8XC196Mx Product Family..................................................................2-2
2-2 State Times at Various Frequencies............................................................................2-8
3-1 Operand Type Definitions............................................................................................. 3-1
3-2 Equivalent Operand Types for Assembly and C Programming Languages.................3-2
3-3 Definition of Temporary Registers................................................................................3-6
4-1 Memory Map .. .............................................................................................................4-2
4-2 Special-purpose Memory Addresses............................................................................4-3
4-3 Memory-mapped SFRs ................................................................................................4-5
4-4 Peripheral SFRs — 8XC196MC...................................................................................4-6
4-5 Peripheral SFRs — 8XC196MD...................................................................................4-7
4-6 Peripheral SFRs — 8XC196MH...................................................................................4-8
4-7 Register File Memory Addresses ..............................................................................4-10
4-8 CPU SFRs..................................................................................................................4-11
4-9 Selecting a Window of Peripheral SFRs.....................................................................4-13
4-10 Selecting a Window of the Upper Register File..........................................................4-14
4-11 Windows.....................................................................................................................4-15
4-12 Windowed Base Addresses .......................................................................................4-15
5-1 Interrupt Signals ...........................................................................................................5-3
5-2 Interrupt and PTS Control and Status Registers.............................................. ............ 5-3
5-3 Interrupt S ources, Vectors, and Prioriti es.................. ............ ............... ....... ............ ..... 5-5
5-4 Execution Times for PTS Cycles................................................................................5-12
5-5 Single Transfer Mode PTSCB....................................................................................5-30
5-6 Block Transfer Mode PTSCB.....................................................................................5-30
5-7 A/D Scan Mode Command/Data Table......................................................................5-34
5-8 Command/Data Table (Example 1)............................................................................5-36
5-9 A/D Scan Mode PTSCB (Example 1).........................................................................5-36
5-10 Command/Data Table (Example 2)............................................................................5-37
5-11 A/D Scan Mode PTSCB (Example 2).........................................................................5-37
5-13 SSIO Transmit Mode PTSCBs...................................................................................5-45
5-14 SSIO Receive Mode PTSCBs. ...................................................................................5-48
5-15 ASIO Transmit Mode PTSCBs...................................................................................5-52
5-16 ASIO Receive Mode PTSCBs. ...................................................................................5-56
6-1 Device I/O Ports ............... ....... ..... ....... ..... ....... ..... ........ ....... ..... ....... ..... ....... ..... ....... .....6-1
6-2 Standard Input-only Port Pins ......................................................................................6-2
6-3 Input-only Port Registers..............................................................................................6-3
6-4 Bidirectional Port Pins ........................................................... ..... ..... ..... .. ..... ..... ..... .......6-5
6-5 Bidirectional Port Control and Status Registers ..................................... ......................6-6
6-6 Logic Table for Bidire ctional Ports in I/O Mode ............................................................6-9
6-7 Logic Table for Bidire ctional Ports in Special-function M od e .......................................6-9
®
96 Microcontroller Datasheets (Commercial/Express)......................................1-7
®
96 Microcontroller Datasheets (Automotive).....................................................1-7
®
96 Microcontroller Quick References................................................................1-8
xvi
CONTENTS
TABLES
Table Page
6-8 Control Register V alues for Each Configuration .........................................................6-11
6-9 Port Configuration Example .......................................................................................6-11
6-10 Port Pin States After Reset and After Example Code Execution................................ 6-12
6-11 Ports 3 and 4 Pins......................................................................................................6-14
6-12 Ports 3 and 4 Control and Status Registers...............................................................6-14
6-13 L ogic T able for Ports 3 and 4 as Open-drain I/O................................................... ..... 6 -16
6-14 Standard Output-only Port Pins..................................................................................6-17
6-15 Output-only Port Control Register ................................................... ............ ............ ... 6-17
7-1 Serial Port Signals................................................................. ....................................... 7-2
7-2 Serial Port Control and Status R egisters.............. ........................................................7-2
7-3 SP
8-1 Frequency Generator Signal ........................................................................................8-2
8-2 Frequency Generator Control and Status Registers...................................................8-2
9-1 Waveform Generator Signals .......................................................................................9-3
9-2 Waveform Generator Control and Status Registers....................................................9-3
9-3 Operation in Center-aligned and Edge-aligned Modes ................................................ 9-8
9-4 Register Updates..........................................................................................................9-8
9-5 Output Configuration .................................................................................................. 9-12
10-1 PWM Signals..............................................................................................................10-2
10-2 PWM C ontrol and Status Registers............................................................................1 0-3
10-3 PWM Output Fre quencies (F
10-4 PWM Output Alternat e Functions...............................................................................10-8
11-1 EPA Channels............................................................................................................1 1-1
11-2 EPA and Timer/Counter Signals.................................................................................11-2
11-3 EPA Control and Status Registers .............................................................................11-3
11-4 Quadrature Mode Truth Table....................................................................................11-8
11-5 Action Taken When a Valid Ed ge Oc curs ................................................................11-12
11-6 E xample EPA Control Register Sett ings for Channels 1, 3, or 5..............................11-18
12-1 A/D C onverter Pins................................... ................. ...................... ...................... ..... 1 2-2
12-2 A/D C ontrol and Status Registers.................. ................. ...................... ................... ... 12-2
13-1 Minim um Required Signals.........................................................................................13-1
13-2 I/O Port Configuration Guide......................................................................................13-2
13-3 Selecting the Watchdog Reset Interval (8XC196MH only)......................................13-13
14-1 Operating Mode Control Signals ................................................................................14-1
14-2 Operati ng Mode Control and Status Registers...........................................................1 4-2
15-1 External Memory Interface Signals.............................................................................15-1
15-2 External Memory Interface Registers .........................................................................15-4
15-3 Register Settings for Configuring External Memory Interface Signals........................15-5
15-4 BUSWID TH Signal Timing Definitions. .....................................................................15-13
15-5 READY Signal Timing Definitions.............................................................................15-20
15-6 B us-control Modes ...................................................................................................15-21
15-7 AC Timing Symbol Definitions..................................................................................15-33
15-8 External Memory Systems Must Meet These Specifications....................................15-33
15-9 Microcontrol ler M eets These Specifications .............................................................15-34
x
_BAUD Values When Using XTAL1 at 16 MHz...................................................7-14
)............. ........................... ...................... .................10-5
PWM
xvii
8XC196MC, MD, MH USER’S MANUAL
TABLES
Table Page
16-1 87C196M
16-2 Memory Protection for Normal Operating Mode.........................................................16-4
16-3 Memory Protection Options for Programming Modes ................................................16-5
16-4 UPROM Programming Values and Locations for Slave Mode...................................16-7
16-5 Example PPW_VALUE Calculations..........................................................................16-9
16-6 Pin Descriptions .......................................................................................................16-11
16-7 PMODE Values ........................................................................................................16-13
16-8 Device Signature Word and Programming Voltages................................................16-16
16-9 Slave Programming Mode Memory Map..................................................................16-17
16-10 Timing Mnemonics...................................................................................................16-24
16-11 8XC196MC/MD Auto Programming Memory Map . .................................................16-27
16-12 8XC196MH Auto Programming Memory Map.........................................................16-27
16-13 PCCB and UPROM Programming Values...............................................................16-32
A-1 Opcode Map (Left Half)......................................................... ................. ..................... A-2
A-1 Opcode Map (Right Half)................ ......................................................................... .... A-3
A-2 Processor Status Word (PSW) Flags.......................................................................... A-4
A-3 Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions......... A-5
A-4 PSW Flag Setting Symbols .........................................................................................A-5
A-5 Operand Variables ......................................................................................................A-6
A-6 Instructio n Set ... ........ .... ..... ........ .... ..... ........ .... ..... ........ ....... .. ........ ....... .. ........ ....... .. .... A-7
A-7 Instructio n Opcodes .................................................................................................. A-41
A-8 Instruction Lengths and Hexadecimal Opcodes........................................................A-47
A-9 Instruction Executio n Times (in State Times)............................................................ A-52
B-1 Signal Name Changes ................................................................................................ B-1
B-2 8XC196MC Signals Arranged by Functional Categories............................................. B-2
B-3 8XC196MD Signals Arranged by Functional Categories............................................. B-6
B-4 8XC196MH Signals Arranged by Functional Categories............................................. B-9
B-5 Description of Columns of Table B-6......................................................................... B-13
B-6 Signal Descriptions....................................................................................................B-13
B-7 Definition of Status Symbols .....................................................................................B-23
B-8 8XC196MC and MD Default Signal Conditions.........................................................B-23
B-9 8XC196MH Default Signal Conditions.......................................................................B-25
C-1 Modules and Related Registers..................................................................................C-1
C-2 Register Name, Address, and Reset Status................................................................C-2
C-3 COMP C-4 EPA C-5 EPA C-6 P C-7 P
C-8 Special-function Signals for Ports 1, 2, 5, 6............... ..... ..... .. ........ ..... .... ..... ..... ..... .... C-32
C-9 P C-10 P
C-11 Output Configurati on .................................................................................................C-65
C-12 WSR Settings and Direct Addresses for Windowable SFRs.....................................C-68
x x
x x
x
OTPROM Memory Map ...................... ....................................................16-3
x
_TIME Addresses and Reset Values............................................................C-17
x
_CON Addresses and Reset Values................................................................C-20
x
_TIME Addresses and Reset Values................................................................C-21
_DIR Addresses and Reset Values.......................................................................C-30
_MODE Addresses and Reset Values..................................................................C-31
_PIN Addresses and Reset Values.......................................................................C-33
_REG Addresses and Reset Values.....................................................................C-34
xviii
Guide to This Manual
1
CHAPT ER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC1 96MC, 8XC196M D, and 8XC196M H embedded microcontrol­lers. It is intended for use by both software and hardware designers familiar with the principles of microcontrollers. This chapter describes what you’ll find in this manual, lists other documents that may be useful, and explains how to access the support services we provide to help you com­plete your design.

1.1 MANUAL CONTENTS

This manual contai ns several chapters and appen dixes, a glossary, and an index. Thi s chapter, Chapter 1, provides an ov e rview of the manua l. Thi s section su m mariz es the conte nts of the re­maining chapters and appendixes. The remainder of this chapter describes notational conventions and terminology used throughout the manual, provides refere nc es to re late d doc ument ation, de­scribes custome r support services, and explains how to access information and assi stance .
Chapter 2 — Architectural Overvi ew — provides an over view of the device hardware. It de­scribes the core, internal timing, int ernal periphera ls, and special operati ng modes.
Chapter 3 — Programming Considerations — provides an overview of the instruction set, de­scribes general standards a nd conventions, and defines the ope rand types and addres sing mode s supported by the MCS tion set, see Appendix A.)
®
96 microcontroller family . (For additional information about the instruc-
Chapter 4 — Me m ory Par titions — describe s the a d dressa ble memory spa ce of the devi ce. It describes the mem ory partitions and explains how to use win dows to increa se the amount of memory that can be accessed with register-direct instructions.
Chapter 5 — Standard and PTS Interrupts — describes the interrupt control circuitry , priority scheme, and timing for standard and perip heral transaction server (PTS) inter rupts. It also ex­plains interrupt programming and control.
Chapter 6 — I/O Ports — describes the input/out put ports and explains how to configure the ports for input, output, or special functions.
Chapter 7 — Serial I/O (SIO) Port — describes the 8XC196M H ’s asynchronous/synchronous serial I/O (SIO) port and explains how to program it.
Chapter 8 — Frequency Generator — describes the 8XC196MD’s frequency generator and ex­plains how to configure it. For additional information and application examples, consult AP-483, Application Examples Usi ng the 8XC196MC / MD Mic rocontroller (order number 272282).
1-1
8XC196MC, MD, MH USER’S MANUAL
Chapter 9 — Waveform Generator — describes the waveform gene rator and expl ains h ow to configure it. For additional information and application examples, consult AP-483, Application Examples Using the 8XC196MC/MD Microcontroller (order number 272282).
Chapter 10 — Pulse-wi dth Modulat or — provides a funct ional overview of the pulse width modulator (PWM) mo dules, describes how to program them, and provides sample circuitry f or converting the PWM outputs to anal o g signals.
Chapter 11 — Event Processor Array (EPA) — describes the eve nt processor array, a tim­er/counter-based, high-speed input/outp ut u nit. It de scri bes t he timer/counters a n d expla ins h ow to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs .
Chapter 12 — Anal og-to-digital (A/D) Converter — provides an overview of the analog-to­digital (A/D) converter and describes how to program the converter, read the conversion results, and interface with external circuitry.
Chapter 13 — Minimum Hardware Considerations — describes options for providing the ba­sic requirements for devi ce operat ion w ithin a system , discuss es other hardware considerati ons, and describes device reset o ptions.
Chapter 14 — Spec ial Operating Modes — provides an overview of the idle, powerdown, and on-circuit emulation (ONCE ) modes and describes how to enter and exit each mode.
Chapter 15 — Interfacing with External Memory — lists the external memory signals and de­scribes the registers tha t control the exte rnal memory interface. It discusses the bus width and memory configurations, the bus-hold protocol, write-control modes, and internal wait states and ready control. Finall y, it provides timing information for the system bus.
Chapter 16 — Programming the Nonvolatile Memory — provides recommended circuits, the corresponding memory maps, and flow diagrams. It also provides procedures for auto program­ming.
Appendix A — Instruction Set Reference — provides reference information for the instruction set. It describes each instruction; defines the processor sta tus word (PSW) flags; shows the rela­tionships between instructions and PSW flags; and lists hexadecimal opcodes, instruction lengths, and execution times. (For additional information about the instruction set, see Chapter 3, “Programming Consideratio ns.”)
Appendix B — Signal Descr iptions — provides referenc e information for the device pins, in­cluding descriptions of the pin functions, reset status of the I/O and control pins, and package pin assignments.
1-2
GUIDE TO THIS MANUAL
Appendix C — Re gisters — provides a compilation of all device special-function registers (SFRs) arranged alphabeti cally by register mnemonic . It also includes tables that list the win­dowed direct addresses for all SFRs in each possible window.
Glossary — define s terms with spec ial me aning used th roughout this manual.
Index — lists key topics with page number references.

1.2 NOTATIONAL CONV ENTI ONS AND TERMINOLOGY

The following notations an d terminol ogy are used throughout this manual. The Glossary defines other terms with special meanings.
# The pound symbol (#) has either of two meanings, depending on the
context. When used wi th a signal name, the symbol means that the signal is active low. When used in an instruction, the symbol prefixes an immediate value in immediate addressing mode.
assert and deassert The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active polarity (low or high) is defined by the signal name. Active-low signals are designated by a pound symbol (#) suffix; active-high signals have no suffix. To assert RD# is to drive it low; to assert ALE is to drive it high; to deassert RD# is to drive it high; to deassert ALE is to drive it low.
clear and set The terms clear and set refer to the value of a bit or the act of giving
it a value. If a bit is c lear, its val ue is “0”; cleari ng a bit gives it a “0” value. If a bit is set, its value is “1”; settin g a bit gives it a “1” value.
instructions Instruction mnem onics are shown in upper case to av oid confusion.
In general, you may use either upper case or lower case when programming. Consult the manual for your assembl er or compiler to determine its specific req uirem ent s.
italics Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible meanings.
Vari able s in regist ers and signal names are commonly represente d by x and y, where x represents the first variable and y represents the second variable . For example, in register P x_MODE.y, x represents the variable that identifies the specific port associated with the register, and y represents the register bit variable (7:0 or 15:0). Vari ables must be replaced with the correct values when configuring or programming regi sters or ident ifyi ng signals.
1-3
8XC196MC, MD, MH USER’S MANUAL
numbers Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are represented by t heir customa ry notations. (That is, 255 is a decimal number and 1111 1111 is a binary number. In some cases, the letter B is appended to binary numbers for clarity.)
register bits Bit locations are indexed by 7:0 (or 15:0), where bit 0 is the least-
significant bit and bit 7 (or 15) is the most-significant bit. An individual bit is represented by the register name, followed by a period and the bit number. For example, WSR.7 is bit 7 of the window selection register. In some discuss ions, bit names are used.
register names Register mnemonics are shown in upper case. For example, TIMER2
is the timer 2 register; timer 2 is the timer. A register name containing a lowercase italic character represents more than one register. For example, the x in Px_REG indicate s that the register name re fers to any of the p ort data registers.
reserved bits Certain bits are described a s reserved bits. In illustrat ions, reserved
bits are indicated with a dash (—). These bits are not used in this device, but they may be used in future implementations. To help ensure that a current software design is compatible with future imple­mentations, rese rved bits should be c leared (given a value of “0”) or left in thei r de fault states, unles s ot he rwis e not ed. Do not rel y o n the values of reserved bits; conside r them undefin ed.
signal names Signal names are shown in upper case. When several signals share a
common name, an individual signal is represented by the signal name followed by a number. For example, the EPA signals are named EPA0, EPA1, EPA2, etc. Port pins are represente d by t he p ort ab bre­viation, a period, a nd the pin number (e.g., P1.0, P 1.1); a range of pins is represented by Px.y:z (e.g., P1.4:0 represents five port pins: P1.4, P1.3, P1.2, P1.1, P1.0). A pound symbol (#) appended to a signal name identifies an active-low signal.
1-4
GUIDE TO THIS MANUAL
units of measure The following abbreviations are used to represent units of measure:
A amps, amperes DCV direct current volts
ytes kilobytes
Kb
z kilohertz
kH kΩ kilo-ohms mA milliamps, milliamperes Mbytes megabytes MHz megahertz ms milliseconds mW milliwatts ns nanoseconds pF picofarads W watts V volts
µA microamps, microamperes µF microfarads µs microseconds µW microwatts
X Uppercase X (no italics) represents an unknown value or an
elevant (“don’t care”) state or condition. The value may be either
irr
or hexadecimal, depending on the context. For example,
binary 2XAFH ind
(hex) indicates that bits 11:8 are unknown; 10XXB (binary)
icates that the two least-significant bits are unknown.

1.3 RELATED DOCUMENTS

The tables in this section list additional documents that you may find useful in designing systems
corporating MCS 96 microcontrollers. These are not comprehensive lists, but are a representa-
in tive sample of relevant documents. For a complete list of available printed documents, please or-
the literature catalog (order number 210621). To order documents, please call the Intel
der literature center for your area (telephone numbers are listed on page 1-11).
1-5
8XC196MC, MD, MH USER’S MANUAL

Table 1-1. Handbooks and Product Information

Title and Description Order Number
Intel Embedded Quick Reference Guide Solution s for Embedd ed Appl icat io ns Guide Data on Dema nd Data on Dema nd
Complete set of Intel handbooks on CD-ROM.
Handboo k Set
Complete set of Intel’s product line handbooks. Contains datasheets, application notes, article reprints and other desig n informatio n on microprocessors, periph­erals, embedded controllers, memory components, single-board computers, microcommunications, software development tools, and operating systems.
Automotive Products
Application notes and article reprints on topics including the MCS 51 and MCS 96 microcon trol le r s. Docu men t s in this handb ook discuss hardware and software implementations and present helpful design techniques.
Embedded A pplications
Datasheets, architecture descriptions, and application notes on topics including flash memor y device s, netwo rkin g chips, an d MCS 51 and MCS 96 microc on­trollers. Documents in this handbook discuss hardware and software implementa­tions and present helpful design techniques.
Embedded Microcontrollers
Datasheets and architecture descriptions for Intel’s three industry-standard micro­controllers, the MCS 48, MCS 51, and MCS 96 microcontrollers.
Peripheral Components
Comprehensive information on Intel’s peripheral components, including datasheets, application notes, and technical briefs.
Flas h Memory
A collection of datasheets and application notes devoted to techniques and information to help design semiconductor memory into an application or system.
Packaging
Detailed information on the manufacturing, applications, and attributes of a variety of semiconductor packages.
Development Tools Handbook
Information on third-party hardware and software tools that support Intel’s embedded microcontrollers.
†
Included in handbook set (order num be r 231003)
fact sheet 240952 annual subscription (6 issues; Windows* version)
— ha ndbooks and product overview
†
†
(2 volume set)
†
handbook (2 volume set)
†
†
†
272439 240691
240897
231003
231792
270648
270646
296467
210830
240800
272326
AB-71, AP-125, AP-155, AR-375,
†
Included in
††
Included in
†††
Included in
1-6

Table 1-2. Application Notes, Application Briefs, and Article Reprints

Title Order Number
Using the SIO on the 8XC196MH
Designing Microcontroller Systems for Electrically Noisy Environments Oscillators for Microcontrollers
Motor Controllers Take the Single-Chip Route
Automotive Products
Embedded Applications
Automotive Products
(application brief) 272594
†††
†††
(article reprin t) 270056
handbook (order number 231792)
handbook (order number 270648)
and
Embedded Applications
handbooks
210313 230659
GUIDE TO THIS MANUAL
Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued)
Title Order Number
AP-406, AP-445, AP-449,
MCS® 96 Analog Acquisition Primer 8XC196KR Peripherals: A User’s Point of View A Comparison of the Event Processor Array (EPA) and High Speed
Input/Output (HSIO) Unit
AP-475,
Using the 8XC196NT
AP-477, AP-483, AP-700, AP-711, AP-715,
† †† †††
Low Voltage Embedded Design Application Examples Using the 8XC196MC/MD Microcontroller Intel Fuzzy Logic Tool Simplifies ABS Design EMI Design Techniques for Microcon tro llers in Auto mo ti ve Appl icat io ns Interfacing an I2C Serial EEPROM to an MCS® 96 Microcontroller
Included in
Included in
Included in
Automotive Products
Embedded Applications
Automotive Products
†
††
handbook (order number 231792)
and
†††
†
††
†
handbook (order number 270648)
Embedded Applications
handbooks

Table 1-3. MCS® 96 Microcontroller Datasheets (Commercial/Express)

Title Order Number
8XC196KR/K Q/JR/ JQ Commercia l/E xpress CHMOS Micro co ntrolle r 8XC196KT Com mercia l CHMOS Microcontro ller
†
87C196KT /87C1 96 KS 20 MHz Advan ced 16-Bit CHMOS Micro co ntrol ler 8XC196MC Industrial Motor Control Microcontroller
†
87C196M D Industrial Motor Control CHMOS Microcon tro ller 8XC196NP Commercial CHMOS 16-Bit Microcontroller
†
8XC196NT CHMOS Microcontroller with 1-Mbyte Linear Address Space 80C196NU Commercial CHMOS 16-Bit Microcontroller
†
Included in
Embedded Microcontro llers
handbook (order number 270646)
†
†
†
†
270365 270873 270968
272315 272324 272282 272595 272324 272680
270912 272266 272513 272323 270946 272459 272267 272644

Table 1-4. MCS® 96 Microcont rol ler Datasheets (Automotive)

Title and Description Order Number
87C196CA/87C196CB 20 MHz Adva nced 16-Bi t CHMOS Mi cro con tro lle r with
Integrated CAN 2.0 87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller 87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller 87C196KR/KQ, 87C196JV/JT, 87C196JR/JQ Advanced 16-Bit CHMOS
Microcontroller 87C196KT/87C196KS Advanced 16-Bit CHMOS Microcontroller 87C196KT/KS 20 MHz Advanced 16-Bit CHMOS Microcontroller
†
Included in
Automotive Products
†
† †
†
†
†
handbook (order number 231792)
272405
272529 272580 270827
270999 272513
1-7
8XC196MC, MD, MH USER’S MANUAL
This Page Left Intentionally Blank
1-
8
GUIDE TO THIS MANUAL
This Page Left Intentionally Blank
1-9
8XC196MC, MD, MH USER’S MANUAL
This Page Left Intentionally Blank
1-10
GUIDE TO THIS MANUAL
1.4.4 World Wide Web
We offer a variety o f information throug h th e World Wide Web (URL:http://www.intel.com/). Se­lect “Embedded Design Products” from the Intel home page.

1.5 TECHNICAL S UPPO RT

In the U.S. and Canada, technical support representatives are availabl e to answer your questions between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice telephone number and indicate whether you prefer a response b y phone or by fax). Outside the U.S. and Canada, please contac t your local distribut or.
1-800-628-8686 U.S. and Canada 916-356-7599 U.S. and Canada 916-356-6100 (fax) U.S. and Canada

1.6 PRODUCT LITE RAT U RE

You can order product literature from the following Intel literat ure centers .
1-800-548-4725 U.S. and Canada 708-296-9333 U.S. (from overseas) 44(0)1793-431155 Europe (U.K.) 44(0)1793-421333 Germany 44(0)1793-421777 France 81(0)120-47-88-32 Japan (fax only)
1-11
Architectural Overview
2
CHAPT ER 2
ARCHITECTURAL OVERVIE W
The 16-bit 8XC196M C, 8XC196MD, and 8XC1 96MH C HMOS m icrocontrollers are desig ned to handle high -speed calcul ations and fast input/out put (I/O) operat ions. They shar e a common architecture and instruction set with other members of the MCS
NOTE
This manual describes a family of microcontrollers. For brevity, the name 8XC196Mx is used when the discussion applies to all family members. When information applies to spe ci fic microcontrollers, individual product names are used.

2.1 TYPICAL APPLICATIONS

MCS 96 microcont rollers are t ypically use d for high-speed event control s ystems. Commerci al applications include modems, motor-control systems, printers, photocopiers, air conditioner con­trol systems, disk drives, and medical instruments. Automotive customers use MCS 96 microcon­trollers in engi ne-control systems, airba gs, suspension systems, and a ntilock braking system s (ABS).

2.2 M ICROCON TROL LER FEATURES

®
96 microcontroller family.
Table 2-1 lists the features of each member of the 8XC196Mx family.
2-1
8XC196MC, MD, MH USER’S MANUAL

T able 2-1. Features of the 8XC196Mx Product Family

OTPROM/
Device Pins
8XC196MH 84 32 K 744 52 6 2 8 8 1 8XC196MH 80 32 K 744 52 6 2 8 8 1 8XC196MH 64 32 K 744 50 6 2 7 8 1 8XC196MC 84 16 K 488 53 8 0 8 13 1 8XC196MC 80 16 K 488 53 8 0 8 13 1 8XC196MC 64 16 K 488 49 7 0 7 12 1 8XC196MD 84 16 K 488 64 12 0 9 14 1 8XC196MD 80 16 K 488 64 12 0 9 14 1
NOTES:
1. No nvol at ile memo r y is optional. The second chara ct er of the device name indicat es the prese nce and type of nonvolat ile memory. 80C196M
2. Re gist er RAM amoun ts include the 24 bytes allocat ed to core SFR s and the stack pointer.
3. The 8XC196MC and 8XC19 6MD have no serial I/O ports, but have PTS modes that allow asynchro­nous or synchronous serial communication.
4. The numb er of PWM ch annels in clud es the ou tputs fro m the PW M periph er al and the waveform gen­erator. For the 8XC196MD, it also includes the output from the frequency generator.
ROM
Bytes
(Note 1)
Register
RAM
Bytes
(Note 2)
I/O
EPA
Pins
Pins
x
= none; 83C196Mx = ROM; 87C196Mx = OTPROM.
SIO
Ports
(Note 3)
PWM
Channels
(Note 4)
A/D
Channels
External
Interrupt
Pins

2.3 FUNCTIONAL OVERVIEW

Figure 2-1 shows the majo r blocks within the m icrocontroll er. The core of the mi crocontrolle r (Figure 2-2) consists of the central processing unit (CPU) and memory controller. The CPU con­tains the register file and the register arithmetic-logic unit (RALU). A 16-bit internal bus connects the CPU to both the memory controller and the interrupt controller. An extension of this bus con­nects the CPU to the internal peripheral mo dules. In addition, an 8-bit internal bus transfers in­struction bytes from the memory controll er to the inst ruction regist er in the RALU .
2-2
ARCHITECTURAL OVERVIEW
Core
Clock and
Power Mgmt.
PWMI/O
Note: The frequency generator is unique to the 8XC196MD. The serial I/O port is unique to the 8XC196MH.
Optional
ROM
WG
Interrupt
Controller
A/DEPA

Figure 2-1. 8XC196Mx Block Diagram

CPU
Register File
RALU
Microcode
Engine
PTS
WDT
Memory Controller
Prefetch Queue
FG
Slave PC
SIO
A2798-02
Register
RAM
CPU SFRs

Figure 2-2. Block Diagram of the Core

ALU
Master PC
PSW
Registers
Address Register
Data Register
Bus Controller
A2797-01
2-3
8XC196MC, MD, MH USER’S MANUAL
2.3.1 CPU Control
The CPU is controlled by the microcode engine, which instructs the RALU to perform operations using bytes, words, or double-words from either the 256-byte lower register file or through a win- dow that directly accesses the upper register file. (See Chapter 4, “Memory Partitions,” for more information about the register file and windowing.) CPU instructions move from the 4-byte prefetch queue in the memory controller into the RALU’s instruction register. The microcode en­gine decodes the instruct i ons an d then generates the seque nce of eve nts that cause desi red fu nc­tions to occur.
2.3.2 Register File
The register file is divided into an upper and a lower file. In the lower register file, the lowest 24 bytes are allocated to the CPU’ s special-function registers (SFRs) and the stack pointer, while the remainder is available as general -purpose register RAM. The upper register file cont ains only general-purpose register RAM. The register RAM can be accessed as bytes, words, or double ­words.
The RALU accesses the upper and lower register files differently. The lower register file is always directly accessible with direct addressing (see “Addressing Modes” on page 3-5). The upper reg­ister file is accessible with direct addressing only when windowing is enabled. Windowing i s a technique that maps blocks of the upper register file into a window in the lower regist er file. See Chapter 4, “Memory Partitions,” for more information about the register file and windowing.
2.3.3 Register Arithmetic-logic Unit (RALU)
The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master pro­gram counter (PC), the processor status word (PSW), and several registers. The regist ers in the RALU are the instr uction register, a constants register, a bit-select register, a loop counter, and three temporary registers (the upper-word, lower-word, and second-operand registers).
The PSW contains one bit (PSW.1) that globally enables or disables servicing of all maskable in­terrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the state of your program. Appendix A, “Instruction Set Refe rence,” provides a detailed descript ion of the PSW.
All registers, except the 3-bit bit-select register and the 6-bit loop counter, are either 16 or 17 bits (16 bits plus a sign extension). Some of these registe rs can reduce the ALU’s workload by per­forming simple operations.
2-4
ARCHITECTURAL OVERVIEW
The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as temporary registers for many instructions. These registers have their own shift logic and are used for operations that require logical shifts, including norm alize, multiply, and divide operations. The six-bit loop counter counts repetitive shifts. The seco nd-operand register stores the second operand for two-operand instructions, including the multiplier during multiply operations and the divisor during divide operations. During subtraction operations, the output of this register is com­plemented before it is moved into the ALU.
The RALU speeds up calculations by storing constants (e.g., 0, 1, and 2) in the constants register so that they are readily available when complem enting, incre menti ng, or decreme nting bytes or words. In addition, the co nstants regi ster ge nera tes singl e-bit mas ks, base d on the bit-se lect reg­ister, for bit-test instructions.
2.3.3.1 Code Execution
The RALU performs most calculations for the microcontrol ler, but it does not use an accumula­tor. Instead it operates directly on the lower register file, which essentially provides 256 accumu-
lators. Because data does not flow through a single accumulator, the microcontroller ’s code executes faster and more efficiently.
2.3.3.2 Instruction Format
MCS 96 microcontrollers combi ne a la rge set of general-purpose registers wi th a three - operand instruction form at. This format allows a single inst ruction to spe cify two source re gisters an d a separate destination register. For example, the following instructio n multiplies two 16-bit vari­ables and stores the 32-bit result in a third variable .
MUL RESULT, FACTOR_1, FACTOR_2 ;multiply FACTOR_1 and FACTOR_2
;and store answer in RESULT ;(RESULT)←(FACTOR_1 × FACTOR_2)
An 80C186 microprocessor requires four instructions to accomplish the same operation. The fol­lowing example shows the equivalent code for an 80C186 microprocessor.
MOV AX, FACTOR_1 ;move FACTOR_1 into accumulator (AX)
MUL FACTOR_2 ;multiply FACTOR_2 and AX
MOV RESULT, AX ;move lower byte into RESULT
MOV RESULT+2, DX ;move upper byte into RESULT+2
;(AX)←FACTOR1 ;(DX:AX)←(AX)×(FACTOR_2) ;(RESULT)←(AX) ;(RESULT+2)←(DX)
2-5
8XC196MC, MD, MH USER’S MANUAL
2.3.4 Memory Interface Unit
The RALU communicates with all memory, except the register file and peripheral SFRs, through the memory controller. (It communicates with the upper register file through the memory control­ler except when windowing is used; see Chapter 4, “Memory Partitions.”) The memory controller contains the prefetch queue, the slave program counter (slave PC), address and data registers, and the bus co ntroller.
The bus controller drives t he memory bus, which consists of an internal memory bus and the ex­ternal address/data bus. The bus controller receives memory-access requests from either the RALU or the prefetch queue; queue requests always have priority. This queue is transparent to the RALU and your software.
NOTE
When using a logic analyzer to debug code, remember that instructi ons are preloaded into the prefetch queue and are not necessari l y execute d immediately aft er they are fetched.
When the bus controller receives a re q uest from the queue, it fetches the code f r om the address contained in the sl ave PC . The slave PC increa ses exec utio n speed bec ause the next inst ructi on byte is available immediately and the processor need not wait for the master PC to send the ad­dress to the memory controller. If a jump, interrupt, call, or return changes the address sequence, the master PC loads the new address into the slave PC, then the CPU flushes the queue and con­tinues processing.
2.3.5 Interru pt Ser vic e
The microcontroller’s flexible interrupt-handling system has two main components: the program­mable interrupt controll er and t he perip heral transa ction se rver (PTS). The programmabl e inter­rupt controller has a hardware priority schem e that can be modified by your software. Interrupts that go through the in terrupt controller are serviced by in terrupt service routines that you provide. The peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides high-speed, low-overhead interrupt handl ing. You can configure m ost interrupts (except NM I, trap, and unimplemented opcode) to be servic ed by the PTS instead of the interrupt contr oll er.
The PTS can transfer bytes or words, either individually or in blocks, between any memory loca­tions, manage multiple analo g-to-digi tal (A/D) conversi o ns, and can generat e puls e-wi dth mod­ulated (PWM) signals. The 8XC196MC and 8XC196MD have additional modes that allow asynchronous or synchronous serial communication. PTS interrupts have a higher priority than standard interrupts and may t emporarily suspend int errupt service routines. See Chapter 5, “Stan­dard and PTS Interrupts,” for more information.
2-6
ARCHITECTURAL OVERVIEW

2.4 INTERNAL TIMING

The clock circuitry (Figure 2-3) receives an input clock signal on XTAL1 provided b y an external crystal or oscillator and divi des the fre quency by two. T he cl ock generato rs accept the divided input frequency from the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2. These signals are active when high.
.
Disable Clock Input
(Powerdown)
F
XTAL1
XTAL2
XTAL1
Disable
Oscillator
(Powerdown)
Divide-by-two
Circuit
Clock
Generators
Disable Clocks
(Powerdown)
Peripheral Clocks (PH1, PH2) CLKOUT CPU Clocks (PH1, PH2)
Disable Clocks (Idle, Powerdown)
NOTE: The CLKOUT pin is unique to the 8XC196MC and MD.
A3115-02

Figure 2-3. Clock Circuitry

The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-4). The clock circuitry routes separate internal clock signals to the CPU and the peripherals to provide flexibil­ity in power manageme nt. (“Reducing Powe r Consumption” on pa ge 14-3 des cribes the p ower management modes.) The 8XC 196MC and 8XC196M D microcontrol lers output the CLKOUT signal on the CLKOUT pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a delayed version of the internal CLKOUT signal. This delay vari es with tem­perature and voltage.
The 8XC196MH mic rocontroller has no CLKOUT pin. If your 8XC1 96MH design requires a system clock, we recommend that you use an external oscillator and add external logic to generate the system clock signal.
2-7
8XC196MC, MD, MH USER’S MANUAL
XTAL1
T
XTAL1
1 State Time
PH1
PH2
CLKOUT
T
XTAL1
1 State Time
Phase 1 Phase 2
Phase 1 Phase 2
A0114-04

Figure 2-4. Internal Clock Phases

The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic time unit known a s a state time or state. Tab le 2-2 l ists state time durations at var ious frequencies.

Table 2-2. State Times at Various Frequencies

F
(Frequency Input to the
Divide-by-two Circu it)
XTAL1
State Time
8 MHz 250 ns 12 MHz 167 ns 16 MHz 125 ns
The following formulas calculate the frequency of PH1 and PH2, the duration of a state time, and the duration of a clock period (T
F
XTAL1
PH1 (in MHz)
------- ----------- -
PH2== State Time (in µs)
2
XTAL1
).
2
----- ----------- -- -
= T
F
XTAL1
XTAL1
=
1
------- ------------
F
XTAL1
Because the microcontroll er can operate at many frequencies, this manua l defines time require­ments (such as instruction exec ution times ) in terms of state ti mes rather tha n spec ific m easu re­ments. Datasheets list AC characteri stics in terms of clock periods (T
XTAL1
or T
OSC
).

2.5 INTERNAL PERIPHERALS

The internal peripheral modules provide special functions for a variety of applications. This sec­tion provides a brief description of the periphera ls; su bsequent chapters descri be them in detail.
2-8
ARCHITECTURAL OVERVIEW
2.5.1 I/O Ports
The 8XC196Mx microcontrollers have seven I/O ports, ports 0–6. The 8XC196MD has an addi­tional port, port 7. Individual port pins are multiplexed to serve as standard I/O or to carry special­function signals associ ated w ith an on-chip peri pheral or an off-chip component. If a particula r special-function s ignal is not use d in an appli ca tion, the as soci ated pi n c an be individual l y con­figured to serve as a standard I/O pin. Ports 3 and 4 are exceptions; they are controlled at the port level, not at the pin level. When the bus controller needs to use the address/data bus, it takes con­trol of the ports. When the address/data bus is idle, you can use the ports for I/O.
Port 0 is an input-only port that is also the analog input for the A/D converter. On the 8XC196MH, port 0 provides two pins for the EPA. On the 8XC196MC and 8XC196MD, port 1 is also an input­only port that provides analog inputs for the A/D converter. On the 8XC196MH, port 1 is a bidi­rectional port that shares pins wit h the seria l I/O port.
Port 2 is a s tandard, bidirectional I/O port th at provides p ins for the EP A and timers. Port 7, which is unique to the 8XC196MD, is a standard, bidirectional I/O port that provides additional pins for the EP A and also provides pins for the frequency generator. Por ts 3, 4, and 5 are memory-mapped, bidirectional I/O ports. Ports 3 and 4 serve as the external address/data bus, while port 5 provides bus-control signals. Port 6 is a standard, output-only port that provides pins for the puls e-width modulator and waveform generator. Chapter 6, “I/O Ports,” describes the I/O ports in more detail.
2.5.2 Seria l I/O (SIO) P ort
The 8XC196MH microcontroller has a two-channel serial I/O port that shares pins with ports 1 and 2. (The 8XC196MC and 8XC196MD have no serial I/O ports, but have PTS modes that allow asynchronous or synchronous serial communication. See Chapter 5, “Standard and PTS Inter­rupts,” for more information.) The serial I/O (SIO) port is an asynchronous/synchronous port that includes a universal asynchronous receiver and transmitter (UART ). The UART has two synchro­nous modes (modes 0 and 4) and three asynchronous modes (modes 1, 2, and 3) for both trans­mission and recepti on. The a sy nchr onous modes are full duplex, meaning that they can transmit and receive data simultaneously. The receiver is buffered, so the reception of a second byte can begin before the first byte is read. The transmitter is also buffered, allowing continuous transmis­sions. The SIO port has two channels (channels 0 and 1) with identical signals and regist ers. See Chapter 7, “Seria l I/O (SIO ) Port,” for details.
2-9
8XC196MC, MD, MH USER’S MANUAL
2.5.3 Event Processor Arra y (EPA) and Timer/Counters
The event processor array (EPA) performs high-speed input and output functions associated with its timer/counte rs. In t he input mode, the EPA monitors an input for signal tra nsitions. When an event occurs, the EPA records the timer value assoc iated with it. This is a capture event . In the output mode, the EPA monitors a timer until its value matches tha t of a stored time value . When a match occurs, the EPA triggers an outp ut event, whic h can se t, clear, or toggle an outp ut pin. This is a compare event. Both capture and compare events can initiate interrupts, which can be serviced by either the inte rrupt controller or the PTS.
Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or ex­tern ally. Each t imer/ counte r is calle d a timer if it is clocked internally and a counter if it is clo cked externally. See Chapter 11, “Event Processor Array (EPA),” for additional information o n the EPA and timer/counters.
2.5.4 Pulse-width M od ul ator (PWM )
The output w aveform from each P WM channel is a variable duty-cycle puls e. Several type s of motors require a PWM waveform for most e fficient operat ion. When filtered, the P WM wa ve­form produces a DC level that can change in 256 steps by varying the duty cycle. The number of steps per PWM period is also programmable (8 bits). See Chapter 10, “Pulse-widt h Modulator,” for more information.
2.5.5 Frequency Gen erato r
The 8XC196MD has a peripheral not f ound on other 8XC19 6Mx microcontrollers — the fre­quency generator . This peripheral produces a waveform with a fixed duty cycle (50%) and a pro­grammable freq uency (ra n ging from 4 kHz to 1 M Hz with a 16 MHz in p ut clock ). See Chapte r 8, “Frequency Generato r,” for details.
2.5.6 Waveform Generator
A waveform generator simplifie s the task of generating synchronized, pulse-w idth modulated (PWM) outputs. Thi s waveform generator is opti mized for motion c ontrol appli cations such a s driving 3-phase AC induction motors, 3-phase DC brushless motors, or 4-phase stepping motors. The waveform generator can produce three inde pendent pai rs of compl ementary PW M o utputs, which share a com mon carrie r peri od, de ad tim e, a nd operat ing m o de. Once it is initialized, the waveform generator operates witho ut CPU interventi on unless you need to chan ge a duty cycle. See Chapter 9, “Waveform Generator,” for more information.
2-10
ARCHITECTURAL OVERVIEW
2.5.7 Analog-to-digital Converter
The analog-to-digital (A/D) converter conve rts an analog input voltage to a digital equivalent. Resolution is either 8 or 10 bits; sampl e and convert times are programma ble. Co nversions can be performed on the analog ground and r ef erence voltage, and the results can be used to calculate gain and zero-offset errors. The internal zero-offset compensation circuit enables automatic zero­offset adjustment. The A/D also has a threshold-detection mode, which can be used to generate an interrupt when a programmable threshold voltage is crossed in either direction. The A/D scan mode of the PTS facilitates automated A/D conversions and result storage. See Chapter 12, “An­alog-to-digital (A/D) Converter,” for more information.
2.5.8 Watchdog Timer
The watchdog timer is a 16-bit internal timer that resets the microcontroll er i f the softwa re fai ls to operate properly. See Chapter 13, “M inimum Hardware Considera tions,” for more informa­tion.

2.6 SPECIAL OPERATING MODES

In addition to the normal execution mode, the microcontroller operates in several special-purpose modes. Idle and powerdown modes conserve power when the microcontroller is inactive. On­circuit emulation (ONCE) m ode electrically isolates the mic rocontroller from the system, and several other modes provide programming options for nonvolatile memory. See Chapter 14, “Special Operating Modes,” for more information about idle, powerdown, and ONCE modes, and see Chapter 16, “Programming the Nonvolatile Memory, ” for detai ls about pro gramming options .
2.6.1 Reducing Power Con sump tion
In idle mode, the CPU stops executing instructions, but the peripheral clocks remain active. Pow­er consumption drops to about 40% of normal execution mode consumption. Either a hardware reset or any enabled interrupt source will bring the microcontroller out of idle mode.
In powerdown mode, all internal clocks are frozen at logic state zero and the internal oscillator is shut off. The register file and most peripherals retain their data if V
is maintained. Power con-
CC
sumption drops into the µW range.
2.6.2 Testing the Printed Circuit Board
The on-circuit emulation (ONCE) mode electrically isolates the microcontroller from the system. By invoking the ONCE mode, you can test the printed circuit board while the microcontroller is soldered onto the board.
2-11
8XC196MC, MD, MH USER’S MANUAL
2.6.3 Prog ram mi ng th e Nonvo lati le Mem or y
MCS 96 microcontrollers that have internal OTPR OM provide several programming options:
• Slave programming allows a master EPR OM programmer to program and verify one or
more slave MCS 96 microcontr ollers. Programming ven dors and Intel distribut ors typically use this mode to program a large number of microcontrollers with a custome r’s code and data.
• Auto programming allows an MCS 96 microcontroller to program itself with code and data
located in an external memory device. Customers typically use this low-cost method to program a small number of microcontrollers after development and testing are complete.
• Run-time programming allows you to program individual nonvolatile memory locations
during normal code execution, un der complet e software co ntrol. Customers typically use this mode to download a small amount of information to the microcontroller after the rest of the array has been programmed. For example, you might use run-time programming to download a unique identificat ion number to a security device.
• ROM dump mode allows you to dump the contents of the microcontroller ’s nonvolatile
memory to a tester or to a memory device (such as flash memory or RAM).
Chapter 16, “Programming the Nonvola tile Memory,” provides recommended circuits, the corre­sponding memory maps, and flow diagrams. It also provides procedures fo r auto programming.
2-12
Programming Considerations
3
CHAPT ER 3
PROGRAMMING CONSIDERATIONS
This section provides an overview of the instruction set of the MCS® 96 microcontrollers and of­fers guidelines for program development. For detailed information ab out specific instructions, see Appendix A.
3.1 OVERVIEW OF THE
INSTRUCTION SET
The instructi on se t supports a variety of operand types likely to be useful in control application s (see Table 3-1).
NOTE
The operand-type variables are shown in all capitals to avoid confusion. For example , a BYT E is an unsigned 8-bit variable in an instruction, while a byte is any 8-bit unit of data (either signed or unsigned).

Table 3-1. Operand Type Definitions

Operand Type
BIT 1 No True (1) or False (0) As components of bytes BYTE 8 No 0 through 2 SHORT-INTEGER 8 Yes –2
WORD 16 No 0 through 2
INTEGER 16 Yes –2
DOUBLE-WORD (Note 1)
LONG-INTEGER (Note 1)
NOTES:
1. The 32-bit variables are supported only as the operand in shift operations, as the dividend in 32-by­16 divide opera ti ons, and as the produ ct of 16-b y- 16 multip ly operations.
2. F or consistency with thir d-party software , you should adopt the C prog ramming conventio ns for addressing 32-bit operands. For more information, refer to page 3-9.
No. of
Signed Possible Values
Bits
7
through +27–1
(–128 through +127)
(0 through 65,535)
15
through +215–1
(–32,768 through +32,767)
32 No 0 through 2
32 Yes –2
(0 through 4,294,967,295)
31
through +231–1 (–2,147,483,648 through +2,147,483,647)
8
–1 (0 through 255) None
16
–1
32
–1
Addressing
Restrictions
None
Even byte address
Even byte address
An address in the lowe r register file that is evenly divisible by four (Note 2)
An address in the lowe r register file that is evenly divisible by four (Note 2)
3-1
8XC196MC, MD, MH USER’S MANUAL
Table 3-2 lists the equivalent operand-type names for both C programming and assembly lan­guage.

Table 3-2. Equivalent Operand Types for Assembly and C Programming Languages

Operand Types Assembly Language Equivalent C Programming Language Equivalent
BYTE BYTE unsigned char
SHORT-INTEGER BYTE char
WORD WORD unsigned int
INTEGER WORD int DOUBLE-WORD LONG unsigned long LONG-INTEGER LONG long
3.1.1 BIT Operands
A BIT is a single-bit variable that can have the Boolean values, “true” and “false.” The architec­ture requires that BITs be addressed as components of BYTEs or WORDs. It does not support the direct addressing of BITs.
3.1.2 BYTE Operands
8
A BYTE is an unsigned, 8-bit variabl e that can take on values from 0 through 255 (2
–1). Arith­metic and relational operators can be applied to BYTE operands, but the result must be interpret­ed in modulo 256 arithmetic. Logical operations on BYTEs are applied bitwise. Bits within BYTEs are label ed from 0 to 7; bit 0 is the least-sig nificant bit. There are no alignme nt restric ­tions for BYTEs, so they may be plac ed anywhere in the address space.
3.1.3 SHORT-INTEGER Operands
7
A SHORT-INTEGER is an 8-bit, signed variable that can take on values from –128 (–2
7
+127 (+2
–1). Arithmetic operations that generate results outside the range of a SHORT-
) through
INTEGER set the overflow flags in the processor status word (PSW). The numeric result is the same as the result of the equivalent operation on BYTE variables. There are no alignment restric­tions on SHORT-INTEGERs, so they may be placed anywhere in the address space.
3.1.4 WORD Operands
16
A WORD is an unsigned, 16-bit variable that can take on values from 0 through 65,535 (2
–1). Arithmetic and relational operators can be applied to WORD operands, but the result must be in­terpreted in modulo 65536 arithmetic. Logical operations on WORDs are appl ied bitwise. Bits within WORDs are labeled from 0 to 15; bit 0 is the least-significant bit.
3-2
PROGRAMMING CONSIDERATIONS
WORDs must be aligned at even byte boundaries in the address space. The least-significant byte of the WORD is in the even byte address, and the most-significant byte is in the next higher (odd) address. The address of a WORD is that of its least-significant byte (the even byte address). WORD operations to odd addresses are not guaranteed to operate in a consistent manner.
3.1.5 INTEGER Operands
15
An INTEGER is a 16-bit, si gned variable that can t ake on values from –32,768 ( –2
15
+32,767 (+2
–1). Arithmetic operations that generate results outside the range of an INTEGER
) through
set the overflow flags in the processor status word (PSW). The nume ric result is the same as the result of the equivalent operati on on WORD varia ble s.
INTEGERs must be aligned at eve n byte boundaries in the address space. The leas t-sig nificant byte of the INTEGER is in the even byte address, and the most-significant byte is in the next high­er (odd) address. The address of an INTEGE R is that of its least-significa nt byte (the even byte address). INTEGE R operations to odd address es are not guaranteed t o operate in a consistent manner.
3.1.6 DOUBLE-WORD Operan ds
A DOUBLE-WORD is an unsigned, 32-bit variable that can take on values from 0 through
32
4,294,967,295 (2
–1). The architecture directly supports DOUBLE-WORD opera nds only as the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations. For these ope rations, a DOUBL E-WOR D vari abl e must reside in the lower registe r file and must be aligned at an address t hat is eve nly divisibl e by four. The address of a DOUBLE-WORD is that of its least-significant byt e (the even byte address). The least-significant word of the DOUBLE-WORD is always in the lower address, even when the data is in the stack. This means that the most-significant word must be pushed into the stack first.
DOUBLE-WORD operations that are not directly supported can be ea sil y im plemen ted with two WORD operations. For example, the following sequences of 16-bit operations perform a 32-bit addition and a 32-bit subtraction, respective ly.
ADD REG1,REG3 ; (2-operand addition) ADDC REG2,REG4
SUB REG1,REG3 ; (2-operand subtraction) SUBC REG2,REG4
3-3
8XC196MC, MD, MH USER’S MANUAL
3.1.7 LONG-INTEGE R Ope rand s
A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648
31
) through +2,147,483,647 (+231–1). The architecture directly supports LONG-INTEGER
(– 2 operands only as the o perand in shi ft operat ions, a s the divi dend in 32-by-16 divide operations, and as the product of 16-by-16 multiply operations. For these operations, a LONG-INTEGER variable must reside in the lower register file and must be aligned at an address that is evenly di­visible by four. The addres s of a LONG-INTEGER is that of its least-significant byt e (the e ven byte address).
LONG-INTEGER operations that are not directly suppor ted can be easily implemented with two INTEGER operations. See the example in “DOUBLE-WORD O perands” on page 3-3.
3.1.8 Converting Operands
The instruction set supports conversions between the operand types. The LDBZE (load byte, zero extended) instruction converts a BYTE to a WORD. CLR (clear) converts a WORD to a DOUBLE-WORD by clea ring (writing zeros to) the upper WORD of the DO UBLE-WORD. LDBSE (load byte, sign extended) convert s a SHORT-INTE GER into an INT EGE R. EXT (sign extend) converts an INTEGER to a LONG-INTEGER.
3.1.9 Conditional Jumps
The instructio ns for a ddit ion, subtraction, an d c ompari s on do not distinguish bet wee n unsi g ned (BYTE, WORD) and signed (SHORT-INTEGER, INTEGER) operands. However, the condition­al jump instructions allow you to treat the results of these operations as signed or unsigned quan­tities. For example, the CMP (compare) instruction is used to compare both signed and unsigned 16-bit quantities. Following a compare operation, you can use the JH (jump if higher) instruction for unsigned operands or the JGT (jump if greater than) instruction for signed operands.
3.1.10 Floating Point Operations
The hardware does not directly support operations on REAL (floating point) variables. Those op­erations are supported by floating point libraries from third-party tool vendors. (See the Develop- ment Tools Handbook.) The performance of these operations is significantly improved by the NORML instruction and by the sticky bit (ST) flag in the pr ocessor status word (PSW). The NORML instruction normalizes a 32-bit variable; the sticky bit (ST) flag can be used in conjunc­tion with the carry (C) flag to achieve finer resolution in roundin g.
3-4
PROGRAMMING CONSIDERATIONS

3.2 ADDRESSING MODES

The instruction set uses four basic addressing modes:
• direct
• immediate
• indirect (with or without autoincrement)
• indexed (short-, long-, or zero-indexed)
The stack pointer ca n be used with indirect addressin g to access the top of the stac k, and it can also be used with short-indexed addressin g to access data within the stack. The zer o register can be used with long-indexed addressing to access any memory location.
An instruction can contain only one immediate, indirect, or indexed reference; any remaining op­erands must be direct references.
This section describes the addressing modes as they are handled by the hardware. An understand­ing of these details will help programmers to take full advantage of the architecture. The assembly language hides some of the details of how these addres sing modes work. “Assembl y Language Addressin g Mode Selectio ns” on page 3-9 describes how the assembl y language handles direct and indexed addressing modes.
The examples in this section assume that temporary registers are defined as shown in this seg ment of assembly code an d describe d in Table 3-3.
AL: DSB 1 BL: DSB 1 CL: DSB 1 DL: DSB 1 AX: DSW 1 BX: DSW 1 CX: DSW 1 DX: DSW 1 THISVAR: DSW 1
Oseg at 1ch
3-5
8XC196MC, MD, MH USER’S MANUAL

Table 3-3. Definition of Temporary Registers

Temporary Register Description
AX word-ali gned 16-bit registe r; AH is the high byte of AX and AL is the low byte BX word-ali gned 16-bit registe r; BH is the high byte of BX and BL is the low byte CX word-align ed 16-b it reg ister; CH is the high byte of CX and CL is the low byte DX word-align ed 16-b it reg ister; DH is the high byte of DX and DL is the low byte
3.2.1 Direct Addressing
Direct addressing directly accesses a location in the 256-byte lower register file, without involv­ing the memory controller. Windowing allows you to remap other sections of memory into the lower register file for direct access (see Chapter 4, “Memory Partitions,” for details). You specify the registers as operands within the instruction. The register addresses must conform to the align­ment rules for the operand type. Depending on the instruction, up to three registers can take part in a calculation. The following instr uctions use direct add ressin g:
ADD AX,BX,CX ; AX ← BX + CX ADDB AL,BL,CL ; AL ← BL + CL MULB AX,BL ; AX ← AX × BL INCB CL ; CL ← CL + 1
3.2.2 Immediate Addressing
Immediate addressing mode a ccepts one immedia te value as an operand in the instruc tion. You specify an immediate value by preceding it with a number symbol (#). An instruction can contain only one imme dia te val ue; t he remaining o perands must be dire ct refe rence s. The foll owing in­structions use immediate addressing:
ADD AX,#340 ; AX ← AX + 340 PUSH #1234H ; SP ← SP - 2
DIVB AX,#10 ; AL ← AX/10
; MEM_WORD(SP) ← 1234H ; AH ← AX MOD 10
3.2.3 Indirect Addressi ng
The indirect addressing mode accesses an operand by obtaining it s address from a WORD regis­ter in the lower register file. Y ou specify the register containing the indirect address by enclosing it in square brackets ([ ]). The indirect address can refer to any location within the address space, including the register file. The regi ster that contains the indirect address must be word-aligne d, and the indirect address must conform to the rules for the operand type. An instruction can contain only one indirect reference; any remaining operands must be direct references. The following in­structions use indirect addressing:
LD AX,[BX] ; AX ← MEM_WORD(BX)
3-6
PROGRAMMING CONSIDERATIONS
ADDB AL,BL,[CX] ; AL ← BL + MEM_BYTE(CX) POP [AX] ; MEM_WORD(AX) ← MEM_WORD(SP)
3.2.3.1 Indirect Addressin g with Autoincrement
; SP ← SP + 2
Y ou c an choose to automatically increment the indirect address after the current access. Y ou spec­ify autoincrementi ng by adding a plus sign (+) to the end of the indirect reference. In this case, the instruction automatically increments the indirect address (by one if the destination is an 8-bit register or by two if it is a 16-bit register). When your code is assembled, the assembler automat­ically sets the least-significa nt bit of the indirec t address register. The following instructions use indirect addressing with autoincrement:
LD AX,[BX]+ ; AX ← MEM_WORD(BX) ADDB AL,BL,[CX]+ ; AL ← BL + MEM_BYTE(CX) PUSH [AX]+ ; SP ← SP - 2
3.2.3.2 Indirect Addressing with the Stack Pointer
; BX ← BX + 2 ; CX ← CX + 1 ; MEM_WORD(SP) ← MEM_WORD(AX)
; AX ← AX + 2
You can also use indirec t addressi ng to acces s the top of the sta ck by using the stac k pointer a s the WORD register in an indirect reference. The following instruction us es indirect addressing with the stack pointer:
PUSH [SP] ; duplicate top of stack
; SP ← SP + 2
3.2.4 Indexed Add ressi ng
Indexed addressing calcula tes an address by adding an offset to a base ad dress. There are three variations of indexed addressing: short-indexed, long-indexed, and zero-indexed. Both short- and long-indexed addressing are use d to a ccess a specific element wi thi n a st ruct ure. Short-indexed addressing can access up to 255 byte locations, long-indexed addressing can access up to 65,535 byte locations, and zero-indexed addressing can access a single location. An instruction can con­tain only one indexed reference; any remaining operands must be direc t reference s.
3.2.4.1 Short-indexed Addressing
In a short-indexed instruction, you specify the offset as an 8-bit constant and the base address as an indirect address register (a WORD). The following instructions use short-indexed addressing.
LD AX,12H[BX] ; AX ← MEM_WORD(BX + 12H) MULB AX,BL,3[CX] ; AX ← BL × MEM_BYTE(CX + 3)
3-7
8XC196MC, MD, MH USER’S MANUAL
The instruction LD AX,12H[BX] loads AX with the contents of the memory location that resides at address BX+12H. That is, the instruct ion adds the c onstant 12H (the offset) to the contents o f BX (the base address), then loads AX with the conte nts of the resultin g address. For example, if BX contains 1000H, then AX is loaded with the contents of location 1012H. Short-indexed ad­dressing is typi cally used to a cc ess elem ent s in a struc ture, whe re BX co nta ins the base addres s of the structure and the constant (12H in this example) is the offset of a specific element in a struc­ture.
You can also use the stack pointer in a short-in dexed instruction to access a particul ar location within the stack, as shown in the following instruct i on.
LD AX,2[SP]
3.2.4.2 Long-indexed Addressing
In a long-indexed instructio n, you specify the ba se address as a 16-bit vari able and the offset a s an indirect address register (a WOR D). The followi ng instruct ions use long-indexe d addressing.
LD AX,TABLE[BX] ; AX ← MEM_WORD(TABLE + BX) AND AX,BX,TABLE[CX] ; AX ← BX AND MEM_WORD(TABLE + CX) ST AX,TABLE[BX] ; MEM_WORD(TABLE + BX) ← AX ADDB AL,BL,LOOKUP[CX] ; AL ← BL + MEM_BYTE(LOOKUP + CX)
The instruction LD AX, T ABLE[BX] loads AX with the contents of the memory location that re­sides at address TABLE+B X. That is, the instructi on adds the contents of BX (the offset) to the constant TABLE (the base address), then loads AX with the contents of the resulting address. For example, if TABLE equals 4000H and BX contains 12H, then AX is loaded with the contents of location 4012H. Long-indexed addressing is typi cally use d to access elements in a table, where TABLE is a constant tha t is the ba se a ddre ss of the struct u re and B X is the sc aled o ffset (n × el­ement size, in bytes) into the str ucture .
3.2.4.3 Zero-indexed Addressing
In a zero-indexed instructi on, you specif y the add ress as a 16-bit va ria ble; the offset is zero, a nd you can express it in one of three ways: [0], [ZERO_REG], or nothing. Each of the following load instructions loads AX with the contents of the variable THISVAR.
LD AX,THISVAR[0] LD AX,THISVAR[ZERO_REG] LD AX,THISVAR
The following instructio ns also use zero-indexed ad dressin g:
ADD AX,1234H[ZERO_REG] ; AX ← AX + MEM_WORD(1234H) POP 5678H[ZERO_REG] ; MEM_WORD(5678H) ← MEM_WORD(SP)
3-8
; SP ← SP + 2
PROGRAMMING CONSIDERATIONS

3.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS

The assembly language simplifies the choice of addressing modes. Use these features wherever possible.
3.3.1 Direct Addressing
The assembly la nguage chooses betwee n direct and zero-indexed addressing depending on the memory location of the operand. Simply refer to the operand by its symbolic name. If the operand is in the lower regis ter file, the asse mbly language choose s a direct reference . If the ope rand is elsewhere in memory, it chooses a zer o-indexed reference.
3.3.2 Indexed Add ressi ng
The assembly language chooses betw een short-indexe d an d long-indexed ad dressing depending on the value of the index expression. If the value can be expressed in eight bits, the assembly lan­guage chooses a short-indexed reference. If the value is greater than eight bits, it chooses a long­indexed reference.

3.4 SOFTWARE STANDARDS AND CONVENTIONS

For a software project of any size, it is a good idea to develop the program in mo dules and to es­tablish standards that control communication between the modules. These standards vary with the needs of the final application. However, all standards must include some mechanism for passing parameters to procedures and returning results from procedures. We recommend that you use the conventions adopted by the C programming language for procedure linkage. These standards are usable for both the assembly language and C programming environments, and they offer compat­ibility between these environments.
3.4.1 Using Registers
The 256-byte lower register file contains the CPU special-function registers and the stack pointer. The remainder of the lower register file and all of the upper register file is available for your use. Peripheral special-function registers (SFRs) and memory-mapped SFRs reside in higher memory . The peripheral SFRs can be windowed into the lower register fi le for direct access. M emory­mapped SFRs cannot be windowed; you must use indirect or indexed addressing to access them. All SFRs can be operated on as BYT Es or WORDs, unless otherwi se specified. See “Special­function Registers (SFRs)” on page 4-4 a nd “Register File” on page 4-9 for more information.
3-9
8XC196MC, MD, MH USER’S MANUAL
To use t hese re gisters effectively, you must have some overall strategy for alloc ating the m. The C programming language adopts a simple, effective strategy. It allocates the eight bytes beginning at address 1CH as temporary storage and treats the remaining area in the register file as a segment of memory that is allocated as required.
NOTE
Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs. Also, because some SFRs are cleared when read, consider the implications of using an SFR as an operand in a read-modify-write instructi on (e.g., XORB ).
3.4.2 Addressing 32-bit Operands
The 32-bit operands (DOUBL E-WORDs and LONG-INTE GERs) are formed by t wo adjacent 16-bit words in m emory. The least-significant word of a DOUBLE-WORD is always in the lower address, even when the data is in the stack (which means that the most-si gni fic ant word must be pushed into the stack first). The address of a 32-bit operand is that of its least-signifi ca nt b yte.
The hardware supports the 32-bit data types as operands in shift operations, as divi dends of 3 2­by-16 divide operations, and as products of 16-by-16 multiply operations. For these operations, the 32-bit operand must reside in the lower register file and must be aligned at an address that is evenly divisible by four.
3.4.3 Linking Subroutines
Parameters are passed to subroutines via the stack. Parameters are pushed into the stack from the rightmost parameter to the left. The 8-bit parameters are pushed into the stack with the high-order byte undefined. The 32 -bit parameters are p ushed into the stack as two 16-bit values; the most­significant hal f of the parame ter is pushe d into the st ack first. As an example, c onsider the fol­lowing procedure:
void example_procedure (char param1, long param2, int param3);
When this procedure executes at run-time, the stack will contain the parameters in the following order:
param3 low word of param2 high word of param2 undefined;param1 return address ← Stack Pointer
3-10
PROGRAMMING CONSIDERATIONS
If a procedure returns a value to the calling code (as opposed to modifying more global variables), the result is returned in the temporary storage space (TMPREG0, in this example) starting at 1CH. TMPREG0 is viewed as either a n 8-, 16-, o r 32bit variable, dependi ng on the type o f the proce­dure.
The standard calling convention adopte d by the C programming language has several key fea­tures:
• Procedure s can alwa ys assume that the eight bytes of registe r file mem ory startin g at 1CH
can be used as temporary storage within the body of the procedure.
• Code that calls a procedure must assume that the procedure modifies the e ight bytes of
register file memory starting at 1CH.
• Code that calls a procedure m ust assume that the procedure mo difies the processor status
word (PSW) condition flags because procedures do not save and restore the PSW.
• Function results from procedures are always returned in the variable TMPREG0.
The C programming language allows the definitio n of i nterrupt p rocedures, whi ch are exe cute d when a predefined interrupt request occ urs. Interrupt procedures do not conform to the rules o f normal procedures. Parameters c annot be passed to these procedures and they cannot return re­sults. Since interrupt procedures can execute essential ly a t any t i me, t hey must save and restore both the PSW and TMPREG0.

3.5 SOFTWARE PROTE CTI ON FEATU RES AND GUI DELINES

The device has several features to assist in recoverin g from hardware and software errors. The unimplemented opcode interrupt provides protection from executing unimplemented opcodes. The hardware reset instruction (RST) can cause a reset if the program counter goes out of bounds. The RST instruction opcode is FFH, so the processor will reset itself if it tries to fetch an instruc­tion from unprogrammed locations in nonvolatile memory or from bus lines that have been pulled high. The watchdog timer (WDT) can also reset the device in the event of a hardware or software error .
We recommend that you fill unused areas of code with NOPs and perio dic jumps to an error rou­tine or RST instruction. This is particularly important in the code surrounding lookup t ables, s ince accidentally exec uting from lookup tables will cause undesired resul ts. Wherever space allows, surround each table with seven NOPs (because the longest device instruction has seven bytes) and a RST or a jump to an error routine. Since RST is a one-byte instruction, the NOPs are unnece s­sary if RSTs are used instead of jumps to an error routine. This will help to ensure a speedy re­covery from a software error.
3-11
8XC196MC, MD, MH USER’S MANUAL
When using the watchdog timer (WDT) for software protection, we recommend that you reset the WDT from only one place in code, reducin g the chance of an undesire d WDT reset. The sec ti on of code that resets the WDT should monitor the other code sections for proper operation. This can be done by checki ng variables to make sure they are wi thin reas onable value s. Simply usin g a software timer to reset the WDT every 10 millisec onds will provide protection only for cata­strophic failures.
3-12
Memory Partitions
4
CHAPT ER 4
MEMORY PARTITIONS
This chapter describes the address space, its major partitions, and a windowing technique for ac­cessing the upper register file and peripheral SFRs with regist er-direct instr uctions.

4.1 MEMORY PARTITIONS

Table 4-1 is a memory map of the 8XC196Mx devices. The remainder of this section describe s the partitions.
4.1.1 External Devi ces (Memo ry or I/O )
Several partitions are assigned to external devices (see Table 4-1). Data can be sto red in any part of this memory. Chapter 15, “Interfacing with External Memory ,” describes the external memory interface and shows examples of external mem ory configurations. These partitions can also be used to interface with external peripherals connected to the address/data bus.
4.1.2 Prog ram and Special-purpose Me m ory
Internal nonv o latil e me mory is an optional component of the 8XC196Mx devices. Va rious devic­es are available with masked ROM, EPROM, QROM, or OTPROM. Please consult the datasheets in the Embedded Microcontrollers databook for details.
If present, the nonvolatile memory occupies the special-purpose memory and program memory partitions (loca tions 2 000H and above; see Table 4-1 on page 4-2). The E A# signa l control s ac­cess to these m emory pa rtitio ns. Accesse s to these part itions are di rected to i nterna l memo ry if EA# is held high and to external memory if EA# is held low. For devices without i nte rnal non­volatile memory, the EA# signal must be tied low. EA# is latched at reset.
4-1
8XC196MC, MD, MH USER’S MANUAL

Table 4-1. Memory Map

Device and
Hex Address
Range
MC, MD MH
FFFF
6000
5FFF
2080
207F
2000
1FFF 1FE0
1FDF 1F00
1EFF
0200
01FF
0100
00FF
0000
NOTES:
1. After a reset, the device fetches its first instruction from 2080H.
2. The content or function of these locations may change in future device revisions, in which case a pro-
FFFF
External device (memory or I/O) connecte d to the
A000
address/data bus
9FFF
Program memo ry (in ter na l nonvola ti le or exte rna l
2080
memory); see Note 1.
207 F
Special-purpose memory (internal nonvolatile or
2000
external memory)
1FFF
Memory-mapped SFRs Indirect or indexed
1FE0
1FDF
Peripheral SFRs
1F00
1EFF
External device (memory or I/O) connecte d to the
0300
address/data bus (future SFR expansion; see Note 2)
02FF
Upper register file (general-purpose register RAM)
0100 00FF
Lower register file (general-purpose register RAM,
0000
stack pointer, and CPU SFRs)
gram that relie s on a locatio n in this rang e migh t not function properl y.
Description Addressing Modes
Indirect or indexed
Indirect or indexed
Indirect or indexed
Indirect, indexed, or windowed direct
Indirect or indexed Indirect, indexed, or
windowed direct Direct, indirect, or indexe d
4.1.3 Prog ram Memory
Program memory oc cupies a memory p art ition beginning at 208 0H. (See Table 4-1 for the ending address for each devic e.) This enti re parti tion is avai lable f or storing executabl e code and dat a. The EA# signal control s acce ss to program memory. Accesses to this address range are directed to internal memory if EA# is held high and to external memory if EA# is held low. For devices without internal nonvolatile memory, the EA# signal must be tied low. EA# is latched at reset.
NOTE
We recommend that you write FFH (the opcode fo r the RST instruction) to unused program memory locations. This causes a device reset if a program unintentional ly begins to exec ute in unused mem o ry.
4-2
MEMORY PARTITIONS
4.1.4 Special-purpose Memory
Special-purpose memory resides in locations 2000–207FH (Table 4-2). It contains seve ral re­served memory locations, the c hip configuratio n bytes (CCBs), and ve ctors for both peri pheral transaction server (PTS) and standard interrupts. Accesses to this address range are directed to internal memory if EA# is held high and to external memory if EA# is held low . For devices with­out internal nonvolatile memory, the EA# signal must be tied low. EA# is latched at reset.

Table 4-2. Special-purpose Memory Addresses

Hex Address Description
207F 205E
205D
2040
203F
2030
202F
2020
201F Reserved (must contain 20H) 201E Reserved (must contain FFH) 201D Reserve d (must contain 20H) 201C Reserved (must contain FFH) 201B Reserved (must contain 20H) 201A CCB1
2019 Reserved (must contain 20H)
2018 CCB0
2017 2014
2013
2000
Reserved (each byte must contain FFH)
PTS vectors
Upper interrupt vectors
Security key
Reserved (each byte must contain FFH)
Lower interrupt vectors
4.1.4.1 Reserved Memory Locations
Several memory locations are reserved for testing or for use in future products. Do not read or write these locations exce pt to initialize the m. The function or contents of thes e locations may change in future revisions; software t hat uses reser ved locations may not functio n properly. Al­ways initialize reserved locati ons to the values listed in Table 4-2.
4.1.4.2 Interrupt and PTS Vectors
The upper and lower interrupt vectors contain the addresses of the interrupt service routines. The peripheral transactio n server (PTS) vectors conta in the addresse s of the PTS control bloc ks. See Chapter 5, “Standard and PTS Interrupts, ” for more information on interrupt and PTS vectors.
4-3
8XC196MC, MD, MH USER’S MANUAL
4.1.4.3 Security Key
The security key prevents unauthorized programming access to the nonvolatile memory. See Chapter 16, “Programming the Nonvolatile Memory,” for details.
4.1.4.4 Chip Configuration Bytes (CCBs)
The chip configurat ion bytes (CCBs) s pecify the operatin g environment. They specif y the bus width, bus-control mode, and wait states. They also control powerdown mode, the watchdog tim­er, and nonvolatile memory protection.
The CCBs are the first bytes fetched from memory when the device leaves the reset state. The post-reset seque nce loa ds the C C Bs int o the chip configurati o n regis ters (CCRs). Once the y are loaded, the CCRs cannot be c hanged until the next device reset. Typically, the CCBs are pro­grammed once when the user program is compiled and are not redefined during normal operation. “Chip Configuration Registers and Chip Configuration Bytes” on page 15-5 describes the CCBs and CCRs.
For devices with customer-programmable nonvolatile memory, the CCBs are loaded for normal operation, but the PCCBs are loaded into the CCRs if the device is entering programming modes. See Chapter 16, “Programming the Nonvolatile Memory,” for details.
4.1.5 Special-function Registers (SFRs)
These devices have both memory-mapped SFRs and peripheral SFRs. The memory-mapped SFRs must be accesse d using indirect or indexed ad dressing modes, an d they cannot be win­dowed. The peripheral SFRs are physically located in the on-chip peripherals, and they can be windowed (see “Windowing” on page 4-12). Do not use reserved SFRs; write zeros to the m or leave them in their default sta te. When read, reserved bit s and reserved SFRs return undefi ned values.
NOTE
Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs. Also, because some SFRs are cleared when read, consider the implications of using an SFR as an operand in a read-modify-write instructi on (e.g., XORB ).
4-4
MEMORY PARTITIONS
4.1.5.1 Memory-mapped SFRs
Locations 1FE0–1FFFH contain mem o ry-mapped SFR s (se e Table 4-3). Locations in this range that are omitted from the table are reserved. The memory-ma pped SFRs must be access ed with indirect or indexed addressing modes, and they cannot be windowed. If you read a location in this range through a window, the SFR appears to contain FFH (al l ones). If y ou write a location in this range through a window, the write operation has no effect on the SFR.
The memory-mapped SFRs are accesse d through the memory controller, so instructions that op­erate on these SFRs execute as they wo uld from external memory wit h zero wait states.

Table 4-3. Memory-mapped SFRs

Ports 3, 4, 5, UPROM SFRs
Hex Address High (Odd) Byte Low (Even) Byte
1FFE P4_PIN P3_PIN 1FFC P4_REG P3_REG
• • • • • • • • • 1FF6 P5_PIN USFR 1FF4 P5_REG Reserved 1FF2 P5_DIR Reserved 1FF0 P5_MODE Reserved
4.1.5.2 Peripheral SFRs
Locations 1F00–1FDFH provide access to the peripheral SFRs. Table 4-6 on page 4-8, Table 4-6 on page 4-8, and Table 4-6 on page 4-8 list the peripheral SFRs of the 8XC196MC, 8XC196MD, and 8XC196MH, respe ctively. Locations that are omitted from the tables are reserved. The pe­ripheral SFRs are I/O control regist ers; they are ph ysically located in t he on-chip peripherals. These peripheral SFRs can be windowed and they can be addressed either as words or bytes, ex­cept as noted in the tables.
The peripheral SFRs are acce ssed directly, without using the memory controller, so instructions that operate on these SFRs execute as they would if they were operating on the register file.
4-5
8XC196MC, MD, MH USER’S MANUAL

Table 4-4. Peripheral SFRs — 8XC196MC

Port 2 SFRs EPA and Timer SFRs
Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte
1FDEH Reserved Reserved
• • • • • • • • • 1F7CH Reserved T2C ON TROL 1FD6H Reserved P2_PIN 1FD4H Reserved P2_REG 1F78H Reserved T1CONTROL 1FD2H Reserved P2_DIR 1F76H Reserved Reserved 1FD0H Reserved P2_MODE 1F74H Reserved Reserved
Waveform Generator SFRs 1F72H T1RELOAD (H) T1RELOAD (L)
Address High (Odd) Byte Low (Even) Byte
1FCEH Reserved WG_PROTECT • • • • • • • • • 1FCCH WG_CONTROL(H) WG_CONTROL(L) 1FCAH WG_COUNTER(H) WG_COUNTER(L) 1F64H Reserved COMP3_CON
1FC8H WG_RELOAD (H) WG_RELOAD (L) 1FC6H WG_COMP3 (H) WG_COMP3 (L) 1F60H Reserved COMP2_CON 1FC4H WG_COMP2 (H) WG_COMP2 (L) 1FC2H WG_COMP1 (H) WG_COMP1 (L) 1F5CH Reserved COMP1_CON 1FC0H WG_OUTPUT (H) WG_OUTPUT (L)
Peripheral Interrupt and PWM SFRs 1F58H Reserved COMP0_CON
Address High (Odd) Byte Low (Even) Byte
1FBEH Reserved PI_PEND • • • • • • • • •
1FBCH Reserved PI_MASK
• • • • • • • • • 1F4CH Reserved EPA3_CON 1FB6H Reserved PWM_COUNT 1FB4H Reserved PWM_ PERIOD 1F48H Reserved EPA2_CON 1FB2H Reserved PWM1 _CONTROL 1FB0H Reserved PWM0 _CONTROL 1F44H Reserved EPA1_CON
A/D SFRs
Address High (Odd) Byte Low (Even) Byte
1FAEH AD_TIME AD_TEST 1FACH Reserved AD_COMMAND 1FAAH AD_RESULT (H) AD_RESULT (L)
1FA8H P1_PIN P0_PIN 1FA6H Reserved Reserved
• • • • • • • • •
1F80H Reserved Reserved
†
Must be addressed as a word.
†
1F7EH TIMER2 (H) TIMER2 (L)
†
1F7AH TIMER1 (H) TIMER1 (L)
1F70H Reserved Reserved
†
1F66H COMP3_TIME (H) COMP3_TIME (L)
†
1F62H COMP2_TIME (H) COMP2_TIME (L)
†
1F5EH COMP1_TIME (H) COMP1_TIME (L)
†
1F5AH COMP0_TIME (H) COMP0_TIME (L)
1F56H Reserved Reserved
†
1F4EH EPA3_TIME (H) EPA3_TIME (L)
†
1F4AH EPA2_TIME (H) EPA2_TIME (L)
†
1F46H EPA1_TIME (H) EPA1_TIME (L)
†
1F42H EPA0_TIME (H) EPA0_TIME (L)
1F40H Reserved EPA0_CON
4-6
MEMORY PARTITIONS

Table 4-5. Peripheral SFRs — 8XC196MD

Ports 2 and 7 SFRs EPA and Timer SFRs
Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte
1FDEH Reserved Reserved 1FDCH Reserved Reserved 1F7CH Reserved T2CONTROL 1FDAH Reserved Reserved 1FD8H Reserved Reserved 1F78H Reserved T1CONTROL 1FD6H P7_PIN P2_PIN 1F76H Reserved Reserved 1FD4H P7_REG P2_REG 1F74H Reserved Reserved 1FD2H P7_DIR P2_DIR 1F72H T1RELOAD (H) T1RELOAD (L) 1FD0H P7_MODE P2_MODE 1F70H Reserved Reserved
Waveform Generat or SFRs
Address High (Odd) Byte Low (Even) Byte
1FCEH Reserved WG_PROTECT 1FCCH WG_CONTROL(H) WG_CONTROL(L) 1F68H Reserved COMP4_CON 1FCAH WG_COUNTER(H) WG_COUNTER(L) 1FC8H WG_RELOAD (H) WG_RELOAD (L) 1F64H Reserved COMP3_CON 1FC6H WG_COMP3 (H) WG_COMP3 (L) 1FC4H WG_COMP2 (H) WG_COMP2 (L) 1F60H Reserved COMP2_CON 1FC2H WG_COMP1 (H) WG_COMP1 (L) 1FC0H WG_OUTPUT (H) WG_OUTPUT (L) 1F5CH Reserved COMP1_CON
Periph. Int., Freq. Gen., and PWM SFRs
Address High (Odd) Byte Low (Even) Byte
1FBEH Reserved PI_PEND 1FBCH Reserved PI_MASK 1F54H Reserved EPA5_CON 1FBAH Reserved FREQ_CNT
1FB8H Reserved FREQ_GEN 1F50H Re se rved EPA4_CON 1FB6H Reserved PWM_COUNT 1FB4H Reserved PWM_ PERIOD 1F4CH Reserved EPA3_CON 1FB2H Reserved PWM1 _CONTROL 1FB0H Reserved PWM0 _CONTROL 1F48H Reserved EPA2_CON
A/D SFRs
Address High (Odd) Byte Low (Even) Byte
1FAEH AD_TIME AD_ TEST 1FACH Reserved AD_COMMAND 1F40H Reserved EPA0_CON 1FAAH AD_RESULT (H) AD_RESULT (L)
1FA8H P1_PIN P0_PIN
• • • • • • • • •
1F80H Reserved Reserved
†
Must be addressed as a word.
†
1F7EH TIMER2 (H) TIMER2 (L)
†
1F7AH TIMER1 (H) TIMER1 (L)
†
1F6EH COMP5_TIME (H) COMP5_TIME (L)
1F6CH Reserved COMP5 _CON
†
1F6AH COMP4_TIME (H) COMP4_TIME (L)
†
1F66H COMP3_TIME (H) COMP3_TIME (L)
†
1F62H COMP2_TIME (H) COMP2_TIME (L)
†
1F5EH COMP1_TIME (H) COMP1_TIME (L)
†
1F5AH COMP0_TIME (H) COMP0_TIME (L)
1F58H Reserved COM P0 _CON
†
1F56H EPA5_TIME (H) EPA5_TIME (L)
†
1F52H EPA4_TIME (H) EPA4_TIME (L)
†
1F4EH EPA3_TIME (H) EPA3_TIME (L)
†
1F4AH EPA2_TIME (H) EPA2_TIME (L)
†
1F46H EPA1_TIME (H) EPA1_TIME (L)
1F44H Reserved EPA1_CON
†
1F42H EPA0_TIME (H) EPA0_TIME (L)
4-7
8XC196MC, MD, MH USER’S MANUAL

Table 4-6. Peripheral SFRs — 8XC196MH

Port 0 and 2 SFRs Port 1 SFRs
Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte
1FDEH Reserved Reserved 1F9EH P1_PIN Reserved 1FDCH Reserved Reserved 1F9C H P1_REG Reserved 1FDAH Reserved P0_PIN 1F9AH P1_DIR Reserved 1FD8H Reserved Reserved 1F98H P1 _M ODE Reserved 1FD6H Reserved P2_ PIN • • • • • • • • • 1FD4H Reserved P2_REG Serial I/O Port SFRs 1FD2H Reserved P2_DIR 1FD0H Reserved P2_MODE 1F8 EH Re served Reserved
Waveform Generat or SFRs 1F8CH SP1_BAUD(H) SP1_BAUD (L)
Address High (Odd) Byte Low (Even) Byte 1F8AH SP1_ C ON SBUF1_TX
1FCEH Reserved WG_PROTECT 1F88H SP1_STATUS SBUF1_ RX 1FCCH WG_CONTROL(H) WG_CONTROL (L) 1F86H Reserved Reserved 1FCAH WG_ COUNTER(H) WG_COUNTER (L) 1F84H SP 0_BAUD (H) SP0_BAUD (L) 1FC8H WG_RELOAD (H) WG_RELOAD (L) 1F82H SP0_CON SBUF0_TX 1FC6H WG_COMP3 (H) WG_COMP3 (L) 1F80H SP0_STATUS SBUF0_RX 1FC4H WG_COMP2 (H) WG_COMP2 (L) EPA and Timer SFRs 1FC2H WG_COMP1 (H) WG_COMP1 (L) 1FC0H WG_OUTPUT (H) WG_OUTPUT (L)
Peripheral Interrupt and PWM SFRs 1F7CH Reserved T2CONTROL
Address High (Odd) Byte Low (Even) Byte
1FBEH Reserved PI_PEND 1F78H Reserved T1CONTROL 1FBCH Reserved PI_MASK • • • • • • • • • 1FBAH Reserved Reserved 1F72H T1RELOAD (H) T1RELOAD (L)
1FB8H Reserved Reser ve d • • • • • • • • • 1FB6H Reserved PWM_COUNT 1FB4H Reserved PWM_ PERIOD 1F60H Reserved COMP2 _CON 1FB2H Reserved PWM1 _CONT ROL 1FB0H Reserved PWM0 _CONT ROL 1F5CH Re served COM P1 _CON
A/D SFRs
Address High (Odd) Byte Low (Even) Byte 1F58H Reserved COMP0 _CON
1FAEH AD_TIME AD_ TEST • • • • • • • • • 1FACH Reserved AD_ COMMAND 1FAAH AD_RESULT (H) AD_RESULT (L) 1F4CH Reserved COMP3_CON
Reset Control SFR • • • • • • • • •
Address High (Odd) Byte Low (Even) Byte
1FA8H Reserved Reserved 1 F4 4H Reserved EPA1_CON
• • • • • • • • •
1FA0H Reserved GEN_CON 1F40H Reserved EPA0_CON
†
Must be addressed as a word.
Address High (Odd) Byte Low (Even) Byte
Address High (Odd) Byte Low (Even) Byte
†
1F7EH TIMER2 (H) TIMER2 (L)
†
1F7AH TIMER1 (H) TIMER1 (L)
†
1F62H COMP2_TIME(H) C O MP2_TIME(L)
†
1F5EH CO MP1_TIME(H ) COMP1_TIME (L )
†
1F5AH COMP0_TIME(H) COMP0_TIME(L)
†
1F4EH CO MP3_TIME(H) COMP3_TIME(L)
†
1F46H EPA1_TIME (H) EPA1_TIME (L)
†
1F42H EPA0_TIME (H) EPA0_TIME (L)
4-8
MEMORY PARTITIONS
4.1.6 Register File
The register fi le (Figure 4-1) is divi ded into an uppe r register file and a lower register fi le. The upper register file consists of general-purpose register RAM. The lower register file contains gen­eral-purpose register RAM along with the stack pointer (SP) and the CPU special-function regis­ters (SFRs).
T ab le 4-1 on page 4-2 l ists the register file memory addresses. The RALU accesses the lower reg­ister file directly, without the use of the memory controller. It also accesses a windowed location directly (see “Windowing” on page 4-12). The upper register file and the peripheral SFRs can be windowed. Registers in the lower register file and registers being windowed can be accessed with register-direct addressing.
NOTE
The register file must n ot contain code. An attempt to exec ute an instruct ion from a location in the register file cause s the me mory controller to fetch the instruction from externa l memo ry.
Address
02FFH (MH)     
0200H 01FFH (MC, MD)  
 
0100H 00FFH   001AH
0019H 0018H
0017H 0000H
Address
02FFH
0100H
00FFH
0000H
  
 
Upper
Register File
Lower
Register File
General-purpose
Register RAM
General-purpose
General-purpose
Register RAM
Register RAM
Stack Pointer
Stack Pointer
CPU SFRs

Figure 4-1. Register File Memory Map

A3066-02
4-9
8XC196MC, MD, MH USER’S MANUAL

Table 4-7. Register File Memory Addresses

Device and Hex
Address Range
MC, MD MH
01FF 0100
00FF 001A
0019 0018
0017 0000
02FF 0100
00FF 001A
0019 0018
0017 0000
Upper register file (register RAM) Indirect, indexed, or windowed direct
Lower register file (register RAM) Direct, indirect, or indexed
Lower register file (stack pointer) Direct, indirect, or indexed
Lower register file (CPU SFRs) Direct, indirect, or indexed
Description Addressing Mode s
4.1.6.1 General-purpose Register RAM
The lower regis ter file conta ins general -purpose register RAM. The s tack pointer l ocations can also be used as general-purpose register RAM when stack operations are not being performed. The RALU can access this m em ory directl y, using register-direct addressing.
The upper register file also conta ins general-p urpose register RAM. The RAL U normally uses indirect or indexed addressing to acces s the RAM in the upper register file . Windowing enables the RALU to use register-direct addressing to access this memory. (S ee Chapt er 3 , “Prog ramming Considerations,” f or a discussion of ad dressin g modes.) Windowing can provide for fast context switching of interrupt tasks and faster program execution. (See “Windowing” on page 4-12.) PTS control blocks and the stack are most efficient when locat ed in the upper register file.
4.1.6.2 Stack Pointer (SP)
Memory locations 0018H and 0019H contain the stack pointer (SP). The SP contains the address of the stack. The SP must point to a word (even) address that is two bytes greater than the desired starting addre ss. Before the CPU executes a subroutine call or interrupt service routine, it decre­ments the SP by t wo and c opies (PUSHes ) the addres s of the next ins tructi on from the p rogram counter onto the stack. It then loads the address of the subroutine or interrupt service routine into the program counter . When it e xecutes the r eturn-from-subro utine ( RET) instruction at the end of the subroutine or interrupt service routine, the C PU loads (POPs ) the contents of the top o f the stack (that is, the return address) into the progra m cou nter and incre ment s the SP by two.
Subroutines may be nested. That is , each subroutine may cal l other subro utines. The CPU pushes the contents of the program counter onto the stack each time it executes a subroutine call. The stack grows downward as entries are added. The only limit to the nesting depth is the amount of available memory. As the CPU returns from each nested subroutine, it pops the address off the top of the stack, and the next return address moves to the top of the stack.
4-10
MEMORY PARTITIONS
Your program must load a word-aligned (even) address into the stack pointer. Select an address that is two byte s grea ter tha n the desi red s tarti ng ad d ress beca use the CP U aut omat ica lly dec re­ments the stack pointer before it pushes the first byte of the return address onto the stack. Remem­ber that the stack grows downward, so allow sufficient room for the maximum number of stack entries. The st ack must be l oca ted in e ither t he i nte rnal re gist er fi le or ext ernal R AM . The st ack can be used most efficiently when it is located in the regis ter file .
The following example init ializes the top of the upper regi ster file (8XC196MC, MD) as the stack. (For the 8XC196MH, the im me dia te value w o uld be #3 00H. )
LD SP, #200H ;Load stack pointer
The following example shows how to allow the linker locator to determine where the stack fits in the memory map that you specify.
LD SP, #STACK
4.1.6.3 CPU Special-function Registers (SFRs)
Locations 0000–0017H in the lower register file are the CPU SFRs (Table 4-8). Appendix C de­scribes the CPU SFR s.

T able 4-8. CPU SFRs

Address High (Odd) Byte Low (Even) Byte
0016H Reserved Reserved 0014H Reserved WSR 0012H INT_MASK1 INT_PEND1 0010H Reserved Reserved 000EH Reserved Reserved 000CH Reserved Reserved 000AH Reserved WATCHDOG 0008H INT_PEND INT_MASK 0006H PTSSRV (H) PTSS RV (L) 0004H PTSSEL (H) PTSSEL (L) 0002H ONES_REG (H) ONES_REG (L) 0000H ZERO_REG (H) ZERO_REG (L)
NOTE
Using any SFR as a base or index register for indirect or indexed operations can cause unpredictable results because external events can change the contents of SFRs. Also, because some SFRs are cleared when read, consider the implications of using an SFR as an operand in a read-modify-write instructi on (e.g., XORB ).
4-11
8XC196MC, MD, MH USER’S MANUAL

4.2 WINDOWING

Windowing expands the amount of memory that is accessible with register-direct addressin g. Register-direct a ddressing can a ccess the lowe r register file with short, fast-executi ng instruc­tions. With windowing, re gist e r-direct addressi ng c an also ac cess t he u pper regi ster fi le and pe­ripheral SFRs.
Windowing maps a se gment of hig her memory (the upper register file or peripheral SFRs) into the lower register file. The window selection register (WSR) selects a 32-, 64-, or 128-byte seg­ment of higher memory to be windowed into the t op of the lower register file space. Figure 4-2 illustrates a 128-byte window.
02FFH
128-byte Window
(WSR = 13H)
WSR Window in
Lower Register File
8XC196MC,MD 8XC196MH
01FFH 0180H
  
 
00FFH
0080H
   
0000H
128-byte Window
(WSR = 13H)
WSR Window in
Lower Register File

Figure 4-2. Windowing

NOTE
Memory-mapped SFRs must be accessed using indirect or indexed addressing modes; they cannot be accessed through a window. Reading a memory­mapped SFR through a window returns FFH (all ones), and writing to a memory-mapped SFR through a window has no effect.
A3062-01
4-12
MEMORY PARTITIONS
4.2.1 Selecting a Window
The window selection register (Figure 4-3) selects a window to be mapped into the top of the low­er register file.
Table 4-9 provides a quick reference of WSR values for windowing the p eripheral SFRs. Table 4-10 on page 4-14 lists the WSR values for windowing the upper register file.
WSR
The window sele ctio n reg iste r (WSR) map s sectio ns of RAM in to the top of the lower regi st er file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA restores it.
7 0
— W6 W5 W4 W3 W2 W1 W0
Bit
Number
7 — Reserve d; for compa tibil ity with future device s, write zero to this bit. 6:0 W6:0 Window Selection
Bit
Mnemonic
Function
These bits specify the window size and number. See Table 4-9 on page 4-13 or T able 4-10 on page 4-14. See T able 4-9 for peripheral SFR windows or Ta b le 4-1 0 for uppe r regi st er fil e windo ws .
Address:
Reset State:

Figure 4-3. Window Selection (WSR) Register

Table 4-9. Selecting a Window of Peripheral SFRs

Periphe rals
Port 2 Waveform generator Port 7 (MD only)
Peripheral interrupts Pulse-wid th modula to r A/D converter Frequency generator (MD only) Reset control (MH only)
Port 1 (MH only) Serial I/O port (MH only)
Timer 1–2 EPA compare 2–3 (MC) EPA compare 0–5 (MD) EPA compare 0–2 (MH)
EPA capture/compare 0–3 (MC) EPA compare 0–1 (MC) EPA capture/compare 0–5 (MD) EPA capture/compare 0–1 (MH) EPA compare 3 (MH)
WSR Value for
32-byte Wind ow
(00E0–00FFH )
7EH 3FH
7DH
7CH
7BH
7AH
WSR Value for
64-byte Window
(00C0–00FFH)
3EH
3DH 1EH
WSR Value for
128-byte Window
(0080–00FFH)
0014H
00H
1FH
4-13
8XC196MC, MD, MH USER’S MANUAL

Table 4-10. Selecting a Window of the Upper Register File

Register RAM
Locations
8XC196 MH Only
02E0–02FFH 57H 02C0–0 2DF H 56H 02A0–02BFH 55H
0260–027FH 53H 0240–025FH 52H 0220–023FH 51H
8XC196MC, 8XC196MD, and 8XC196MH
01E0–01FFH 4FH 01C0–01DFH 4EH 01A0–01BFH 4DH
0160–017FH 4BH 0140–015FH 4AH 0120–013FH 49H
WSR Value
for 32-byte Window
(00E0–00FFH)
WSR Value
for 64-byte Window
(00C0–00FFH)
2BH
2AH0280–029FH 54H
29H
28H0200–021FH 50H
27H
26H0180–019FH 4CH
25H
24H0100–011FH 48H
WSR Value
for 128-byte Window
(0080–00FFH)
15H
14H
13H
12H
4.2.2 Addressing a Location Through a Window
After you have selected the desired window, you need to know the windowed direct address of the memory location (the address in the lower register fi le). Calculate the wi ndowed direct ad­dress as follow s:
1. Subtract the base address of the area to be remap ped (from Table 4-11 on page 4-15) from the address of the desired location. This give s you the offset of that particular locat ion.
2. Add the offset to the base address of the window (from Table 4-12 on page 4-15). The result is the windowed direct address.
Appendix C includes a table of the windowable SFRs with the WSR values and windowed direct addresses for each window size. Examples beginning on page 4-16 explain how to determine the WSR value and windowed direct address for any windowable location. An additional example shows how to set up a window by using the linker locator.
4-14
MEMORY PARTITIONS

Table 4-11. Windows

Base
Address
Periphe ral SFRs
1FE0H 7FH (Note) 1FC0H 7EH 1FA0H 7DH
1F60H 7BH 1F40H 7AH 1F20H 7 9H
02E0H 57H 02C0 H 5 6 H 02A0H 55H
0260H 53 H 0240H 52 H 0220H 51 H
01E0H 4FH 01C0 H 4EH 01A0H 4DH
0160H 4BH 0140H 4AH 0120H 49 H
NOTE: Locations 1FE0– 1FFFH contain memory-ma pped SFRs that cannot be acces sed thro ugh a
window. Reading these locations through a window returns FFH; writing these locations through a window has no effect.
WSR Value
for 32-byte Window
(00E0–00FFH)
WSR Value
for 64-byte Window
(00C0–00FFH)
3FH (Note)
3EH1F80H 7CH
3DH
3CH1F00H 78H
2BH
2AH0280H 54H
29H
28H0200 H 50H
27H
26H0180 H 4CH
25H
24H0100 H 48H
WSR Value for
128-byte
Window
(0080–00FFH)
1FH (Note)
1EH
15H
14H
13H
12H

Table 4-12. Windowed Base Addresses

Window Size
32-byte 00E0H 64-byte 00C0H
128-byte 0080H
WSR Windowed Bas e Addre ss
(Base Address in Lower Register File)
4-15
8XC196MC, MD, MH USER’S MANUAL
Appendix C includes a table of the windowable SFRs with the WSR values and direct addresses for each window size. The following examples explain how to determine the WSR value and di­rect address for any windowable location. An additional example shows how to set up a window by using the linker locator.
4.2.2.1 32-byte Windowing Example
Assume that you wish to access location 014BH (a location in the upper register file used for gen­eral-purpose register RAM) with register-direct addressing through a 32-byte window . T able 4-11 on page 4-15 shows that you need to write 4AH to the window selection register. It also shows that the base address of the 32-byte memory area is 0140H. To determine the offset, subtract that base address from the address to be accessed (014B H – 01 40H = 000BH). Add the offset t o the base address of the window in the lower regi ster file (00E0H, from Table 4-12). The direct ad­dress is 00EBH (000BH + 00E0H).
4.2.2.2 64-byte Windowing Example
Assume that you wish to access the WG_CONTROL register (location 1FCCH) with register-di­rect addressing through a 64-byte window. Table 4-11 shows that you need to write 3FH to the window selection register. It also shows that the base address of the 64-byte memory area is 1FC0H. To determine the offset, subtract that base address from the address to be accessed (1FCCH – 1FC0H = 000C H). Add the offset to the base address of t he window in the lower reg­ister file (00C0H, from Table 4-12). The direct address is 00CCH (000CH + 00C0H).
4.2.2.3 128-byte Windowing Ex ample
Assume that you wish to access location 1F42H (the EPA0_TIME regist er) with register-direct addressing through a 128-byte window. Table 4-11 shows that you need to write 1EH to the win­dow selection register. It also shows that the base address of the 128-byte memory area is 1F00H. To determine the offset, su btract that base address f rom the address to be accesse d (1F42H – 1F00H = 0042H). Add the offset to the base address of the window in the lower register file (0080H, from Table 4-12). The direct address is 00C2H (0042H + 0080H).
4.2.2.4 Unsupported Locations Windowing Example
Assume that y ou wish to access location 1FF1H (the P5_MODE register, a memory-mapped SFR) with register-direct addressing through a 128-byte window. This location is in the range of addresses (1FE0–1FFFH) that cannot be windowed. Although you could set up the window by writing 1FH to the WSR, reading this location through the window would return FFH (all ones) and writing to it would not change the contents. However, you could access the peripheral SFRs in the range of 1F80–1FDFH with the ir windowed direct addresses.
4-16
MEMORY PARTITIONS
4.2.2.5 Using the Linker Locator to Set Up a Window
In this example, the linker locator is used to set up a window. The linker locator locates the win­dow in the upper register file and determines the value to load in the WSR for access to that win­dow. (Please consul t the manual provided with the linker locato r for details.)
********* mod1 ************** mod1 module main ;Main module for linker public function1 extrn ?WSR ;Must declare ?WSR as external
wsr equ 14h:byte sp equ 18h:word
oseg var1: dsw 1 ;Allocate variables in an var2: dsw 1 ;overlayable segment var3: dsw 1
cseg
function1: push wsr ;Prolog code for wsr ldb wsr, #?WSR ;Prolog code for wsr
add var1, var2, var3 ;Use the variables as registers ; ; ;
ldb wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr ret end
******** mod2 ************** public function2 extrn ?WSR
wsr equ 14h:byte sp equ 18h:word
oseg var1: dsw 1 var2: dsw 1 var3: dsw 1
cseg
function2: push wsr ;Prolog code for wsr
4-17
8XC196MC, MD, MH USER’S MANUAL
ldb wsr, #?WSR ;Prolog code for wsr
add var1, var2, var3 ; ; ;
ldb wsr, [sp] ;Epilog code for wsr add sp, #2 ;Epilog code for wsr ret end ******************************
The following is an example of a linker invocation to link and loc ate the modules and to deter­mine the proper windowing.
RL196 MOD1.OBJ, MOD2.OBJ registers(100h-01ffh) windowsize(32)
The above linker control s tel l the lin ker to us e regist ers 0100– 0 1FFH for windowing an d to use a window size of 32 bytes. (These two controls enable windowing.)
The following is the map listing for the resultant output module (MOD1 by default):
SEGMENT MAP FOR mod1(MOD1):
TYPE BASE LENGTH ALIGNMENT MODULE NAME
---- ---- ------ --------- ----------­**RESERVED* 0000H 001AH STACK 001AH 0006H WORD *** GAP *** 0020H 00E0H OVRLY 0100H 0006H WORD MOD2 OVRLY 0106H 0006H WORD MOD1 *** GAP *** 010CH 1F74H CODE 2080H 0011H BYTE MOD2 CODE 2091H 0011H BYTE MOD1 *** GAP *** 20A2H DF5EH
This listing shows the disassembled code:
2080H ;C814 | PUSH WSR 2082H ;B14814 | LDB WSR,#48H 2085H ;44E4E2E0 | ADD E0H,E2H,E4H 2089H ;B21814 | LDB WSR,[SP] 208CH ;65020018 | ADD SP,#02H 2090H ;F0 | RET 2091H ;C814 | PUSH WSR 2093H ;B14814 | LDB WSR,#48H 2096H ;44EAE8E6 | ADD E6H,E8H,EAH 209AH ;B21814 | LDB WSR,[SP] 209DH ;65020018 | ADD SP,#02H 20A1H ;F0 | RET
4-18
MEMORY PARTITIONS
The C compiler can also take a dvantage of this fea ture if the “windows” switch is enabled. F or details, see the MCS 96 microcontroller architecture software products in the Development Tools Handbook.
4.2.3 Windowi ng and Add ressi ng Modes
Once windowing is enabled, the windowed locations can be accessed both through the window using direct (8-bit) addressing and by the usual 16-bit addressing. The lower register file locations that are covered b y the window are a lways acc essible by indire ct or indexed opera tions. To re­enable direc t acce ss t o the ent ire lower regi ste r file, c lear t he W SR. To enable direct a cc ess to a particular location in the lower register file, you can select a sma ller window that does not cover that locatio n.
When windowing is enabled:
• a register-direct instruction that uses an address within the lower register file actually
accesses the window in the upper register file;
• an indirect, indexe d, or zero -regist er inst ruct ion that uses an address withi n eit her the lowe r
register file or the upper register file accesses the actual location in me mory.
The following sample code illustrates the difference between register-direct and indexed address­ing when using windowing.
PUSHA ; pushes the contents of WSR onto the stack LDB WSR, #12H ; select window 12H, a 128-byte block
ADD 40H, 80H ; mem_word(40H)←mem_word(40H) + mem_word(380H) ADD 40H, 80H[0] ; mem_word(40H)←mem_word(40H) + mem_word(80H +0)
ADD 40H, 380H[0] ; mem_word(40H)←mem_word(40H) + mem_word(380H +0) POPA ; reloads the previous contents into WSR
; The next instruction uses register-direct addr
; The next two instructions use indirect addr
4-19
Standard and PTS Interrupts
5
CHAPT ER 5
STANDARD AND PTS INTERRUPTS
This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and peripheral transaction server (PTS) interrupts. I t discusses the three special interrupts and the sev­en PTS modes, f our of which are us ed with the EPA to provide a software serial I/O channel for both synchronous and asynchronous transfers and receptions. It also explains interrupt program­ming and control.

5.1 OVERVIEW OF INTERRUPTS

The interrupt control circuitry withi n a microcontrolle r permits real-time events to cont rol pro­gram flow. When an event generates an interrupt, the device suspends the execution of current instructions while it performs some service in response to the interrupt. When the interrupt is ser­viced, program executi on resume s at the point whe re t he interrupt oc curred. An inte r nal periph­eral, an external signa l, or an instruction can generate an interrupt request. In the simplest case, the device receives the request, performs the service, and returns to the task that was interrupted.
This microcontroller’s flexible interrupt-handling system has tw o main comp onents: the pro­grammable interrupt c ontroller and the periphera l transaction server (PTS). The programmable interrupt controller has a hardware priority scheme that can be modified by your software. Inter­rupts that go through the inte rrupt controller are serviced by interrupt servic e routines that you provide. The upper and lower interrupt vectors in special-purpose memory (see Chapter 4, “Memory Partitions”) co ntain the interrupt service routi nes’ addresses. The periphera l transac­tion server (PTS), a microcoded hardware interrupt processor, provide s high-speed, low-over­head interrupt handling; it does not modify the stack or the PSW. You can configure most interrupts (except NMI, trap, and unimple mente d opcode) to be se rviced by t he PTS instead of the interrupt controller.
The PTS supports seven speci al mi croc oded r outines that enabl e i t t o compl ete specific tasks i n much less time than an eq uivalent interrupt ser vice routine can. It can transfer byte s or words, either individually or in blocks, between any memory locations; manage multiple analog-to-dig­ital (A/D) conversions; and transmit and receive serial data in eithe r asynchronous or synchro­nous mode (MC, MD only). PTS interrupts have a higher priority than standard interrupts and may temporarily suspend inter rupt service routines .
A block of data called the PTS control block (PTSCB) contains the specific deta ils for each PTS routine (see “Initializing the PTS Control Blocks” on page 5-24). When a PTS interrupt occurs, the priority encoder selects the appropriate vector and fetches the PTS control block (PTSCB).
5-1
8XC196MC, MD, MH USER’S MANUAL
Interrupt Pending or PTSSRV Bit Set
INT _MASK.
Yes
Yes
PTSSEL.
Yes
Highest Priority PTS Interrupt
Reset INT_PEND.x
Execute 1 PTS Cycle
(Microcoded)
Decrement
PTSCOUNT
NMI
Pending
?
No
= 1?
PTS
Enabled?
Bit = 1?
Priority
Encoder
Bit
Yes
No
x
No
No
x
Return
Yes No
Reset PTSSRV.x
Bit
Interrupts
Enabled
?
Yes
Priority
Encoder
PTSSRV.
= 1?
PUSH PC
on Stack
No
Highest Priority Interrupt
x
Reset INT_PEND.
Bit
Return
x
5-2
LJMP to
ISR
Execute Interrupt
Service Routine
POP PC
from Stack
Return
Return
No
PTSCOUNT
= 0?
Yes
Clear PTSSEL.
Set PTSSRV.x Bit
Return
x
Bit

Figure 5-1. Flow Diagram for PTS and Standard Interrupts

A0320-02
STANDARD AND PTS INTERRUPTS
Figure 5-1 illustrates the interrupt pr ocessing flow. In this flow diagram, “INT_MASK” repre­sents both the INT _MASK and INT_M ASK1 regi sters, and “INT_PE ND” represents bot h the INT_PEND and INT_PEND 1 registers.

5.2 INTERRUPT SIGNALS AND REGISTERS

Table 5-1 describe s the exte rnal int errupt signal s and Table 5-2 describes t he control and statu s registers for both the interrupt controller and PTS.

Table 5-1. Interr upt Sign als

Port Pin Interrupt Signal Type Des crip tion
— EXTINT I Exte rn al Interr upt
This programmable interrupt is controlled by the WG_PROTECT registe r. This register controls whether the interrupt is edge triggered or sampled and whether a rising edge/hi gh level or fal ling edge/l ow level activate s the interr u pt.
In powerdown mode, asserting the EXTINT signal for at least 50 ns causes the device to resume normal operation. The interrupt need not be enabled . If the EXTINT interru pt is enabled, the CPU executes the interrup t service routine. Otherwise, the CPU executes the instruction that immediately follows the command that invoked the power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to resume normal operation.
— NMI I Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmas kabl e interr up t. NMI has the highe st prior ity of all prioritized interrupts. Assert NMI for greater than one state time to guarantee that it is recognized.

Table 5-2. Interrupt and PTS Control and Status Registers

Mnemonic Address Description
INT_MASK INT_MASK1
INT_PEND INT_PEND1
PI_MAS K 1FB C H Peripheral Int errupt Mask
0008H 0013H
0009H 0012H
Interrupt Mask Registers These registers enable/disable each maskable interrupt (that is,
each interrupt except unimplemented opcode, software trap, and NMI).
Interrupt Pending Registers The bits in this registe r are set by hardwa re to in dica te that an
interrupt is pending.
The bits in this register enable and disable (mask) the timer 1 and 2 overflow/underflow interrupt requests, the waveform generator interrupt request (MC, MD), the EPA compare-only channel 5 interrupt request (MD), and the serial port error interrupts (MH).
5-3
8XC196MC, MD, MH USER’S MANUAL
Table 5-2. Interrupt and PTS Control and Status Registers (Continued)
Mnemonic Addre ss Description
PI_PE ND 1FBEH Peripheral Interru pt Pend in g
Any bit set indicates a pending interrupt request.
PSW No direct access Processor Status Word
This registe r conta ins one bit that globall y enab le s or disa bles servici ng of all mas kabl e interrupts and anoth er that en ab les or disables the PTS. These bits are set or cleared by execu ting the enable interrupts (EI), disable interrupts (DI), enable PTS (EPTS), and disable PTS (DPTS) instructions.
PTSSEL 0004H, 0005H PTS Select Register
This registe r selects eith er a PTS routi ne or a standar d interru pt service rout in e for ea ch of the maskable interru pt requests.
PTSSRV 0006H, 0007H PTS Service Register
The bits in this register are set by hardware to request an end-of­PTS interrupt.

5.3 INTERRUPT SOURCES AND PRIORITIES

Table 5-3 lists the interrupts so urces, their default priorities (30 is highest and 0 is lowest), an d their vector addresses . The unimplemented opco de and software trap interrupts are not priori­tized; they go dire ctly to the i nterrupt cont roller for s ervicing. The pri ority enc oder determ ines the priority of all other pending interrupt requests. NMI has the highest priority of all prioritized interrupts, PTS interrupts have the next highest priority, and standard interrupts have the lowest. The priority encoder selec ts the highest priority pendin g request and the interrupt controller se­lects the corresponding vector location in special-purpose memory. This vector contains the start­ing (base) address of the corres pondin g PTS control block (PTSCB) or inte rr upt servi ce routine. PTSCBs must be located on a quad-word boundary in the internal register file.
5-4

Table 5-3. Interrupt Sources, Vectors, and Priorities

Interrupt Source Mnemonic
STANDARD AND PTS INTERRUPTS
Interrupt Controller
Service
PTS Service
Name
Vector
Priority
Name
Vector
Nonmaskable Interrupt NMI INT15 203EH 30 — — — EXTINT Pin EXTINT INT14 203CH 14 PTS14 205CH 29 WF Gen (MC) WF Gen & EPA Comp 5 (MD) Waveform Generator (MH) Reserved (MC)
EPA Cap/Comp 5 (MD) SIO0 & 1 Receive Err (MH) Reserved (MC) EPA Compare 4 (MD) SIO1 Receive (MH) Reserved (MC) EPA Cap/Comp 4 (MD) SIO0 Receive (MH) EPA Compare 3 (MC, MD) SIO1 Transmit (MH) EPA Cap/Comp 3 (MC, MD) SIO0 Transmit (MH)
PI
†
PI WG
— EPA5
†
SPI —
COMP4 RI1
— EPA4 RI0
COMP3 TI1 EPA3 TI0
INT13 203AH 13 PTS13 205AH 28
INT12 2038H 12 PTS1 2 2058H 27
INT11 2036H 11 PTS11 2056H 26
INT10 2034H 10 PTS1 0 2054H 25
INT09 2032H 09 PTS0 9 2052H 24
INT08 2030H 08 PTS0 8 2050H 23
Unimplemented Opcode — — 2012H — — — — Software TRAP Instruction — — 2010H — — — — EPA Compare 2 (MC, MD) EPA Compare 3 (MH) EPA Cap/Comp 2 (MC, MD) EPA Compare 2 (MH)
COMP2 COMP3 EPA2 COMP2
INT07 200EH 07 PTS07 204EH 22
INT06 200CH 06 PTS06 204CH 21
EPA Compare 1 COMP1 INT05 200AH 05 PTS05 204AH 20 EPA Capture/Compare 1 EPA1 INT04 2008H 04 PTS04 2048H 19 EPA Compare 0 COMP0 INT03 2006H 03 PTS03 2046H 18 EPA Capture/Compare 0 EPA0 INT02 2004H 02 PTS02 2044H 17 A/D Conversion Complete AD_DONE INT01 2002H 01 PTS01 2042H 16 Timer 1 or 2 Overflow OVRTM
†
PTS service is not useful for multiplexe d int erru pt s because the PTS cannot readily det ermin e the
†
INT00 2000H 00 PTS00 2040H 15
source of these interru pt s.
Priority
5-5
8XC196MC, MD, MH USER’S MANUAL
5.3.1 Special Interrupts
This microcontroller has three special interrupt sources that are always enabled: unimplemented opcode, softwa re tra p, an d NMI . These interrupts are n ot a ffected b y the E I (e nable i nter rupts) and DI (disable interrupts) instruc tions, and they cannot be maske d. All of these interrupts are serviced by the interrupt controller; they cannot be assigned to the PTS. Of these three, only NMI goes through the transition detector and priority encode r. The other two special interrupts go di­rectly to the interrupt controller for servicing. Be aware that these interrupts are often assigned to special functions in development tools .
5.3.1.1 Unimplemented Opcode
If the CPU attempts to execute an unimplemented opcode, an indirect vector through location 2012H occurs. This prevents random software exe cut ion durin g hardware and software failures. The interrupt vector should contain the starting address of an error routine that will not further corrupt an a lready erroneous s ituation. The unimplemented opcode interrupt prevents other inter­rupt requests from being acknowledged until after the next instruction is executed.
5.3.1.2 Software Trap
The TRAP instr uction (opcode F7H) cause s an interrupt call that is vectored th rough location 2010H. The TRAP inst ruct ion pr ovides a single-i nstruc tio n inter rupt tha t is useful when debug­ging software or generating software inte rrupts. The TRAP instr uction prevents other inter rupt requests from being ack nowle dge d until aft er the next inst ruct ion is exec ute d.
5.3.1.3 NMI
The external NMI pin generat es a nonmaska ble interrupt for implem ent at ion of critical inter rupt routines. NMI has the highest priority o f all the prioritize d interrupts. It is passed directly f rom the transition detector to the priority encoder, and it vectors indirectly through location 203EH. The NMI pin is sampled during phase 2 (CLKOUT high) and is latched internally. Because inter­rupts are edge-triggered, only one interrupt is generated, even if the pin is held high.
If your system does not use the NMI interrupt, connect the NMI pin to V
to prevent sp urious
SS
interrupts.
5.3.2 External Interru pt Pi n
The protection ci rcuitry in t he waveform generat or (Figure 5 -2) monitors the external inter rupt (EXTINT) signal. When it detects a valid event on the input, it sumultaneously disables the wave­form generator outputs and generates an EXTINT interrupt request. Bits 2 and 3 in the waveform generator protection (WG_PROTECT) regi ster (Figure 9-9 on page 9-15) select the type of ex­ternal event that will generate an interrupt request: a falling or rising edge or a low or high level.
5-6
STANDARD AND PTS INTERRUPTS
When the level-sensi tive eve nt is selecte d, the externa l interrupt si gnal must rem ain asse rte d for at least 24 T
XTAL1
(24/F
the level sam pler sample s the le vel of the signa l thre e ti mes during a 24 T
) to be recognized a s a valid i nte rrupt. When the signal i s a sse rte d,
XTAL1
period. When a
XTAL1
valid level occurs, the level sampler generates a a single output pulse. The output pulse generates the EXTINT interrupt re quest. T he l eve l-sensitive mo de is use f ul in noisy environments, where a noise spike might cause an unintenti ona l interrupt request.
When an edge-triggered event is selected, the input must remain asserted for at least two T (2/F
) to be recognized as a valid interrupt. When a valid transition occurs, the transition de-
XTAL1
XTAL1
tector generates a single output pulse. The output pulse generates the EXTINT interrupt request.
EXTINT
F
XTAL1
ES, IT
Falling
Transition
Detector
Level
Sampler
Rising
Low
High
00
01
10
11

Figure 5-2. Waveform Generator Protection Circuitry

Pulse
EXTINT Interrupt Request
CPU Bus
DP
EO Bit
Register
R
OD#
Q
S
CPU Read EOCPU Write EO
A2661-01
5.3.3 Multiplexed Interrupt Sources
The PI (MD), OVRTM (Mx), and SPI (MH) interrupts have multiple s ourc es (see Table 5-3 on page 5-5). An individual source will generate the interrupt only if software enables both the in­terrupt source and multiplexed interrupt. To enable the multiplexed interrupt, set the appropriate bit in the interrupt mask register (Figures 5-7 and 5-8). To enable an interrupt source, set the ap­propriate bit in the PI_MASK regis ter (Figure 5 -9 on pa ge 5- 17). Figure 5 -3 shows the flow fo r the timer interrupt.
NOTE
Although the PI interrupt on the 8XC196MC has a single source (the waveform generator), software must still enable both the source interrupt (WG) in the PI_PEND register and the PI interrupt in the INT_MASK register.
5-7
8XC196MC, MD, MH USER’S MANUAL
The interrupt service routine should read the PI_PEND (Figure 5-12 on page 5-23) register to de­termine the source of the interrupt. Before executin g the return instruct ion, the i nterrupt se rvice routine should check to see i f any of the ot her inte rr upt sources are pe nding. Ge nerally, PTS in­terrupt service is not useful for multiple xed inte rr upts because the PTS cannot readily determine the interrupt source.
Timer x
Overflows
Set OVRTM
bit in PI_PEND
Is OVRTM
bit set in
PI_MASK
Set OVRTM
bit in INT_PEND
Is OVRTM
bit set in
INT_MASK
Generate
OVRTM interrupt
x
x
?
Yes
?
Yes
No
No
OVRTM bit
is not set
in INT_PEND
OVRTM interrupt
is not generated
5-8
Read PI_PEND
to see which
timer overflowed
A3254-01

Figure 5-3. Flow Diagram for the OVRTM Interrupt

STANDARD AND PTS INTERRUPTS
5.3.4 End-of-PT S Interrupts
When the PTSCOUNT regis ter decrem ents to zero at the end of a single transfer, block transfer, A/D scan, or seria l I/O routine, hardware clears the corresponding bit in the PTSSEL regist er, (Figure 5-6 on page 5-14) which disables PTS service for that interrupt. It also sets the corre­sponding PTSSRV bit, requesting an end-of-P TS in terrupt. An end-of-P TS interrupt has the same priority as a corresponding standard interrupt. The interrupt controller processes it with an inter­rupt service routine that is stored in the memory location pointed to by the standard interrupt vec­tor. For example , the PTS services the EPA0 interrupt if PTSS EL.2 is set. The interrupt vectors through 2044H, but the corresponding end-of-PTS interrupt vectors through 2004H, the standard EPA 0 interrupt vector. When the end-of-PTS interrupt vectors to the interrupt service routine, hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine should reinitialize the PTSCB, if required, and set the appropriate PTSSE L bit to re-enable PTS interrupt service.

5.4 INTERRUPT LATENCY

Interrupt latency is the total del ay between the time that the interrupt reque st is generated (not acknowledged) and the time that the device begins executing either the standard interrupt service routine or the PTS interrupt service ro utine. A delay occurs between the time that the interr upt request is detected an d the time that it is acknowle dged. An interrupt req uest is acknowledged when the current instructi on finishe s execut ing. If t he inte r rupt request occurs during o ne of the last four state times of the instruction, it may not be acknowledged until after the next instruction finishes. This additional delay occurs because instructions are prefetched and prepared a few state times before they are executed. Thus, the maximum del ay between interrupt request and ac­knowledgment is four state times plus the execut ion time of the next instr uctio n.
When a standard interrupt request is acknowledged, the hardware clears the interrupt pending bit and forces a call to the address cont ained i n the corresponding i nter rupt vector. When a PTS in­terrupt request is acknowledged, the hardware immediately vectors to the PTSCB and begins ex­ecuting the PTS routine.
5.4.1 Situations that In crease Interrupt Late ncy
If an interrupt request occurs while any of the following instr uctions are exe cut ing, the interr upt will not be acknowledged until after the next instruction is execute d:
• the signed prefix opcode (FE) for the two-byte, signed multiply and divide instructions
• any of these eight protected instructions: DI, EI, DPTS, EPTS, POPA, POPF, PUSHA,
PUSHF (see Appendix A for descriptions of these instructions)
• any of the read-modify-write instructions: AND, ANDB , OR, ORB, XOR, XORB
Both the unimplemented opcode interrupt and the software trap interrupt prevent other inter rupt requests from being ack nowle dge d until aft er the next inst ruct ion is exec ute d.
5-9
8XC196MC, MD, MH USER’S MANUAL
Each PTS cycle wi thin a PTS routine can not be i nterrupted. A PTS cycle i s the ent ire PTS re­sponse to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer of an entire block of bytes or words. This means a worst-case latency of 500 states if you assume a block transfer of 32 words from one external memory location to another. See T able 5-4 on page 5-12 for PTS cycle execution times.
5.4.2 Calculatin g Latency
The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol­lowing the current instruction. The following worst-case calculation assumes that the current in­struction is not a protected instructi on. To calculate latency, add the following terms :
• Time for the current instruction to finish executi on (4 state times ).
— I f this is a protected inst ruct ion, t he inst ruct ion tha t follows it must also exec ute bef ore
the interrupt can be acknowledged. Add the execution time of the instruction that follows a protected instruction.
• Time for the next instruction to execut e. (The longest instruc tion, NORML, takes 39 state
times. However, the BMOV instruction could actually take longer if it is transferring a large block of data. If your code contains routines that transfer large blocks of data, you may get a more accurate worst-case value if you use the BMOV instruction in your calculation instead of NORML. See A ppendix A for instruction exec uti on ti me s.)
• For standard interrupts only, the response time to get the vector and force the call.
— 11 state times for an internal stack or 13 for an exte rnal stack (assuming a zero-wait-
state bus)
5.4.2.1 Standard Interrupt Latency
The worst-case delay for a standard interrupt is 56 state times (4 + 39 + 11 + 2) if the stack is in external memory (Figure 5 -4). This de lay time d oes not include the tim e needed to exec ute the first instruction in the interrupt service routine or to execute the instruction following a protected instruction.
5-10
STANDARD AND PTS INTERRUPTS
Execution
EXTINT
Pending Interrupt
Response
Time
4 3 2 1
Ending
Instruction
"NORML"
End
"NORML"
56 State Times
11 2 1239
Call is
Forced
ClearedSet
If Stack
External
"PUSHA"
6
If Stack
External
Interrupt Routine
A0136-02

Figure 5-4. Standard Interrupt Response Time

5.4.2.2 PTS Interrupt Latency
The maximum delay for a PTS interrupt is 43 state times (4 + 39) as shown in Figure 5-5. This delay time does not include the added delay if a protected instruction is being executed or if a PTS request is already in progress. See Table 5-4 for execution times for PTS cycles.
39
End
"NORML"
Vector to PTS
Control Block
PTS Interrupt Routine
PTS
PTS
Execution
EXTINT
4 3 2 1
Ending
Instruction
"NORML"
Pending Interrupt
Response Time
ClearedSet
Latency Time
43 State Times
A0142-01

Figure 5-5. PTS Interrupt Response Time

5-11
8XC196MC, MD, MH USER’S MANUAL

Table 5-4. Execution Times for PTS Cycles

PTS Mode Execution Time (in State Times)
Single transfer mode
register/register memory/re gister memory/memory
Block transfer mode
register/register memory/register memory/memory
A/D scan mode
register/register register/memory
ASIO receive mode (MC, MD only)
Majority disabled
†
†
†
†
†
†
†
†
18 per byte or word transfer + 1 21 per byte or word transfer + 1 24 per byte or word transfer + 1
13 + 7 per byte or word transfer (1 minimum) 16 + 7 per byte or word transfer (1 minimum) 19 + 7 per byte or word transfer (1 minimum)
21 25
24 + 2 (if parity enabled)
Majority enabled
ASIO transmit mode (MC, MD only) 29 + 3 (if parity enabled) SSIO receive mode (MC, MD only) 29 (receive data bit)
SSIO transmit mode (MC, MD only) 30 (transmit data bit)
†
Register
indicates an access to the register file or peripheral SFR.
memory-map ped register, I/O, or memory. See Table 4-1 on page 4-2 for address information.
36 + sample time (second sample) 36 + 7 + sample time (third sample) 36 + 2 (if parity enabled)
21 (no reception)
20 (no transmission)
Memory
indicates an access to a

5.5 PROG RAM MING THE INTERRUPTS

The PTS select register (PTSSEL) selects either PTS service or a standard software interrupt ser­vice routine for each of the maskable interrupt requests (see Figure 5-6). The bits in the interrupt mask registers, INT_M ASK and INT_MASK1, ena ble or disable (mask) individual interrupts (see Figures 5-7 and 5-8). For the mul tiplexed interrupt sources, bits in the PI_MASK regi ster (Figure 5-9 on page 5-17) enable or disable (mask) the individual interrupt sources. With the ex­ception of the nonmaskable interrupt (NMI) bit (INT_MASK1.7), setting a bit enables the corre­sponding interrupt source and clearin g a bit disables the source.
To disable any inte r rupt, clear i ts ma sk bit . To enable an interrupt for standard interrupt service, set its mask bit a nd clear its PTS select bit . To enable an interrupt for PTS service, set both the mask bit and the PTS select bit.
5-12
STANDARD AND PTS INTERRUPTS
When you assign an interrupt to the PTS, you must set up a PTS control block (PTSCB) for each interrupt source (see “Initiali zing the PTS Control Blocks” on page 5-24) and us e the EPTS in­struction to globally enable the PTS. When you assign an interrupt to a standard software service routine, use the EI (enable interr upts) inst ruction to globally enabl e interrupt servi ci ng.
NOTE
The DI (disable interrupts) instruction does not disable PTS service. However, it does disable service for the end-of-PTS interrupt request. If an interrupt request occurs while interrupts are disabl ed, the corresp onding pending bit is set in the INT_PEND or INT_PEND1 register.
PTS servic e is not useful for multiple xed inte rrupts because the PTS cannot readily determine the source of these interrupts.
5-13
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use