Intel 8XC152JA, 8XC152JB, 8XC152JC, 8XC152JD User Manual

查询80C152JA供应商

UNIVERSAL COMMUNICATION CONTROLLER

Superset of 80C51 Architecture

Multi-Protocol Serial Communication I/O Port (2.048 Mbps/2.4 Mbps Max) Ð SDLC/HDLC Only Ð CSMA/CD and SDLC/HDLC Ð User Definable Protocols

Full Duplex/Half Duplex

MCSÉ-51 Compatible UART

16.5 MHz Maximum Clock Frequency

Multiple Power Conservation Modes

64KB Program Memory Addressing

8XC152JA/JB/JC/JD

8-BIT MICROCONTROLLER

8K Factory Mask Programmable ROM Available

64KB Data Memory Addressing

256 Bytes On-Chip RAM

Dual On-Chip DMA Channels

Hold/Hold Acknowledge

Two General Purpose Timer/Counters

5 or 7 I/O Ports

56 Special Function Registers

11 Interrupt Sources

Available in 48 Pin Dual-in-Line Package and 68 Pin Surface Mount PLCC Package

(See Packaging Spec. OrderÝ231369)

The 80C152, which is based on the MCSÉ-51 CPU, is a highly integrated single-chip 8-bit microcontroller designed for cost-sensitive, high-speed, serial communications. It is well suited for implementing Integrated Services Digital Networks (ISDN), emerging Local Area Networks, and user defined serial backplane applications. In addition to the multi-protocol communication capability, the 80C152 offers traditional microcontroller features for peripheral I/O interface and control.

Silicon implementations are much more cost effective than multi-wire cables found in board level parallel-toserial and serial-to-parallel converters. The 83C152 contains, in silicon, all the features needed for the serialto-parallel conversion. Other 83C152 benefits include: 1) better noise immunity through differential signaling or fiber optic connections, 2) data integrity utilizing the standard, designed in CRC checks, and 3) better modularity of hardware and software designs. All of theseÐcost, network parameter and real estate improvementsÐ apply to 83C152 serial links between boards or systems and 83C152 serial links on a single board.

*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

8XC152JA/JB/JC/JD

270431– 2

270431– 1

270431– 3

Figure 1. Connection Diagrams

8XC152JA/JB/JC/JD

*On 80C152JB/JD Only 270431– 18

Figure 2. Block Diagram

8XC152JA/JB/JC/JD

is used in conjunction with Port 5 and Port 6

80C152JB/JD General Description

The 80C152JB/JD is a ROMless extension of the 80C152 Universal Communication controller. The 80C152JB has the same five 8-bit I/O ports of the 80C152, plus an additional two 8-bit I/O ports, Port 5 and Port 6. The 80C152JB/JD also has two additional control pins, EBEN (EPROM Bus ENable), and EPSEN

(EPROM bus Program Store ENable).

EBEN selects the functionality of Port 5 and Port 6. When EBEN is low, these ports are strictly I/O, similar to Port 4. The SFR location for Port 5 is 91H and Port 6 is 0A1H. This means Port 5 and Port 6 are not bit addressable. With EBEN low, all program memory fetches take place via Port 0 and Port 2. (The 80C152 is a ROMless only product). When EBEN is high, Port 5 and Port 6 form an address/data bus called the E-Bus (EPROM-Bus) for program memory operations.

Table 1. Program Memory Fetches

EBEN EA

0 0 P0, P2 Active Inactive Addresses 0–0FFFFH

0 1 N/A N/A N/A Invalid Combination

1 0 P5, P6 Inactive Active Addresses 0–0FFFFH

1 1 P5, P6 Inactive Active Addresses 0–1FFFH

Program

Fetch via

P0, P2 Active Inactive Addresses

EPSEN program memory operations. EPSEN

during program memory operation, but sup-

PSEN ports Port 5 and Port 6. EPSEN external program memory for Port 5 and Port 6. EPSEN

is activated twice during each machine cycle unless an external data memory operation occurs on Port(s) 0 and Port 2. When external data memory is accessed the second activation of EPSEN skipped, which is the same as when using PSEN Note that data memory fetches cannot be made through Ports 5 and 6.

When EBEN is high and EA is low, all program memory operations take place via Ports 5 and 6. The high byte of the address goes out on Port 6, and the low byte is output on Port 5. ALE is still used to latch the address on Port 5. Next, the op code is read on Port

5. The timing is the same as when using Ports 0 and 2 for external program memory operations.

PSEN

EPSEN Comments

is the read strobe to

functions like

2000H

Table 2. 8XC152 Product Differences

ROMless

Version

80C152JA

80C152JB

80C152JC

80C152JD

NOTES:

options available

0 standard frequency range 3.5 MHz to 12 MHz

1’’ frequency range 3.5 MHz to 16.5 MHz

0‘‘

CSMA/CD

and

HDLC/SDLC Available DIP

HDLC/SDLC

Only

** ***

ROM PLCC

Version and

(83C152JA)

(83C152JC)

PLCC 5 I/O 7 I/0

Only Ports Ports

***

8XC152JA/JB/JC/JD

DIP PLCC

(1)

48 2 VCCÐSupply voltage.

24 3,33

(2)

VSSÐCircuit ground.

18-21, 27-30, Port 0ÐPort 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin 25-28 34-37 can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that

state can be used as high-impedance inputs.

Port 0 is also the multiplexed low-order address and data bus during accesses to external program memory if EBEN is pulled low. During accesses to external Data Memory, Port 0 always emits the low-order address byte and serves as the multiplexed data bus. In these applications it uses strong internal pullups when emitting 1s.

Port 0 also outputs the code bytes during program verification. External pullups are required during program verification.

1-8 4-11 Port 1ÐPort 1 is an 8-bit bidirectional I/O port with internal pullups. Port 1 pins that

have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I

, on the data sheet) because of the internal pullups.

Port 1 also serves the functions of various special features of the 8XC152, as listed below:

Pin Name Alternate Function

P1.0 GRXD GSC data input pin P1.1 GTXD GSC data output pin P1.2 DEN GSC enable signal for an external driver P1.3 TXC P1.4 RXC P1.5 HLD P1.6 HLDA DMA hold acknowledge input/output

29-36 41-48 Port 2ÐPort 2 is an 8-bit bidirectional I/O port with internal pullups. Port 2 pins that

have 1s written to them are pulled high by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external Program Memory if EBEN is pulled low. During accesses to external Data Memory that use 16bit addresses (MOVX

DPTR and DMA operations), Port 2 emits the high-order

address byte. In these applications it uses strong internal pullups when emitting 1s.

During accesses to external Data Memory that use 8-bit addresses (MOVX Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits during program verification.

10- 17 14-16, Port 3ÐPort 3 is an 8-bit bidirectional I/O port with internal pullups. Port 3 pins that

18, 19, have 1s written to them are pulled high by the internal pullups, and in that state can be 23-25 used as inputs. As inputs, Port 3 pins that are externally being pulled low will source

current (I

, on the data sheet) because of the pullups.

Port 3 also serves the functions of various special features of the MCS-51 Family, as listed below:

Pin Name Alternate Function

P3.0 RXD Serial input line P3.1 TXD Serial output line P3.2 INT0 P3.3 INT1 P3.4 T0 Timer 0 external input P3.5 T1 Timer 1 external input P3.6 WR External Data Memory Write strobe P3.7 RD

Pin Description

GSC input pin for external transmit clock GSC input pin for external receive clock DMA hold input/output

External Interrupt 0 External Interrupt 1

External Data Memory Read strobe

Ri),

8XC152JA/JB/JC/JD

Pin Description (Continued)

47-40 65-58 Port 4ÐPort 4 is an 8-bit bidirectional I/O port with internal pullups. Port 4 pins that

have 1s written to them are pulled high by the internal pullups, and in that state can

be used as inputs. As inputs, Port 4 pins that are externally being pulled low will

source current (I

Port 4 also receives the low-order address bytes during program verification.

, on the data sheet) because of the internal pullups. In addition,

913RSTÐReset input. A logic low on this pin for three machine cycles while the

oscillator is running resets the device. An internal pullup resistor permits a power-on

reset to be generated using only an external capacitor to VSS. Although the GSC

recognizes the reset after three machine cycles, data may continue to be

transmitted for up to 4 machine cycles after Reset is first applied.

38 55 ALEÐAddress Latch Enable output signal for latching the low byte of the address

during accesses to external memory.

In normal operation ALE is emitted at a constant rate of (/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. While in Reset, ALE remains at a constant high level.

37 54 PSENÐProgram Store Enable is the Read strobe to External Program Memory.

When the 8XC152 is executing from external program memory, PSEN (low). When the device is executing code from External Program Memory, PSEN activated twice each machine cycle, except that two PSEN during each access to External Data Memory. While in Reset, PSEN constant high level.

39 56 EAÐExternal Access enable. EA must be externally pulled low in order to enable

the 8XC152 to fetch code from External Program Memory locations 0000H to 0FFFH.

must be connected to VCCfor internal program execution.

23 32 XTAL1ÐInput to the inverting oscillator amplifier and input to the internal clock

generating circuits.

22 31 XTAL2ÐOutput from the inverting oscillator amplifier.

N/A 17, 20 Port 5ÐPort 5 is an 8-bit bidirectional I/O port with internal pullups. Port 5 pins that

21, 22 have 1s written to them are pulled high by the internal pullups, and in that state can 38, 39 be used as inputs. As inputs, Port 5 pins that are externally being pulled low will 40, 49 source current (I

Port 5 is also the multiplexed low-order address and data bus during accesses to

, on the data sheet) because of the internal pullups.

external program memory if EBEN is pulled high. In this application it uses strong pullups when emitting 1s.

N/A 67, 66 Port 6ÐPort 6 is an 8-bit bidirectional I/O port with internal pullups. Port 6 pins that

52, 57 have 1s written to them are pulled high by the internal pullups, and in that state can 50, 68 be used as inputs. As inputs, Port 6 pins that are externally pulled low will source 1, 51 current (I

, on the data sheet) because of the internal pullups.

Port 6 emits the high-order address byte during fetches from external Program Memory if EBEN is pulled high. In this application it uses strong pullups when emitting 1s.

N/A 12 EBENÐE-Bus Enable input that designates whether program memory fetches take

place via Ports 0 and 2 or Ports 5 and 6. Table 1 shows how the ports are used in conjunction with EBEN.

N/A 53 EPSENÐE-bus Program Store Enable is the Read strobe to external program

memory when EBEN is high. Table 2 shows when EPSEN depending on the status of EBEN and EA.

Pin Description

is active

activations are skipped

remains at a

is used relative to PSEN

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